1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/slab.h> 24 #include <linux/platform_device.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/bitops.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinconf-generic.h> 31 #include <linux/pinctrl/pinmux.h> 32 #include <linux/string_choices.h> 33 #include <linux/suspend.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 #ifdef CONFIG_SUSPEND 40 static struct amd_gpio *pinctrl_dev; 41 #endif 42 43 static inline void __iomem *amd_gpio_pin_reg(struct amd_gpio *gpio_dev, unsigned int pin) 44 { 45 if (gpio_dev->base_rgpio && pin >= AMD_GPIO_RGPIO_PIN_BASE) 46 return gpio_dev->base_rgpio + (pin - AMD_GPIO_RGPIO_PIN_BASE) * 4; 47 return gpio_dev->base + pin * 4; 48 } 49 50 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 51 { 52 unsigned long flags; 53 u32 pin_reg; 54 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 55 56 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 57 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 58 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 59 60 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 61 return GPIO_LINE_DIRECTION_OUT; 62 63 return GPIO_LINE_DIRECTION_IN; 64 } 65 66 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 67 { 68 unsigned long flags; 69 u32 pin_reg; 70 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 71 72 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 73 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 74 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 75 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); 76 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 77 78 return 0; 79 } 80 81 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 82 int value) 83 { 84 u32 pin_reg; 85 unsigned long flags; 86 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 87 88 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 89 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 90 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 91 if (value) 92 pin_reg |= BIT(OUTPUT_VALUE_OFF); 93 else 94 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 95 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); 96 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 97 98 return 0; 99 } 100 101 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 102 { 103 u32 pin_reg; 104 unsigned long flags; 105 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 106 107 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 108 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 109 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 110 111 return !!(pin_reg & BIT(PIN_STS_OFF)); 112 } 113 114 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset, 115 int value) 116 { 117 u32 pin_reg; 118 unsigned long flags; 119 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 120 121 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 122 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 123 if (value) 124 pin_reg |= BIT(OUTPUT_VALUE_OFF); 125 else 126 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 127 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); 128 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 129 130 return 0; 131 } 132 133 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset, 134 unsigned int debounce) 135 { 136 u32 time; 137 u32 pin_reg; 138 int ret = 0; 139 140 /* Use special handling for Pin0 debounce */ 141 if (offset == 0) { 142 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 143 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) 144 debounce = 0; 145 } 146 147 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, offset)); 148 149 if (debounce) { 150 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 151 pin_reg &= ~DB_TMR_OUT_MASK; 152 /* 153 Debounce Debounce Timer Max 154 TmrLarge TmrOutUnit Unit Debounce 155 Time 156 0 0 61 usec (2 RtcClk) 976 usec 157 0 1 244 usec (8 RtcClk) 3.9 msec 158 1 0 15.6 msec (512 RtcClk) 250 msec 159 1 1 62.5 msec (2048 RtcClk) 1 sec 160 */ 161 162 if (debounce < 61) { 163 pin_reg |= 1; 164 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 165 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 166 } else if (debounce < 976) { 167 time = debounce / 61; 168 pin_reg |= time & DB_TMR_OUT_MASK; 169 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 170 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 171 } else if (debounce < 3900) { 172 time = debounce / 244; 173 pin_reg |= time & DB_TMR_OUT_MASK; 174 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 175 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 176 } else if (debounce < 250000) { 177 time = debounce / 15625; 178 pin_reg |= time & DB_TMR_OUT_MASK; 179 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 180 pin_reg |= BIT(DB_TMR_LARGE_OFF); 181 } else if (debounce < 1000000) { 182 time = debounce / 62500; 183 pin_reg |= time & DB_TMR_OUT_MASK; 184 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 185 pin_reg |= BIT(DB_TMR_LARGE_OFF); 186 } else { 187 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 188 ret = -EINVAL; 189 } 190 } else { 191 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 192 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 193 pin_reg &= ~DB_TMR_OUT_MASK; 194 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 195 } 196 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, offset)); 197 198 return ret; 199 } 200 201 #ifdef CONFIG_DEBUG_FS 202 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 203 { 204 u32 pin_reg; 205 u32 db_cntrl; 206 unsigned long flags; 207 unsigned int bank, i, pin_num; 208 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 209 210 bool tmr_out_unit; 211 bool tmr_large; 212 213 char *level_trig; 214 char *active_level; 215 char *interrupt_mask; 216 char *wake_cntrl0; 217 char *wake_cntrl1; 218 char *wake_cntrl2; 219 char *pin_sts; 220 char *interrupt_sts; 221 char *wake_sts; 222 char *orientation; 223 char debounce_value[40]; 224 char *debounce_enable; 225 char *wake_cntrlz; 226 227 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); 228 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 229 unsigned int time = 0; 230 unsigned int unit = 0; 231 232 switch (bank) { 233 case 0: 234 i = 0; 235 pin_num = AMD_GPIO_PINS_BANK0; 236 break; 237 case 1: 238 i = 64; 239 pin_num = AMD_GPIO_PINS_BANK1 + i; 240 break; 241 case 2: 242 i = 128; 243 pin_num = AMD_GPIO_PINS_BANK2 + i; 244 break; 245 case 3: 246 i = 192; 247 pin_num = AMD_GPIO_PINS_BANK3 + i; 248 break; 249 case 4: 250 i = AMD_GPIO_RGPIO_PIN_BASE; 251 pin_num = AMD_GPIO_PINS_BANK4 + i; 252 break; 253 default: 254 /* Illegal bank number, ignore */ 255 continue; 256 } 257 seq_printf(s, "GPIO bank%d\n", bank); 258 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n"); 259 for (; i < pin_num; i++) { 260 seq_printf(s, "#%d\t", i); 261 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 262 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, i)); 263 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 264 265 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 266 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 267 ACTIVE_LEVEL_MASK; 268 269 if (level == ACTIVE_LEVEL_HIGH) 270 active_level = "↑"; 271 else if (level == ACTIVE_LEVEL_LOW) 272 active_level = "↓"; 273 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 274 level == ACTIVE_LEVEL_BOTH) 275 active_level = "b"; 276 else 277 active_level = "?"; 278 279 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 280 level_trig = "level"; 281 else 282 level_trig = " edge"; 283 284 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 285 interrupt_mask = "��"; 286 else 287 interrupt_mask = "��"; 288 289 if (pin_reg & BIT(INTERRUPT_STS_OFF)) 290 interrupt_sts = "��"; 291 else 292 interrupt_sts = " "; 293 294 seq_printf(s, "%s %s| %s| %s|", 295 interrupt_sts, 296 interrupt_mask, 297 active_level, 298 level_trig); 299 } else 300 seq_puts(s, " ∅| | |"); 301 302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 303 wake_cntrl0 = "⏰"; 304 else 305 wake_cntrl0 = " "; 306 seq_printf(s, " %s| ", wake_cntrl0); 307 308 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 309 wake_cntrl1 = "⏰"; 310 else 311 wake_cntrl1 = " "; 312 seq_printf(s, "%s|", wake_cntrl1); 313 314 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 315 wake_cntrl2 = "⏰"; 316 else 317 wake_cntrl2 = " "; 318 seq_printf(s, " %s|", wake_cntrl2); 319 320 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 321 wake_cntrlz = "⏰"; 322 else 323 wake_cntrlz = " "; 324 seq_printf(s, "%s|", wake_cntrlz); 325 326 if (pin_reg & BIT(WAKE_STS_OFF)) 327 wake_sts = "��"; 328 else 329 wake_sts = " "; 330 seq_printf(s, " %s|", wake_sts); 331 332 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 333 seq_puts(s, " ↑ |"); 334 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) { 335 seq_puts(s, " ↓ |"); 336 } else { 337 seq_puts(s, " |"); 338 } 339 340 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 341 pin_sts = "output"; 342 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 343 orientation = "↑"; 344 else 345 orientation = "↓"; 346 } else { 347 pin_sts = "input "; 348 if (pin_reg & BIT(PIN_STS_OFF)) 349 orientation = "↑"; 350 else 351 orientation = "↓"; 352 } 353 seq_printf(s, "%s %s|", pin_sts, orientation); 354 355 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 356 if (db_cntrl) { 357 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 358 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 359 time = pin_reg & DB_TMR_OUT_MASK; 360 if (tmr_large) { 361 if (tmr_out_unit) 362 unit = 62500; 363 else 364 unit = 15625; 365 } else { 366 if (tmr_out_unit) 367 unit = 244; 368 else 369 unit = 61; 370 } 371 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 372 debounce_enable = "b"; 373 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 374 debounce_enable = "↓"; 375 else 376 debounce_enable = "↑"; 377 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit); 378 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value); 379 } else { 380 seq_puts(s, " |"); 381 } 382 seq_printf(s, "0x%x\n", pin_reg); 383 } 384 } 385 } 386 #else 387 #define amd_gpio_dbg_show NULL 388 #endif 389 390 static void amd_gpio_irq_enable(struct irq_data *d) 391 { 392 u32 pin_reg; 393 unsigned long flags; 394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 395 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 396 irq_hw_number_t hwirq = irqd_to_hwirq(d); 397 398 gpiochip_enable_irq(gc, hwirq); 399 400 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 401 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 402 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 403 pin_reg |= BIT(INTERRUPT_MASK_OFF); 404 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 405 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 406 } 407 408 static void amd_gpio_irq_disable(struct irq_data *d) 409 { 410 u32 pin_reg; 411 unsigned long flags; 412 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 413 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 414 irq_hw_number_t hwirq = irqd_to_hwirq(d); 415 416 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 417 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 418 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 419 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 420 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 421 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 422 423 gpiochip_disable_irq(gc, hwirq); 424 } 425 426 static void amd_gpio_irq_mask(struct irq_data *d) 427 { 428 u32 pin_reg; 429 unsigned long flags; 430 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 431 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 432 irq_hw_number_t hwirq = irqd_to_hwirq(d); 433 434 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 435 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 436 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 437 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 439 } 440 441 static void amd_gpio_irq_unmask(struct irq_data *d) 442 { 443 u32 pin_reg; 444 unsigned long flags; 445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 447 irq_hw_number_t hwirq = irqd_to_hwirq(d); 448 449 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 450 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 451 pin_reg |= BIT(INTERRUPT_MASK_OFF); 452 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 453 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 454 } 455 456 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 457 { 458 u32 pin_reg; 459 unsigned long flags; 460 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 461 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 462 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 463 irq_hw_number_t hwirq = irqd_to_hwirq(d); 464 int err; 465 466 pm_pr_dbg("Setting wake for GPIO %lu to %s\n", 467 hwirq, str_enable_disable(on)); 468 469 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 470 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 471 472 if (on) 473 pin_reg |= wake_mask; 474 else 475 pin_reg &= ~wake_mask; 476 477 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 478 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 479 480 if (on) 481 err = enable_irq_wake(gpio_dev->irq); 482 else 483 err = disable_irq_wake(gpio_dev->irq); 484 485 if (err) 486 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 487 str_enable_disable(on)); 488 489 return 0; 490 } 491 492 static void amd_gpio_irq_eoi(struct irq_data *d) 493 { 494 u32 reg; 495 unsigned long flags; 496 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 497 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 498 499 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 500 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 501 reg |= EOI_MASK; 502 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 503 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 504 } 505 506 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 507 { 508 int ret = 0; 509 u32 pin_reg, pin_reg_irq_en, mask, reg; 510 unsigned long flags; 511 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 512 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 513 irq_hw_number_t hwirq = irqd_to_hwirq(d); 514 515 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 516 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, hwirq)); 517 518 switch (type & IRQ_TYPE_SENSE_MASK) { 519 case IRQ_TYPE_EDGE_RISING: 520 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 521 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 522 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 523 irq_set_handler_locked(d, handle_edge_irq); 524 break; 525 526 case IRQ_TYPE_EDGE_FALLING: 527 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 528 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 529 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 530 irq_set_handler_locked(d, handle_edge_irq); 531 break; 532 533 case IRQ_TYPE_EDGE_BOTH: 534 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 535 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 536 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF; 537 irq_set_handler_locked(d, handle_edge_irq); 538 break; 539 540 case IRQ_TYPE_LEVEL_HIGH: 541 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 542 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 543 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 544 irq_set_handler_locked(d, handle_level_irq); 545 break; 546 547 case IRQ_TYPE_LEVEL_LOW: 548 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 549 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 550 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 551 irq_set_handler_locked(d, handle_level_irq); 552 break; 553 554 case IRQ_TYPE_NONE: 555 break; 556 557 default: 558 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 559 ret = -EINVAL; 560 } 561 562 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 563 /* 564 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 565 * debounce registers of any GPIO will block wake/interrupt status 566 * generation for *all* GPIOs for a length of time that depends on 567 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 568 * INTERRUPT_ENABLE bit will read as 0. 569 * 570 * We temporarily enable irq for the GPIO whose configuration is 571 * changing, and then wait for it to read back as 1 to know when 572 * debounce has settled and then disable the irq again. 573 * We do this polling with the spinlock held to ensure other GPIO 574 * access routines do not read an incorrect value for the irq enable 575 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 576 * spurious irqs, and disable the irq again after polling. 577 */ 578 mask = BIT(INTERRUPT_ENABLE_OFF); 579 pin_reg_irq_en = pin_reg; 580 pin_reg_irq_en |= mask; 581 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 582 writel(pin_reg_irq_en, amd_gpio_pin_reg(gpio_dev, hwirq)); 583 if (readl_poll_timeout_atomic(amd_gpio_pin_reg(gpio_dev, hwirq), reg, 584 (reg & mask) == mask, 1, 1000)) 585 ret = -ETIMEDOUT; 586 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, hwirq)); 587 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 588 589 return ret; 590 } 591 592 static void amd_irq_ack(struct irq_data *d) 593 { 594 /* 595 * based on HW design,there is no need to ack HW 596 * before handle current irq. But this routine is 597 * necessary for handle_edge_irq 598 */ 599 } 600 601 static const struct irq_chip amd_gpio_irqchip = { 602 .name = "amd_gpio", 603 .irq_ack = amd_irq_ack, 604 .irq_enable = amd_gpio_irq_enable, 605 .irq_disable = amd_gpio_irq_disable, 606 .irq_mask = amd_gpio_irq_mask, 607 .irq_unmask = amd_gpio_irq_unmask, 608 .irq_set_wake = amd_gpio_irq_set_wake, 609 .irq_eoi = amd_gpio_irq_eoi, 610 .irq_set_type = amd_gpio_irq_set_type, 611 /* 612 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 613 * also generates an IRQ. We need the IRQ so the irq_handler can clear 614 * the wake event. Otherwise the wake event will never clear and 615 * prevent the system from suspending. 616 */ 617 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 618 GPIOCHIP_IRQ_RESOURCE_HELPERS, 619 }; 620 621 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 622 623 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 624 { 625 struct amd_gpio *gpio_dev = dev_id; 626 struct gpio_chip *gc = &gpio_dev->gc; 627 unsigned int i, irqnr; 628 unsigned long flags; 629 bool ret = false; 630 u32 regval; 631 u64 status, mask; 632 633 /* Read the wake status */ 634 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 635 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 636 status <<= 32; 637 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 638 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 639 640 /* Bit 0-45 contain the relevant status bits */ 641 status &= (1ULL << 46) - 1; 642 for (mask = 1, irqnr = 0; status; mask <<= 1, irqnr += 4) { 643 if (!(status & mask)) 644 continue; 645 status &= ~mask; 646 647 /* Each status bit covers four pins */ 648 for (i = 0; i < 4; i++) { 649 regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i)); 650 651 if (regval & PIN_IRQ_PENDING) 652 pm_pr_dbg("GPIO %d is active: 0x%x", 653 irqnr + i, regval); 654 655 /* caused wake on resume context for shared IRQ */ 656 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 657 return true; 658 659 if (!(regval & PIN_IRQ_PENDING) || 660 !(regval & BIT(INTERRUPT_MASK_OFF))) 661 continue; 662 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 663 664 /* Clear interrupt. 665 * We must read the pin register again, in case the 666 * value was changed while executing 667 * generic_handle_domain_irq() above. 668 * If the line is not an irq, disable it in order to 669 * avoid a system hang caused by an interrupt storm. 670 */ 671 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 672 regval = readl(amd_gpio_pin_reg(gpio_dev, irqnr + i)); 673 if (!gpiochip_line_is_irq(gc, irqnr + i)) { 674 regval &= ~BIT(INTERRUPT_MASK_OFF); 675 dev_dbg(&gpio_dev->pdev->dev, 676 "Disabling spurious GPIO IRQ %d\n", 677 irqnr + i); 678 } else { 679 ret = true; 680 } 681 writel(regval, amd_gpio_pin_reg(gpio_dev, irqnr + i)); 682 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 683 } 684 } 685 686 /* 687 * Unlike WAKE_INT_STATUS_REG0/1, where each status bit covers four 688 * pins, the RGPIO status register uses one bit per pin. As with the 689 * main bank status registers, a bit is cleared by acknowledging the 690 * pending interrupt on its pin below (clearing PIN_IRQ_PENDING); no 691 * separate write to the RGPIO status register is required. 692 */ 693 if (gpio_dev->base_rgpio) { 694 u32 status_rgpio; 695 696 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 697 status_rgpio = readl(gpio_dev->base_rgpio + WAKE_INT_STATUS_REG_RGPIO); 698 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 699 700 status_rgpio &= GENMASK(AMD_GPIO_PINS_BANK4 - 1, 0); 701 702 for (i = 0; i < AMD_GPIO_PINS_BANK4; i++) { 703 unsigned int pin = AMD_GPIO_RGPIO_PIN_BASE + i; 704 705 if (!(status_rgpio & BIT(i))) 706 continue; 707 708 regval = readl(amd_gpio_pin_reg(gpio_dev, pin)); 709 710 if (regval & PIN_IRQ_PENDING) 711 pm_pr_dbg("GPIO %d is active: 0x%x", pin, regval); 712 713 /* caused wake on resume context for shared IRQ */ 714 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 715 return true; 716 717 if (!(regval & PIN_IRQ_PENDING) || 718 !(regval & BIT(INTERRUPT_MASK_OFF))) 719 continue; 720 generic_handle_domain_irq_safe(gc->irq.domain, pin); 721 722 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 723 regval = readl(amd_gpio_pin_reg(gpio_dev, pin)); 724 if (!gpiochip_line_is_irq(gc, pin)) { 725 regval &= ~BIT(INTERRUPT_MASK_OFF); 726 dev_dbg(&gpio_dev->pdev->dev, 727 "Disabling spurious GPIO IRQ %d\n", 728 pin); 729 } else { 730 ret = true; 731 } 732 writel(regval, amd_gpio_pin_reg(gpio_dev, pin)); 733 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 734 } 735 } 736 737 /* did not cause wake on resume context for shared IRQ */ 738 if (irq < 0) 739 return false; 740 741 /* Signal EOI to the GPIO unit */ 742 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 743 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 744 regval |= EOI_MASK; 745 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 746 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 747 748 return ret; 749 } 750 751 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 752 { 753 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 754 } 755 756 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 757 { 758 return do_amd_gpio_irq_handler(-1, dev_id); 759 } 760 761 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 762 { 763 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 764 765 return gpio_dev->ngroups; 766 } 767 768 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 769 unsigned group) 770 { 771 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 772 773 return gpio_dev->groups[group].name; 774 } 775 776 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 777 unsigned group, 778 const unsigned **pins, 779 unsigned *num_pins) 780 { 781 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 782 783 *pins = gpio_dev->groups[group].pins; 784 *num_pins = gpio_dev->groups[group].npins; 785 return 0; 786 } 787 788 static const struct pinctrl_ops amd_pinctrl_ops = { 789 .get_groups_count = amd_get_groups_count, 790 .get_group_name = amd_get_group_name, 791 .get_group_pins = amd_get_group_pins, 792 #ifdef CONFIG_OF 793 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 794 .dt_free_map = pinctrl_utils_free_map, 795 #endif 796 }; 797 798 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 799 unsigned int pin, 800 unsigned long *config) 801 { 802 u32 pin_reg; 803 unsigned arg; 804 unsigned long flags; 805 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 806 enum pin_config_param param = pinconf_to_config_param(*config); 807 808 if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) 809 return -EOPNOTSUPP; 810 811 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 812 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); 813 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 814 switch (param) { 815 case PIN_CONFIG_INPUT_DEBOUNCE: 816 arg = pin_reg & DB_TMR_OUT_MASK; 817 break; 818 819 case PIN_CONFIG_BIAS_PULL_DOWN: 820 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 821 break; 822 823 case PIN_CONFIG_BIAS_PULL_UP: 824 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0); 825 break; 826 827 case PIN_CONFIG_DRIVE_STRENGTH: 828 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 829 break; 830 831 default: 832 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 833 param); 834 return -ENOTSUPP; 835 } 836 837 *config = pinconf_to_config_packed(param, arg); 838 839 return 0; 840 } 841 842 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 843 unsigned long *configs, unsigned int num_configs) 844 { 845 int i; 846 u32 arg; 847 int ret = 0; 848 u32 pin_reg; 849 unsigned long flags; 850 enum pin_config_param param; 851 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 852 853 if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) 854 return -EOPNOTSUPP; 855 856 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 857 for (i = 0; i < num_configs; i++) { 858 param = pinconf_to_config_param(configs[i]); 859 arg = pinconf_to_config_argument(configs[i]); 860 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); 861 862 switch (param) { 863 case PIN_CONFIG_INPUT_DEBOUNCE: 864 ret = amd_gpio_set_debounce(gpio_dev, pin, arg); 865 goto out_unlock; 866 867 case PIN_CONFIG_BIAS_PULL_DOWN: 868 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 869 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 870 break; 871 872 case PIN_CONFIG_BIAS_PULL_UP: 873 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 874 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF; 875 break; 876 877 case PIN_CONFIG_DRIVE_STRENGTH: 878 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 879 << DRV_STRENGTH_SEL_OFF); 880 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 881 << DRV_STRENGTH_SEL_OFF; 882 break; 883 884 default: 885 dev_dbg(&gpio_dev->pdev->dev, 886 "Invalid config param %04x\n", param); 887 ret = -ENOTSUPP; 888 } 889 890 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin)); 891 } 892 out_unlock: 893 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 894 895 return ret; 896 } 897 898 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 899 unsigned int group, 900 unsigned long *config) 901 { 902 const unsigned *pins; 903 unsigned npins; 904 int ret; 905 906 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 907 if (ret) 908 return ret; 909 910 if (amd_pinconf_get(pctldev, pins[0], config)) 911 return -ENOTSUPP; 912 913 return 0; 914 } 915 916 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 917 unsigned group, unsigned long *configs, 918 unsigned num_configs) 919 { 920 const unsigned *pins; 921 unsigned npins; 922 int i, ret; 923 924 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 925 if (ret) 926 return ret; 927 for (i = 0; i < npins; i++) { 928 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 929 return -ENOTSUPP; 930 } 931 return 0; 932 } 933 934 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, 935 unsigned long config) 936 { 937 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 938 939 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); 940 } 941 942 static const struct pinconf_ops amd_pinconf_ops = { 943 .pin_config_get = amd_pinconf_get, 944 .pin_config_set = amd_pinconf_set, 945 .pin_config_group_get = amd_pinconf_group_get, 946 .pin_config_group_set = amd_pinconf_group_set, 947 }; 948 949 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 950 { 951 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 952 unsigned long flags; 953 u32 pin_reg, mask; 954 int i; 955 956 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 957 958 #ifdef CONFIG_ACPI 959 /* 960 * Platforms without _AEI leave GPIO wake sources to firmware, so 961 * preserve their S4 wake bits. 962 */ 963 if (acpi_has_method(ACPI_HANDLE(&gpio_dev->pdev->dev), "_AEI")) 964 mask |= BIT(WAKE_CNTRL_OFF_S4); 965 #endif 966 967 for (i = 0; i < desc->npins; i++) { 968 int pin = desc->pins[i].number; 969 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 970 971 if (!pd) 972 continue; 973 974 if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) 975 continue; 976 977 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 978 979 pin_reg = readl(amd_gpio_pin_reg(gpio_dev, pin)); 980 pin_reg &= ~mask; 981 writel(pin_reg, amd_gpio_pin_reg(gpio_dev, pin)); 982 983 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 984 } 985 } 986 987 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI) 988 static void amd_gpio_check_pending(void) 989 { 990 struct amd_gpio *gpio_dev = pinctrl_dev; 991 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 992 int i; 993 994 if (!pm_debug_messages_on) 995 return; 996 997 for (i = 0; i < desc->npins; i++) { 998 int pin = desc->pins[i].number; 999 u32 tmp; 1000 1001 if (pin >= AMD_GPIO_RGPIO_PIN_BASE && !gpio_dev->base_rgpio) 1002 continue; 1003 1004 tmp = readl(amd_gpio_pin_reg(gpio_dev, pin)); 1005 if (tmp & PIN_IRQ_PENDING) 1006 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp); 1007 } 1008 } 1009 1010 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = { 1011 .check = amd_gpio_check_pending, 1012 }; 1013 1014 static void amd_gpio_register_s2idle_ops(void) 1015 { 1016 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 1017 } 1018 1019 static void amd_gpio_unregister_s2idle_ops(void) 1020 { 1021 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops); 1022 } 1023 #else 1024 static inline void amd_gpio_register_s2idle_ops(void) {} 1025 static inline void amd_gpio_unregister_s2idle_ops(void) {} 1026 #endif 1027 1028 #ifdef CONFIG_PM_SLEEP 1029 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 1030 { 1031 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 1032 1033 if (!pd) 1034 return false; 1035 1036 /* 1037 * Only restore the pin if it is actually in use by the kernel (or 1038 * by userspace). 1039 */ 1040 if (pd->mux_owner || pd->gpio_owner || 1041 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 1042 return true; 1043 1044 return false; 1045 } 1046 1047 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend) 1048 { 1049 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1050 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1051 unsigned long flags; 1052 int i; 1053 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE; 1054 1055 for (i = 0; i < desc->npins; i++) { 1056 int pin = desc->pins[i].number; 1057 1058 if (!amd_gpio_should_save(gpio_dev, pin)) 1059 continue; 1060 1061 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1062 gpio_dev->saved_regs[i] = readl(amd_gpio_pin_reg(gpio_dev, pin)) & ~PIN_IRQ_PENDING; 1063 1064 /* mask any interrupts not intended to be a wake source */ 1065 if (!(gpio_dev->saved_regs[i] & wake_mask)) { 1066 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF), 1067 amd_gpio_pin_reg(gpio_dev, pin)); 1068 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n", 1069 pin, is_suspend ? "suspend" : "hibernate"); 1070 } 1071 1072 /* 1073 * debounce enabled over suspend has shown issues with a GPIO 1074 * being unable to wake the system, as we're only interested in 1075 * the actual wakeup event, clear it. 1076 */ 1077 if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) { 1078 amd_gpio_set_debounce(gpio_dev, pin, 0); 1079 pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n", 1080 pin, is_suspend ? "suspend" : "hibernate"); 1081 } 1082 1083 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1084 } 1085 1086 return 0; 1087 } 1088 1089 static int amd_gpio_suspend(struct device *dev) 1090 { 1091 #ifdef CONFIG_SUSPEND 1092 pinctrl_dev = dev_get_drvdata(dev); 1093 #endif 1094 return amd_gpio_suspend_hibernate_common(dev, true); 1095 } 1096 1097 static int amd_gpio_hibernate(struct device *dev) 1098 { 1099 return amd_gpio_suspend_hibernate_common(dev, false); 1100 } 1101 1102 static int amd_gpio_resume(struct device *dev) 1103 { 1104 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 1105 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 1106 unsigned long flags; 1107 int i; 1108 1109 for (i = 0; i < desc->npins; i++) { 1110 int pin = desc->pins[i].number; 1111 1112 if (!amd_gpio_should_save(gpio_dev, pin)) 1113 continue; 1114 1115 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 1116 gpio_dev->saved_regs[i] |= readl(amd_gpio_pin_reg(gpio_dev, pin)) & PIN_IRQ_PENDING; 1117 writel(gpio_dev->saved_regs[i], amd_gpio_pin_reg(gpio_dev, pin)); 1118 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 1119 } 1120 1121 return 0; 1122 } 1123 1124 static const struct dev_pm_ops amd_gpio_pm_ops = { 1125 .suspend_late = amd_gpio_suspend, 1126 .resume_early = amd_gpio_resume, 1127 .freeze_late = amd_gpio_hibernate, 1128 .thaw_early = amd_gpio_resume, 1129 .poweroff_late = amd_gpio_hibernate, 1130 .restore_early = amd_gpio_resume, 1131 }; 1132 #endif 1133 1134 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 1135 { 1136 return ARRAY_SIZE(pmx_functions); 1137 } 1138 1139 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 1140 { 1141 return pmx_functions[selector].name; 1142 } 1143 1144 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 1145 const char * const **groups, 1146 unsigned int * const num_groups) 1147 { 1148 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1149 1150 if (!gpio_dev->iomux_base && 1151 pmx_functions[selector].index < AMD_GPIO_RGPIO_PIN_BASE) { 1152 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 1153 return -EINVAL; 1154 } 1155 1156 *groups = pmx_functions[selector].groups; 1157 *num_groups = pmx_functions[selector].ngroups; 1158 return 0; 1159 } 1160 1161 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 1162 { 1163 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 1164 struct device *dev = &gpio_dev->pdev->dev; 1165 struct pin_desc *pd; 1166 int ind, index; 1167 unsigned int pin = gpio_dev->groups[group].pins[0]; 1168 1169 if (pin >= AMD_GPIO_RGPIO_PIN_BASE) { 1170 if (!gpio_dev->base_rgpio) 1171 return -EINVAL; 1172 1173 for (index = 0; index < NSELECTS; index++) 1174 if (!strcmp(gpio_dev->groups[group].name, 1175 pmx_functions[function].groups[index])) 1176 break; 1177 if (index >= NSELECTS) 1178 return -EINVAL; 1179 1180 writeb(index, gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET + 1181 (pin - AMD_GPIO_RGPIO_PIN_BASE)); 1182 1183 if (index != (readb(gpio_dev->base_rgpio + AMD_GPIO_RGPIO_MUX_OFFSET + 1184 (pin - AMD_GPIO_RGPIO_PIN_BASE)) & FUNCTION_MASK)) { 1185 dev_err(dev, "RGPIO_GPIO %u mux not present or supported\n", pin); 1186 return -EINVAL; 1187 } 1188 1189 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1190 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1191 pd->mux_owner = gpio_dev->groups[group].name; 1192 } 1193 return 0; 1194 } 1195 1196 if (!gpio_dev->iomux_base) 1197 return -EINVAL; 1198 1199 for (index = 0; index < NSELECTS; index++) { 1200 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1201 continue; 1202 1203 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1204 FUNCTION_INVALID) { 1205 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1206 pmx_functions[function].index); 1207 return -EINVAL; 1208 } 1209 1210 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1211 1212 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1213 FUNCTION_MASK)) { 1214 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1215 pmx_functions[function].index); 1216 return -EINVAL; 1217 } 1218 1219 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1220 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1221 continue; 1222 1223 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1224 pd->mux_owner = gpio_dev->groups[group].name; 1225 } 1226 break; 1227 } 1228 1229 return 0; 1230 } 1231 1232 static const struct pinmux_ops amd_pmxops = { 1233 .get_functions_count = amd_get_functions_count, 1234 .get_function_name = amd_get_fname, 1235 .get_function_groups = amd_get_groups, 1236 .set_mux = amd_set_mux, 1237 }; 1238 1239 static struct pinctrl_desc amd_pinctrl_desc = { 1240 .pins = kerncz_pins, 1241 .npins = ARRAY_SIZE(kerncz_pins), 1242 .pctlops = &amd_pinctrl_ops, 1243 .pmxops = &amd_pmxops, 1244 .confops = &amd_pinconf_ops, 1245 .owner = THIS_MODULE, 1246 }; 1247 1248 static void __iomem *amd_get_named_res(struct device *dev, struct platform_device *pdev, 1249 const char *name, resource_size_t minsz) 1250 { 1251 struct resource *res; 1252 void __iomem *base; 1253 int index; 1254 1255 index = device_property_match_string(dev, "pinctrl-resource-names", name); 1256 if (index < 0) { 1257 dev_dbg(dev, "%s not supported\n", name); 1258 return NULL; 1259 } 1260 1261 base = devm_platform_get_and_ioremap_resource(pdev, index, &res); 1262 if (IS_ERR(base)) { 1263 dev_dbg(dev, "%s not supported %d io resource\n", name, index); 1264 return NULL; 1265 } 1266 1267 if (resource_size(res) < minsz) { 1268 dev_err(dev, "%s resource too small\n", name); 1269 return NULL; 1270 } 1271 1272 return base; 1273 } 1274 1275 static int amd_gpio_probe(struct platform_device *pdev) 1276 { 1277 int ret = 0; 1278 struct resource *res; 1279 struct amd_gpio *gpio_dev; 1280 struct gpio_irq_chip *girq; 1281 1282 gpio_dev = devm_kzalloc(&pdev->dev, 1283 sizeof(struct amd_gpio), GFP_KERNEL); 1284 if (!gpio_dev) 1285 return -ENOMEM; 1286 1287 raw_spin_lock_init(&gpio_dev->lock); 1288 1289 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1290 if (IS_ERR(gpio_dev->base)) { 1291 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1292 return PTR_ERR(gpio_dev->base); 1293 } 1294 1295 gpio_dev->base_rgpio = amd_get_named_res(&pdev->dev, pdev, "rgpio", 1296 WAKE_INT_STATUS_REG_RGPIO + sizeof(u32)); 1297 /* 1298 * RGPIO pins are numbered from AMD_GPIO_RGPIO_PIN_BASE, so the main 1299 * bank must span exactly that many register slots for the RGPIO pin 1300 * numbering to line up. Disable RGPIO if the main bank is a different 1301 * size. 1302 */ 1303 if (gpio_dev->base_rgpio && resource_size(res) / 4 != AMD_GPIO_RGPIO_PIN_BASE) { 1304 dev_err(&pdev->dev, "unexpected GPIO bank size, disabling RGPIO\n"); 1305 gpio_dev->base_rgpio = NULL; 1306 } 1307 1308 gpio_dev->irq = platform_get_irq(pdev, 0); 1309 if (gpio_dev->irq < 0) 1310 return gpio_dev->irq; 1311 1312 #ifdef CONFIG_SUSPEND 1313 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1314 sizeof(*gpio_dev->saved_regs), 1315 GFP_KERNEL); 1316 if (!gpio_dev->saved_regs) 1317 return -ENOMEM; 1318 #endif 1319 1320 gpio_dev->pdev = pdev; 1321 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1322 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1323 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1324 gpio_dev->gc.get = amd_gpio_get_value; 1325 gpio_dev->gc.set = amd_gpio_set_value; 1326 gpio_dev->gc.set_config = amd_gpio_set_config; 1327 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1328 1329 gpio_dev->gc.base = -1; 1330 gpio_dev->gc.label = pdev->name; 1331 gpio_dev->gc.owner = THIS_MODULE; 1332 gpio_dev->gc.parent = &pdev->dev; 1333 gpio_dev->gc.ngpio = resource_size(res) / 4; 1334 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1335 if (gpio_dev->base_rgpio) { 1336 gpio_dev->gc.ngpio += AMD_GPIO_PINS_BANK4; 1337 gpio_dev->hwbank_num++; 1338 } 1339 gpio_dev->groups = kerncz_groups; 1340 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1341 1342 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1343 gpio_dev->iomux_base = amd_get_named_res(&pdev->dev, pdev, "iomux", 0); 1344 if (!gpio_dev->iomux_base && !gpio_dev->base_rgpio) 1345 amd_pinctrl_desc.pmxops = NULL; 1346 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1347 gpio_dev); 1348 if (IS_ERR(gpio_dev->pctrl)) { 1349 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1350 return PTR_ERR(gpio_dev->pctrl); 1351 } 1352 1353 /* Disable and mask interrupts */ 1354 amd_gpio_irq_init(gpio_dev); 1355 1356 girq = &gpio_dev->gc.irq; 1357 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1358 /* This will let us handle the parent IRQ in the driver */ 1359 girq->parent_handler = NULL; 1360 girq->num_parents = 0; 1361 girq->parents = NULL; 1362 girq->default_type = IRQ_TYPE_NONE; 1363 girq->handler = handle_simple_irq; 1364 1365 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1366 if (ret) 1367 return ret; 1368 1369 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1370 0, 0, gpio_dev->gc.ngpio); 1371 if (ret) { 1372 dev_err(&pdev->dev, "Failed to add pin range\n"); 1373 goto out2; 1374 } 1375 1376 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1377 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev); 1378 if (ret) 1379 goto out2; 1380 1381 platform_set_drvdata(pdev, gpio_dev); 1382 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1383 amd_gpio_register_s2idle_ops(); 1384 1385 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1386 return ret; 1387 1388 out2: 1389 gpiochip_remove(&gpio_dev->gc); 1390 1391 return ret; 1392 } 1393 1394 static void amd_gpio_remove(struct platform_device *pdev) 1395 { 1396 struct amd_gpio *gpio_dev; 1397 1398 gpio_dev = platform_get_drvdata(pdev); 1399 1400 gpiochip_remove(&gpio_dev->gc); 1401 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1402 amd_gpio_unregister_s2idle_ops(); 1403 } 1404 1405 #ifdef CONFIG_ACPI 1406 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1407 { "AMD0030", 0 }, 1408 { "AMDI0030", 0}, 1409 { "AMDI0031", 0}, 1410 { "AMDI0033", 0}, 1411 { }, 1412 }; 1413 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1414 #endif 1415 1416 static struct platform_driver amd_gpio_driver = { 1417 .driver = { 1418 .name = "amd_gpio", 1419 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1420 #ifdef CONFIG_PM_SLEEP 1421 .pm = &amd_gpio_pm_ops, 1422 #endif 1423 }, 1424 .probe = amd_gpio_probe, 1425 .remove = amd_gpio_remove, 1426 }; 1427 1428 module_platform_driver(amd_gpio_driver); 1429 1430 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1431 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1432