xref: /linux/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c (revision 91ec2035134982b98fab0609a9fd8480e8217dc1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3   STMMAC Ethtool support
4 
5   Copyright (C) 2007-2009  STMicroelectronics Ltd
6 
7 
8   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10 
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/mii.h>
16 #include <linux/phylink.h>
17 #include <linux/net_tstamp.h>
18 
19 #include "stmmac.h"
20 #include "stmmac_fpe.h"
21 #include "dwmac_dma.h"
22 #include "dwxgmac2.h"
23 
24 #define REG_SPACE_SIZE	0x1060
25 #define GMAC4_REG_SPACE_SIZE	0x116C
26 #define MAC100_ETHTOOL_NAME	"st_mac100"
27 #define GMAC_ETHTOOL_NAME	"st_gmac"
28 #define XGMAC_ETHTOOL_NAME	"st_xgmac"
29 
30 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
31  *
32  * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
33  * same time due to the conflicting macro names.
34  */
35 #define GMAC4_DMA_CHAN_BASE_ADDR  0x00001100
36 
37 #define ETHTOOL_DMA_OFFSET	55
38 
39 struct stmmac_stats {
40 	char stat_string[ETH_GSTRING_LEN] __nonstring;
41 	int sizeof_stat;
42 	int stat_offset;
43 };
44 
45 #define STMMAC_STAT(m)	\
46 	{ #m, sizeof_field(struct stmmac_extra_stats, m),	\
47 	offsetof(struct stmmac_priv, xstats.m)}
48 
49 static const struct stmmac_stats stmmac_gstrings_stats[] = {
50 	/* Transmit errors */
51 	STMMAC_STAT(tx_underflow),
52 	STMMAC_STAT(tx_carrier),
53 	STMMAC_STAT(tx_losscarrier),
54 	STMMAC_STAT(vlan_tag),
55 	STMMAC_STAT(tx_deferred),
56 	STMMAC_STAT(tx_vlan),
57 	STMMAC_STAT(tx_jabber),
58 	STMMAC_STAT(tx_frame_flushed),
59 	STMMAC_STAT(tx_payload_error),
60 	STMMAC_STAT(tx_ip_header_error),
61 	/* Receive errors */
62 	STMMAC_STAT(rx_desc),
63 	STMMAC_STAT(sa_filter_fail),
64 	STMMAC_STAT(overflow_error),
65 	STMMAC_STAT(ipc_csum_error),
66 	STMMAC_STAT(rx_collision),
67 	STMMAC_STAT(rx_crc_errors),
68 	STMMAC_STAT(dribbling_bit),
69 	STMMAC_STAT(rx_length),
70 	STMMAC_STAT(rx_mii),
71 	STMMAC_STAT(rx_multicast),
72 	STMMAC_STAT(rx_gmac_overflow),
73 	STMMAC_STAT(rx_watchdog),
74 	STMMAC_STAT(da_rx_filter_fail),
75 	STMMAC_STAT(sa_rx_filter_fail),
76 	STMMAC_STAT(rx_missed_cntr),
77 	STMMAC_STAT(rx_overflow_cntr),
78 	STMMAC_STAT(rx_vlan),
79 	STMMAC_STAT(rx_split_hdr_pkt_n),
80 	/* Tx/Rx IRQ error info */
81 	STMMAC_STAT(tx_undeflow_irq),
82 	STMMAC_STAT(tx_process_stopped_irq),
83 	STMMAC_STAT(tx_jabber_irq),
84 	STMMAC_STAT(rx_overflow_irq),
85 	STMMAC_STAT(rx_buf_unav_irq),
86 	STMMAC_STAT(rx_process_stopped_irq),
87 	STMMAC_STAT(rx_watchdog_irq),
88 	STMMAC_STAT(tx_early_irq),
89 	STMMAC_STAT(fatal_bus_error_irq),
90 	/* Tx/Rx IRQ Events */
91 	STMMAC_STAT(rx_early_irq),
92 	STMMAC_STAT(threshold),
93 	STMMAC_STAT(irq_receive_pmt_irq_n),
94 	/* MMC info */
95 	STMMAC_STAT(mmc_tx_irq_n),
96 	STMMAC_STAT(mmc_rx_irq_n),
97 	STMMAC_STAT(mmc_rx_csum_offload_irq_n),
98 	/* EEE */
99 	STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
100 	STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
101 	STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
102 	STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
103 	STMMAC_STAT(phy_eee_wakeup_error_n),
104 	/* Extended RDES status */
105 	STMMAC_STAT(ip_hdr_err),
106 	STMMAC_STAT(ip_payload_err),
107 	STMMAC_STAT(ip_csum_bypassed),
108 	STMMAC_STAT(ipv4_pkt_rcvd),
109 	STMMAC_STAT(ipv6_pkt_rcvd),
110 	STMMAC_STAT(no_ptp_rx_msg_type_ext),
111 	STMMAC_STAT(ptp_rx_msg_type_sync),
112 	STMMAC_STAT(ptp_rx_msg_type_follow_up),
113 	STMMAC_STAT(ptp_rx_msg_type_delay_req),
114 	STMMAC_STAT(ptp_rx_msg_type_delay_resp),
115 	STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
116 	STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
117 	STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
118 	STMMAC_STAT(ptp_rx_msg_type_announce),
119 	STMMAC_STAT(ptp_rx_msg_type_management),
120 	STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
121 	STMMAC_STAT(ptp_frame_type),
122 	STMMAC_STAT(ptp_ver),
123 	STMMAC_STAT(timestamp_dropped),
124 	STMMAC_STAT(av_pkt_rcvd),
125 	STMMAC_STAT(av_tagged_pkt_rcvd),
126 	STMMAC_STAT(vlan_tag_priority_val),
127 	STMMAC_STAT(l3_filter_match),
128 	STMMAC_STAT(l4_filter_match),
129 	STMMAC_STAT(l3_l4_filter_no_match),
130 	/* PCS */
131 	STMMAC_STAT(irq_pcs_ane_n),
132 	STMMAC_STAT(irq_pcs_link_n),
133 	STMMAC_STAT(irq_rgmii_n),
134 	/* DEBUG */
135 	STMMAC_STAT(mtl_tx_status_fifo_full),
136 	STMMAC_STAT(mtl_tx_fifo_not_empty),
137 	STMMAC_STAT(mmtl_fifo_ctrl),
138 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
139 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
140 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
141 	STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
142 	STMMAC_STAT(mac_tx_in_pause),
143 	STMMAC_STAT(mac_tx_frame_ctrl_xfer),
144 	STMMAC_STAT(mac_tx_frame_ctrl_idle),
145 	STMMAC_STAT(mac_tx_frame_ctrl_wait),
146 	STMMAC_STAT(mac_tx_frame_ctrl_pause),
147 	STMMAC_STAT(mac_gmii_tx_proto_engine),
148 	STMMAC_STAT(mtl_rx_fifo_fill_level_full),
149 	STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
150 	STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
151 	STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
152 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
153 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
154 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
155 	STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
156 	STMMAC_STAT(mtl_rx_fifo_ctrl_active),
157 	STMMAC_STAT(mac_rx_frame_ctrl_fifo),
158 	STMMAC_STAT(mac_gmii_rx_proto_engine),
159 	/* EST */
160 	STMMAC_STAT(mtl_est_cgce),
161 	STMMAC_STAT(mtl_est_hlbs),
162 	STMMAC_STAT(mtl_est_hlbf),
163 	STMMAC_STAT(mtl_est_btre),
164 	STMMAC_STAT(mtl_est_btrlm),
165 };
166 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
167 
168 /* statistics collected in queue which will be summed up for all TX or RX
169  * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n).
170  */
171 static const char stmmac_qstats_string[][ETH_GSTRING_LEN] = {
172 	"rx_pkt_n",
173 	"rx_normal_irq_n",
174 	"tx_pkt_n",
175 	"tx_normal_irq_n",
176 	"tx_clean",
177 	"tx_set_ic_bit",
178 	"tx_tso_frames",
179 	"tx_tso_nfrags",
180 	"normal_irq_n",
181 	"napi_poll",
182 };
183 #define STMMAC_QSTATS ARRAY_SIZE(stmmac_qstats_string)
184 
185 /* HW MAC Management counters (if supported) */
186 #define STMMAC_MMC_STAT(m)	\
187 	{ #m, sizeof_field(struct stmmac_counters, m),	\
188 	offsetof(struct stmmac_priv, mmc.m)}
189 
190 static const struct stmmac_stats stmmac_mmc[] = {
191 	STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
192 	STMMAC_MMC_STAT(mmc_tx_framecount_gb),
193 	STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
194 	STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
195 	STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
196 	STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
197 	STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
198 	STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
199 	STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
200 	STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
201 	STMMAC_MMC_STAT(mmc_tx_unicast_gb),
202 	STMMAC_MMC_STAT(mmc_tx_multicast_gb),
203 	STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
204 	STMMAC_MMC_STAT(mmc_tx_underflow_error),
205 	STMMAC_MMC_STAT(mmc_tx_singlecol_g),
206 	STMMAC_MMC_STAT(mmc_tx_multicol_g),
207 	STMMAC_MMC_STAT(mmc_tx_deferred),
208 	STMMAC_MMC_STAT(mmc_tx_latecol),
209 	STMMAC_MMC_STAT(mmc_tx_exesscol),
210 	STMMAC_MMC_STAT(mmc_tx_carrier_error),
211 	STMMAC_MMC_STAT(mmc_tx_octetcount_g),
212 	STMMAC_MMC_STAT(mmc_tx_framecount_g),
213 	STMMAC_MMC_STAT(mmc_tx_excessdef),
214 	STMMAC_MMC_STAT(mmc_tx_pause_frame),
215 	STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
216 	STMMAC_MMC_STAT(mmc_tx_oversize_g),
217 	STMMAC_MMC_STAT(mmc_tx_lpi_usec),
218 	STMMAC_MMC_STAT(mmc_tx_lpi_tran),
219 	STMMAC_MMC_STAT(mmc_rx_framecount_gb),
220 	STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
221 	STMMAC_MMC_STAT(mmc_rx_octetcount_g),
222 	STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
223 	STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
224 	STMMAC_MMC_STAT(mmc_rx_crc_error),
225 	STMMAC_MMC_STAT(mmc_rx_align_error),
226 	STMMAC_MMC_STAT(mmc_rx_run_error),
227 	STMMAC_MMC_STAT(mmc_rx_jabber_error),
228 	STMMAC_MMC_STAT(mmc_rx_undersize_g),
229 	STMMAC_MMC_STAT(mmc_rx_oversize_g),
230 	STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
231 	STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
232 	STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
233 	STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
234 	STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
235 	STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
236 	STMMAC_MMC_STAT(mmc_rx_unicast_g),
237 	STMMAC_MMC_STAT(mmc_rx_length_error),
238 	STMMAC_MMC_STAT(mmc_rx_autofrangetype),
239 	STMMAC_MMC_STAT(mmc_rx_pause_frames),
240 	STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
241 	STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
242 	STMMAC_MMC_STAT(mmc_rx_watchdog_error),
243 	STMMAC_MMC_STAT(mmc_rx_error),
244 	STMMAC_MMC_STAT(mmc_rx_lpi_usec),
245 	STMMAC_MMC_STAT(mmc_rx_lpi_tran),
246 	STMMAC_MMC_STAT(mmc_rx_discard_frames_gb),
247 	STMMAC_MMC_STAT(mmc_rx_discard_octets_gb),
248 	STMMAC_MMC_STAT(mmc_rx_align_err_frames),
249 	STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
250 	STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
251 	STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
252 	STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
253 	STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
254 	STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
255 	STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
256 	STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
257 	STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
258 	STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
259 	STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
260 	STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
261 	STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
262 	STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
263 	STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
264 	STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
265 	STMMAC_MMC_STAT(mmc_rx_udp_gd),
266 	STMMAC_MMC_STAT(mmc_rx_udp_err),
267 	STMMAC_MMC_STAT(mmc_rx_tcp_gd),
268 	STMMAC_MMC_STAT(mmc_rx_tcp_err),
269 	STMMAC_MMC_STAT(mmc_rx_icmp_gd),
270 	STMMAC_MMC_STAT(mmc_rx_icmp_err),
271 	STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
272 	STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
273 	STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
274 	STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
275 	STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
276 	STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
277 	STMMAC_MMC_STAT(mmc_sgf_pass_fragment_cntr),
278 	STMMAC_MMC_STAT(mmc_sgf_fail_fragment_cntr),
279 	STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
280 	STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
281 	STMMAC_MMC_STAT(mmc_tx_gate_overrun_cntr),
282 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
283 	STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
284 	STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
285 	STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
286 };
287 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
288 
289 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = {
290 	"tx_pkt_n",
291 	"tx_irq_n",
292 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string)
293 };
294 
295 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = {
296 	"rx_pkt_n",
297 	"rx_irq_n",
298 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string)
299 };
300 
stmmac_ethtool_getdrvinfo(struct net_device * dev,struct ethtool_drvinfo * info)301 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
302 				      struct ethtool_drvinfo *info)
303 {
304 	struct stmmac_priv *priv = netdev_priv(dev);
305 
306 	if (priv->plat->core_type == DWMAC_CORE_GMAC ||
307 	    priv->plat->core_type == DWMAC_CORE_GMAC4)
308 		strscpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
309 	else if (priv->plat->core_type == DWMAC_CORE_XGMAC)
310 		strscpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
311 	else
312 		strscpy(info->driver, MAC100_ETHTOOL_NAME,
313 			sizeof(info->driver));
314 
315 	if (priv->plat->provide_bus_info)
316 		strscpy(info->bus_info, dev_name(priv->device),
317 			sizeof(info->bus_info));
318 }
319 
stmmac_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)320 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
321 					     struct ethtool_link_ksettings *cmd)
322 {
323 	struct stmmac_priv *priv = netdev_priv(dev);
324 
325 	return phylink_ethtool_ksettings_get(priv->phylink, cmd);
326 }
327 
328 static int
stmmac_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)329 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
330 				  const struct ethtool_link_ksettings *cmd)
331 {
332 	struct stmmac_priv *priv = netdev_priv(dev);
333 
334 	return phylink_ethtool_ksettings_set(priv->phylink, cmd);
335 }
336 
stmmac_ethtool_getmsglevel(struct net_device * dev)337 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
338 {
339 	struct stmmac_priv *priv = netdev_priv(dev);
340 	return priv->msg_enable;
341 }
342 
stmmac_ethtool_setmsglevel(struct net_device * dev,u32 level)343 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
344 {
345 	struct stmmac_priv *priv = netdev_priv(dev);
346 	priv->msg_enable = level;
347 
348 }
349 
stmmac_ethtool_get_regs_len(struct net_device * dev)350 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
351 {
352 	struct stmmac_priv *priv = netdev_priv(dev);
353 
354 	if (priv->plat->core_type == DWMAC_CORE_XGMAC)
355 		return XGMAC_REGSIZE * 4;
356 	else if (priv->plat->core_type == DWMAC_CORE_GMAC4)
357 		return GMAC4_REG_SPACE_SIZE;
358 	return REG_SPACE_SIZE;
359 }
360 
stmmac_ethtool_gregs(struct net_device * dev,struct ethtool_regs * regs,void * space)361 static void stmmac_ethtool_gregs(struct net_device *dev,
362 			  struct ethtool_regs *regs, void *space)
363 {
364 	struct stmmac_priv *priv = netdev_priv(dev);
365 	u32 *reg_space = (u32 *) space;
366 
367 	stmmac_dump_mac_regs(priv, priv->hw, reg_space);
368 	stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
369 
370 	/* Copy DMA registers to where ethtool expects them */
371 	if (priv->plat->core_type == DWMAC_CORE_GMAC4) {
372 		/* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
373 		memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
374 		       &reg_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
375 		       NUM_DWMAC4_DMA_REGS * 4);
376 	} else if (priv->plat->core_type != DWMAC_CORE_XGMAC) {
377 		memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
378 		       &reg_space[DMA_BUS_MODE / 4],
379 		       NUM_DWMAC1000_DMA_REGS * 4);
380 	}
381 }
382 
stmmac_nway_reset(struct net_device * dev)383 static int stmmac_nway_reset(struct net_device *dev)
384 {
385 	struct stmmac_priv *priv = netdev_priv(dev);
386 
387 	return phylink_ethtool_nway_reset(priv->phylink);
388 }
389 
stmmac_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)390 static void stmmac_get_ringparam(struct net_device *netdev,
391 				 struct ethtool_ringparam *ring,
392 				 struct kernel_ethtool_ringparam *kernel_ring,
393 				 struct netlink_ext_ack *extack)
394 {
395 	struct stmmac_priv *priv = netdev_priv(netdev);
396 
397 	ring->rx_max_pending = DMA_MAX_RX_SIZE;
398 	ring->tx_max_pending = DMA_MAX_TX_SIZE;
399 	ring->rx_pending = priv->dma_conf.dma_rx_size;
400 	ring->tx_pending = priv->dma_conf.dma_tx_size;
401 }
402 
stmmac_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)403 static int stmmac_set_ringparam(struct net_device *netdev,
404 				struct ethtool_ringparam *ring,
405 				struct kernel_ethtool_ringparam *kernel_ring,
406 				struct netlink_ext_ack *extack)
407 {
408 	if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
409 	    ring->rx_pending < DMA_MIN_RX_SIZE ||
410 	    ring->rx_pending > DMA_MAX_RX_SIZE ||
411 	    !is_power_of_2(ring->rx_pending) ||
412 	    ring->tx_pending < DMA_MIN_TX_SIZE ||
413 	    ring->tx_pending > DMA_MAX_TX_SIZE ||
414 	    !is_power_of_2(ring->tx_pending))
415 		return -EINVAL;
416 
417 	return stmmac_reinit_ringparam(netdev, ring->rx_pending,
418 				       ring->tx_pending);
419 }
420 
421 static void
stmmac_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)422 stmmac_get_pauseparam(struct net_device *netdev,
423 		      struct ethtool_pauseparam *pause)
424 {
425 	struct stmmac_priv *priv = netdev_priv(netdev);
426 
427 	phylink_ethtool_get_pauseparam(priv->phylink, pause);
428 }
429 
430 static int
stmmac_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)431 stmmac_set_pauseparam(struct net_device *netdev,
432 		      struct ethtool_pauseparam *pause)
433 {
434 	struct stmmac_priv *priv = netdev_priv(netdev);
435 
436 	return phylink_ethtool_set_pauseparam(priv->phylink, pause);
437 }
438 
stmmac_get_rx_normal_irq_n(struct stmmac_priv * priv,int q)439 static u64 stmmac_get_rx_normal_irq_n(struct stmmac_priv *priv, int q)
440 {
441 	u64 total;
442 	int cpu;
443 
444 	total = 0;
445 	for_each_possible_cpu(cpu) {
446 		struct stmmac_pcpu_stats *pcpu;
447 		unsigned int start;
448 		u64 irq_n;
449 
450 		pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu);
451 		do {
452 			start = u64_stats_fetch_begin(&pcpu->syncp);
453 			irq_n = u64_stats_read(&pcpu->rx_normal_irq_n[q]);
454 		} while (u64_stats_fetch_retry(&pcpu->syncp, start));
455 		total += irq_n;
456 	}
457 	return total;
458 }
459 
stmmac_get_tx_normal_irq_n(struct stmmac_priv * priv,int q)460 static u64 stmmac_get_tx_normal_irq_n(struct stmmac_priv *priv, int q)
461 {
462 	u64 total;
463 	int cpu;
464 
465 	total = 0;
466 	for_each_possible_cpu(cpu) {
467 		struct stmmac_pcpu_stats *pcpu;
468 		unsigned int start;
469 		u64 irq_n;
470 
471 		pcpu = per_cpu_ptr(priv->xstats.pcpu_stats, cpu);
472 		do {
473 			start = u64_stats_fetch_begin(&pcpu->syncp);
474 			irq_n = u64_stats_read(&pcpu->tx_normal_irq_n[q]);
475 		} while (u64_stats_fetch_retry(&pcpu->syncp, start));
476 		total += irq_n;
477 	}
478 	return total;
479 }
480 
stmmac_get_per_qstats(struct stmmac_priv * priv,u64 * data)481 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)
482 {
483 	u32 tx_cnt = priv->plat->tx_queues_to_use;
484 	u32 rx_cnt = priv->plat->rx_queues_to_use;
485 	unsigned int start;
486 	int q;
487 
488 	for (q = 0; q < tx_cnt; q++) {
489 		struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
490 		u64 pkt_n;
491 
492 		do {
493 			start = u64_stats_fetch_begin(&txq_stats->napi_syncp);
494 			pkt_n = u64_stats_read(&txq_stats->napi.tx_pkt_n);
495 		} while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start));
496 
497 		*data++ = pkt_n;
498 		*data++ = stmmac_get_tx_normal_irq_n(priv, q);
499 	}
500 
501 	for (q = 0; q < rx_cnt; q++) {
502 		struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[q];
503 		u64 pkt_n;
504 
505 		do {
506 			start = u64_stats_fetch_begin(&rxq_stats->napi_syncp);
507 			pkt_n = u64_stats_read(&rxq_stats->napi.rx_pkt_n);
508 		} while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start));
509 
510 		*data++ = pkt_n;
511 		*data++ = stmmac_get_rx_normal_irq_n(priv, q);
512 	}
513 }
514 
stmmac_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * dummy,u64 * data)515 static void stmmac_get_ethtool_stats(struct net_device *dev,
516 				 struct ethtool_stats *dummy, u64 *data)
517 {
518 	struct stmmac_priv *priv = netdev_priv(dev);
519 	u32 rx_queues_count = priv->plat->rx_queues_to_use;
520 	u32 tx_queues_count = priv->plat->tx_queues_to_use;
521 	u64 napi_poll = 0, normal_irq_n = 0;
522 	int i, j = 0, pos, ret;
523 	unsigned long count;
524 	unsigned int start;
525 
526 	if (priv->dma_cap.asp) {
527 		for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
528 			if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
529 						&count, NULL))
530 				data[j++] = count;
531 		}
532 	}
533 
534 	/* Update the DMA HW counters for dwmac10/100 */
535 	ret = stmmac_dma_diagnostic_fr(priv, &priv->xstats, priv->ioaddr);
536 	if (ret) {
537 		/* If supported, for new GMAC chips expose the MMC counters */
538 		if (priv->dma_cap.rmon) {
539 			stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
540 
541 			for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
542 				char *p;
543 				p = (char *)priv + stmmac_mmc[i].stat_offset;
544 
545 				data[j++] = (stmmac_mmc[i].sizeof_stat ==
546 					     sizeof(u64)) ? (*(u64 *)p) :
547 					     (*(u32 *)p);
548 			}
549 		}
550 		if (priv->dma_cap.eee) {
551 			int val = phylink_get_eee_err(priv->phylink);
552 			if (val)
553 				priv->xstats.phy_eee_wakeup_error_n = val;
554 		}
555 
556 		if (priv->synopsys_id >= DWMAC_CORE_3_50)
557 			stmmac_mac_debug(priv, priv->ioaddr,
558 					(void *)&priv->xstats,
559 					rx_queues_count, tx_queues_count);
560 	}
561 	for (i = 0; i < STMMAC_STATS_LEN; i++) {
562 		char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
563 		data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
564 			     sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
565 	}
566 
567 	pos = j;
568 	for (i = 0; i < rx_queues_count; i++) {
569 		struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[i];
570 		struct stmmac_napi_rx_stats snapshot;
571 		u64 n_irq;
572 
573 		j = pos;
574 		do {
575 			start = u64_stats_fetch_begin(&rxq_stats->napi_syncp);
576 			snapshot = rxq_stats->napi;
577 		} while (u64_stats_fetch_retry(&rxq_stats->napi_syncp, start));
578 
579 		data[j++] += u64_stats_read(&snapshot.rx_pkt_n);
580 		n_irq = stmmac_get_rx_normal_irq_n(priv, i);
581 		data[j++] += n_irq;
582 		normal_irq_n += n_irq;
583 		napi_poll += u64_stats_read(&snapshot.poll);
584 	}
585 
586 	pos = j;
587 	for (i = 0; i < tx_queues_count; i++) {
588 		struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[i];
589 		struct stmmac_napi_tx_stats napi_snapshot;
590 		struct stmmac_q_tx_stats q_snapshot;
591 		u64 n_irq;
592 
593 		j = pos;
594 		do {
595 			start = u64_stats_fetch_begin(&txq_stats->q_syncp);
596 			q_snapshot = txq_stats->q;
597 		} while (u64_stats_fetch_retry(&txq_stats->q_syncp, start));
598 		do {
599 			start = u64_stats_fetch_begin(&txq_stats->napi_syncp);
600 			napi_snapshot = txq_stats->napi;
601 		} while (u64_stats_fetch_retry(&txq_stats->napi_syncp, start));
602 
603 		data[j++] += u64_stats_read(&napi_snapshot.tx_pkt_n);
604 		n_irq = stmmac_get_tx_normal_irq_n(priv, i);
605 		data[j++] += n_irq;
606 		normal_irq_n += n_irq;
607 		data[j++] += u64_stats_read(&napi_snapshot.tx_clean);
608 		data[j++] += u64_stats_read(&q_snapshot.tx_set_ic_bit) +
609 			u64_stats_read(&napi_snapshot.tx_set_ic_bit);
610 		data[j++] += u64_stats_read(&q_snapshot.tx_tso_frames);
611 		data[j++] += u64_stats_read(&q_snapshot.tx_tso_nfrags);
612 		napi_poll += u64_stats_read(&napi_snapshot.poll);
613 	}
614 	normal_irq_n += priv->xstats.rx_early_irq;
615 	data[j++] = normal_irq_n;
616 	data[j++] = napi_poll;
617 
618 	stmmac_get_per_qstats(priv, &data[j]);
619 }
620 
stmmac_get_sset_count(struct net_device * netdev,int sset)621 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
622 {
623 	struct stmmac_priv *priv = netdev_priv(netdev);
624 	u32 tx_cnt = priv->plat->tx_queues_to_use;
625 	u32 rx_cnt = priv->plat->rx_queues_to_use;
626 	int i, len, safety_len = 0;
627 
628 	switch (sset) {
629 	case ETH_SS_STATS:
630 		len = STMMAC_STATS_LEN + STMMAC_QSTATS +
631 		      STMMAC_TXQ_STATS * tx_cnt +
632 		      STMMAC_RXQ_STATS * rx_cnt;
633 
634 		if (priv->dma_cap.rmon)
635 			len += STMMAC_MMC_STATS_LEN;
636 		if (priv->dma_cap.asp) {
637 			for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
638 				if (!stmmac_safety_feat_dump(priv,
639 							&priv->sstats, i,
640 							NULL, NULL))
641 					safety_len++;
642 			}
643 
644 			len += safety_len;
645 		}
646 
647 		return len;
648 	case ETH_SS_TEST:
649 		return stmmac_selftest_get_count(priv);
650 	default:
651 		return -EOPNOTSUPP;
652 	}
653 }
654 
stmmac_get_qstats_string(struct stmmac_priv * priv,u8 * data)655 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data)
656 {
657 	u32 tx_cnt = priv->plat->tx_queues_to_use;
658 	u32 rx_cnt = priv->plat->rx_queues_to_use;
659 	int q, stat;
660 
661 	for (q = 0; q < tx_cnt; q++) {
662 		for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
663 			snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
664 				 stmmac_qstats_tx_string[stat]);
665 			data += ETH_GSTRING_LEN;
666 		}
667 	}
668 	for (q = 0; q < rx_cnt; q++) {
669 		for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
670 			snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
671 				 stmmac_qstats_rx_string[stat]);
672 			data += ETH_GSTRING_LEN;
673 		}
674 	}
675 }
676 
stmmac_get_strings(struct net_device * dev,u32 stringset,u8 * data)677 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
678 {
679 	int i;
680 	u8 *p = data;
681 	struct stmmac_priv *priv = netdev_priv(dev);
682 
683 	switch (stringset) {
684 	case ETH_SS_STATS:
685 		if (priv->dma_cap.asp) {
686 			for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
687 				const char *desc;
688 				if (!stmmac_safety_feat_dump(priv,
689 							&priv->sstats, i,
690 							NULL, &desc)) {
691 					memcpy(p, desc, ETH_GSTRING_LEN);
692 					p += ETH_GSTRING_LEN;
693 				}
694 			}
695 		}
696 		if (priv->dma_cap.rmon)
697 			for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
698 				memcpy(p, stmmac_mmc[i].stat_string,
699 				       ETH_GSTRING_LEN);
700 				p += ETH_GSTRING_LEN;
701 			}
702 		for (i = 0; i < STMMAC_STATS_LEN; i++) {
703 			memcpy(p, stmmac_gstrings_stats[i].stat_string, ETH_GSTRING_LEN);
704 			p += ETH_GSTRING_LEN;
705 		}
706 		for (i = 0; i < STMMAC_QSTATS; i++) {
707 			memcpy(p, stmmac_qstats_string[i], ETH_GSTRING_LEN);
708 			p += ETH_GSTRING_LEN;
709 		}
710 		stmmac_get_qstats_string(priv, p);
711 		break;
712 	case ETH_SS_TEST:
713 		stmmac_selftest_get_strings(priv, p);
714 		break;
715 	default:
716 		WARN_ON(1);
717 		break;
718 	}
719 }
720 
721 /* Currently only support WOL through Magic packet. */
stmmac_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)722 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
723 {
724 	struct stmmac_priv *priv = netdev_priv(dev);
725 
726 	return phylink_ethtool_get_wol(priv->phylink, wol);
727 }
728 
stmmac_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)729 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
730 {
731 	struct stmmac_priv *priv = netdev_priv(dev);
732 
733 	return phylink_ethtool_set_wol(priv->phylink, wol);
734 }
735 
stmmac_ethtool_op_get_eee(struct net_device * dev,struct ethtool_keee * edata)736 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
737 				     struct ethtool_keee *edata)
738 {
739 	struct stmmac_priv *priv = netdev_priv(dev);
740 
741 	return phylink_ethtool_get_eee(priv->phylink, edata);
742 }
743 
stmmac_ethtool_op_set_eee(struct net_device * dev,struct ethtool_keee * edata)744 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
745 				     struct ethtool_keee *edata)
746 {
747 	struct stmmac_priv *priv = netdev_priv(dev);
748 
749 	return phylink_ethtool_set_eee(priv->phylink, edata);
750 }
751 
stmmac_usec2riwt(u32 usec,struct stmmac_priv * priv)752 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
753 {
754 	unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
755 
756 	if (!clk) {
757 		clk = priv->plat->clk_ref_rate;
758 		if (!clk)
759 			return 0;
760 	}
761 
762 	/* Receive Interrupt Watchdog Timer (riwt) has a resolution of 256
763 	 * ticks.
764 	 */
765 	return DIV_ROUND_CLOSEST(usec * (clk / USEC_PER_SEC), 256);
766 }
767 
stmmac_riwt2usec(u32 riwt,struct stmmac_priv * priv)768 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
769 {
770 	unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
771 
772 	if (!clk) {
773 		clk = priv->plat->clk_ref_rate;
774 		if (!clk)
775 			return 0;
776 	}
777 
778 	return DIV_ROUND_CLOSEST(riwt * 256, clk / USEC_PER_SEC);
779 }
780 
__stmmac_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,int queue)781 static int __stmmac_get_coalesce(struct net_device *dev,
782 				 struct ethtool_coalesce *ec,
783 				 int queue)
784 {
785 	struct stmmac_priv *priv = netdev_priv(dev);
786 	u32 max_cnt;
787 	u32 rx_cnt;
788 	u32 tx_cnt;
789 
790 	rx_cnt = priv->plat->rx_queues_to_use;
791 	tx_cnt = priv->plat->tx_queues_to_use;
792 	max_cnt = max(rx_cnt, tx_cnt);
793 
794 	if (queue < 0)
795 		queue = 0;
796 	else if (queue >= max_cnt)
797 		return -EINVAL;
798 
799 	if (queue < tx_cnt) {
800 		ec->tx_coalesce_usecs = priv->tx_coal_timer[queue];
801 		ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue];
802 	} else {
803 		ec->tx_coalesce_usecs = 0;
804 		ec->tx_max_coalesced_frames = 0;
805 	}
806 
807 	if (priv->use_riwt && queue < rx_cnt) {
808 		ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue];
809 		ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue],
810 							 priv);
811 	} else {
812 		ec->rx_max_coalesced_frames = 0;
813 		ec->rx_coalesce_usecs = 0;
814 	}
815 
816 	return 0;
817 }
818 
stmmac_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)819 static int stmmac_get_coalesce(struct net_device *dev,
820 			       struct ethtool_coalesce *ec,
821 			       struct kernel_ethtool_coalesce *kernel_coal,
822 			       struct netlink_ext_ack *extack)
823 {
824 	return __stmmac_get_coalesce(dev, ec, -1);
825 }
826 
stmmac_get_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * ec)827 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue,
828 					 struct ethtool_coalesce *ec)
829 {
830 	return __stmmac_get_coalesce(dev, ec, queue);
831 }
832 
__stmmac_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,int queue)833 static int __stmmac_set_coalesce(struct net_device *dev,
834 				 struct ethtool_coalesce *ec,
835 				 int queue)
836 {
837 	struct stmmac_priv *priv = netdev_priv(dev);
838 	bool all_queues = false;
839 	unsigned int rx_riwt;
840 	u32 max_cnt;
841 	u32 rx_cnt;
842 	u32 tx_cnt;
843 
844 	rx_cnt = priv->plat->rx_queues_to_use;
845 	tx_cnt = priv->plat->tx_queues_to_use;
846 	max_cnt = max(rx_cnt, tx_cnt);
847 
848 	if (queue < 0)
849 		all_queues = true;
850 	else if (queue >= max_cnt)
851 		return -EINVAL;
852 
853 	if (priv->use_riwt) {
854 		rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
855 
856 		if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
857 			return -EINVAL;
858 
859 		if (all_queues) {
860 			int i;
861 
862 			for (i = 0; i < rx_cnt; i++) {
863 				priv->rx_riwt[i] = rx_riwt;
864 				stmmac_rx_watchdog(priv, priv->ioaddr,
865 						   rx_riwt, i);
866 				priv->rx_coal_frames[i] =
867 					ec->rx_max_coalesced_frames;
868 			}
869 		} else if (queue < rx_cnt) {
870 			priv->rx_riwt[queue] = rx_riwt;
871 			stmmac_rx_watchdog(priv, priv->ioaddr,
872 					   rx_riwt, queue);
873 			priv->rx_coal_frames[queue] =
874 				ec->rx_max_coalesced_frames;
875 		}
876 	}
877 
878 	if ((ec->tx_coalesce_usecs == 0) &&
879 	    (ec->tx_max_coalesced_frames == 0))
880 		return -EINVAL;
881 
882 	if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
883 	    (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
884 		return -EINVAL;
885 
886 	if (all_queues) {
887 		int i;
888 
889 		for (i = 0; i < tx_cnt; i++) {
890 			priv->tx_coal_frames[i] =
891 				ec->tx_max_coalesced_frames;
892 			priv->tx_coal_timer[i] =
893 				ec->tx_coalesce_usecs;
894 		}
895 	} else if (queue < tx_cnt) {
896 		priv->tx_coal_frames[queue] =
897 			ec->tx_max_coalesced_frames;
898 		priv->tx_coal_timer[queue] =
899 			ec->tx_coalesce_usecs;
900 	}
901 
902 	return 0;
903 }
904 
stmmac_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)905 static int stmmac_set_coalesce(struct net_device *dev,
906 			       struct ethtool_coalesce *ec,
907 			       struct kernel_ethtool_coalesce *kernel_coal,
908 			       struct netlink_ext_ack *extack)
909 {
910 	return __stmmac_set_coalesce(dev, ec, -1);
911 }
912 
stmmac_set_per_queue_coalesce(struct net_device * dev,u32 queue,struct ethtool_coalesce * ec)913 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue,
914 					 struct ethtool_coalesce *ec)
915 {
916 	return __stmmac_set_coalesce(dev, ec, queue);
917 }
918 
stmmac_get_rx_ring_count(struct net_device * dev)919 static u32 stmmac_get_rx_ring_count(struct net_device *dev)
920 {
921 	struct stmmac_priv *priv = netdev_priv(dev);
922 
923 	return priv->plat->rx_queues_to_use;
924 }
925 
stmmac_get_rxfh_key_size(struct net_device * dev)926 static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
927 {
928 	struct stmmac_priv *priv = netdev_priv(dev);
929 
930 	return sizeof(priv->rss.key);
931 }
932 
stmmac_get_rxfh_indir_size(struct net_device * dev)933 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
934 {
935 	struct stmmac_priv *priv = netdev_priv(dev);
936 
937 	return ARRAY_SIZE(priv->rss.table);
938 }
939 
stmmac_get_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh)940 static int stmmac_get_rxfh(struct net_device *dev,
941 			   struct ethtool_rxfh_param *rxfh)
942 {
943 	struct stmmac_priv *priv = netdev_priv(dev);
944 	int i;
945 
946 	if (rxfh->indir) {
947 		for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
948 			rxfh->indir[i] = priv->rss.table[i];
949 	}
950 
951 	if (rxfh->key)
952 		memcpy(rxfh->key, priv->rss.key, sizeof(priv->rss.key));
953 	rxfh->hfunc = ETH_RSS_HASH_TOP;
954 
955 	return 0;
956 }
957 
stmmac_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)958 static int stmmac_set_rxfh(struct net_device *dev,
959 			   struct ethtool_rxfh_param *rxfh,
960 			   struct netlink_ext_ack *extack)
961 {
962 	struct stmmac_priv *priv = netdev_priv(dev);
963 	int i;
964 
965 	if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
966 	    rxfh->hfunc != ETH_RSS_HASH_TOP)
967 		return -EOPNOTSUPP;
968 
969 	if (rxfh->indir) {
970 		for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
971 			priv->rss.table[i] = rxfh->indir[i];
972 	}
973 
974 	if (rxfh->key)
975 		memcpy(priv->rss.key, rxfh->key, sizeof(priv->rss.key));
976 
977 	return stmmac_rss_configure(priv, priv->hw, &priv->rss,
978 				    priv->plat->rx_queues_to_use);
979 }
980 
stmmac_get_channels(struct net_device * dev,struct ethtool_channels * chan)981 static void stmmac_get_channels(struct net_device *dev,
982 				struct ethtool_channels *chan)
983 {
984 	struct stmmac_priv *priv = netdev_priv(dev);
985 
986 	chan->rx_count = priv->plat->rx_queues_to_use;
987 	chan->tx_count = priv->plat->tx_queues_to_use;
988 	chan->max_rx = priv->dma_cap.number_rx_queues;
989 	chan->max_tx = priv->dma_cap.number_tx_queues;
990 }
991 
stmmac_set_channels(struct net_device * dev,struct ethtool_channels * chan)992 static int stmmac_set_channels(struct net_device *dev,
993 			       struct ethtool_channels *chan)
994 {
995 	struct stmmac_priv *priv = netdev_priv(dev);
996 
997 	if (chan->rx_count > priv->dma_cap.number_rx_queues ||
998 	    chan->tx_count > priv->dma_cap.number_tx_queues ||
999 	    !chan->rx_count || !chan->tx_count)
1000 		return -EINVAL;
1001 
1002 	return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
1003 }
1004 
stmmac_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)1005 static int stmmac_get_ts_info(struct net_device *dev,
1006 			      struct kernel_ethtool_ts_info *info)
1007 {
1008 	struct stmmac_priv *priv = netdev_priv(dev);
1009 
1010 	if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
1011 
1012 		info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1013 					SOF_TIMESTAMPING_TX_HARDWARE |
1014 					SOF_TIMESTAMPING_RX_HARDWARE |
1015 					SOF_TIMESTAMPING_RAW_HARDWARE;
1016 
1017 		if (priv->ptp_clock)
1018 			info->phc_index = ptp_clock_index(priv->ptp_clock);
1019 		else
1020 			info->phc_index = 0;
1021 
1022 		info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1023 
1024 		info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
1025 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1026 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1027 				    (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1028 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1029 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1030 				    (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1031 				    (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1032 				    (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1033 				    (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
1034 				    (1 << HWTSTAMP_FILTER_ALL));
1035 		return 0;
1036 	} else
1037 		return ethtool_op_get_ts_info(dev, info);
1038 }
1039 
stmmac_get_mm(struct net_device * ndev,struct ethtool_mm_state * state)1040 static int stmmac_get_mm(struct net_device *ndev,
1041 			 struct ethtool_mm_state *state)
1042 {
1043 	struct stmmac_priv *priv = netdev_priv(ndev);
1044 	u32 frag_size;
1045 
1046 	if (!stmmac_fpe_supported(priv))
1047 		return -EOPNOTSUPP;
1048 
1049 	state->rx_min_frag_size = ETH_ZLEN;
1050 	frag_size = stmmac_fpe_get_add_frag_size(priv);
1051 	state->tx_min_frag_size = ethtool_mm_frag_size_add_to_min(frag_size);
1052 
1053 	ethtool_mmsv_get_mm(&priv->fpe_cfg.mmsv, state);
1054 
1055 	return 0;
1056 }
1057 
stmmac_set_mm(struct net_device * ndev,struct ethtool_mm_cfg * cfg,struct netlink_ext_ack * extack)1058 static int stmmac_set_mm(struct net_device *ndev, struct ethtool_mm_cfg *cfg,
1059 			 struct netlink_ext_ack *extack)
1060 {
1061 	struct stmmac_priv *priv = netdev_priv(ndev);
1062 	u32 frag_size;
1063 	int err;
1064 
1065 	err = ethtool_mm_frag_size_min_to_add(cfg->tx_min_frag_size,
1066 					      &frag_size, extack);
1067 	if (err)
1068 		return err;
1069 
1070 	stmmac_fpe_set_add_frag_size(priv, frag_size);
1071 	ethtool_mmsv_set_mm(&priv->fpe_cfg.mmsv, cfg);
1072 
1073 	return 0;
1074 }
1075 
stmmac_get_mm_stats(struct net_device * ndev,struct ethtool_mm_stats * s)1076 static void stmmac_get_mm_stats(struct net_device *ndev,
1077 				struct ethtool_mm_stats *s)
1078 {
1079 	struct stmmac_priv *priv = netdev_priv(ndev);
1080 	struct stmmac_counters *mmc = &priv->mmc;
1081 
1082 	if (!priv->dma_cap.rmon)
1083 		return;
1084 
1085 	stmmac_mmc_read(priv, priv->mmcaddr, mmc);
1086 
1087 	s->MACMergeFrameAssErrorCount = mmc->mmc_rx_packet_assembly_err_cntr;
1088 	s->MACMergeFrameAssOkCount = mmc->mmc_rx_packet_assembly_ok_cntr;
1089 	s->MACMergeFrameSmdErrorCount = mmc->mmc_rx_packet_smd_err_cntr;
1090 	s->MACMergeFragCountRx = mmc->mmc_rx_fpe_fragment_cntr;
1091 	s->MACMergeFragCountTx = mmc->mmc_tx_fpe_fragment_cntr;
1092 	s->MACMergeHoldCount = mmc->mmc_tx_hold_req_cntr;
1093 }
1094 
1095 static const struct ethtool_ops stmmac_ethtool_ops = {
1096 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1097 				     ETHTOOL_COALESCE_MAX_FRAMES,
1098 	.get_drvinfo = stmmac_ethtool_getdrvinfo,
1099 	.get_msglevel = stmmac_ethtool_getmsglevel,
1100 	.set_msglevel = stmmac_ethtool_setmsglevel,
1101 	.get_regs = stmmac_ethtool_gregs,
1102 	.get_regs_len = stmmac_ethtool_get_regs_len,
1103 	.get_link = ethtool_op_get_link,
1104 	.nway_reset = stmmac_nway_reset,
1105 	.get_ringparam = stmmac_get_ringparam,
1106 	.set_ringparam = stmmac_set_ringparam,
1107 	.get_pauseparam = stmmac_get_pauseparam,
1108 	.set_pauseparam = stmmac_set_pauseparam,
1109 	.self_test = stmmac_selftest_run,
1110 	.get_ethtool_stats = stmmac_get_ethtool_stats,
1111 	.get_strings = stmmac_get_strings,
1112 	.get_wol = stmmac_get_wol,
1113 	.set_wol = stmmac_set_wol,
1114 	.get_eee = stmmac_ethtool_op_get_eee,
1115 	.set_eee = stmmac_ethtool_op_set_eee,
1116 	.get_sset_count	= stmmac_get_sset_count,
1117 	.get_rx_ring_count = stmmac_get_rx_ring_count,
1118 	.get_rxfh_key_size = stmmac_get_rxfh_key_size,
1119 	.get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1120 	.get_rxfh = stmmac_get_rxfh,
1121 	.set_rxfh = stmmac_set_rxfh,
1122 	.get_ts_info = stmmac_get_ts_info,
1123 	.get_coalesce = stmmac_get_coalesce,
1124 	.set_coalesce = stmmac_set_coalesce,
1125 	.get_per_queue_coalesce = stmmac_get_per_queue_coalesce,
1126 	.set_per_queue_coalesce = stmmac_set_per_queue_coalesce,
1127 	.get_channels = stmmac_get_channels,
1128 	.set_channels = stmmac_set_channels,
1129 	.get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1130 	.set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1131 	.get_mm = stmmac_get_mm,
1132 	.set_mm = stmmac_set_mm,
1133 	.get_mm_stats = stmmac_get_mm_stats,
1134 };
1135 
stmmac_set_ethtool_ops(struct net_device * netdev)1136 void stmmac_set_ethtool_ops(struct net_device *netdev)
1137 {
1138 	netdev->ethtool_ops = &stmmac_ethtool_ops;
1139 }
1140