1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 */
6 #include <linux/of.h>
7 #include <linux/of_net.h>
8 #include <linux/of_reserved_mem.h>
9 #include <linux/platform_device.h>
10 #include <linux/tcp.h>
11 #include <linux/u64_stats_sync.h>
12 #include <net/dst_metadata.h>
13 #include <net/page_pool/helpers.h>
14 #include <net/pkt_cls.h>
15 #include <uapi/linux/ppp_defs.h>
16
17 #include "airoha_regs.h"
18 #include "airoha_eth.h"
19
airoha_rr(void __iomem * base,u32 offset)20 u32 airoha_rr(void __iomem *base, u32 offset)
21 {
22 return readl(base + offset);
23 }
24
airoha_wr(void __iomem * base,u32 offset,u32 val)25 void airoha_wr(void __iomem *base, u32 offset, u32 val)
26 {
27 writel(val, base + offset);
28 }
29
airoha_rmw(void __iomem * base,u32 offset,u32 mask,u32 val)30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
31 {
32 val |= (airoha_rr(base, offset) & ~mask);
33 airoha_wr(base, offset, val);
34
35 return val;
36 }
37
airoha_qdma_set_irqmask(struct airoha_irq_bank * irq_bank,int index,u32 clear,u32 set)38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank,
39 int index, u32 clear, u32 set)
40 {
41 struct airoha_qdma *qdma = irq_bank->qdma;
42 int bank = irq_bank - &qdma->irq_banks[0];
43 unsigned long flags;
44
45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask)))
46 return;
47
48 spin_lock_irqsave(&irq_bank->irq_lock, flags);
49
50 irq_bank->irqmask[index] &= ~clear;
51 irq_bank->irqmask[index] |= set;
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index),
53 irq_bank->irqmask[index]);
54 /* Read irq_enable register in order to guarantee the update above
55 * completes in the spinlock critical section.
56 */
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index));
58
59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags);
60 }
61
airoha_qdma_irq_enable(struct airoha_irq_bank * irq_bank,int index,u32 mask)62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank,
63 int index, u32 mask)
64 {
65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask);
66 }
67
airoha_qdma_irq_disable(struct airoha_irq_bank * irq_bank,int index,u32 mask)68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank,
69 int index, u32 mask)
70 {
71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0);
72 }
73
airoha_set_macaddr(struct airoha_gdm_port * port,const u8 * addr)74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr)
75 {
76 struct airoha_eth *eth = port->qdma->eth;
77 u32 val, reg;
78
79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H
80 : REG_FE_WAN_MAC_H;
81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2];
82 airoha_fe_wr(eth, reg, val);
83
84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5];
85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val);
86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val);
87
88 airoha_ppe_init_upd_mem(port);
89 }
90
airoha_set_gdm_port_fwd_cfg(struct airoha_eth * eth,u32 addr,u32 val)91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr,
92 u32 val)
93 {
94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK,
95 FIELD_PREP(GDM_OCFQ_MASK, val));
96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK,
97 FIELD_PREP(GDM_MCFQ_MASK, val));
98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK,
99 FIELD_PREP(GDM_BCFQ_MASK, val));
100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK,
101 FIELD_PREP(GDM_UCFQ_MASK, val));
102 }
103
airoha_set_vip_for_gdm_port(struct airoha_gdm_port * port,bool enable)104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port,
105 bool enable)
106 {
107 struct airoha_eth *eth = port->qdma->eth;
108 u32 vip_port;
109
110 switch (port->id) {
111 case 3:
112 /* FIXME: handle XSI_PCIE1_PORT */
113 vip_port = XSI_PCIE0_VIP_PORT_MASK;
114 break;
115 case 4:
116 /* FIXME: handle XSI_USB_PORT */
117 vip_port = XSI_ETH_VIP_PORT_MASK;
118 break;
119 default:
120 return 0;
121 }
122
123 if (enable) {
124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);
125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);
126 } else {
127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port);
128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port);
129 }
130
131 return 0;
132 }
133
airoha_fe_maccr_init(struct airoha_eth * eth)134 static void airoha_fe_maccr_init(struct airoha_eth *eth)
135 {
136 int p;
137
138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++)
139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p),
140 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM |
141 GDM_DROP_CRC_ERR);
142
143 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK,
144 FIELD_PREP(CDM1_VLAN_MASK, 0x8100));
145
146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD);
147 }
148
airoha_fe_vip_setup(struct airoha_eth * eth)149 static void airoha_fe_vip_setup(struct airoha_eth *eth)
150 {
151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC);
152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK);
153
154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP);
155 airoha_fe_wr(eth, REG_FE_VIP_EN(4),
156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
157 PATN_EN_MASK);
158
159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP);
160 airoha_fe_wr(eth, REG_FE_VIP_EN(6),
161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
162 PATN_EN_MASK);
163
164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP);
165 airoha_fe_wr(eth, REG_FE_VIP_EN(7),
166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
167 PATN_EN_MASK);
168
169 /* BOOTP (0x43) */
170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43);
171 airoha_fe_wr(eth, REG_FE_VIP_EN(8),
172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |
173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
174
175 /* BOOTP (0x44) */
176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44);
177 airoha_fe_wr(eth, REG_FE_VIP_EN(9),
178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK |
179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
180
181 /* ISAKMP */
182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4);
183 airoha_fe_wr(eth, REG_FE_VIP_EN(10),
184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |
185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
186
187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP);
188 airoha_fe_wr(eth, REG_FE_VIP_EN(11),
189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
190 PATN_EN_MASK);
191
192 /* DHCPv6 */
193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223);
194 airoha_fe_wr(eth, REG_FE_VIP_EN(12),
195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK |
196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK);
197
198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP);
199 airoha_fe_wr(eth, REG_FE_VIP_EN(19),
200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) |
201 PATN_EN_MASK);
202
203 /* ETH->ETH_P_1905 (0x893a) */
204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a);
205 airoha_fe_wr(eth, REG_FE_VIP_EN(20),
206 PATN_FCPU_EN_MASK | PATN_EN_MASK);
207
208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP);
209 airoha_fe_wr(eth, REG_FE_VIP_EN(21),
210 PATN_FCPU_EN_MASK | PATN_EN_MASK);
211 }
212
airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth * eth,u32 port,u32 queue)213 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth,
214 u32 port, u32 queue)
215 {
216 u32 val;
217
218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,
219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK,
220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) |
221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue));
222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL);
223
224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val);
225 }
226
airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth * eth,u32 port,u32 queue,u32 val)227 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth,
228 u32 port, u32 queue, u32 val)
229 {
230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK,
231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val));
232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR,
233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK |
234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK,
235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) |
236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) |
237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK);
238 }
239
airoha_fe_get_pse_all_rsv(struct airoha_eth * eth)240 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)
241 {
242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);
243
244 return FIELD_GET(PSE_ALLRSV_MASK, val);
245 }
246
airoha_fe_set_pse_oq_rsv(struct airoha_eth * eth,u32 port,u32 queue,u32 val)247 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,
248 u32 port, u32 queue, u32 val)
249 {
250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);
251 u32 tmp, all_rsv, fq_limit;
252
253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);
254
255 /* modify all rsv */
256 all_rsv = airoha_fe_get_pse_all_rsv(eth);
257 all_rsv += (val - orig_val);
258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,
259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));
260
261 /* modify hthd */
262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG);
263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp);
264 tmp = fq_limit - all_rsv - 0x20;
265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,
266 PSE_SHARE_USED_HTHD_MASK,
267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp));
268
269 tmp = fq_limit - all_rsv - 0x100;
270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD,
271 PSE_SHARE_USED_MTHD_MASK,
272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp));
273 tmp = (3 * tmp) >> 2;
274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET,
275 PSE_SHARE_USED_LTHD_MASK,
276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp));
277
278 return 0;
279 }
280
airoha_fe_pse_ports_init(struct airoha_eth * eth)281 static void airoha_fe_pse_ports_init(struct airoha_eth *eth)
282 {
283 const u32 pse_port_num_queues[] = {
284 [FE_PSE_PORT_CDM1] = 6,
285 [FE_PSE_PORT_GDM1] = 6,
286 [FE_PSE_PORT_GDM2] = 32,
287 [FE_PSE_PORT_GDM3] = 6,
288 [FE_PSE_PORT_PPE1] = 4,
289 [FE_PSE_PORT_CDM2] = 6,
290 [FE_PSE_PORT_CDM3] = 8,
291 [FE_PSE_PORT_CDM4] = 10,
292 [FE_PSE_PORT_PPE2] = 4,
293 [FE_PSE_PORT_GDM4] = 2,
294 [FE_PSE_PORT_CDM5] = 2,
295 };
296 u32 all_rsv;
297 int q;
298
299 all_rsv = airoha_fe_get_pse_all_rsv(eth);
300 /* hw misses PPE2 oq rsv */
301 all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2];
302 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv);
303
304 /* CMD1 */
305 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)
306 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q,
307 PSE_QUEUE_RSV_PAGES);
308 /* GMD1 */
309 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++)
310 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q,
311 PSE_QUEUE_RSV_PAGES);
312 /* GMD2 */
313 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++)
314 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0);
315 /* GMD3 */
316 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++)
317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q,
318 PSE_QUEUE_RSV_PAGES);
319 /* PPE1 */
320 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) {
321 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1])
322 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q,
323 PSE_QUEUE_RSV_PAGES);
324 else
325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0);
326 }
327 /* CDM2 */
328 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++)
329 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q,
330 PSE_QUEUE_RSV_PAGES);
331 /* CDM3 */
332 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++)
333 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0);
334 /* CDM4 */
335 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)
336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,
337 PSE_QUEUE_RSV_PAGES);
338 /* PPE2 */
339 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) {
340 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)
341 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q,
342 PSE_QUEUE_RSV_PAGES);
343 else
344 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0);
345 }
346 /* GMD4 */
347 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)
348 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q,
349 PSE_QUEUE_RSV_PAGES);
350 /* CDM5 */
351 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++)
352 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q,
353 PSE_QUEUE_RSV_PAGES);
354 }
355
airoha_fe_mc_vlan_clear(struct airoha_eth * eth)356 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth)
357 {
358 int i;
359
360 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) {
361 int err, j;
362 u32 val;
363
364 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);
365
366 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) |
367 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK;
368 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val);
369 err = read_poll_timeout(airoha_fe_rr, val,
370 val & MC_VLAN_CFG_CMD_DONE_MASK,
371 USEC_PER_MSEC, 5 * USEC_PER_MSEC,
372 false, eth, REG_MC_VLAN_CFG);
373 if (err)
374 return err;
375
376 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) {
377 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0);
378
379 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) |
380 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) |
381 MC_VLAN_CFG_RW_MASK;
382 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val);
383 err = read_poll_timeout(airoha_fe_rr, val,
384 val & MC_VLAN_CFG_CMD_DONE_MASK,
385 USEC_PER_MSEC,
386 5 * USEC_PER_MSEC, false, eth,
387 REG_MC_VLAN_CFG);
388 if (err)
389 return err;
390 }
391 }
392
393 return 0;
394 }
395
airoha_fe_crsn_qsel_init(struct airoha_eth * eth)396 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth)
397 {
398 /* CDM1_CRSN_QSEL */
399 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2),
400 CDM1_CRSN_QSEL_REASON_MASK(CRSN_22),
401 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22),
402 CDM_CRSN_QSEL_Q1));
403 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2),
404 CDM1_CRSN_QSEL_REASON_MASK(CRSN_08),
405 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08),
406 CDM_CRSN_QSEL_Q1));
407 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2),
408 CDM1_CRSN_QSEL_REASON_MASK(CRSN_21),
409 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21),
410 CDM_CRSN_QSEL_Q1));
411 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2),
412 CDM1_CRSN_QSEL_REASON_MASK(CRSN_24),
413 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24),
414 CDM_CRSN_QSEL_Q6));
415 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2),
416 CDM1_CRSN_QSEL_REASON_MASK(CRSN_25),
417 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25),
418 CDM_CRSN_QSEL_Q1));
419 /* CDM2_CRSN_QSEL */
420 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2),
421 CDM2_CRSN_QSEL_REASON_MASK(CRSN_08),
422 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08),
423 CDM_CRSN_QSEL_Q1));
424 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2),
425 CDM2_CRSN_QSEL_REASON_MASK(CRSN_21),
426 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21),
427 CDM_CRSN_QSEL_Q1));
428 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2),
429 CDM2_CRSN_QSEL_REASON_MASK(CRSN_22),
430 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22),
431 CDM_CRSN_QSEL_Q1));
432 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2),
433 CDM2_CRSN_QSEL_REASON_MASK(CRSN_24),
434 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24),
435 CDM_CRSN_QSEL_Q6));
436 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2),
437 CDM2_CRSN_QSEL_REASON_MASK(CRSN_25),
438 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25),
439 CDM_CRSN_QSEL_Q1));
440 }
441
airoha_fe_init(struct airoha_eth * eth)442 static int airoha_fe_init(struct airoha_eth *eth)
443 {
444 airoha_fe_maccr_init(eth);
445
446 /* PSE IQ reserve */
447 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK,
448 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10));
449 airoha_fe_rmw(eth, REG_PSE_IQ_REV2,
450 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK,
451 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) |
452 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34));
453
454 /* enable FE copy engine for MC/KA/DPI */
455 airoha_fe_wr(eth, REG_FE_PCE_CFG,
456 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK);
457 /* set vip queue selection to ring 1 */
458 airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK,
459 FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4));
460 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK,
461 FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4));
462 /* set GDM4 source interface offset to 8 */
463 airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET,
464 GDM4_SPORT_OFF2_MASK |
465 GDM4_SPORT_OFF1_MASK |
466 GDM4_SPORT_OFF0_MASK,
467 FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) |
468 FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) |
469 FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8));
470
471 /* set PSE Page as 128B */
472 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG,
473 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK,
474 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) |
475 FE_DMA_GLO_PG_SZ_MASK);
476 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG,
477 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK |
478 FE_RST_GDM4_MBI_ARB_MASK);
479 usleep_range(1000, 2000);
480
481 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1
482 * connect other rings to PSE Port0 OQ-0
483 */
484 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4));
485 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28));
486 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4));
487 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28));
488
489 airoha_fe_vip_setup(eth);
490 airoha_fe_pse_ports_init(eth);
491
492 airoha_fe_set(eth, REG_GDM_MISC_CFG,
493 GDM2_RDM_ACK_WAIT_PREF_MASK |
494 GDM2_CHN_VLD_MODE_MASK);
495 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK,
496 FIELD_PREP(CDM2_OAM_QSEL_MASK, 15));
497
498 /* init fragment and assemble Force Port */
499 /* NPU Core-3, NPU Bridge Channel-3 */
500 airoha_fe_rmw(eth, REG_IP_FRAG_FP,
501 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK,
502 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) |
503 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3));
504 /* QDMA LAN, RX Ring-22 */
505 airoha_fe_rmw(eth, REG_IP_FRAG_FP,
506 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK,
507 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) |
508 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22));
509
510 airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK);
511 airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK);
512
513 airoha_fe_crsn_qsel_init(eth);
514
515 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK);
516 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK);
517
518 /* default aging mode for mbi unlock issue */
519 airoha_fe_rmw(eth, REG_GDM2_CHN_RLS,
520 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK,
521 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) |
522 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3));
523
524 /* disable IFC by default */
525 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK);
526
527 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0),
528 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM1) |
529 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM1) |
530 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM1) |
531 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM1) |
532 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM1) |
533 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM1) |
534 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM1) |
535 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM1));
536 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(1),
537 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM2) |
538 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM2) |
539 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM2) |
540 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM2) |
541 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM2) |
542 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM2) |
543 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM2) |
544 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM2));
545
546 /* enable 1:N vlan action, init vlan table */
547 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK);
548
549 return airoha_fe_mc_vlan_clear(eth);
550 }
551
airoha_qdma_fill_rx_queue(struct airoha_queue * q)552 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
553 {
554 struct airoha_qdma *qdma = q->qdma;
555 int qid = q - &qdma->q_rx[0];
556 int nframes = 0;
557
558 while (q->queued < q->ndesc - 1) {
559 struct airoha_queue_entry *e = &q->entry[q->head];
560 struct airoha_qdma_desc *desc = &q->desc[q->head];
561 struct page *page;
562 int offset;
563 u32 val;
564
565 page = page_pool_dev_alloc_frag(q->page_pool, &offset,
566 q->buf_size);
567 if (!page)
568 break;
569
570 q->head = (q->head + 1) % q->ndesc;
571 q->queued++;
572 nframes++;
573
574 e->buf = page_address(page) + offset;
575 e->dma_addr = page_pool_get_dma_addr(page) + offset;
576 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size);
577
578 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len);
579 WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
580 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr));
581 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head);
582 WRITE_ONCE(desc->data, cpu_to_le32(val));
583 WRITE_ONCE(desc->msg0, 0);
584 WRITE_ONCE(desc->msg1, 0);
585 WRITE_ONCE(desc->msg2, 0);
586 WRITE_ONCE(desc->msg3, 0);
587
588 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid),
589 RX_RING_CPU_IDX_MASK,
590 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
591 }
592
593 return nframes;
594 }
595
airoha_qdma_get_gdm_port(struct airoha_eth * eth,struct airoha_qdma_desc * desc)596 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
597 struct airoha_qdma_desc *desc)
598 {
599 u32 port, sport, msg1 = le32_to_cpu(desc->msg1);
600
601 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1);
602 switch (sport) {
603 case 0x10 ... 0x14:
604 port = 0;
605 break;
606 case 0x2 ... 0x4:
607 port = sport - 1;
608 break;
609 default:
610 return -EINVAL;
611 }
612
613 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
614 }
615
airoha_qdma_rx_process(struct airoha_queue * q,int budget)616 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
617 {
618 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool);
619 struct airoha_qdma *qdma = q->qdma;
620 struct airoha_eth *eth = qdma->eth;
621 int qid = q - &qdma->q_rx[0];
622 int done = 0;
623
624 while (done < budget) {
625 struct airoha_queue_entry *e = &q->entry[q->tail];
626 struct airoha_qdma_desc *desc = &q->desc[q->tail];
627 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
628 struct page *page = virt_to_head_page(e->buf);
629 u32 desc_ctrl = le32_to_cpu(desc->ctrl);
630 struct airoha_gdm_port *port;
631 int data_len, len, p;
632
633 if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
634 break;
635
636 q->tail = (q->tail + 1) % q->ndesc;
637 q->queued--;
638
639 dma_sync_single_for_cpu(eth->dev, e->dma_addr,
640 SKB_WITH_OVERHEAD(q->buf_size), dir);
641
642 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl);
643 data_len = q->skb ? q->buf_size
644 : SKB_WITH_OVERHEAD(q->buf_size);
645 if (!len || data_len < len)
646 goto free_frag;
647
648 p = airoha_qdma_get_gdm_port(eth, desc);
649 if (p < 0 || !eth->ports[p])
650 goto free_frag;
651
652 port = eth->ports[p];
653 if (!q->skb) { /* first buffer */
654 q->skb = napi_build_skb(e->buf, q->buf_size);
655 if (!q->skb)
656 goto free_frag;
657
658 __skb_put(q->skb, len);
659 skb_mark_for_recycle(q->skb);
660 q->skb->dev = port->dev;
661 q->skb->protocol = eth_type_trans(q->skb, port->dev);
662 q->skb->ip_summed = CHECKSUM_UNNECESSARY;
663 skb_record_rx_queue(q->skb, qid);
664 } else { /* scattered frame */
665 struct skb_shared_info *shinfo = skb_shinfo(q->skb);
666 int nr_frags = shinfo->nr_frags;
667
668 if (nr_frags >= ARRAY_SIZE(shinfo->frags))
669 goto free_frag;
670
671 skb_add_rx_frag(q->skb, nr_frags, page,
672 e->buf - page_address(page), len,
673 q->buf_size);
674 }
675
676 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
677 continue;
678
679 if (netdev_uses_dsa(port->dev)) {
680 /* PPE module requires untagged packets to work
681 * properly and it provides DSA port index via the
682 * DMA descriptor. Report DSA tag to the DSA stack
683 * via skb dst info.
684 */
685 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG,
686 le32_to_cpu(desc->msg0));
687
688 if (sptag < ARRAY_SIZE(port->dsa_meta) &&
689 port->dsa_meta[sptag])
690 skb_dst_set_noref(q->skb,
691 &port->dsa_meta[sptag]->dst);
692 }
693
694 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1);
695 if (hash != AIROHA_RXD4_FOE_ENTRY)
696 skb_set_hash(q->skb, jhash_1word(hash, 0),
697 PKT_HASH_TYPE_L4);
698
699 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1);
700 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
701 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash,
702 false);
703
704 done++;
705 napi_gro_receive(&q->napi, q->skb);
706 q->skb = NULL;
707 continue;
708 free_frag:
709 if (q->skb) {
710 dev_kfree_skb(q->skb);
711 q->skb = NULL;
712 } else {
713 page_pool_put_full_page(q->page_pool, page, true);
714 }
715 }
716 airoha_qdma_fill_rx_queue(q);
717
718 return done;
719 }
720
airoha_qdma_rx_napi_poll(struct napi_struct * napi,int budget)721 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
722 {
723 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi);
724 int cur, done = 0;
725
726 do {
727 cur = airoha_qdma_rx_process(q, budget - done);
728 done += cur;
729 } while (cur && done < budget);
730
731 if (done < budget && napi_complete(napi)) {
732 struct airoha_qdma *qdma = q->qdma;
733 int i, qid = q - &qdma->q_rx[0];
734 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
735 : QDMA_INT_REG_IDX2;
736
737 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
738 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))
739 continue;
740
741 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
742 BIT(qid % RX_DONE_HIGH_OFFSET));
743 }
744 }
745
746 return done;
747 }
748
airoha_qdma_init_rx_queue(struct airoha_queue * q,struct airoha_qdma * qdma,int ndesc)749 static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
750 struct airoha_qdma *qdma, int ndesc)
751 {
752 const struct page_pool_params pp_params = {
753 .order = 0,
754 .pool_size = 256,
755 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
756 .dma_dir = DMA_FROM_DEVICE,
757 .max_len = PAGE_SIZE,
758 .nid = NUMA_NO_NODE,
759 .dev = qdma->eth->dev,
760 .napi = &q->napi,
761 };
762 struct airoha_eth *eth = qdma->eth;
763 int qid = q - &qdma->q_rx[0], thr;
764 dma_addr_t dma_addr;
765
766 q->buf_size = PAGE_SIZE / 2;
767 q->ndesc = ndesc;
768 q->qdma = qdma;
769
770 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
771 GFP_KERNEL);
772 if (!q->entry)
773 return -ENOMEM;
774
775 q->page_pool = page_pool_create(&pp_params);
776 if (IS_ERR(q->page_pool)) {
777 int err = PTR_ERR(q->page_pool);
778
779 q->page_pool = NULL;
780 return err;
781 }
782
783 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
784 &dma_addr, GFP_KERNEL);
785 if (!q->desc)
786 return -ENOMEM;
787
788 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll);
789
790 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr);
791 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid),
792 RX_RING_SIZE_MASK,
793 FIELD_PREP(RX_RING_SIZE_MASK, ndesc));
794
795 thr = clamp(ndesc >> 3, 1, 32);
796 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK,
797 FIELD_PREP(RX_RING_THR_MASK, thr));
798 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
799 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
800 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK);
801
802 airoha_qdma_fill_rx_queue(q);
803
804 return 0;
805 }
806
airoha_qdma_cleanup_rx_queue(struct airoha_queue * q)807 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q)
808 {
809 struct airoha_eth *eth = q->qdma->eth;
810
811 while (q->queued) {
812 struct airoha_queue_entry *e = &q->entry[q->tail];
813 struct page *page = virt_to_head_page(e->buf);
814
815 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len,
816 page_pool_get_dma_dir(q->page_pool));
817 page_pool_put_full_page(q->page_pool, page, false);
818 q->tail = (q->tail + 1) % q->ndesc;
819 q->queued--;
820 }
821 }
822
airoha_qdma_init_rx(struct airoha_qdma * qdma)823 static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
824 {
825 int i;
826
827 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
828 int err;
829
830 if (!(RX_DONE_INT_MASK & BIT(i))) {
831 /* rx-queue not binded to irq */
832 continue;
833 }
834
835 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma,
836 RX_DSCP_NUM(i));
837 if (err)
838 return err;
839 }
840
841 return 0;
842 }
843
airoha_qdma_tx_napi_poll(struct napi_struct * napi,int budget)844 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
845 {
846 struct airoha_tx_irq_queue *irq_q;
847 int id, done = 0, irq_queued;
848 struct airoha_qdma *qdma;
849 struct airoha_eth *eth;
850 u32 status, head;
851
852 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi);
853 qdma = irq_q->qdma;
854 id = irq_q - &qdma->q_tx_irq[0];
855 eth = qdma->eth;
856
857 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id));
858 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status);
859 head = head % irq_q->size;
860 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status);
861
862 while (irq_queued > 0 && done < budget) {
863 u32 qid, val = irq_q->q[head];
864 struct airoha_qdma_desc *desc;
865 struct airoha_queue_entry *e;
866 struct airoha_queue *q;
867 u32 index, desc_ctrl;
868 struct sk_buff *skb;
869
870 if (val == 0xff)
871 break;
872
873 irq_q->q[head] = 0xff; /* mark as done */
874 head = (head + 1) % irq_q->size;
875 irq_queued--;
876 done++;
877
878 qid = FIELD_GET(IRQ_RING_IDX_MASK, val);
879 if (qid >= ARRAY_SIZE(qdma->q_tx))
880 continue;
881
882 q = &qdma->q_tx[qid];
883 if (!q->ndesc)
884 continue;
885
886 index = FIELD_GET(IRQ_DESC_IDX_MASK, val);
887 if (index >= q->ndesc)
888 continue;
889
890 spin_lock_bh(&q->lock);
891
892 if (!q->queued)
893 goto unlock;
894
895 desc = &q->desc[index];
896 desc_ctrl = le32_to_cpu(desc->ctrl);
897
898 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) &&
899 !(desc_ctrl & QDMA_DESC_DROP_MASK))
900 goto unlock;
901
902 e = &q->entry[index];
903 skb = e->skb;
904
905 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
906 DMA_TO_DEVICE);
907 memset(e, 0, sizeof(*e));
908 WRITE_ONCE(desc->msg0, 0);
909 WRITE_ONCE(desc->msg1, 0);
910 q->queued--;
911
912 /* completion ring can report out-of-order indexes if hw QoS
913 * is enabled and packets with different priority are queued
914 * to same DMA ring. Take into account possible out-of-order
915 * reports incrementing DMA ring tail pointer
916 */
917 while (q->tail != q->head && !q->entry[q->tail].dma_addr)
918 q->tail = (q->tail + 1) % q->ndesc;
919
920 if (skb) {
921 u16 queue = skb_get_queue_mapping(skb);
922 struct netdev_queue *txq;
923
924 txq = netdev_get_tx_queue(skb->dev, queue);
925 netdev_tx_completed_queue(txq, 1, skb->len);
926 if (netif_tx_queue_stopped(txq) &&
927 q->ndesc - q->queued >= q->free_thr)
928 netif_tx_wake_queue(txq);
929
930 dev_kfree_skb_any(skb);
931 }
932 unlock:
933 spin_unlock_bh(&q->lock);
934 }
935
936 if (done) {
937 int i, len = done >> 7;
938
939 for (i = 0; i < len; i++)
940 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
941 IRQ_CLEAR_LEN_MASK, 0x80);
942 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id),
943 IRQ_CLEAR_LEN_MASK, (done & 0x7f));
944 }
945
946 if (done < budget && napi_complete(napi))
947 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
948 TX_DONE_INT_MASK(id));
949
950 return done;
951 }
952
airoha_qdma_init_tx_queue(struct airoha_queue * q,struct airoha_qdma * qdma,int size)953 static int airoha_qdma_init_tx_queue(struct airoha_queue *q,
954 struct airoha_qdma *qdma, int size)
955 {
956 struct airoha_eth *eth = qdma->eth;
957 int i, qid = q - &qdma->q_tx[0];
958 dma_addr_t dma_addr;
959
960 spin_lock_init(&q->lock);
961 q->ndesc = size;
962 q->qdma = qdma;
963 q->free_thr = 1 + MAX_SKB_FRAGS;
964
965 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
966 GFP_KERNEL);
967 if (!q->entry)
968 return -ENOMEM;
969
970 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
971 &dma_addr, GFP_KERNEL);
972 if (!q->desc)
973 return -ENOMEM;
974
975 for (i = 0; i < q->ndesc; i++) {
976 u32 val;
977
978 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1);
979 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val));
980 }
981
982 /* xmit ring drop default setting */
983 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid),
984 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK);
985
986 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr);
987 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
988 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));
989 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
990 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head));
991
992 return 0;
993 }
994
airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue * irq_q,struct airoha_qdma * qdma,int size)995 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,
996 struct airoha_qdma *qdma, int size)
997 {
998 int id = irq_q - &qdma->q_tx_irq[0];
999 struct airoha_eth *eth = qdma->eth;
1000 dma_addr_t dma_addr;
1001
1002 netif_napi_add_tx(eth->napi_dev, &irq_q->napi,
1003 airoha_qdma_tx_napi_poll);
1004 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32),
1005 &dma_addr, GFP_KERNEL);
1006 if (!irq_q->q)
1007 return -ENOMEM;
1008
1009 memset(irq_q->q, 0xff, size * sizeof(u32));
1010 irq_q->size = size;
1011 irq_q->qdma = qdma;
1012
1013 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr);
1014 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK,
1015 FIELD_PREP(TX_IRQ_DEPTH_MASK, size));
1016 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK,
1017 FIELD_PREP(TX_IRQ_THR_MASK, 1));
1018
1019 return 0;
1020 }
1021
airoha_qdma_init_tx(struct airoha_qdma * qdma)1022 static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
1023 {
1024 int i, err;
1025
1026 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1027 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma,
1028 IRQ_QUEUE_LEN(i));
1029 if (err)
1030 return err;
1031 }
1032
1033 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1034 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma,
1035 TX_DSCP_NUM);
1036 if (err)
1037 return err;
1038 }
1039
1040 return 0;
1041 }
1042
airoha_qdma_cleanup_tx_queue(struct airoha_queue * q)1043 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
1044 {
1045 struct airoha_eth *eth = q->qdma->eth;
1046
1047 spin_lock_bh(&q->lock);
1048 while (q->queued) {
1049 struct airoha_queue_entry *e = &q->entry[q->tail];
1050
1051 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len,
1052 DMA_TO_DEVICE);
1053 dev_kfree_skb_any(e->skb);
1054 e->skb = NULL;
1055
1056 q->tail = (q->tail + 1) % q->ndesc;
1057 q->queued--;
1058 }
1059 spin_unlock_bh(&q->lock);
1060 }
1061
airoha_qdma_init_hfwd_queues(struct airoha_qdma * qdma)1062 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
1063 {
1064 int size, index, num_desc = HW_DSCP_NUM;
1065 struct airoha_eth *eth = qdma->eth;
1066 int id = qdma - ð->qdma[0];
1067 u32 status, buf_size;
1068 dma_addr_t dma_addr;
1069 const char *name;
1070
1071 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
1072 if (!name)
1073 return -ENOMEM;
1074
1075 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE;
1076 index = of_property_match_string(eth->dev->of_node,
1077 "memory-region-names", name);
1078 if (index >= 0) {
1079 struct reserved_mem *rmem;
1080 struct device_node *np;
1081
1082 /* Consume reserved memory for hw forwarding buffers queue if
1083 * available in the DTS
1084 */
1085 np = of_parse_phandle(eth->dev->of_node, "memory-region",
1086 index);
1087 if (!np)
1088 return -ENODEV;
1089
1090 rmem = of_reserved_mem_lookup(np);
1091 of_node_put(np);
1092 dma_addr = rmem->base;
1093 /* Compute the number of hw descriptors according to the
1094 * reserved memory size and the payload buffer size
1095 */
1096 num_desc = div_u64(rmem->size, buf_size);
1097 } else {
1098 size = buf_size * num_desc;
1099 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,
1100 GFP_KERNEL))
1101 return -ENOMEM;
1102 }
1103
1104 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
1105
1106 size = num_desc * sizeof(struct airoha_qdma_fwd_desc);
1107 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
1108 return -ENOMEM;
1109
1110 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
1111 /* QDMA0: 2KB. QDMA1: 1KB */
1112 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
1113 HW_FWD_DSCP_PAYLOAD_SIZE_MASK,
1114 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id));
1115 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK,
1116 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128));
1117 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
1118 LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
1119 HW_FWD_DESC_NUM_MASK,
1120 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) |
1121 LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
1122
1123 return read_poll_timeout(airoha_qdma_rr, status,
1124 !(status & LMGR_INIT_START), USEC_PER_MSEC,
1125 30 * USEC_PER_MSEC, true, qdma,
1126 REG_LMGR_INIT_CFG);
1127 }
1128
airoha_qdma_init_qos(struct airoha_qdma * qdma)1129 static void airoha_qdma_init_qos(struct airoha_qdma *qdma)
1130 {
1131 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK);
1132 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK);
1133
1134 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG,
1135 PSE_BUF_ESTIMATE_EN_MASK);
1136
1137 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG,
1138 EGRESS_RATE_METER_EN_MASK |
1139 EGRESS_RATE_METER_EQ_RATE_EN_MASK);
1140 /* 2047us x 31 = 63.457ms */
1141 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1142 EGRESS_RATE_METER_WINDOW_SZ_MASK,
1143 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f));
1144 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG,
1145 EGRESS_RATE_METER_TIMESLICE_MASK,
1146 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff));
1147
1148 /* ratelimit init */
1149 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK);
1150 /* fast-tick 25us */
1151 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK,
1152 FIELD_PREP(GLB_FAST_TICK_MASK, 25));
1153 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK,
1154 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40));
1155
1156 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK);
1157 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK,
1158 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25));
1159 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG,
1160 EGRESS_SLOW_TICK_RATIO_MASK,
1161 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40));
1162
1163 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK);
1164 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG,
1165 INGRESS_TRTCM_MODE_MASK);
1166 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK,
1167 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125));
1168 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG,
1169 INGRESS_SLOW_TICK_RATIO_MASK,
1170 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8));
1171
1172 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK);
1173 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK,
1174 FIELD_PREP(SLA_FAST_TICK_MASK, 25));
1175 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK,
1176 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40));
1177 }
1178
airoha_qdma_init_qos_stats(struct airoha_qdma * qdma)1179 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma)
1180 {
1181 int i;
1182
1183 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) {
1184 /* Tx-cpu transferred count */
1185 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0);
1186 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1187 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
1188 CNTR_ALL_DSCP_RING_EN_MASK |
1189 FIELD_PREP(CNTR_CHAN_MASK, i));
1190 /* Tx-fwd transferred count */
1191 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0);
1192 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1),
1193 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK |
1194 CNTR_ALL_DSCP_RING_EN_MASK |
1195 FIELD_PREP(CNTR_SRC_MASK, 1) |
1196 FIELD_PREP(CNTR_CHAN_MASK, i));
1197 }
1198 }
1199
airoha_qdma_hw_init(struct airoha_qdma * qdma)1200 static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
1201 {
1202 int i;
1203
1204 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1205 /* clear pending irqs */
1206 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
1207 /* setup rx irqs */
1208 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0,
1209 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1210 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1,
1211 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1212 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2,
1213 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1214 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3,
1215 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i)));
1216 }
1217 /* setup tx irqs */
1218 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
1219 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK);
1220 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4,
1221 TX_COHERENT_HIGH_INT_MASK);
1222
1223 /* setup irq binding */
1224 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1225 if (!qdma->q_tx[i].ndesc)
1226 continue;
1227
1228 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i))
1229 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i),
1230 TX_RING_IRQ_BLOCKING_CFG_MASK);
1231 else
1232 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i),
1233 TX_RING_IRQ_BLOCKING_CFG_MASK);
1234 }
1235
1236 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG,
1237 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) |
1238 GLOBAL_CFG_CPU_TXR_RR_MASK |
1239 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK |
1240 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK |
1241 GLOBAL_CFG_MULTICAST_EN_MASK |
1242 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK |
1243 GLOBAL_CFG_TX_WB_DONE_MASK |
1244 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2));
1245
1246 airoha_qdma_init_qos(qdma);
1247
1248 /* disable qdma rx delay interrupt */
1249 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1250 if (!qdma->q_rx[i].ndesc)
1251 continue;
1252
1253 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i),
1254 RX_DELAY_INT_MASK);
1255 }
1256
1257 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG,
1258 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN);
1259 airoha_qdma_init_qos_stats(qdma);
1260
1261 return 0;
1262 }
1263
airoha_irq_handler(int irq,void * dev_instance)1264 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)
1265 {
1266 struct airoha_irq_bank *irq_bank = dev_instance;
1267 struct airoha_qdma *qdma = irq_bank->qdma;
1268 u32 rx_intr_mask = 0, rx_intr1, rx_intr2;
1269 u32 intr[ARRAY_SIZE(irq_bank->irqmask)];
1270 int i;
1271
1272 for (i = 0; i < ARRAY_SIZE(intr); i++) {
1273 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i));
1274 intr[i] &= irq_bank->irqmask[i];
1275 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]);
1276 }
1277
1278 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
1279 return IRQ_NONE;
1280
1281 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK;
1282 if (rx_intr1) {
1283 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);
1284 rx_intr_mask |= rx_intr1;
1285 }
1286
1287 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK;
1288 if (rx_intr2) {
1289 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);
1290 rx_intr_mask |= (rx_intr2 << 16);
1291 }
1292
1293 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
1294 if (!qdma->q_rx[i].ndesc)
1295 continue;
1296
1297 if (rx_intr_mask & BIT(i))
1298 napi_schedule(&qdma->q_rx[i].napi);
1299 }
1300
1301 if (intr[0] & INT_TX_MASK) {
1302 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
1303 if (!(intr[0] & TX_DONE_INT_MASK(i)))
1304 continue;
1305
1306 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0,
1307 TX_DONE_INT_MASK(i));
1308 napi_schedule(&qdma->q_tx_irq[i].napi);
1309 }
1310 }
1311
1312 return IRQ_HANDLED;
1313 }
1314
airoha_qdma_init_irq_banks(struct platform_device * pdev,struct airoha_qdma * qdma)1315 static int airoha_qdma_init_irq_banks(struct platform_device *pdev,
1316 struct airoha_qdma *qdma)
1317 {
1318 struct airoha_eth *eth = qdma->eth;
1319 int i, id = qdma - ð->qdma[0];
1320
1321 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
1322 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i];
1323 int err, irq_index = 4 * id + i;
1324 const char *name;
1325
1326 spin_lock_init(&irq_bank->irq_lock);
1327 irq_bank->qdma = qdma;
1328
1329 irq_bank->irq = platform_get_irq(pdev, irq_index);
1330 if (irq_bank->irq < 0)
1331 return irq_bank->irq;
1332
1333 name = devm_kasprintf(eth->dev, GFP_KERNEL,
1334 KBUILD_MODNAME ".%d", irq_index);
1335 if (!name)
1336 return -ENOMEM;
1337
1338 err = devm_request_irq(eth->dev, irq_bank->irq,
1339 airoha_irq_handler, IRQF_SHARED, name,
1340 irq_bank);
1341 if (err)
1342 return err;
1343 }
1344
1345 return 0;
1346 }
1347
airoha_qdma_init(struct platform_device * pdev,struct airoha_eth * eth,struct airoha_qdma * qdma)1348 static int airoha_qdma_init(struct platform_device *pdev,
1349 struct airoha_eth *eth,
1350 struct airoha_qdma *qdma)
1351 {
1352 int err, id = qdma - ð->qdma[0];
1353 const char *res;
1354
1355 qdma->eth = eth;
1356 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id);
1357 if (!res)
1358 return -ENOMEM;
1359
1360 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res);
1361 if (IS_ERR(qdma->regs))
1362 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs),
1363 "failed to iomap qdma%d regs\n", id);
1364
1365 err = airoha_qdma_init_irq_banks(pdev, qdma);
1366 if (err)
1367 return err;
1368
1369 err = airoha_qdma_init_rx(qdma);
1370 if (err)
1371 return err;
1372
1373 err = airoha_qdma_init_tx(qdma);
1374 if (err)
1375 return err;
1376
1377 err = airoha_qdma_init_hfwd_queues(qdma);
1378 if (err)
1379 return err;
1380
1381 return airoha_qdma_hw_init(qdma);
1382 }
1383
airoha_hw_init(struct platform_device * pdev,struct airoha_eth * eth)1384 static int airoha_hw_init(struct platform_device *pdev,
1385 struct airoha_eth *eth)
1386 {
1387 int err, i;
1388
1389 /* disable xsi */
1390 err = reset_control_bulk_assert(ARRAY_SIZE(eth->xsi_rsts),
1391 eth->xsi_rsts);
1392 if (err)
1393 return err;
1394
1395 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts);
1396 if (err)
1397 return err;
1398
1399 msleep(20);
1400 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts);
1401 if (err)
1402 return err;
1403
1404 msleep(20);
1405 err = airoha_fe_init(eth);
1406 if (err)
1407 return err;
1408
1409 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
1410 err = airoha_qdma_init(pdev, eth, ð->qdma[i]);
1411 if (err)
1412 return err;
1413 }
1414
1415 err = airoha_ppe_init(eth);
1416 if (err)
1417 return err;
1418
1419 set_bit(DEV_STATE_INITIALIZED, ð->state);
1420
1421 return 0;
1422 }
1423
airoha_hw_cleanup(struct airoha_qdma * qdma)1424 static void airoha_hw_cleanup(struct airoha_qdma *qdma)
1425 {
1426 int i;
1427
1428 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1429 if (!qdma->q_rx[i].ndesc)
1430 continue;
1431
1432 netif_napi_del(&qdma->q_rx[i].napi);
1433 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]);
1434 if (qdma->q_rx[i].page_pool)
1435 page_pool_destroy(qdma->q_rx[i].page_pool);
1436 }
1437
1438 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1439 netif_napi_del(&qdma->q_tx_irq[i].napi);
1440
1441 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1442 if (!qdma->q_tx[i].ndesc)
1443 continue;
1444
1445 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1446 }
1447 }
1448
airoha_qdma_start_napi(struct airoha_qdma * qdma)1449 static void airoha_qdma_start_napi(struct airoha_qdma *qdma)
1450 {
1451 int i;
1452
1453 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1454 napi_enable(&qdma->q_tx_irq[i].napi);
1455
1456 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1457 if (!qdma->q_rx[i].ndesc)
1458 continue;
1459
1460 napi_enable(&qdma->q_rx[i].napi);
1461 }
1462 }
1463
airoha_qdma_stop_napi(struct airoha_qdma * qdma)1464 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)
1465 {
1466 int i;
1467
1468 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
1469 napi_disable(&qdma->q_tx_irq[i].napi);
1470
1471 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
1472 if (!qdma->q_rx[i].ndesc)
1473 continue;
1474
1475 napi_disable(&qdma->q_rx[i].napi);
1476 }
1477 }
1478
airoha_update_hw_stats(struct airoha_gdm_port * port)1479 static void airoha_update_hw_stats(struct airoha_gdm_port *port)
1480 {
1481 struct airoha_eth *eth = port->qdma->eth;
1482 u32 val, i = 0;
1483
1484 spin_lock(&port->stats.lock);
1485 u64_stats_update_begin(&port->stats.syncp);
1486
1487 /* TX */
1488 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id));
1489 port->stats.tx_ok_pkts += ((u64)val << 32);
1490 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id));
1491 port->stats.tx_ok_pkts += val;
1492
1493 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id));
1494 port->stats.tx_ok_bytes += ((u64)val << 32);
1495 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id));
1496 port->stats.tx_ok_bytes += val;
1497
1498 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id));
1499 port->stats.tx_drops += val;
1500
1501 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id));
1502 port->stats.tx_broadcast += val;
1503
1504 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id));
1505 port->stats.tx_multicast += val;
1506
1507 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id));
1508 port->stats.tx_len[i] += val;
1509
1510 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id));
1511 port->stats.tx_len[i] += ((u64)val << 32);
1512 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id));
1513 port->stats.tx_len[i++] += val;
1514
1515 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id));
1516 port->stats.tx_len[i] += ((u64)val << 32);
1517 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id));
1518 port->stats.tx_len[i++] += val;
1519
1520 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id));
1521 port->stats.tx_len[i] += ((u64)val << 32);
1522 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id));
1523 port->stats.tx_len[i++] += val;
1524
1525 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id));
1526 port->stats.tx_len[i] += ((u64)val << 32);
1527 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id));
1528 port->stats.tx_len[i++] += val;
1529
1530 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id));
1531 port->stats.tx_len[i] += ((u64)val << 32);
1532 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id));
1533 port->stats.tx_len[i++] += val;
1534
1535 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id));
1536 port->stats.tx_len[i] += ((u64)val << 32);
1537 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id));
1538 port->stats.tx_len[i++] += val;
1539
1540 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id));
1541 port->stats.tx_len[i++] += val;
1542
1543 /* RX */
1544 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id));
1545 port->stats.rx_ok_pkts += ((u64)val << 32);
1546 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id));
1547 port->stats.rx_ok_pkts += val;
1548
1549 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id));
1550 port->stats.rx_ok_bytes += ((u64)val << 32);
1551 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id));
1552 port->stats.rx_ok_bytes += val;
1553
1554 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id));
1555 port->stats.rx_drops += val;
1556
1557 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id));
1558 port->stats.rx_broadcast += val;
1559
1560 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id));
1561 port->stats.rx_multicast += val;
1562
1563 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id));
1564 port->stats.rx_errors += val;
1565
1566 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id));
1567 port->stats.rx_crc_error += val;
1568
1569 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id));
1570 port->stats.rx_over_errors += val;
1571
1572 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id));
1573 port->stats.rx_fragment += val;
1574
1575 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id));
1576 port->stats.rx_jabber += val;
1577
1578 i = 0;
1579 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id));
1580 port->stats.rx_len[i] += val;
1581
1582 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id));
1583 port->stats.rx_len[i] += ((u64)val << 32);
1584 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id));
1585 port->stats.rx_len[i++] += val;
1586
1587 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id));
1588 port->stats.rx_len[i] += ((u64)val << 32);
1589 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id));
1590 port->stats.rx_len[i++] += val;
1591
1592 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id));
1593 port->stats.rx_len[i] += ((u64)val << 32);
1594 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id));
1595 port->stats.rx_len[i++] += val;
1596
1597 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id));
1598 port->stats.rx_len[i] += ((u64)val << 32);
1599 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id));
1600 port->stats.rx_len[i++] += val;
1601
1602 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id));
1603 port->stats.rx_len[i] += ((u64)val << 32);
1604 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id));
1605 port->stats.rx_len[i++] += val;
1606
1607 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id));
1608 port->stats.rx_len[i] += ((u64)val << 32);
1609 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id));
1610 port->stats.rx_len[i++] += val;
1611
1612 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id));
1613 port->stats.rx_len[i++] += val;
1614
1615 /* reset mib counters */
1616 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id),
1617 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
1618
1619 u64_stats_update_end(&port->stats.syncp);
1620 spin_unlock(&port->stats.lock);
1621 }
1622
airoha_dev_open(struct net_device * dev)1623 static int airoha_dev_open(struct net_device *dev)
1624 {
1625 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN;
1626 struct airoha_gdm_port *port = netdev_priv(dev);
1627 struct airoha_qdma *qdma = port->qdma;
1628
1629 netif_tx_start_all_queues(dev);
1630 err = airoha_set_vip_for_gdm_port(port, true);
1631 if (err)
1632 return err;
1633
1634 if (netdev_uses_dsa(dev))
1635 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1636 GDM_STAG_EN_MASK);
1637 else
1638 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
1639 GDM_STAG_EN_MASK);
1640
1641 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id),
1642 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
1643 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
1644 FIELD_PREP(GDM_LONG_LEN_MASK, len));
1645
1646 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
1647 GLOBAL_CFG_TX_DMA_EN_MASK |
1648 GLOBAL_CFG_RX_DMA_EN_MASK);
1649 atomic_inc(&qdma->users);
1650
1651 return 0;
1652 }
1653
airoha_dev_stop(struct net_device * dev)1654 static int airoha_dev_stop(struct net_device *dev)
1655 {
1656 struct airoha_gdm_port *port = netdev_priv(dev);
1657 struct airoha_qdma *qdma = port->qdma;
1658 int i, err;
1659
1660 netif_tx_disable(dev);
1661 err = airoha_set_vip_for_gdm_port(port, false);
1662 if (err)
1663 return err;
1664
1665 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++)
1666 netdev_tx_reset_subqueue(dev, i);
1667
1668 if (atomic_dec_and_test(&qdma->users)) {
1669 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG,
1670 GLOBAL_CFG_TX_DMA_EN_MASK |
1671 GLOBAL_CFG_RX_DMA_EN_MASK);
1672
1673 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
1674 if (!qdma->q_tx[i].ndesc)
1675 continue;
1676
1677 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]);
1678 }
1679 }
1680
1681 return 0;
1682 }
1683
airoha_dev_set_macaddr(struct net_device * dev,void * p)1684 static int airoha_dev_set_macaddr(struct net_device *dev, void *p)
1685 {
1686 struct airoha_gdm_port *port = netdev_priv(dev);
1687 int err;
1688
1689 err = eth_mac_addr(dev, p);
1690 if (err)
1691 return err;
1692
1693 airoha_set_macaddr(port, dev->dev_addr);
1694
1695 return 0;
1696 }
1697
airhoha_set_gdm2_loopback(struct airoha_gdm_port * port)1698 static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port)
1699 {
1700 u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4;
1701 struct airoha_eth *eth = port->qdma->eth;
1702 u32 chan = port->id == 3 ? 4 : 0;
1703
1704 /* Forward the traffic to the proper GDM port */
1705 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port);
1706 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC);
1707
1708 /* Enable GDM2 loopback */
1709 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff);
1710 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff);
1711 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2),
1712 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK,
1713 FIELD_PREP(LPBK_CHAN_MASK, chan) |
1714 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK |
1715 LBK_CHAN_MODE_MASK | LPBK_EN_MASK);
1716 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2),
1717 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
1718 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
1719 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU));
1720
1721 /* Disable VIP and IFC for GDM2 */
1722 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2));
1723 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2));
1724
1725 if (port->id == 3) {
1726 /* FIXME: handle XSI_PCE1_PORT */
1727 airoha_fe_rmw(eth, REG_FE_WAN_PORT,
1728 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
1729 FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT));
1730 airoha_fe_rmw(eth,
1731 REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3),
1732 SP_CPORT_PCIE0_MASK,
1733 FIELD_PREP(SP_CPORT_PCIE0_MASK,
1734 FE_PSE_PORT_CDM2));
1735 } else {
1736 /* FIXME: handle XSI_USB_PORT */
1737 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6,
1738 FC_ID_OF_SRC_PORT24_MASK,
1739 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2));
1740 airoha_fe_rmw(eth, REG_FE_WAN_PORT,
1741 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK,
1742 FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT));
1743 airoha_fe_rmw(eth,
1744 REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3),
1745 SP_CPORT_ETH_MASK,
1746 FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2));
1747 }
1748 }
1749
airoha_dev_init(struct net_device * dev)1750 static int airoha_dev_init(struct net_device *dev)
1751 {
1752 struct airoha_gdm_port *port = netdev_priv(dev);
1753 struct airoha_eth *eth = port->qdma->eth;
1754 u32 pse_port;
1755
1756 airoha_set_macaddr(port, dev->dev_addr);
1757
1758 switch (port->id) {
1759 case 3:
1760 case 4:
1761 /* If GDM2 is active we can't enable loopback */
1762 if (!eth->ports[1])
1763 airhoha_set_gdm2_loopback(port);
1764 fallthrough;
1765 case 2:
1766 pse_port = FE_PSE_PORT_PPE2;
1767 break;
1768 default:
1769 pse_port = FE_PSE_PORT_PPE1;
1770 break;
1771 }
1772
1773 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port);
1774
1775 return 0;
1776 }
1777
airoha_dev_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)1778 static void airoha_dev_get_stats64(struct net_device *dev,
1779 struct rtnl_link_stats64 *storage)
1780 {
1781 struct airoha_gdm_port *port = netdev_priv(dev);
1782 unsigned int start;
1783
1784 airoha_update_hw_stats(port);
1785 do {
1786 start = u64_stats_fetch_begin(&port->stats.syncp);
1787 storage->rx_packets = port->stats.rx_ok_pkts;
1788 storage->tx_packets = port->stats.tx_ok_pkts;
1789 storage->rx_bytes = port->stats.rx_ok_bytes;
1790 storage->tx_bytes = port->stats.tx_ok_bytes;
1791 storage->multicast = port->stats.rx_multicast;
1792 storage->rx_errors = port->stats.rx_errors;
1793 storage->rx_dropped = port->stats.rx_drops;
1794 storage->tx_dropped = port->stats.tx_drops;
1795 storage->rx_crc_errors = port->stats.rx_crc_error;
1796 storage->rx_over_errors = port->stats.rx_over_errors;
1797 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
1798 }
1799
airoha_dev_change_mtu(struct net_device * dev,int mtu)1800 static int airoha_dev_change_mtu(struct net_device *dev, int mtu)
1801 {
1802 struct airoha_gdm_port *port = netdev_priv(dev);
1803 struct airoha_eth *eth = port->qdma->eth;
1804 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN;
1805
1806 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id),
1807 GDM_LONG_LEN_MASK,
1808 FIELD_PREP(GDM_LONG_LEN_MASK, len));
1809 WRITE_ONCE(dev->mtu, mtu);
1810
1811 return 0;
1812 }
1813
airoha_dev_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)1814 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,
1815 struct net_device *sb_dev)
1816 {
1817 struct airoha_gdm_port *port = netdev_priv(dev);
1818 int queue, channel;
1819
1820 /* For dsa device select QoS channel according to the dsa user port
1821 * index, rely on port id otherwise. Select QoS queue based on the
1822 * skb priority.
1823 */
1824 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id;
1825 channel = channel % AIROHA_NUM_QOS_CHANNELS;
1826 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */
1827 queue = channel * AIROHA_NUM_QOS_QUEUES + queue;
1828
1829 return queue < dev->num_tx_queues ? queue : 0;
1830 }
1831
airoha_get_dsa_tag(struct sk_buff * skb,struct net_device * dev)1832 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev)
1833 {
1834 #if IS_ENABLED(CONFIG_NET_DSA)
1835 struct ethhdr *ehdr;
1836 u8 xmit_tpid;
1837 u16 tag;
1838
1839 if (!netdev_uses_dsa(dev))
1840 return 0;
1841
1842 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
1843 return 0;
1844
1845 if (skb_cow_head(skb, 0))
1846 return 0;
1847
1848 ehdr = (struct ethhdr *)skb->data;
1849 tag = be16_to_cpu(ehdr->h_proto);
1850 xmit_tpid = tag >> 8;
1851
1852 switch (xmit_tpid) {
1853 case MTK_HDR_XMIT_TAGGED_TPID_8100:
1854 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q);
1855 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8);
1856 break;
1857 case MTK_HDR_XMIT_TAGGED_TPID_88A8:
1858 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD);
1859 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8);
1860 break;
1861 default:
1862 /* PPE module requires untagged DSA packets to work properly,
1863 * so move DSA tag to DMA descriptor.
1864 */
1865 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN);
1866 __skb_pull(skb, MTK_HDR_LEN);
1867 break;
1868 }
1869
1870 return tag;
1871 #else
1872 return 0;
1873 #endif
1874 }
1875
airoha_dev_xmit(struct sk_buff * skb,struct net_device * dev)1876 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
1877 struct net_device *dev)
1878 {
1879 struct airoha_gdm_port *port = netdev_priv(dev);
1880 struct airoha_qdma *qdma = port->qdma;
1881 u32 nr_frags, tag, msg0, msg1, len;
1882 struct netdev_queue *txq;
1883 struct airoha_queue *q;
1884 void *data;
1885 int i, qid;
1886 u16 index;
1887 u8 fport;
1888
1889 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx);
1890 tag = airoha_get_dsa_tag(skb, dev);
1891
1892 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK,
1893 qid / AIROHA_NUM_QOS_QUEUES) |
1894 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK,
1895 qid % AIROHA_NUM_QOS_QUEUES) |
1896 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag);
1897 if (skb->ip_summed == CHECKSUM_PARTIAL)
1898 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) |
1899 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) |
1900 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1);
1901
1902 /* TSO: fill MSS info in tcp checksum field */
1903 if (skb_is_gso(skb)) {
1904 if (skb_cow_head(skb, 0))
1905 goto error;
1906
1907 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 |
1908 SKB_GSO_TCPV6)) {
1909 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size);
1910
1911 tcp_hdr(skb)->check = (__force __sum16)csum;
1912 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1);
1913 }
1914 }
1915
1916 fport = port->id == 4 ? FE_PSE_PORT_GDM4 : port->id;
1917 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
1918 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
1919
1920 q = &qdma->q_tx[qid];
1921 if (WARN_ON_ONCE(!q->ndesc))
1922 goto error;
1923
1924 spin_lock_bh(&q->lock);
1925
1926 txq = netdev_get_tx_queue(dev, qid);
1927 nr_frags = 1 + skb_shinfo(skb)->nr_frags;
1928
1929 if (q->queued + nr_frags > q->ndesc) {
1930 /* not enough space in the queue */
1931 netif_tx_stop_queue(txq);
1932 spin_unlock_bh(&q->lock);
1933 return NETDEV_TX_BUSY;
1934 }
1935
1936 len = skb_headlen(skb);
1937 data = skb->data;
1938 index = q->head;
1939
1940 for (i = 0; i < nr_frags; i++) {
1941 struct airoha_qdma_desc *desc = &q->desc[index];
1942 struct airoha_queue_entry *e = &q->entry[index];
1943 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1944 dma_addr_t addr;
1945 u32 val;
1946
1947 addr = dma_map_single(dev->dev.parent, data, len,
1948 DMA_TO_DEVICE);
1949 if (unlikely(dma_mapping_error(dev->dev.parent, addr)))
1950 goto error_unmap;
1951
1952 index = (index + 1) % q->ndesc;
1953
1954 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len);
1955 if (i < nr_frags - 1)
1956 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1);
1957 WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
1958 WRITE_ONCE(desc->addr, cpu_to_le32(addr));
1959 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index);
1960 WRITE_ONCE(desc->data, cpu_to_le32(val));
1961 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0));
1962 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1));
1963 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff));
1964
1965 e->skb = i ? NULL : skb;
1966 e->dma_addr = addr;
1967 e->dma_len = len;
1968
1969 data = skb_frag_address(frag);
1970 len = skb_frag_size(frag);
1971 }
1972
1973 q->head = index;
1974 q->queued += i;
1975
1976 skb_tx_timestamp(skb);
1977 netdev_tx_sent_queue(txq, skb->len);
1978
1979 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1980 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid),
1981 TX_RING_CPU_IDX_MASK,
1982 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head));
1983
1984 if (q->ndesc - q->queued < q->free_thr)
1985 netif_tx_stop_queue(txq);
1986
1987 spin_unlock_bh(&q->lock);
1988
1989 return NETDEV_TX_OK;
1990
1991 error_unmap:
1992 for (i--; i >= 0; i--) {
1993 index = (q->head + i) % q->ndesc;
1994 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr,
1995 q->entry[index].dma_len, DMA_TO_DEVICE);
1996 }
1997
1998 spin_unlock_bh(&q->lock);
1999 error:
2000 dev_kfree_skb_any(skb);
2001 dev->stats.tx_dropped++;
2002
2003 return NETDEV_TX_OK;
2004 }
2005
airoha_ethtool_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2006 static void airoha_ethtool_get_drvinfo(struct net_device *dev,
2007 struct ethtool_drvinfo *info)
2008 {
2009 struct airoha_gdm_port *port = netdev_priv(dev);
2010 struct airoha_eth *eth = port->qdma->eth;
2011
2012 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver));
2013 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info));
2014 }
2015
airoha_ethtool_get_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * stats)2016 static void airoha_ethtool_get_mac_stats(struct net_device *dev,
2017 struct ethtool_eth_mac_stats *stats)
2018 {
2019 struct airoha_gdm_port *port = netdev_priv(dev);
2020 unsigned int start;
2021
2022 airoha_update_hw_stats(port);
2023 do {
2024 start = u64_stats_fetch_begin(&port->stats.syncp);
2025 stats->MulticastFramesXmittedOK = port->stats.tx_multicast;
2026 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast;
2027 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast;
2028 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
2029 }
2030
2031 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = {
2032 { 0, 64 },
2033 { 65, 127 },
2034 { 128, 255 },
2035 { 256, 511 },
2036 { 512, 1023 },
2037 { 1024, 1518 },
2038 { 1519, 10239 },
2039 {},
2040 };
2041
2042 static void
airoha_ethtool_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * stats,const struct ethtool_rmon_hist_range ** ranges)2043 airoha_ethtool_get_rmon_stats(struct net_device *dev,
2044 struct ethtool_rmon_stats *stats,
2045 const struct ethtool_rmon_hist_range **ranges)
2046 {
2047 struct airoha_gdm_port *port = netdev_priv(dev);
2048 struct airoha_hw_stats *hw_stats = &port->stats;
2049 unsigned int start;
2050
2051 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
2052 ARRAY_SIZE(hw_stats->tx_len) + 1);
2053 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
2054 ARRAY_SIZE(hw_stats->rx_len) + 1);
2055
2056 *ranges = airoha_ethtool_rmon_ranges;
2057 airoha_update_hw_stats(port);
2058 do {
2059 int i;
2060
2061 start = u64_stats_fetch_begin(&port->stats.syncp);
2062 stats->fragments = hw_stats->rx_fragment;
2063 stats->jabbers = hw_stats->rx_jabber;
2064 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1;
2065 i++) {
2066 stats->hist[i] = hw_stats->rx_len[i];
2067 stats->hist_tx[i] = hw_stats->tx_len[i];
2068 }
2069 } while (u64_stats_fetch_retry(&port->stats.syncp, start));
2070 }
2071
airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port * port,int channel,enum tx_sched_mode mode,const u16 * weights,u8 n_weights)2072 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port,
2073 int channel, enum tx_sched_mode mode,
2074 const u16 *weights, u8 n_weights)
2075 {
2076 int i;
2077
2078 for (i = 0; i < AIROHA_NUM_TX_RING; i++)
2079 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel),
2080 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i));
2081
2082 for (i = 0; i < n_weights; i++) {
2083 u32 status;
2084 int err;
2085
2086 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG,
2087 TWRR_RW_CMD_MASK |
2088 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) |
2089 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) |
2090 FIELD_PREP(TWRR_VALUE_MASK, weights[i]));
2091 err = read_poll_timeout(airoha_qdma_rr, status,
2092 status & TWRR_RW_CMD_DONE,
2093 USEC_PER_MSEC, 10 * USEC_PER_MSEC,
2094 true, port->qdma,
2095 REG_TXWRR_WEIGHT_CFG);
2096 if (err)
2097 return err;
2098 }
2099
2100 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3),
2101 CHAN_QOS_MODE_MASK(channel),
2102 mode << __ffs(CHAN_QOS_MODE_MASK(channel)));
2103
2104 return 0;
2105 }
2106
airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port * port,int channel)2107 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port,
2108 int channel)
2109 {
2110 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {};
2111
2112 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w,
2113 ARRAY_SIZE(w));
2114 }
2115
airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port * port,int channel,struct tc_ets_qopt_offload * opt)2116 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port,
2117 int channel,
2118 struct tc_ets_qopt_offload *opt)
2119 {
2120 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params;
2121 enum tx_sched_mode mode = TC_SCH_SP;
2122 u16 w[AIROHA_NUM_QOS_QUEUES] = {};
2123 int i, nstrict = 0;
2124
2125 if (p->bands > AIROHA_NUM_QOS_QUEUES)
2126 return -EINVAL;
2127
2128 for (i = 0; i < p->bands; i++) {
2129 if (!p->quanta[i])
2130 nstrict++;
2131 }
2132
2133 /* this configuration is not supported by the hw */
2134 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1)
2135 return -EINVAL;
2136
2137 /* EN7581 SoC supports fixed QoS band priority where WRR queues have
2138 * lowest priorities with respect to SP ones.
2139 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn
2140 */
2141 for (i = 0; i < nstrict; i++) {
2142 if (p->priomap[p->bands - i - 1] != i)
2143 return -EINVAL;
2144 }
2145
2146 for (i = 0; i < p->bands - nstrict; i++) {
2147 if (p->priomap[i] != nstrict + i)
2148 return -EINVAL;
2149
2150 w[i] = p->weights[nstrict + i];
2151 }
2152
2153 if (!nstrict)
2154 mode = TC_SCH_WRR8;
2155 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1)
2156 mode = nstrict + 1;
2157
2158 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w,
2159 ARRAY_SIZE(w));
2160 }
2161
airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port * port,int channel,struct tc_ets_qopt_offload * opt)2162 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port,
2163 int channel,
2164 struct tc_ets_qopt_offload *opt)
2165 {
2166 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma,
2167 REG_CNTR_VAL(channel << 1));
2168 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma,
2169 REG_CNTR_VAL((channel << 1) + 1));
2170 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) +
2171 (fwd_tx_packets - port->fwd_tx_packets);
2172 _bstats_update(opt->stats.bstats, 0, tx_packets);
2173
2174 port->cpu_tx_packets = cpu_tx_packets;
2175 port->fwd_tx_packets = fwd_tx_packets;
2176
2177 return 0;
2178 }
2179
airoha_tc_setup_qdisc_ets(struct airoha_gdm_port * port,struct tc_ets_qopt_offload * opt)2180 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port,
2181 struct tc_ets_qopt_offload *opt)
2182 {
2183 int channel;
2184
2185 if (opt->parent == TC_H_ROOT)
2186 return -EINVAL;
2187
2188 channel = TC_H_MAJ(opt->handle) >> 16;
2189 channel = channel % AIROHA_NUM_QOS_CHANNELS;
2190
2191 switch (opt->command) {
2192 case TC_ETS_REPLACE:
2193 return airoha_qdma_set_tx_ets_sched(port, channel, opt);
2194 case TC_ETS_DESTROY:
2195 /* PRIO is default qdisc scheduler */
2196 return airoha_qdma_set_tx_prio_sched(port, channel);
2197 case TC_ETS_STATS:
2198 return airoha_qdma_get_tx_ets_stats(port, channel, opt);
2199 default:
2200 return -EOPNOTSUPP;
2201 }
2202 }
2203
airoha_qdma_get_rl_param(struct airoha_qdma * qdma,int queue_id,u32 addr,enum trtcm_param_type param,u32 * val_low,u32 * val_high)2204 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id,
2205 u32 addr, enum trtcm_param_type param,
2206 u32 *val_low, u32 *val_high)
2207 {
2208 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id);
2209 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) |
2210 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) |
2211 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx);
2212
2213 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2214 if (read_poll_timeout(airoha_qdma_rr, val,
2215 val & RATE_LIMIT_PARAM_RW_DONE_MASK,
2216 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma,
2217 REG_TRTCM_CFG_PARAM(addr)))
2218 return -ETIMEDOUT;
2219
2220 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2221 if (val_high)
2222 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2223
2224 return 0;
2225 }
2226
airoha_qdma_set_rl_param(struct airoha_qdma * qdma,int queue_id,u32 addr,enum trtcm_param_type param,u32 val)2227 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id,
2228 u32 addr, enum trtcm_param_type param,
2229 u32 val)
2230 {
2231 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id);
2232 u32 config = RATE_LIMIT_PARAM_RW_MASK |
2233 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) |
2234 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) |
2235 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx);
2236
2237 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2238 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2239
2240 return read_poll_timeout(airoha_qdma_rr, val,
2241 val & RATE_LIMIT_PARAM_RW_DONE_MASK,
2242 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2243 qdma, REG_TRTCM_CFG_PARAM(addr));
2244 }
2245
airoha_qdma_set_rl_config(struct airoha_qdma * qdma,int queue_id,u32 addr,bool enable,u32 enable_mask)2246 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id,
2247 u32 addr, bool enable, u32 enable_mask)
2248 {
2249 u32 val;
2250 int err;
2251
2252 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2253 &val, NULL);
2254 if (err)
2255 return err;
2256
2257 val = enable ? val | enable_mask : val & ~enable_mask;
2258
2259 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE,
2260 val);
2261 }
2262
airoha_qdma_set_rl_token_bucket(struct airoha_qdma * qdma,int queue_id,u32 rate_val,u32 bucket_size)2263 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma,
2264 int queue_id, u32 rate_val,
2265 u32 bucket_size)
2266 {
2267 u32 val, config, tick, unit, rate, rate_frac;
2268 int err;
2269
2270 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2271 TRTCM_MISC_MODE, &config, NULL);
2272 if (err)
2273 return err;
2274
2275 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG);
2276 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val);
2277 if (config & TRTCM_TICK_SEL)
2278 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val);
2279 if (!tick)
2280 return -EINVAL;
2281
2282 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick;
2283 if (!unit)
2284 return -EINVAL;
2285
2286 rate = rate_val / unit;
2287 rate_frac = rate_val % unit;
2288 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit;
2289 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) |
2290 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac);
2291
2292 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2293 TRTCM_TOKEN_RATE_MODE, rate);
2294 if (err)
2295 return err;
2296
2297 val = bucket_size;
2298 if (!(config & TRTCM_PKT_MODE))
2299 val = max_t(u32, val, MIN_TOKEN_SIZE);
2300 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
2301
2302 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2303 TRTCM_BUCKETSIZE_SHIFT_MODE, val);
2304 }
2305
airoha_qdma_init_rl_config(struct airoha_qdma * qdma,int queue_id,bool enable,enum trtcm_unit_type unit)2306 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id,
2307 bool enable, enum trtcm_unit_type unit)
2308 {
2309 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8;
2310 enum trtcm_param mode = TRTCM_METER_MODE;
2311 int err;
2312
2313 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0;
2314 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2315 enable, mode);
2316 if (err)
2317 return err;
2318
2319 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG,
2320 tick_sel, TRTCM_TICK_SEL);
2321 }
2322
airoha_qdma_get_trtcm_param(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_param_type param,enum trtcm_mode_type mode,u32 * val_low,u32 * val_high)2323 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel,
2324 u32 addr, enum trtcm_param_type param,
2325 enum trtcm_mode_type mode,
2326 u32 *val_low, u32 *val_high)
2327 {
2328 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
2329 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
2330 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
2331 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
2332 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
2333
2334 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2335 if (read_poll_timeout(airoha_qdma_rr, val,
2336 val & TRTCM_PARAM_RW_DONE_MASK,
2337 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2338 qdma, REG_TRTCM_CFG_PARAM(addr)))
2339 return -ETIMEDOUT;
2340
2341 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr));
2342 if (val_high)
2343 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr));
2344
2345 return 0;
2346 }
2347
airoha_qdma_set_trtcm_param(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_param_type param,enum trtcm_mode_type mode,u32 val)2348 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel,
2349 u32 addr, enum trtcm_param_type param,
2350 enum trtcm_mode_type mode, u32 val)
2351 {
2352 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel);
2353 u32 config = TRTCM_PARAM_RW_MASK |
2354 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) |
2355 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) |
2356 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) |
2357 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode);
2358
2359 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val);
2360 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config);
2361
2362 return read_poll_timeout(airoha_qdma_rr, val,
2363 val & TRTCM_PARAM_RW_DONE_MASK,
2364 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true,
2365 qdma, REG_TRTCM_CFG_PARAM(addr));
2366 }
2367
airoha_qdma_set_trtcm_config(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_mode_type mode,bool enable,u32 enable_mask)2368 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel,
2369 u32 addr, enum trtcm_mode_type mode,
2370 bool enable, u32 enable_mask)
2371 {
2372 u32 val;
2373
2374 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2375 mode, &val, NULL))
2376 return -EINVAL;
2377
2378 val = enable ? val | enable_mask : val & ~enable_mask;
2379
2380 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2381 mode, val);
2382 }
2383
airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma * qdma,int channel,u32 addr,enum trtcm_mode_type mode,u32 rate_val,u32 bucket_size)2384 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma,
2385 int channel, u32 addr,
2386 enum trtcm_mode_type mode,
2387 u32 rate_val, u32 bucket_size)
2388 {
2389 u32 val, config, tick, unit, rate, rate_frac;
2390 int err;
2391
2392 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE,
2393 mode, &config, NULL))
2394 return -EINVAL;
2395
2396 val = airoha_qdma_rr(qdma, addr);
2397 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val);
2398 if (config & TRTCM_TICK_SEL)
2399 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val);
2400 if (!tick)
2401 return -EINVAL;
2402
2403 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick;
2404 if (!unit)
2405 return -EINVAL;
2406
2407 rate = rate_val / unit;
2408 rate_frac = rate_val % unit;
2409 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit;
2410 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) |
2411 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac);
2412
2413 err = airoha_qdma_set_trtcm_param(qdma, channel, addr,
2414 TRTCM_TOKEN_RATE_MODE, mode, rate);
2415 if (err)
2416 return err;
2417
2418 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE);
2419 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET);
2420
2421 return airoha_qdma_set_trtcm_param(qdma, channel, addr,
2422 TRTCM_BUCKETSIZE_SHIFT_MODE,
2423 mode, val);
2424 }
2425
airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port * port,int channel,u32 rate,u32 bucket_size)2426 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port,
2427 int channel, u32 rate,
2428 u32 bucket_size)
2429 {
2430 int i, err;
2431
2432 for (i = 0; i <= TRTCM_PEAK_MODE; i++) {
2433 err = airoha_qdma_set_trtcm_config(port->qdma, channel,
2434 REG_EGRESS_TRTCM_CFG, i,
2435 !!rate, TRTCM_METER_MODE);
2436 if (err)
2437 return err;
2438
2439 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel,
2440 REG_EGRESS_TRTCM_CFG,
2441 i, rate, bucket_size);
2442 if (err)
2443 return err;
2444 }
2445
2446 return 0;
2447 }
2448
airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2449 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port,
2450 struct tc_htb_qopt_offload *opt)
2451 {
2452 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2453 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */
2454 struct net_device *dev = port->dev;
2455 int num_tx_queues = dev->real_num_tx_queues;
2456 int err;
2457
2458 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) {
2459 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid");
2460 return -EINVAL;
2461 }
2462
2463 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum);
2464 if (err) {
2465 NL_SET_ERR_MSG_MOD(opt->extack,
2466 "failed configuring htb offload");
2467 return err;
2468 }
2469
2470 if (opt->command == TC_HTB_NODE_MODIFY)
2471 return 0;
2472
2473 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1);
2474 if (err) {
2475 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum);
2476 NL_SET_ERR_MSG_MOD(opt->extack,
2477 "failed setting real_num_tx_queues");
2478 return err;
2479 }
2480
2481 set_bit(channel, port->qos_sq_bmap);
2482 opt->qid = AIROHA_NUM_TX_RING + channel;
2483
2484 return 0;
2485 }
2486
airoha_qdma_set_rx_meter(struct airoha_gdm_port * port,u32 rate,u32 bucket_size,enum trtcm_unit_type unit_type)2487 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port,
2488 u32 rate, u32 bucket_size,
2489 enum trtcm_unit_type unit_type)
2490 {
2491 struct airoha_qdma *qdma = port->qdma;
2492 int i;
2493
2494 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
2495 int err;
2496
2497 if (!qdma->q_rx[i].ndesc)
2498 continue;
2499
2500 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type);
2501 if (err)
2502 return err;
2503
2504 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate,
2505 bucket_size);
2506 if (err)
2507 return err;
2508 }
2509
2510 return 0;
2511 }
2512
airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload * f)2513 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f)
2514 {
2515 const struct flow_action *actions = &f->rule->action;
2516 const struct flow_action_entry *act;
2517
2518 if (!flow_action_has_entries(actions)) {
2519 NL_SET_ERR_MSG_MOD(f->common.extack,
2520 "filter run with no actions");
2521 return -EINVAL;
2522 }
2523
2524 if (!flow_offload_has_one_action(actions)) {
2525 NL_SET_ERR_MSG_MOD(f->common.extack,
2526 "only once action per filter is supported");
2527 return -EOPNOTSUPP;
2528 }
2529
2530 act = &actions->entries[0];
2531 if (act->id != FLOW_ACTION_POLICE) {
2532 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action");
2533 return -EOPNOTSUPP;
2534 }
2535
2536 if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
2537 NL_SET_ERR_MSG_MOD(f->common.extack,
2538 "invalid exceed action id");
2539 return -EOPNOTSUPP;
2540 }
2541
2542 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) {
2543 NL_SET_ERR_MSG_MOD(f->common.extack,
2544 "invalid notexceed action id");
2545 return -EOPNOTSUPP;
2546 }
2547
2548 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
2549 !flow_action_is_last_entry(actions, act)) {
2550 NL_SET_ERR_MSG_MOD(f->common.extack,
2551 "action accept must be last");
2552 return -EOPNOTSUPP;
2553 }
2554
2555 if (act->police.peakrate_bytes_ps || act->police.avrate ||
2556 act->police.overhead || act->police.mtu) {
2557 NL_SET_ERR_MSG_MOD(f->common.extack,
2558 "peakrate/avrate/overhead/mtu unsupported");
2559 return -EOPNOTSUPP;
2560 }
2561
2562 return 0;
2563 }
2564
airoha_dev_tc_matchall(struct net_device * dev,struct tc_cls_matchall_offload * f)2565 static int airoha_dev_tc_matchall(struct net_device *dev,
2566 struct tc_cls_matchall_offload *f)
2567 {
2568 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT;
2569 struct airoha_gdm_port *port = netdev_priv(dev);
2570 u32 rate = 0, bucket_size = 0;
2571
2572 switch (f->command) {
2573 case TC_CLSMATCHALL_REPLACE: {
2574 const struct flow_action_entry *act;
2575 int err;
2576
2577 err = airoha_tc_matchall_act_validate(f);
2578 if (err)
2579 return err;
2580
2581 act = &f->rule->action.entries[0];
2582 if (act->police.rate_pkt_ps) {
2583 rate = act->police.rate_pkt_ps;
2584 bucket_size = act->police.burst_pkt;
2585 unit_type = TRTCM_PACKET_UNIT;
2586 } else {
2587 rate = div_u64(act->police.rate_bytes_ps, 1000);
2588 rate = rate << 3; /* Kbps */
2589 bucket_size = act->police.burst;
2590 }
2591 fallthrough;
2592 }
2593 case TC_CLSMATCHALL_DESTROY:
2594 return airoha_qdma_set_rx_meter(port, rate, bucket_size,
2595 unit_type);
2596 default:
2597 return -EOPNOTSUPP;
2598 }
2599 }
2600
airoha_dev_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2601 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type,
2602 void *type_data, void *cb_priv)
2603 {
2604 struct net_device *dev = cb_priv;
2605 struct airoha_gdm_port *port = netdev_priv(dev);
2606 struct airoha_eth *eth = port->qdma->eth;
2607
2608 if (!tc_can_offload(dev))
2609 return -EOPNOTSUPP;
2610
2611 switch (type) {
2612 case TC_SETUP_CLSFLOWER:
2613 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data);
2614 case TC_SETUP_CLSMATCHALL:
2615 return airoha_dev_tc_matchall(dev, type_data);
2616 default:
2617 return -EOPNOTSUPP;
2618 }
2619 }
2620
airoha_dev_setup_tc_block(struct airoha_gdm_port * port,struct flow_block_offload * f)2621 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port,
2622 struct flow_block_offload *f)
2623 {
2624 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb;
2625 static LIST_HEAD(block_cb_list);
2626 struct flow_block_cb *block_cb;
2627
2628 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2629 return -EOPNOTSUPP;
2630
2631 f->driver_block_list = &block_cb_list;
2632 switch (f->command) {
2633 case FLOW_BLOCK_BIND:
2634 block_cb = flow_block_cb_lookup(f->block, cb, port->dev);
2635 if (block_cb) {
2636 flow_block_cb_incref(block_cb);
2637 return 0;
2638 }
2639 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL);
2640 if (IS_ERR(block_cb))
2641 return PTR_ERR(block_cb);
2642
2643 flow_block_cb_incref(block_cb);
2644 flow_block_cb_add(block_cb, f);
2645 list_add_tail(&block_cb->driver_list, &block_cb_list);
2646 return 0;
2647 case FLOW_BLOCK_UNBIND:
2648 block_cb = flow_block_cb_lookup(f->block, cb, port->dev);
2649 if (!block_cb)
2650 return -ENOENT;
2651
2652 if (!flow_block_cb_decref(block_cb)) {
2653 flow_block_cb_remove(block_cb, f);
2654 list_del(&block_cb->driver_list);
2655 }
2656 return 0;
2657 default:
2658 return -EOPNOTSUPP;
2659 }
2660 }
2661
airoha_tc_remove_htb_queue(struct airoha_gdm_port * port,int queue)2662 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue)
2663 {
2664 struct net_device *dev = port->dev;
2665
2666 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1);
2667 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0);
2668 clear_bit(queue, port->qos_sq_bmap);
2669 }
2670
airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2671 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port,
2672 struct tc_htb_qopt_offload *opt)
2673 {
2674 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2675
2676 if (!test_bit(channel, port->qos_sq_bmap)) {
2677 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
2678 return -EINVAL;
2679 }
2680
2681 airoha_tc_remove_htb_queue(port, channel);
2682
2683 return 0;
2684 }
2685
airoha_tc_htb_destroy(struct airoha_gdm_port * port)2686 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port)
2687 {
2688 int q;
2689
2690 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS)
2691 airoha_tc_remove_htb_queue(port, q);
2692
2693 return 0;
2694 }
2695
airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2696 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port,
2697 struct tc_htb_qopt_offload *opt)
2698 {
2699 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS;
2700
2701 if (!test_bit(channel, port->qos_sq_bmap)) {
2702 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id");
2703 return -EINVAL;
2704 }
2705
2706 opt->qid = AIROHA_NUM_TX_RING + channel;
2707
2708 return 0;
2709 }
2710
airoha_tc_setup_qdisc_htb(struct airoha_gdm_port * port,struct tc_htb_qopt_offload * opt)2711 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port,
2712 struct tc_htb_qopt_offload *opt)
2713 {
2714 switch (opt->command) {
2715 case TC_HTB_CREATE:
2716 break;
2717 case TC_HTB_DESTROY:
2718 return airoha_tc_htb_destroy(port);
2719 case TC_HTB_NODE_MODIFY:
2720 case TC_HTB_LEAF_ALLOC_QUEUE:
2721 return airoha_tc_htb_alloc_leaf_queue(port, opt);
2722 case TC_HTB_LEAF_DEL:
2723 case TC_HTB_LEAF_DEL_LAST:
2724 case TC_HTB_LEAF_DEL_LAST_FORCE:
2725 return airoha_tc_htb_delete_leaf_queue(port, opt);
2726 case TC_HTB_LEAF_QUERY_QUEUE:
2727 return airoha_tc_get_htb_get_leaf_queue(port, opt);
2728 default:
2729 return -EOPNOTSUPP;
2730 }
2731
2732 return 0;
2733 }
2734
airoha_dev_tc_setup(struct net_device * dev,enum tc_setup_type type,void * type_data)2735 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type,
2736 void *type_data)
2737 {
2738 struct airoha_gdm_port *port = netdev_priv(dev);
2739
2740 switch (type) {
2741 case TC_SETUP_QDISC_ETS:
2742 return airoha_tc_setup_qdisc_ets(port, type_data);
2743 case TC_SETUP_QDISC_HTB:
2744 return airoha_tc_setup_qdisc_htb(port, type_data);
2745 case TC_SETUP_BLOCK:
2746 case TC_SETUP_FT:
2747 return airoha_dev_setup_tc_block(port, type_data);
2748 default:
2749 return -EOPNOTSUPP;
2750 }
2751 }
2752
2753 static const struct net_device_ops airoha_netdev_ops = {
2754 .ndo_init = airoha_dev_init,
2755 .ndo_open = airoha_dev_open,
2756 .ndo_stop = airoha_dev_stop,
2757 .ndo_change_mtu = airoha_dev_change_mtu,
2758 .ndo_select_queue = airoha_dev_select_queue,
2759 .ndo_start_xmit = airoha_dev_xmit,
2760 .ndo_get_stats64 = airoha_dev_get_stats64,
2761 .ndo_set_mac_address = airoha_dev_set_macaddr,
2762 .ndo_setup_tc = airoha_dev_tc_setup,
2763 };
2764
2765 static const struct ethtool_ops airoha_ethtool_ops = {
2766 .get_drvinfo = airoha_ethtool_get_drvinfo,
2767 .get_eth_mac_stats = airoha_ethtool_get_mac_stats,
2768 .get_rmon_stats = airoha_ethtool_get_rmon_stats,
2769 };
2770
airoha_metadata_dst_alloc(struct airoha_gdm_port * port)2771 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port)
2772 {
2773 int i;
2774
2775 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) {
2776 struct metadata_dst *md_dst;
2777
2778 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
2779 GFP_KERNEL);
2780 if (!md_dst)
2781 return -ENOMEM;
2782
2783 md_dst->u.port_info.port_id = i;
2784 port->dsa_meta[i] = md_dst;
2785 }
2786
2787 return 0;
2788 }
2789
airoha_metadata_dst_free(struct airoha_gdm_port * port)2790 static void airoha_metadata_dst_free(struct airoha_gdm_port *port)
2791 {
2792 int i;
2793
2794 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) {
2795 if (!port->dsa_meta[i])
2796 continue;
2797
2798 metadata_dst_free(port->dsa_meta[i]);
2799 }
2800 }
2801
airoha_is_valid_gdm_port(struct airoha_eth * eth,struct airoha_gdm_port * port)2802 bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
2803 struct airoha_gdm_port *port)
2804 {
2805 int i;
2806
2807 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
2808 if (eth->ports[i] == port)
2809 return true;
2810 }
2811
2812 return false;
2813 }
2814
airoha_alloc_gdm_port(struct airoha_eth * eth,struct device_node * np,int index)2815 static int airoha_alloc_gdm_port(struct airoha_eth *eth,
2816 struct device_node *np, int index)
2817 {
2818 const __be32 *id_ptr = of_get_property(np, "reg", NULL);
2819 struct airoha_gdm_port *port;
2820 struct airoha_qdma *qdma;
2821 struct net_device *dev;
2822 int err, p;
2823 u32 id;
2824
2825 if (!id_ptr) {
2826 dev_err(eth->dev, "missing gdm port id\n");
2827 return -EINVAL;
2828 }
2829
2830 id = be32_to_cpup(id_ptr);
2831 p = id - 1;
2832
2833 if (!id || id > ARRAY_SIZE(eth->ports)) {
2834 dev_err(eth->dev, "invalid gdm port id: %d\n", id);
2835 return -EINVAL;
2836 }
2837
2838 if (eth->ports[p]) {
2839 dev_err(eth->dev, "duplicate gdm port id: %d\n", id);
2840 return -EINVAL;
2841 }
2842
2843 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port),
2844 AIROHA_NUM_NETDEV_TX_RINGS,
2845 AIROHA_NUM_RX_RING);
2846 if (!dev) {
2847 dev_err(eth->dev, "alloc_etherdev failed\n");
2848 return -ENOMEM;
2849 }
2850
2851 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA];
2852 dev->netdev_ops = &airoha_netdev_ops;
2853 dev->ethtool_ops = &airoha_ethtool_ops;
2854 dev->max_mtu = AIROHA_MAX_MTU;
2855 dev->watchdog_timeo = 5 * HZ;
2856 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2857 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM |
2858 NETIF_F_SG | NETIF_F_TSO |
2859 NETIF_F_HW_TC;
2860 dev->features |= dev->hw_features;
2861 dev->vlan_features = dev->hw_features;
2862 dev->dev.of_node = np;
2863 dev->irq = qdma->irq_banks[0].irq;
2864 SET_NETDEV_DEV(dev, eth->dev);
2865
2866 /* reserve hw queues for HTB offloading */
2867 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING);
2868 if (err)
2869 return err;
2870
2871 err = of_get_ethdev_address(np, dev);
2872 if (err) {
2873 if (err == -EPROBE_DEFER)
2874 return err;
2875
2876 eth_hw_addr_random(dev);
2877 dev_info(eth->dev, "generated random MAC address %pM\n",
2878 dev->dev_addr);
2879 }
2880
2881 port = netdev_priv(dev);
2882 u64_stats_init(&port->stats.syncp);
2883 spin_lock_init(&port->stats.lock);
2884 port->qdma = qdma;
2885 port->dev = dev;
2886 port->id = id;
2887 eth->ports[p] = port;
2888
2889 err = airoha_metadata_dst_alloc(port);
2890 if (err)
2891 return err;
2892
2893 err = register_netdev(dev);
2894 if (err)
2895 goto free_metadata_dst;
2896
2897 return 0;
2898
2899 free_metadata_dst:
2900 airoha_metadata_dst_free(port);
2901 return err;
2902 }
2903
airoha_probe(struct platform_device * pdev)2904 static int airoha_probe(struct platform_device *pdev)
2905 {
2906 struct device_node *np;
2907 struct airoha_eth *eth;
2908 int i, err;
2909
2910 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2911 if (!eth)
2912 return -ENOMEM;
2913
2914 eth->dev = &pdev->dev;
2915
2916 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32));
2917 if (err) {
2918 dev_err(eth->dev, "failed configuring DMA mask\n");
2919 return err;
2920 }
2921
2922 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe");
2923 if (IS_ERR(eth->fe_regs))
2924 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs),
2925 "failed to iomap fe regs\n");
2926
2927 eth->rsts[0].id = "fe";
2928 eth->rsts[1].id = "pdma";
2929 eth->rsts[2].id = "qdma";
2930 err = devm_reset_control_bulk_get_exclusive(eth->dev,
2931 ARRAY_SIZE(eth->rsts),
2932 eth->rsts);
2933 if (err) {
2934 dev_err(eth->dev, "failed to get bulk reset lines\n");
2935 return err;
2936 }
2937
2938 eth->xsi_rsts[0].id = "xsi-mac";
2939 eth->xsi_rsts[1].id = "hsi0-mac";
2940 eth->xsi_rsts[2].id = "hsi1-mac";
2941 eth->xsi_rsts[3].id = "hsi-mac";
2942 eth->xsi_rsts[4].id = "xfp-mac";
2943 err = devm_reset_control_bulk_get_exclusive(eth->dev,
2944 ARRAY_SIZE(eth->xsi_rsts),
2945 eth->xsi_rsts);
2946 if (err) {
2947 dev_err(eth->dev, "failed to get bulk xsi reset lines\n");
2948 return err;
2949 }
2950
2951 eth->napi_dev = alloc_netdev_dummy(0);
2952 if (!eth->napi_dev)
2953 return -ENOMEM;
2954
2955 /* Enable threaded NAPI by default */
2956 eth->napi_dev->threaded = true;
2957 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name));
2958 platform_set_drvdata(pdev, eth);
2959
2960 err = airoha_hw_init(pdev, eth);
2961 if (err)
2962 goto error_hw_cleanup;
2963
2964 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2965 airoha_qdma_start_napi(ð->qdma[i]);
2966
2967 i = 0;
2968 for_each_child_of_node(pdev->dev.of_node, np) {
2969 if (!of_device_is_compatible(np, "airoha,eth-mac"))
2970 continue;
2971
2972 if (!of_device_is_available(np))
2973 continue;
2974
2975 err = airoha_alloc_gdm_port(eth, np, i++);
2976 if (err) {
2977 of_node_put(np);
2978 goto error_napi_stop;
2979 }
2980 }
2981
2982 return 0;
2983
2984 error_napi_stop:
2985 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2986 airoha_qdma_stop_napi(ð->qdma[i]);
2987 airoha_ppe_deinit(eth);
2988 error_hw_cleanup:
2989 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++)
2990 airoha_hw_cleanup(ð->qdma[i]);
2991
2992 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
2993 struct airoha_gdm_port *port = eth->ports[i];
2994
2995 if (port && port->dev->reg_state == NETREG_REGISTERED) {
2996 unregister_netdev(port->dev);
2997 airoha_metadata_dst_free(port);
2998 }
2999 }
3000 free_netdev(eth->napi_dev);
3001 platform_set_drvdata(pdev, NULL);
3002
3003 return err;
3004 }
3005
airoha_remove(struct platform_device * pdev)3006 static void airoha_remove(struct platform_device *pdev)
3007 {
3008 struct airoha_eth *eth = platform_get_drvdata(pdev);
3009 int i;
3010
3011 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) {
3012 airoha_qdma_stop_napi(ð->qdma[i]);
3013 airoha_hw_cleanup(ð->qdma[i]);
3014 }
3015
3016 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
3017 struct airoha_gdm_port *port = eth->ports[i];
3018
3019 if (!port)
3020 continue;
3021
3022 airoha_dev_stop(port->dev);
3023 unregister_netdev(port->dev);
3024 airoha_metadata_dst_free(port);
3025 }
3026 free_netdev(eth->napi_dev);
3027
3028 airoha_ppe_deinit(eth);
3029 platform_set_drvdata(pdev, NULL);
3030 }
3031
3032 static const struct of_device_id of_airoha_match[] = {
3033 { .compatible = "airoha,en7581-eth" },
3034 { /* sentinel */ }
3035 };
3036 MODULE_DEVICE_TABLE(of, of_airoha_match);
3037
3038 static struct platform_driver airoha_driver = {
3039 .probe = airoha_probe,
3040 .remove = airoha_remove,
3041 .driver = {
3042 .name = KBUILD_MODNAME,
3043 .of_match_table = of_airoha_match,
3044 },
3045 };
3046 module_platform_driver(airoha_driver);
3047
3048 MODULE_LICENSE("GPL");
3049 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
3050 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC");
3051