1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 12#include <dt-bindings/pinctrl/pinctrl-tegra.h> 13 14/ { 15 compatible = "nvidia,tegra234"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &gen1_i2c; 22 i2c1 = &gen2_i2c; 23 i2c2 = &cam_i2c; 24 i2c3 = &dp_aux_ch1_i2c; 25 i2c4 = &bpmp_i2c; 26 i2c5 = &dp_aux_ch0_i2c; 27 i2c6 = &dp_aux_ch2_i2c; 28 i2c7 = &gen8_i2c; 29 i2c8 = &dp_aux_ch3_i2c; 30 }; 31 32 bus@0 { 33 compatible = "simple-bus"; 34 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 38 39 misc@100000 { 40 compatible = "nvidia,tegra234-misc"; 41 reg = <0x0 0x00100000 0x0 0xf000>, 42 <0x0 0x0010f000 0x0 0x1000>; 43 }; 44 45 timer@2080000 { 46 compatible = "nvidia,tegra234-timer"; 47 reg = <0x0 0x02080000 0x0 0x00121000>; 48 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 64 }; 65 66 gpio: gpio@2200000 { 67 compatible = "nvidia,tegra234-gpio"; 68 reg-names = "security", "gpio"; 69 reg = <0x0 0x02200000 0x0 0x10000>, 70 <0x0 0x02210000 0x0 0x10000>; 71 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 119 #interrupt-cells = <2>; 120 interrupt-controller; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pinmux 0 0 164>; 124 }; 125 126 pinmux: pinmux@2430000 { 127 compatible = "nvidia,tegra234-pinmux"; 128 reg = <0x0 0x2430000 0x0 0x19100>; 129 130 pex_rst_c4_in_state: pinmux-pex-rst-c4-in { 131 pex_rst { 132 nvidia,pins = "pex_l4_rst_n_pl1"; 133 nvidia,function = "rsvd1"; 134 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 135 nvidia,tristate = <TEGRA_PIN_ENABLE>; 136 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 137 }; 138 }; 139 140 pex_rst_c5_in_state: pinmux-pex-rst-c5-in { 141 pex_rst { 142 nvidia,pins = "pex_l5_rst_n_paf1"; 143 nvidia,function = "rsvd1"; 144 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 145 nvidia,tristate = <TEGRA_PIN_ENABLE>; 146 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 147 }; 148 }; 149 150 pex_rst_c6_in_state: pinmux-pex-rst-c6-in { 151 pex_rst { 152 nvidia,pins = "pex_l6_rst_n_paf3"; 153 nvidia,function = "rsvd1"; 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 155 nvidia,tristate = <TEGRA_PIN_ENABLE>; 156 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 157 }; 158 }; 159 160 pex_rst_c7_in_state: pinmux-pex-rst-c7-in { 161 pex_rst { 162 nvidia,pins = "pex_l7_rst_n_pag1"; 163 nvidia,function = "rsvd1"; 164 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 165 nvidia,tristate = <TEGRA_PIN_ENABLE>; 166 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 167 }; 168 }; 169 170 pex_rst_c10_in_state: pinmux-pex-rst-c10-in { 171 pex_rst { 172 nvidia,pins = "pex_l10_rst_n_pag7"; 173 nvidia,function = "rsvd1"; 174 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 175 nvidia,tristate = <TEGRA_PIN_ENABLE>; 176 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 177 }; 178 }; 179 }; 180 181 gpcdma: dma-controller@2600000 { 182 compatible = "nvidia,tegra234-gpcdma", 183 "nvidia,tegra186-gpcdma"; 184 reg = <0x0 0x2600000 0x0 0x210000>; 185 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 186 reset-names = "gpcdma"; 187 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 219 #dma-cells = <1>; 220 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 221 dma-channel-mask = <0xfffffffe>; 222 dma-coherent; 223 }; 224 225 aconnect@2900000 { 226 compatible = "nvidia,tegra234-aconnect", 227 "nvidia,tegra210-aconnect"; 228 clocks = <&bpmp TEGRA234_CLK_APE>, 229 <&bpmp TEGRA234_CLK_APB2APE>; 230 clock-names = "ape", "apb2ape"; 231 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 232 status = "disabled"; 233 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 237 238 tegra_ahub: ahub@2900800 { 239 compatible = "nvidia,tegra234-ahub"; 240 reg = <0x0 0x02900800 0x0 0x800>; 241 clocks = <&bpmp TEGRA234_CLK_AHUB>; 242 clock-names = "ahub"; 243 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 244 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 245 assigned-clock-rates = <81600000>; 246 status = "disabled"; 247 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0x02900000 0x0 0x02900000 0x20000>; 251 252 tegra_i2s1: i2s@2901000 { 253 compatible = "nvidia,tegra234-i2s", 254 "nvidia,tegra210-i2s"; 255 reg = <0x2901000 0x100>; 256 clocks = <&bpmp TEGRA234_CLK_I2S1>, 257 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 258 clock-names = "i2s", "sync_input"; 259 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 260 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 261 assigned-clock-rates = <1536000>; 262 sound-name-prefix = "I2S1"; 263 status = "disabled"; 264 265 ports { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 port@0 { 270 reg = <0>; 271 272 i2s1_cif: endpoint { 273 remote-endpoint = <&xbar_i2s1>; 274 }; 275 }; 276 277 i2s1_port: port@1 { 278 reg = <1>; 279 280 i2s1_dap: endpoint { 281 dai-format = "i2s"; 282 /* placeholder for external codec */ 283 }; 284 }; 285 }; 286 }; 287 288 tegra_i2s2: i2s@2901100 { 289 compatible = "nvidia,tegra234-i2s", 290 "nvidia,tegra210-i2s"; 291 reg = <0x2901100 0x100>; 292 clocks = <&bpmp TEGRA234_CLK_I2S2>, 293 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 294 clock-names = "i2s", "sync_input"; 295 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 296 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 297 assigned-clock-rates = <1536000>; 298 sound-name-prefix = "I2S2"; 299 status = "disabled"; 300 301 ports { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 port@0 { 306 reg = <0>; 307 308 i2s2_cif: endpoint { 309 remote-endpoint = <&xbar_i2s2>; 310 }; 311 }; 312 313 i2s2_port: port@1 { 314 reg = <1>; 315 316 i2s2_dap: endpoint { 317 dai-format = "i2s"; 318 /* placeholder for external codec */ 319 }; 320 }; 321 }; 322 }; 323 324 tegra_i2s3: i2s@2901200 { 325 compatible = "nvidia,tegra234-i2s", 326 "nvidia,tegra210-i2s"; 327 reg = <0x2901200 0x100>; 328 clocks = <&bpmp TEGRA234_CLK_I2S3>, 329 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 330 clock-names = "i2s", "sync_input"; 331 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 332 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 333 assigned-clock-rates = <1536000>; 334 sound-name-prefix = "I2S3"; 335 status = "disabled"; 336 337 ports { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 port@0 { 342 reg = <0>; 343 344 i2s3_cif: endpoint { 345 remote-endpoint = <&xbar_i2s3>; 346 }; 347 }; 348 349 i2s3_port: port@1 { 350 reg = <1>; 351 352 i2s3_dap: endpoint { 353 dai-format = "i2s"; 354 /* placeholder for external codec */ 355 }; 356 }; 357 }; 358 }; 359 360 tegra_i2s4: i2s@2901300 { 361 compatible = "nvidia,tegra234-i2s", 362 "nvidia,tegra210-i2s"; 363 reg = <0x2901300 0x100>; 364 clocks = <&bpmp TEGRA234_CLK_I2S4>, 365 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 366 clock-names = "i2s", "sync_input"; 367 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 368 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 369 assigned-clock-rates = <1536000>; 370 sound-name-prefix = "I2S4"; 371 status = "disabled"; 372 373 ports { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 377 port@0 { 378 reg = <0>; 379 380 i2s4_cif: endpoint { 381 remote-endpoint = <&xbar_i2s4>; 382 }; 383 }; 384 385 i2s4_port: port@1 { 386 reg = <1>; 387 388 i2s4_dap: endpoint { 389 dai-format = "i2s"; 390 /* placeholder for external codec */ 391 }; 392 }; 393 }; 394 }; 395 396 tegra_i2s5: i2s@2901400 { 397 compatible = "nvidia,tegra234-i2s", 398 "nvidia,tegra210-i2s"; 399 reg = <0x2901400 0x100>; 400 clocks = <&bpmp TEGRA234_CLK_I2S5>, 401 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 402 clock-names = "i2s", "sync_input"; 403 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 404 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 405 assigned-clock-rates = <1536000>; 406 sound-name-prefix = "I2S5"; 407 status = "disabled"; 408 409 ports { 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 port@0 { 414 reg = <0>; 415 416 i2s5_cif: endpoint { 417 remote-endpoint = <&xbar_i2s5>; 418 }; 419 }; 420 421 i2s5_port: port@1 { 422 reg = <1>; 423 424 i2s5_dap: endpoint { 425 dai-format = "i2s"; 426 /* placeholder for external codec */ 427 }; 428 }; 429 }; 430 }; 431 432 tegra_i2s6: i2s@2901500 { 433 compatible = "nvidia,tegra234-i2s", 434 "nvidia,tegra210-i2s"; 435 reg = <0x2901500 0x100>; 436 clocks = <&bpmp TEGRA234_CLK_I2S6>, 437 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 438 clock-names = "i2s", "sync_input"; 439 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 440 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 441 assigned-clock-rates = <1536000>; 442 sound-name-prefix = "I2S6"; 443 status = "disabled"; 444 445 ports { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 449 port@0 { 450 reg = <0>; 451 452 i2s6_cif: endpoint { 453 remote-endpoint = <&xbar_i2s6>; 454 }; 455 }; 456 457 i2s6_port: port@1 { 458 reg = <1>; 459 460 i2s6_dap: endpoint { 461 dai-format = "i2s"; 462 /* placeholder for external codec */ 463 }; 464 }; 465 }; 466 }; 467 468 tegra_sfc1: sfc@2902000 { 469 compatible = "nvidia,tegra234-sfc", 470 "nvidia,tegra210-sfc"; 471 reg = <0x2902000 0x200>; 472 sound-name-prefix = "SFC1"; 473 474 ports { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 478 port@0 { 479 reg = <0>; 480 481 sfc1_cif_in: endpoint { 482 remote-endpoint = <&xbar_sfc1_in>; 483 }; 484 }; 485 486 sfc1_out_port: port@1 { 487 reg = <1>; 488 489 sfc1_cif_out: endpoint { 490 remote-endpoint = <&xbar_sfc1_out>; 491 }; 492 }; 493 }; 494 }; 495 496 tegra_sfc2: sfc@2902200 { 497 compatible = "nvidia,tegra234-sfc", 498 "nvidia,tegra210-sfc"; 499 reg = <0x2902200 0x200>; 500 sound-name-prefix = "SFC2"; 501 502 ports { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 port@0 { 507 reg = <0>; 508 509 sfc2_cif_in: endpoint { 510 remote-endpoint = <&xbar_sfc2_in>; 511 }; 512 }; 513 514 sfc2_out_port: port@1 { 515 reg = <1>; 516 517 sfc2_cif_out: endpoint { 518 remote-endpoint = <&xbar_sfc2_out>; 519 }; 520 }; 521 }; 522 }; 523 524 tegra_sfc3: sfc@2902400 { 525 compatible = "nvidia,tegra234-sfc", 526 "nvidia,tegra210-sfc"; 527 reg = <0x2902400 0x200>; 528 sound-name-prefix = "SFC3"; 529 530 ports { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 534 port@0 { 535 reg = <0>; 536 537 sfc3_cif_in: endpoint { 538 remote-endpoint = <&xbar_sfc3_in>; 539 }; 540 }; 541 542 sfc3_out_port: port@1 { 543 reg = <1>; 544 545 sfc3_cif_out: endpoint { 546 remote-endpoint = <&xbar_sfc3_out>; 547 }; 548 }; 549 }; 550 }; 551 552 tegra_sfc4: sfc@2902600 { 553 compatible = "nvidia,tegra234-sfc", 554 "nvidia,tegra210-sfc"; 555 reg = <0x2902600 0x200>; 556 sound-name-prefix = "SFC4"; 557 558 ports { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 562 port@0 { 563 reg = <0>; 564 565 sfc4_cif_in: endpoint { 566 remote-endpoint = <&xbar_sfc4_in>; 567 }; 568 }; 569 570 sfc4_out_port: port@1 { 571 reg = <1>; 572 573 sfc4_cif_out: endpoint { 574 remote-endpoint = <&xbar_sfc4_out>; 575 }; 576 }; 577 }; 578 }; 579 580 tegra_amx1: amx@2903000 { 581 compatible = "nvidia,tegra234-amx", 582 "nvidia,tegra194-amx"; 583 reg = <0x2903000 0x100>; 584 sound-name-prefix = "AMX1"; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 590 port@0 { 591 reg = <0>; 592 593 amx1_in1: endpoint { 594 remote-endpoint = <&xbar_amx1_in1>; 595 }; 596 }; 597 598 port@1 { 599 reg = <1>; 600 601 amx1_in2: endpoint { 602 remote-endpoint = <&xbar_amx1_in2>; 603 }; 604 }; 605 606 port@2 { 607 reg = <2>; 608 609 amx1_in3: endpoint { 610 remote-endpoint = <&xbar_amx1_in3>; 611 }; 612 }; 613 614 port@3 { 615 reg = <3>; 616 617 amx1_in4: endpoint { 618 remote-endpoint = <&xbar_amx1_in4>; 619 }; 620 }; 621 622 amx1_out_port: port@4 { 623 reg = <4>; 624 625 amx1_out: endpoint { 626 remote-endpoint = <&xbar_amx1_out>; 627 }; 628 }; 629 }; 630 }; 631 632 tegra_amx2: amx@2903100 { 633 compatible = "nvidia,tegra234-amx", 634 "nvidia,tegra194-amx"; 635 reg = <0x2903100 0x100>; 636 sound-name-prefix = "AMX2"; 637 638 ports { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 port@0 { 643 reg = <0>; 644 645 amx2_in1: endpoint { 646 remote-endpoint = <&xbar_amx2_in1>; 647 }; 648 }; 649 650 port@1 { 651 reg = <1>; 652 653 amx2_in2: endpoint { 654 remote-endpoint = <&xbar_amx2_in2>; 655 }; 656 }; 657 658 port@2 { 659 reg = <2>; 660 661 amx2_in3: endpoint { 662 remote-endpoint = <&xbar_amx2_in3>; 663 }; 664 }; 665 666 port@3 { 667 reg = <3>; 668 669 amx2_in4: endpoint { 670 remote-endpoint = <&xbar_amx2_in4>; 671 }; 672 }; 673 674 amx2_out_port: port@4 { 675 reg = <4>; 676 677 amx2_out: endpoint { 678 remote-endpoint = <&xbar_amx2_out>; 679 }; 680 }; 681 }; 682 }; 683 684 tegra_amx3: amx@2903200 { 685 compatible = "nvidia,tegra234-amx", 686 "nvidia,tegra194-amx"; 687 reg = <0x2903200 0x100>; 688 sound-name-prefix = "AMX3"; 689 690 ports { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 port@0 { 695 reg = <0>; 696 697 amx3_in1: endpoint { 698 remote-endpoint = <&xbar_amx3_in1>; 699 }; 700 }; 701 702 port@1 { 703 reg = <1>; 704 705 amx3_in2: endpoint { 706 remote-endpoint = <&xbar_amx3_in2>; 707 }; 708 }; 709 710 port@2 { 711 reg = <2>; 712 713 amx3_in3: endpoint { 714 remote-endpoint = <&xbar_amx3_in3>; 715 }; 716 }; 717 718 port@3 { 719 reg = <3>; 720 721 amx3_in4: endpoint { 722 remote-endpoint = <&xbar_amx3_in4>; 723 }; 724 }; 725 726 amx3_out_port: port@4 { 727 reg = <4>; 728 729 amx3_out: endpoint { 730 remote-endpoint = <&xbar_amx3_out>; 731 }; 732 }; 733 }; 734 }; 735 736 tegra_amx4: amx@2903300 { 737 compatible = "nvidia,tegra234-amx", 738 "nvidia,tegra194-amx"; 739 reg = <0x2903300 0x100>; 740 sound-name-prefix = "AMX4"; 741 742 ports { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 746 port@0 { 747 reg = <0>; 748 749 amx4_in1: endpoint { 750 remote-endpoint = <&xbar_amx4_in1>; 751 }; 752 }; 753 754 port@1 { 755 reg = <1>; 756 757 amx4_in2: endpoint { 758 remote-endpoint = <&xbar_amx4_in2>; 759 }; 760 }; 761 762 port@2 { 763 reg = <2>; 764 765 amx4_in3: endpoint { 766 remote-endpoint = <&xbar_amx4_in3>; 767 }; 768 }; 769 770 port@3 { 771 reg = <3>; 772 773 amx4_in4: endpoint { 774 remote-endpoint = <&xbar_amx4_in4>; 775 }; 776 }; 777 778 amx4_out_port: port@4 { 779 reg = <4>; 780 781 amx4_out: endpoint { 782 remote-endpoint = <&xbar_amx4_out>; 783 }; 784 }; 785 }; 786 }; 787 788 tegra_adx1: adx@2903800 { 789 compatible = "nvidia,tegra234-adx", 790 "nvidia,tegra210-adx"; 791 reg = <0x2903800 0x100>; 792 sound-name-prefix = "ADX1"; 793 794 ports { 795 #address-cells = <1>; 796 #size-cells = <0>; 797 798 port@0 { 799 reg = <0>; 800 801 adx1_in: endpoint { 802 remote-endpoint = <&xbar_adx1_in>; 803 }; 804 }; 805 806 adx1_out1_port: port@1 { 807 reg = <1>; 808 809 adx1_out1: endpoint { 810 remote-endpoint = <&xbar_adx1_out1>; 811 }; 812 }; 813 814 adx1_out2_port: port@2 { 815 reg = <2>; 816 817 adx1_out2: endpoint { 818 remote-endpoint = <&xbar_adx1_out2>; 819 }; 820 }; 821 822 adx1_out3_port: port@3 { 823 reg = <3>; 824 825 adx1_out3: endpoint { 826 remote-endpoint = <&xbar_adx1_out3>; 827 }; 828 }; 829 830 adx1_out4_port: port@4 { 831 reg = <4>; 832 833 adx1_out4: endpoint { 834 remote-endpoint = <&xbar_adx1_out4>; 835 }; 836 }; 837 }; 838 }; 839 840 tegra_adx2: adx@2903900 { 841 compatible = "nvidia,tegra234-adx", 842 "nvidia,tegra210-adx"; 843 reg = <0x2903900 0x100>; 844 sound-name-prefix = "ADX2"; 845 846 ports { 847 #address-cells = <1>; 848 #size-cells = <0>; 849 850 port@0 { 851 reg = <0>; 852 853 adx2_in: endpoint { 854 remote-endpoint = <&xbar_adx2_in>; 855 }; 856 }; 857 858 adx2_out1_port: port@1 { 859 reg = <1>; 860 861 adx2_out1: endpoint { 862 remote-endpoint = <&xbar_adx2_out1>; 863 }; 864 }; 865 866 adx2_out2_port: port@2 { 867 reg = <2>; 868 869 adx2_out2: endpoint { 870 remote-endpoint = <&xbar_adx2_out2>; 871 }; 872 }; 873 874 adx2_out3_port: port@3 { 875 reg = <3>; 876 877 adx2_out3: endpoint { 878 remote-endpoint = <&xbar_adx2_out3>; 879 }; 880 }; 881 882 adx2_out4_port: port@4 { 883 reg = <4>; 884 885 adx2_out4: endpoint { 886 remote-endpoint = <&xbar_adx2_out4>; 887 }; 888 }; 889 }; 890 }; 891 892 tegra_adx3: adx@2903a00 { 893 compatible = "nvidia,tegra234-adx", 894 "nvidia,tegra210-adx"; 895 reg = <0x2903a00 0x100>; 896 sound-name-prefix = "ADX3"; 897 898 ports { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 902 port@0 { 903 reg = <0>; 904 905 adx3_in: endpoint { 906 remote-endpoint = <&xbar_adx3_in>; 907 }; 908 }; 909 910 adx3_out1_port: port@1 { 911 reg = <1>; 912 913 adx3_out1: endpoint { 914 remote-endpoint = <&xbar_adx3_out1>; 915 }; 916 }; 917 918 adx3_out2_port: port@2 { 919 reg = <2>; 920 921 adx3_out2: endpoint { 922 remote-endpoint = <&xbar_adx3_out2>; 923 }; 924 }; 925 926 adx3_out3_port: port@3 { 927 reg = <3>; 928 929 adx3_out3: endpoint { 930 remote-endpoint = <&xbar_adx3_out3>; 931 }; 932 }; 933 934 adx3_out4_port: port@4 { 935 reg = <4>; 936 937 adx3_out4: endpoint { 938 remote-endpoint = <&xbar_adx3_out4>; 939 }; 940 }; 941 }; 942 }; 943 944 tegra_adx4: adx@2903b00 { 945 compatible = "nvidia,tegra234-adx", 946 "nvidia,tegra210-adx"; 947 reg = <0x2903b00 0x100>; 948 sound-name-prefix = "ADX4"; 949 950 ports { 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 port@0 { 955 reg = <0>; 956 957 adx4_in: endpoint { 958 remote-endpoint = <&xbar_adx4_in>; 959 }; 960 }; 961 962 adx4_out1_port: port@1 { 963 reg = <1>; 964 965 adx4_out1: endpoint { 966 remote-endpoint = <&xbar_adx4_out1>; 967 }; 968 }; 969 970 adx4_out2_port: port@2 { 971 reg = <2>; 972 973 adx4_out2: endpoint { 974 remote-endpoint = <&xbar_adx4_out2>; 975 }; 976 }; 977 978 adx4_out3_port: port@3 { 979 reg = <3>; 980 981 adx4_out3: endpoint { 982 remote-endpoint = <&xbar_adx4_out3>; 983 }; 984 }; 985 986 adx4_out4_port: port@4 { 987 reg = <4>; 988 989 adx4_out4: endpoint { 990 remote-endpoint = <&xbar_adx4_out4>; 991 }; 992 }; 993 }; 994 }; 995 996 997 tegra_dmic1: dmic@2904000 { 998 compatible = "nvidia,tegra234-dmic", 999 "nvidia,tegra210-dmic"; 1000 reg = <0x2904000 0x100>; 1001 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 1002 clock-names = "dmic"; 1003 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 1004 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1005 assigned-clock-rates = <3072000>; 1006 sound-name-prefix = "DMIC1"; 1007 status = "disabled"; 1008 1009 ports { 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 1013 port@0 { 1014 reg = <0>; 1015 1016 dmic1_cif: endpoint { 1017 remote-endpoint = <&xbar_dmic1>; 1018 }; 1019 }; 1020 1021 dmic1_port: port@1 { 1022 reg = <1>; 1023 1024 dmic1_dap: endpoint { 1025 /* placeholder for external codec */ 1026 }; 1027 }; 1028 }; 1029 }; 1030 1031 tegra_dmic2: dmic@2904100 { 1032 compatible = "nvidia,tegra234-dmic", 1033 "nvidia,tegra210-dmic"; 1034 reg = <0x2904100 0x100>; 1035 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 1036 clock-names = "dmic"; 1037 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 1038 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1039 assigned-clock-rates = <3072000>; 1040 sound-name-prefix = "DMIC2"; 1041 status = "disabled"; 1042 1043 ports { 1044 #address-cells = <1>; 1045 #size-cells = <0>; 1046 1047 port@0 { 1048 reg = <0>; 1049 1050 dmic2_cif: endpoint { 1051 remote-endpoint = <&xbar_dmic2>; 1052 }; 1053 }; 1054 1055 dmic2_port: port@1 { 1056 reg = <1>; 1057 1058 dmic2_dap: endpoint { 1059 /* placeholder for external codec */ 1060 }; 1061 }; 1062 }; 1063 }; 1064 1065 tegra_dmic3: dmic@2904200 { 1066 compatible = "nvidia,tegra234-dmic", 1067 "nvidia,tegra210-dmic"; 1068 reg = <0x2904200 0x100>; 1069 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1070 clock-names = "dmic"; 1071 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1072 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1073 assigned-clock-rates = <3072000>; 1074 sound-name-prefix = "DMIC3"; 1075 status = "disabled"; 1076 1077 ports { 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 1081 port@0 { 1082 reg = <0>; 1083 1084 dmic3_cif: endpoint { 1085 remote-endpoint = <&xbar_dmic3>; 1086 }; 1087 }; 1088 1089 dmic3_port: port@1 { 1090 reg = <1>; 1091 1092 dmic3_dap: endpoint { 1093 /* placeholder for external codec */ 1094 }; 1095 }; 1096 }; 1097 }; 1098 1099 tegra_dmic4: dmic@2904300 { 1100 compatible = "nvidia,tegra234-dmic", 1101 "nvidia,tegra210-dmic"; 1102 reg = <0x2904300 0x100>; 1103 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1104 clock-names = "dmic"; 1105 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1106 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1107 assigned-clock-rates = <3072000>; 1108 sound-name-prefix = "DMIC4"; 1109 status = "disabled"; 1110 1111 ports { 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 port@0 { 1116 reg = <0>; 1117 1118 dmic4_cif: endpoint { 1119 remote-endpoint = <&xbar_dmic4>; 1120 }; 1121 }; 1122 1123 dmic4_port: port@1 { 1124 reg = <1>; 1125 1126 dmic4_dap: endpoint { 1127 /* placeholder for external codec */ 1128 }; 1129 }; 1130 }; 1131 }; 1132 1133 tegra_dspk1: dspk@2905000 { 1134 compatible = "nvidia,tegra234-dspk", 1135 "nvidia,tegra186-dspk"; 1136 reg = <0x2905000 0x100>; 1137 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1138 clock-names = "dspk"; 1139 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1140 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1141 assigned-clock-rates = <12288000>; 1142 sound-name-prefix = "DSPK1"; 1143 status = "disabled"; 1144 1145 ports { 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 port@0 { 1150 reg = <0>; 1151 1152 dspk1_cif: endpoint { 1153 remote-endpoint = <&xbar_dspk1>; 1154 }; 1155 }; 1156 1157 dspk1_port: port@1 { 1158 reg = <1>; 1159 1160 dspk1_dap: endpoint { 1161 /* placeholder for external codec */ 1162 }; 1163 }; 1164 }; 1165 }; 1166 1167 tegra_dspk2: dspk@2905100 { 1168 compatible = "nvidia,tegra234-dspk", 1169 "nvidia,tegra186-dspk"; 1170 reg = <0x2905100 0x100>; 1171 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1172 clock-names = "dspk"; 1173 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1174 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1175 assigned-clock-rates = <12288000>; 1176 sound-name-prefix = "DSPK2"; 1177 status = "disabled"; 1178 1179 ports { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 port@0 { 1184 reg = <0>; 1185 1186 dspk2_cif: endpoint { 1187 remote-endpoint = <&xbar_dspk2>; 1188 }; 1189 }; 1190 1191 dspk2_port: port@1 { 1192 reg = <1>; 1193 1194 dspk2_dap: endpoint { 1195 /* placeholder for external codec */ 1196 }; 1197 }; 1198 }; 1199 }; 1200 1201 tegra_ope1: processing-engine@2908000 { 1202 compatible = "nvidia,tegra234-ope", 1203 "nvidia,tegra210-ope"; 1204 reg = <0x2908000 0x100>; 1205 sound-name-prefix = "OPE1"; 1206 1207 #address-cells = <1>; 1208 #size-cells = <1>; 1209 ranges; 1210 1211 equalizer@2908100 { 1212 compatible = "nvidia,tegra234-peq", 1213 "nvidia,tegra210-peq"; 1214 reg = <0x2908100 0x100>; 1215 }; 1216 1217 dynamic-range-compressor@2908200 { 1218 compatible = "nvidia,tegra234-mbdrc", 1219 "nvidia,tegra210-mbdrc"; 1220 reg = <0x2908200 0x200>; 1221 }; 1222 1223 ports { 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 port@0 { 1228 reg = <0x0>; 1229 1230 ope1_cif_in_ep: endpoint { 1231 remote-endpoint = 1232 <&xbar_ope1_in_ep>; 1233 }; 1234 }; 1235 1236 ope1_out_port: port@1 { 1237 reg = <0x1>; 1238 1239 ope1_cif_out_ep: endpoint { 1240 remote-endpoint = 1241 <&xbar_ope1_out_ep>; 1242 }; 1243 }; 1244 }; 1245 }; 1246 1247 tegra_mvc1: mvc@290a000 { 1248 compatible = "nvidia,tegra234-mvc", 1249 "nvidia,tegra210-mvc"; 1250 reg = <0x290a000 0x200>; 1251 sound-name-prefix = "MVC1"; 1252 1253 ports { 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 1257 port@0 { 1258 reg = <0>; 1259 1260 mvc1_cif_in: endpoint { 1261 remote-endpoint = <&xbar_mvc1_in>; 1262 }; 1263 }; 1264 1265 mvc1_out_port: port@1 { 1266 reg = <1>; 1267 1268 mvc1_cif_out: endpoint { 1269 remote-endpoint = <&xbar_mvc1_out>; 1270 }; 1271 }; 1272 }; 1273 }; 1274 1275 tegra_mvc2: mvc@290a200 { 1276 compatible = "nvidia,tegra234-mvc", 1277 "nvidia,tegra210-mvc"; 1278 reg = <0x290a200 0x200>; 1279 sound-name-prefix = "MVC2"; 1280 1281 ports { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 1285 port@0 { 1286 reg = <0>; 1287 1288 mvc2_cif_in: endpoint { 1289 remote-endpoint = <&xbar_mvc2_in>; 1290 }; 1291 }; 1292 1293 mvc2_out_port: port@1 { 1294 reg = <1>; 1295 1296 mvc2_cif_out: endpoint { 1297 remote-endpoint = <&xbar_mvc2_out>; 1298 }; 1299 }; 1300 }; 1301 }; 1302 1303 tegra_amixer: amixer@290bb00 { 1304 compatible = "nvidia,tegra234-amixer", 1305 "nvidia,tegra210-amixer"; 1306 reg = <0x290bb00 0x800>; 1307 sound-name-prefix = "MIXER1"; 1308 1309 ports { 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 1313 port@0 { 1314 reg = <0x0>; 1315 1316 mix_in1: endpoint { 1317 remote-endpoint = <&xbar_mix_in1>; 1318 }; 1319 }; 1320 1321 port@1 { 1322 reg = <0x1>; 1323 1324 mix_in2: endpoint { 1325 remote-endpoint = <&xbar_mix_in2>; 1326 }; 1327 }; 1328 1329 port@2 { 1330 reg = <0x2>; 1331 1332 mix_in3: endpoint { 1333 remote-endpoint = <&xbar_mix_in3>; 1334 }; 1335 }; 1336 1337 port@3 { 1338 reg = <0x3>; 1339 1340 mix_in4: endpoint { 1341 remote-endpoint = <&xbar_mix_in4>; 1342 }; 1343 }; 1344 1345 port@4 { 1346 reg = <0x4>; 1347 1348 mix_in5: endpoint { 1349 remote-endpoint = <&xbar_mix_in5>; 1350 }; 1351 }; 1352 1353 port@5 { 1354 reg = <0x5>; 1355 1356 mix_in6: endpoint { 1357 remote-endpoint = <&xbar_mix_in6>; 1358 }; 1359 }; 1360 1361 port@6 { 1362 reg = <0x6>; 1363 1364 mix_in7: endpoint { 1365 remote-endpoint = <&xbar_mix_in7>; 1366 }; 1367 }; 1368 1369 port@7 { 1370 reg = <0x7>; 1371 1372 mix_in8: endpoint { 1373 remote-endpoint = <&xbar_mix_in8>; 1374 }; 1375 }; 1376 1377 port@8 { 1378 reg = <0x8>; 1379 1380 mix_in9: endpoint { 1381 remote-endpoint = <&xbar_mix_in9>; 1382 }; 1383 }; 1384 1385 port@9 { 1386 reg = <0x9>; 1387 1388 mix_in10: endpoint { 1389 remote-endpoint = <&xbar_mix_in10>; 1390 }; 1391 }; 1392 1393 mix_out1_port: port@a { 1394 reg = <0xa>; 1395 1396 mix_out1: endpoint { 1397 remote-endpoint = <&xbar_mix_out1>; 1398 }; 1399 }; 1400 1401 mix_out2_port: port@b { 1402 reg = <0xb>; 1403 1404 mix_out2: endpoint { 1405 remote-endpoint = <&xbar_mix_out2>; 1406 }; 1407 }; 1408 1409 mix_out3_port: port@c { 1410 reg = <0xc>; 1411 1412 mix_out3: endpoint { 1413 remote-endpoint = <&xbar_mix_out3>; 1414 }; 1415 }; 1416 1417 mix_out4_port: port@d { 1418 reg = <0xd>; 1419 1420 mix_out4: endpoint { 1421 remote-endpoint = <&xbar_mix_out4>; 1422 }; 1423 }; 1424 1425 mix_out5_port: port@e { 1426 reg = <0xe>; 1427 1428 mix_out5: endpoint { 1429 remote-endpoint = <&xbar_mix_out5>; 1430 }; 1431 }; 1432 }; 1433 }; 1434 1435 tegra_admaif: admaif@290f000 { 1436 compatible = "nvidia,tegra234-admaif", 1437 "nvidia,tegra186-admaif"; 1438 reg = <0x0290f000 0x1000>; 1439 dmas = <&adma 1>, <&adma 1>, 1440 <&adma 2>, <&adma 2>, 1441 <&adma 3>, <&adma 3>, 1442 <&adma 4>, <&adma 4>, 1443 <&adma 5>, <&adma 5>, 1444 <&adma 6>, <&adma 6>, 1445 <&adma 7>, <&adma 7>, 1446 <&adma 8>, <&adma 8>, 1447 <&adma 9>, <&adma 9>, 1448 <&adma 10>, <&adma 10>, 1449 <&adma 11>, <&adma 11>, 1450 <&adma 12>, <&adma 12>, 1451 <&adma 13>, <&adma 13>, 1452 <&adma 14>, <&adma 14>, 1453 <&adma 15>, <&adma 15>, 1454 <&adma 16>, <&adma 16>, 1455 <&adma 17>, <&adma 17>, 1456 <&adma 18>, <&adma 18>, 1457 <&adma 19>, <&adma 19>, 1458 <&adma 20>, <&adma 20>; 1459 dma-names = "rx1", "tx1", 1460 "rx2", "tx2", 1461 "rx3", "tx3", 1462 "rx4", "tx4", 1463 "rx5", "tx5", 1464 "rx6", "tx6", 1465 "rx7", "tx7", 1466 "rx8", "tx8", 1467 "rx9", "tx9", 1468 "rx10", "tx10", 1469 "rx11", "tx11", 1470 "rx12", "tx12", 1471 "rx13", "tx13", 1472 "rx14", "tx14", 1473 "rx15", "tx15", 1474 "rx16", "tx16", 1475 "rx17", "tx17", 1476 "rx18", "tx18", 1477 "rx19", "tx19", 1478 "rx20", "tx20"; 1479 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 1480 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 1481 interconnect-names = "dma-mem", "write"; 1482 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 1483 1484 ports { 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 1488 admaif0_port: port@0 { 1489 reg = <0x0>; 1490 1491 admaif0: endpoint { 1492 remote-endpoint = <&xbar_admaif0>; 1493 }; 1494 }; 1495 1496 admaif1_port: port@1 { 1497 reg = <0x1>; 1498 1499 admaif1: endpoint { 1500 remote-endpoint = <&xbar_admaif1>; 1501 }; 1502 }; 1503 1504 admaif2_port: port@2 { 1505 reg = <0x2>; 1506 1507 admaif2: endpoint { 1508 remote-endpoint = <&xbar_admaif2>; 1509 }; 1510 }; 1511 1512 admaif3_port: port@3 { 1513 reg = <0x3>; 1514 1515 admaif3: endpoint { 1516 remote-endpoint = <&xbar_admaif3>; 1517 }; 1518 }; 1519 1520 admaif4_port: port@4 { 1521 reg = <0x4>; 1522 1523 admaif4: endpoint { 1524 remote-endpoint = <&xbar_admaif4>; 1525 }; 1526 }; 1527 1528 admaif5_port: port@5 { 1529 reg = <0x5>; 1530 1531 admaif5: endpoint { 1532 remote-endpoint = <&xbar_admaif5>; 1533 }; 1534 }; 1535 1536 admaif6_port: port@6 { 1537 reg = <0x6>; 1538 1539 admaif6: endpoint { 1540 remote-endpoint = <&xbar_admaif6>; 1541 }; 1542 }; 1543 1544 admaif7_port: port@7 { 1545 reg = <0x7>; 1546 1547 admaif7: endpoint { 1548 remote-endpoint = <&xbar_admaif7>; 1549 }; 1550 }; 1551 1552 admaif8_port: port@8 { 1553 reg = <0x8>; 1554 1555 admaif8: endpoint { 1556 remote-endpoint = <&xbar_admaif8>; 1557 }; 1558 }; 1559 1560 admaif9_port: port@9 { 1561 reg = <0x9>; 1562 1563 admaif9: endpoint { 1564 remote-endpoint = <&xbar_admaif9>; 1565 }; 1566 }; 1567 1568 admaif10_port: port@a { 1569 reg = <0xa>; 1570 1571 admaif10: endpoint { 1572 remote-endpoint = <&xbar_admaif10>; 1573 }; 1574 }; 1575 1576 admaif11_port: port@b { 1577 reg = <0xb>; 1578 1579 admaif11: endpoint { 1580 remote-endpoint = <&xbar_admaif11>; 1581 }; 1582 }; 1583 1584 admaif12_port: port@c { 1585 reg = <0xc>; 1586 1587 admaif12: endpoint { 1588 remote-endpoint = <&xbar_admaif12>; 1589 }; 1590 }; 1591 1592 admaif13_port: port@d { 1593 reg = <0xd>; 1594 1595 admaif13: endpoint { 1596 remote-endpoint = <&xbar_admaif13>; 1597 }; 1598 }; 1599 1600 admaif14_port: port@e { 1601 reg = <0xe>; 1602 1603 admaif14: endpoint { 1604 remote-endpoint = <&xbar_admaif14>; 1605 }; 1606 }; 1607 1608 admaif15_port: port@f { 1609 reg = <0xf>; 1610 1611 admaif15: endpoint { 1612 remote-endpoint = <&xbar_admaif15>; 1613 }; 1614 }; 1615 1616 admaif16_port: port@10 { 1617 reg = <0x10>; 1618 1619 admaif16: endpoint { 1620 remote-endpoint = <&xbar_admaif16>; 1621 }; 1622 }; 1623 1624 admaif17_port: port@11 { 1625 reg = <0x11>; 1626 1627 admaif17: endpoint { 1628 remote-endpoint = <&xbar_admaif17>; 1629 }; 1630 }; 1631 1632 admaif18_port: port@12 { 1633 reg = <0x12>; 1634 1635 admaif18: endpoint { 1636 remote-endpoint = <&xbar_admaif18>; 1637 }; 1638 }; 1639 1640 admaif19_port: port@13 { 1641 reg = <0x13>; 1642 1643 admaif19: endpoint { 1644 remote-endpoint = <&xbar_admaif19>; 1645 }; 1646 }; 1647 }; 1648 }; 1649 1650 tegra_asrc: asrc@2910000 { 1651 compatible = "nvidia,tegra234-asrc", 1652 "nvidia,tegra186-asrc"; 1653 reg = <0x2910000 0x2000>; 1654 sound-name-prefix = "ASRC1"; 1655 1656 ports { 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 port@0 { 1661 reg = <0x0>; 1662 1663 asrc_in1_ep: endpoint { 1664 remote-endpoint = 1665 <&xbar_asrc_in1_ep>; 1666 }; 1667 }; 1668 1669 port@1 { 1670 reg = <0x1>; 1671 1672 asrc_in2_ep: endpoint { 1673 remote-endpoint = 1674 <&xbar_asrc_in2_ep>; 1675 }; 1676 }; 1677 1678 port@2 { 1679 reg = <0x2>; 1680 1681 asrc_in3_ep: endpoint { 1682 remote-endpoint = 1683 <&xbar_asrc_in3_ep>; 1684 }; 1685 }; 1686 1687 port@3 { 1688 reg = <0x3>; 1689 1690 asrc_in4_ep: endpoint { 1691 remote-endpoint = 1692 <&xbar_asrc_in4_ep>; 1693 }; 1694 }; 1695 1696 port@4 { 1697 reg = <0x4>; 1698 1699 asrc_in5_ep: endpoint { 1700 remote-endpoint = 1701 <&xbar_asrc_in5_ep>; 1702 }; 1703 }; 1704 1705 port@5 { 1706 reg = <0x5>; 1707 1708 asrc_in6_ep: endpoint { 1709 remote-endpoint = 1710 <&xbar_asrc_in6_ep>; 1711 }; 1712 }; 1713 1714 port@6 { 1715 reg = <0x6>; 1716 1717 asrc_in7_ep: endpoint { 1718 remote-endpoint = 1719 <&xbar_asrc_in7_ep>; 1720 }; 1721 }; 1722 1723 asrc_out1_port: port@7 { 1724 reg = <0x7>; 1725 1726 asrc_out1_ep: endpoint { 1727 remote-endpoint = 1728 <&xbar_asrc_out1_ep>; 1729 }; 1730 }; 1731 1732 asrc_out2_port: port@8 { 1733 reg = <0x8>; 1734 1735 asrc_out2_ep: endpoint { 1736 remote-endpoint = 1737 <&xbar_asrc_out2_ep>; 1738 }; 1739 }; 1740 1741 asrc_out3_port: port@9 { 1742 reg = <0x9>; 1743 1744 asrc_out3_ep: endpoint { 1745 remote-endpoint = 1746 <&xbar_asrc_out3_ep>; 1747 }; 1748 }; 1749 1750 asrc_out4_port: port@a { 1751 reg = <0xa>; 1752 1753 asrc_out4_ep: endpoint { 1754 remote-endpoint = 1755 <&xbar_asrc_out4_ep>; 1756 }; 1757 }; 1758 1759 asrc_out5_port: port@b { 1760 reg = <0xb>; 1761 1762 asrc_out5_ep: endpoint { 1763 remote-endpoint = 1764 <&xbar_asrc_out5_ep>; 1765 }; 1766 }; 1767 1768 asrc_out6_port: port@c { 1769 reg = <0xc>; 1770 1771 asrc_out6_ep: endpoint { 1772 remote-endpoint = 1773 <&xbar_asrc_out6_ep>; 1774 }; 1775 }; 1776 }; 1777 }; 1778 1779 ports { 1780 #address-cells = <1>; 1781 #size-cells = <0>; 1782 1783 port@0 { 1784 reg = <0x0>; 1785 1786 xbar_admaif0: endpoint { 1787 remote-endpoint = <&admaif0>; 1788 }; 1789 }; 1790 1791 port@1 { 1792 reg = <0x1>; 1793 1794 xbar_admaif1: endpoint { 1795 remote-endpoint = <&admaif1>; 1796 }; 1797 }; 1798 1799 port@2 { 1800 reg = <0x2>; 1801 1802 xbar_admaif2: endpoint { 1803 remote-endpoint = <&admaif2>; 1804 }; 1805 }; 1806 1807 port@3 { 1808 reg = <0x3>; 1809 1810 xbar_admaif3: endpoint { 1811 remote-endpoint = <&admaif3>; 1812 }; 1813 }; 1814 1815 port@4 { 1816 reg = <0x4>; 1817 1818 xbar_admaif4: endpoint { 1819 remote-endpoint = <&admaif4>; 1820 }; 1821 }; 1822 1823 port@5 { 1824 reg = <0x5>; 1825 1826 xbar_admaif5: endpoint { 1827 remote-endpoint = <&admaif5>; 1828 }; 1829 }; 1830 1831 port@6 { 1832 reg = <0x6>; 1833 1834 xbar_admaif6: endpoint { 1835 remote-endpoint = <&admaif6>; 1836 }; 1837 }; 1838 1839 port@7 { 1840 reg = <0x7>; 1841 1842 xbar_admaif7: endpoint { 1843 remote-endpoint = <&admaif7>; 1844 }; 1845 }; 1846 1847 port@8 { 1848 reg = <0x8>; 1849 1850 xbar_admaif8: endpoint { 1851 remote-endpoint = <&admaif8>; 1852 }; 1853 }; 1854 1855 port@9 { 1856 reg = <0x9>; 1857 1858 xbar_admaif9: endpoint { 1859 remote-endpoint = <&admaif9>; 1860 }; 1861 }; 1862 1863 port@a { 1864 reg = <0xa>; 1865 1866 xbar_admaif10: endpoint { 1867 remote-endpoint = <&admaif10>; 1868 }; 1869 }; 1870 1871 port@b { 1872 reg = <0xb>; 1873 1874 xbar_admaif11: endpoint { 1875 remote-endpoint = <&admaif11>; 1876 }; 1877 }; 1878 1879 port@c { 1880 reg = <0xc>; 1881 1882 xbar_admaif12: endpoint { 1883 remote-endpoint = <&admaif12>; 1884 }; 1885 }; 1886 1887 port@d { 1888 reg = <0xd>; 1889 1890 xbar_admaif13: endpoint { 1891 remote-endpoint = <&admaif13>; 1892 }; 1893 }; 1894 1895 port@e { 1896 reg = <0xe>; 1897 1898 xbar_admaif14: endpoint { 1899 remote-endpoint = <&admaif14>; 1900 }; 1901 }; 1902 1903 port@f { 1904 reg = <0xf>; 1905 1906 xbar_admaif15: endpoint { 1907 remote-endpoint = <&admaif15>; 1908 }; 1909 }; 1910 1911 port@10 { 1912 reg = <0x10>; 1913 1914 xbar_admaif16: endpoint { 1915 remote-endpoint = <&admaif16>; 1916 }; 1917 }; 1918 1919 port@11 { 1920 reg = <0x11>; 1921 1922 xbar_admaif17: endpoint { 1923 remote-endpoint = <&admaif17>; 1924 }; 1925 }; 1926 1927 port@12 { 1928 reg = <0x12>; 1929 1930 xbar_admaif18: endpoint { 1931 remote-endpoint = <&admaif18>; 1932 }; 1933 }; 1934 1935 port@13 { 1936 reg = <0x13>; 1937 1938 xbar_admaif19: endpoint { 1939 remote-endpoint = <&admaif19>; 1940 }; 1941 }; 1942 1943 xbar_i2s1_port: port@14 { 1944 reg = <0x14>; 1945 1946 xbar_i2s1: endpoint { 1947 remote-endpoint = <&i2s1_cif>; 1948 }; 1949 }; 1950 1951 xbar_i2s2_port: port@15 { 1952 reg = <0x15>; 1953 1954 xbar_i2s2: endpoint { 1955 remote-endpoint = <&i2s2_cif>; 1956 }; 1957 }; 1958 1959 xbar_i2s3_port: port@16 { 1960 reg = <0x16>; 1961 1962 xbar_i2s3: endpoint { 1963 remote-endpoint = <&i2s3_cif>; 1964 }; 1965 }; 1966 1967 xbar_i2s4_port: port@17 { 1968 reg = <0x17>; 1969 1970 xbar_i2s4: endpoint { 1971 remote-endpoint = <&i2s4_cif>; 1972 }; 1973 }; 1974 1975 xbar_i2s5_port: port@18 { 1976 reg = <0x18>; 1977 1978 xbar_i2s5: endpoint { 1979 remote-endpoint = <&i2s5_cif>; 1980 }; 1981 }; 1982 1983 xbar_i2s6_port: port@19 { 1984 reg = <0x19>; 1985 1986 xbar_i2s6: endpoint { 1987 remote-endpoint = <&i2s6_cif>; 1988 }; 1989 }; 1990 1991 xbar_dmic1_port: port@1a { 1992 reg = <0x1a>; 1993 1994 xbar_dmic1: endpoint { 1995 remote-endpoint = <&dmic1_cif>; 1996 }; 1997 }; 1998 1999 xbar_dmic2_port: port@1b { 2000 reg = <0x1b>; 2001 2002 xbar_dmic2: endpoint { 2003 remote-endpoint = <&dmic2_cif>; 2004 }; 2005 }; 2006 2007 xbar_dmic3_port: port@1c { 2008 reg = <0x1c>; 2009 2010 xbar_dmic3: endpoint { 2011 remote-endpoint = <&dmic3_cif>; 2012 }; 2013 }; 2014 2015 xbar_dmic4_port: port@1d { 2016 reg = <0x1d>; 2017 2018 xbar_dmic4: endpoint { 2019 remote-endpoint = <&dmic4_cif>; 2020 }; 2021 }; 2022 2023 xbar_dspk1_port: port@1e { 2024 reg = <0x1e>; 2025 2026 xbar_dspk1: endpoint { 2027 remote-endpoint = <&dspk1_cif>; 2028 }; 2029 }; 2030 2031 xbar_dspk2_port: port@1f { 2032 reg = <0x1f>; 2033 2034 xbar_dspk2: endpoint { 2035 remote-endpoint = <&dspk2_cif>; 2036 }; 2037 }; 2038 2039 xbar_sfc1_in_port: port@20 { 2040 reg = <0x20>; 2041 2042 xbar_sfc1_in: endpoint { 2043 remote-endpoint = <&sfc1_cif_in>; 2044 }; 2045 }; 2046 2047 port@21 { 2048 reg = <0x21>; 2049 2050 xbar_sfc1_out: endpoint { 2051 remote-endpoint = <&sfc1_cif_out>; 2052 }; 2053 }; 2054 2055 xbar_sfc2_in_port: port@22 { 2056 reg = <0x22>; 2057 2058 xbar_sfc2_in: endpoint { 2059 remote-endpoint = <&sfc2_cif_in>; 2060 }; 2061 }; 2062 2063 port@23 { 2064 reg = <0x23>; 2065 2066 xbar_sfc2_out: endpoint { 2067 remote-endpoint = <&sfc2_cif_out>; 2068 }; 2069 }; 2070 2071 xbar_sfc3_in_port: port@24 { 2072 reg = <0x24>; 2073 2074 xbar_sfc3_in: endpoint { 2075 remote-endpoint = <&sfc3_cif_in>; 2076 }; 2077 }; 2078 2079 port@25 { 2080 reg = <0x25>; 2081 2082 xbar_sfc3_out: endpoint { 2083 remote-endpoint = <&sfc3_cif_out>; 2084 }; 2085 }; 2086 2087 xbar_sfc4_in_port: port@26 { 2088 reg = <0x26>; 2089 2090 xbar_sfc4_in: endpoint { 2091 remote-endpoint = <&sfc4_cif_in>; 2092 }; 2093 }; 2094 2095 port@27 { 2096 reg = <0x27>; 2097 2098 xbar_sfc4_out: endpoint { 2099 remote-endpoint = <&sfc4_cif_out>; 2100 }; 2101 }; 2102 2103 xbar_mvc1_in_port: port@28 { 2104 reg = <0x28>; 2105 2106 xbar_mvc1_in: endpoint { 2107 remote-endpoint = <&mvc1_cif_in>; 2108 }; 2109 }; 2110 2111 port@29 { 2112 reg = <0x29>; 2113 2114 xbar_mvc1_out: endpoint { 2115 remote-endpoint = <&mvc1_cif_out>; 2116 }; 2117 }; 2118 2119 xbar_mvc2_in_port: port@2a { 2120 reg = <0x2a>; 2121 2122 xbar_mvc2_in: endpoint { 2123 remote-endpoint = <&mvc2_cif_in>; 2124 }; 2125 }; 2126 2127 port@2b { 2128 reg = <0x2b>; 2129 2130 xbar_mvc2_out: endpoint { 2131 remote-endpoint = <&mvc2_cif_out>; 2132 }; 2133 }; 2134 2135 xbar_amx1_in1_port: port@2c { 2136 reg = <0x2c>; 2137 2138 xbar_amx1_in1: endpoint { 2139 remote-endpoint = <&amx1_in1>; 2140 }; 2141 }; 2142 2143 xbar_amx1_in2_port: port@2d { 2144 reg = <0x2d>; 2145 2146 xbar_amx1_in2: endpoint { 2147 remote-endpoint = <&amx1_in2>; 2148 }; 2149 }; 2150 2151 xbar_amx1_in3_port: port@2e { 2152 reg = <0x2e>; 2153 2154 xbar_amx1_in3: endpoint { 2155 remote-endpoint = <&amx1_in3>; 2156 }; 2157 }; 2158 2159 xbar_amx1_in4_port: port@2f { 2160 reg = <0x2f>; 2161 2162 xbar_amx1_in4: endpoint { 2163 remote-endpoint = <&amx1_in4>; 2164 }; 2165 }; 2166 2167 port@30 { 2168 reg = <0x30>; 2169 2170 xbar_amx1_out: endpoint { 2171 remote-endpoint = <&amx1_out>; 2172 }; 2173 }; 2174 2175 xbar_amx2_in1_port: port@31 { 2176 reg = <0x31>; 2177 2178 xbar_amx2_in1: endpoint { 2179 remote-endpoint = <&amx2_in1>; 2180 }; 2181 }; 2182 2183 xbar_amx2_in2_port: port@32 { 2184 reg = <0x32>; 2185 2186 xbar_amx2_in2: endpoint { 2187 remote-endpoint = <&amx2_in2>; 2188 }; 2189 }; 2190 2191 xbar_amx2_in3_port: port@33 { 2192 reg = <0x33>; 2193 2194 xbar_amx2_in3: endpoint { 2195 remote-endpoint = <&amx2_in3>; 2196 }; 2197 }; 2198 2199 xbar_amx2_in4_port: port@34 { 2200 reg = <0x34>; 2201 2202 xbar_amx2_in4: endpoint { 2203 remote-endpoint = <&amx2_in4>; 2204 }; 2205 }; 2206 2207 port@35 { 2208 reg = <0x35>; 2209 2210 xbar_amx2_out: endpoint { 2211 remote-endpoint = <&amx2_out>; 2212 }; 2213 }; 2214 2215 xbar_amx3_in1_port: port@36 { 2216 reg = <0x36>; 2217 2218 xbar_amx3_in1: endpoint { 2219 remote-endpoint = <&amx3_in1>; 2220 }; 2221 }; 2222 2223 xbar_amx3_in2_port: port@37 { 2224 reg = <0x37>; 2225 2226 xbar_amx3_in2: endpoint { 2227 remote-endpoint = <&amx3_in2>; 2228 }; 2229 }; 2230 2231 xbar_amx3_in3_port: port@38 { 2232 reg = <0x38>; 2233 2234 xbar_amx3_in3: endpoint { 2235 remote-endpoint = <&amx3_in3>; 2236 }; 2237 }; 2238 2239 xbar_amx3_in4_port: port@39 { 2240 reg = <0x39>; 2241 2242 xbar_amx3_in4: endpoint { 2243 remote-endpoint = <&amx3_in4>; 2244 }; 2245 }; 2246 2247 port@3a { 2248 reg = <0x3a>; 2249 2250 xbar_amx3_out: endpoint { 2251 remote-endpoint = <&amx3_out>; 2252 }; 2253 }; 2254 2255 xbar_amx4_in1_port: port@3b { 2256 reg = <0x3b>; 2257 2258 xbar_amx4_in1: endpoint { 2259 remote-endpoint = <&amx4_in1>; 2260 }; 2261 }; 2262 2263 xbar_amx4_in2_port: port@3c { 2264 reg = <0x3c>; 2265 2266 xbar_amx4_in2: endpoint { 2267 remote-endpoint = <&amx4_in2>; 2268 }; 2269 }; 2270 2271 xbar_amx4_in3_port: port@3d { 2272 reg = <0x3d>; 2273 2274 xbar_amx4_in3: endpoint { 2275 remote-endpoint = <&amx4_in3>; 2276 }; 2277 }; 2278 2279 xbar_amx4_in4_port: port@3e { 2280 reg = <0x3e>; 2281 2282 xbar_amx4_in4: endpoint { 2283 remote-endpoint = <&amx4_in4>; 2284 }; 2285 }; 2286 2287 port@3f { 2288 reg = <0x3f>; 2289 2290 xbar_amx4_out: endpoint { 2291 remote-endpoint = <&amx4_out>; 2292 }; 2293 }; 2294 2295 xbar_adx1_in_port: port@40 { 2296 reg = <0x40>; 2297 2298 xbar_adx1_in: endpoint { 2299 remote-endpoint = <&adx1_in>; 2300 }; 2301 }; 2302 2303 port@41 { 2304 reg = <0x41>; 2305 2306 xbar_adx1_out1: endpoint { 2307 remote-endpoint = <&adx1_out1>; 2308 }; 2309 }; 2310 2311 port@42 { 2312 reg = <0x42>; 2313 2314 xbar_adx1_out2: endpoint { 2315 remote-endpoint = <&adx1_out2>; 2316 }; 2317 }; 2318 2319 port@43 { 2320 reg = <0x43>; 2321 2322 xbar_adx1_out3: endpoint { 2323 remote-endpoint = <&adx1_out3>; 2324 }; 2325 }; 2326 2327 port@44 { 2328 reg = <0x44>; 2329 2330 xbar_adx1_out4: endpoint { 2331 remote-endpoint = <&adx1_out4>; 2332 }; 2333 }; 2334 2335 xbar_adx2_in_port: port@45 { 2336 reg = <0x45>; 2337 2338 xbar_adx2_in: endpoint { 2339 remote-endpoint = <&adx2_in>; 2340 }; 2341 }; 2342 2343 port@46 { 2344 reg = <0x46>; 2345 2346 xbar_adx2_out1: endpoint { 2347 remote-endpoint = <&adx2_out1>; 2348 }; 2349 }; 2350 2351 port@47 { 2352 reg = <0x47>; 2353 2354 xbar_adx2_out2: endpoint { 2355 remote-endpoint = <&adx2_out2>; 2356 }; 2357 }; 2358 2359 port@48 { 2360 reg = <0x48>; 2361 2362 xbar_adx2_out3: endpoint { 2363 remote-endpoint = <&adx2_out3>; 2364 }; 2365 }; 2366 2367 port@49 { 2368 reg = <0x49>; 2369 2370 xbar_adx2_out4: endpoint { 2371 remote-endpoint = <&adx2_out4>; 2372 }; 2373 }; 2374 2375 xbar_adx3_in_port: port@4a { 2376 reg = <0x4a>; 2377 2378 xbar_adx3_in: endpoint { 2379 remote-endpoint = <&adx3_in>; 2380 }; 2381 }; 2382 2383 port@4b { 2384 reg = <0x4b>; 2385 2386 xbar_adx3_out1: endpoint { 2387 remote-endpoint = <&adx3_out1>; 2388 }; 2389 }; 2390 2391 port@4c { 2392 reg = <0x4c>; 2393 2394 xbar_adx3_out2: endpoint { 2395 remote-endpoint = <&adx3_out2>; 2396 }; 2397 }; 2398 2399 port@4d { 2400 reg = <0x4d>; 2401 2402 xbar_adx3_out3: endpoint { 2403 remote-endpoint = <&adx3_out3>; 2404 }; 2405 }; 2406 2407 port@4e { 2408 reg = <0x4e>; 2409 2410 xbar_adx3_out4: endpoint { 2411 remote-endpoint = <&adx3_out4>; 2412 }; 2413 }; 2414 2415 xbar_adx4_in_port: port@4f { 2416 reg = <0x4f>; 2417 2418 xbar_adx4_in: endpoint { 2419 remote-endpoint = <&adx4_in>; 2420 }; 2421 }; 2422 2423 port@50 { 2424 reg = <0x50>; 2425 2426 xbar_adx4_out1: endpoint { 2427 remote-endpoint = <&adx4_out1>; 2428 }; 2429 }; 2430 2431 port@51 { 2432 reg = <0x51>; 2433 2434 xbar_adx4_out2: endpoint { 2435 remote-endpoint = <&adx4_out2>; 2436 }; 2437 }; 2438 2439 port@52 { 2440 reg = <0x52>; 2441 2442 xbar_adx4_out3: endpoint { 2443 remote-endpoint = <&adx4_out3>; 2444 }; 2445 }; 2446 2447 port@53 { 2448 reg = <0x53>; 2449 2450 xbar_adx4_out4: endpoint { 2451 remote-endpoint = <&adx4_out4>; 2452 }; 2453 }; 2454 2455 xbar_mix_in1_port: port@54 { 2456 reg = <0x54>; 2457 2458 xbar_mix_in1: endpoint { 2459 remote-endpoint = <&mix_in1>; 2460 }; 2461 }; 2462 2463 xbar_mix_in2_port: port@55 { 2464 reg = <0x55>; 2465 2466 xbar_mix_in2: endpoint { 2467 remote-endpoint = <&mix_in2>; 2468 }; 2469 }; 2470 2471 xbar_mix_in3_port: port@56 { 2472 reg = <0x56>; 2473 2474 xbar_mix_in3: endpoint { 2475 remote-endpoint = <&mix_in3>; 2476 }; 2477 }; 2478 2479 xbar_mix_in4_port: port@57 { 2480 reg = <0x57>; 2481 2482 xbar_mix_in4: endpoint { 2483 remote-endpoint = <&mix_in4>; 2484 }; 2485 }; 2486 2487 xbar_mix_in5_port: port@58 { 2488 reg = <0x58>; 2489 2490 xbar_mix_in5: endpoint { 2491 remote-endpoint = <&mix_in5>; 2492 }; 2493 }; 2494 2495 xbar_mix_in6_port: port@59 { 2496 reg = <0x59>; 2497 2498 xbar_mix_in6: endpoint { 2499 remote-endpoint = <&mix_in6>; 2500 }; 2501 }; 2502 2503 xbar_mix_in7_port: port@5a { 2504 reg = <0x5a>; 2505 2506 xbar_mix_in7: endpoint { 2507 remote-endpoint = <&mix_in7>; 2508 }; 2509 }; 2510 2511 xbar_mix_in8_port: port@5b { 2512 reg = <0x5b>; 2513 2514 xbar_mix_in8: endpoint { 2515 remote-endpoint = <&mix_in8>; 2516 }; 2517 }; 2518 2519 xbar_mix_in9_port: port@5c { 2520 reg = <0x5c>; 2521 2522 xbar_mix_in9: endpoint { 2523 remote-endpoint = <&mix_in9>; 2524 }; 2525 }; 2526 2527 xbar_mix_in10_port: port@5d { 2528 reg = <0x5d>; 2529 2530 xbar_mix_in10: endpoint { 2531 remote-endpoint = <&mix_in10>; 2532 }; 2533 }; 2534 2535 port@5e { 2536 reg = <0x5e>; 2537 2538 xbar_mix_out1: endpoint { 2539 remote-endpoint = <&mix_out1>; 2540 }; 2541 }; 2542 2543 port@5f { 2544 reg = <0x5f>; 2545 2546 xbar_mix_out2: endpoint { 2547 remote-endpoint = <&mix_out2>; 2548 }; 2549 }; 2550 2551 port@60 { 2552 reg = <0x60>; 2553 2554 xbar_mix_out3: endpoint { 2555 remote-endpoint = <&mix_out3>; 2556 }; 2557 }; 2558 2559 port@61 { 2560 reg = <0x61>; 2561 2562 xbar_mix_out4: endpoint { 2563 remote-endpoint = <&mix_out4>; 2564 }; 2565 }; 2566 2567 port@62 { 2568 reg = <0x62>; 2569 2570 xbar_mix_out5: endpoint { 2571 remote-endpoint = <&mix_out5>; 2572 }; 2573 }; 2574 2575 xbar_asrc_in1_port: port@63 { 2576 reg = <0x63>; 2577 2578 xbar_asrc_in1_ep: endpoint { 2579 remote-endpoint = <&asrc_in1_ep>; 2580 }; 2581 }; 2582 2583 port@64 { 2584 reg = <0x64>; 2585 2586 xbar_asrc_out1_ep: endpoint { 2587 remote-endpoint = <&asrc_out1_ep>; 2588 }; 2589 }; 2590 2591 xbar_asrc_in2_port: port@65 { 2592 reg = <0x65>; 2593 2594 xbar_asrc_in2_ep: endpoint { 2595 remote-endpoint = <&asrc_in2_ep>; 2596 }; 2597 }; 2598 2599 port@66 { 2600 reg = <0x66>; 2601 2602 xbar_asrc_out2_ep: endpoint { 2603 remote-endpoint = <&asrc_out2_ep>; 2604 }; 2605 }; 2606 2607 xbar_asrc_in3_port: port@67 { 2608 reg = <0x67>; 2609 2610 xbar_asrc_in3_ep: endpoint { 2611 remote-endpoint = <&asrc_in3_ep>; 2612 }; 2613 }; 2614 2615 port@68 { 2616 reg = <0x68>; 2617 2618 xbar_asrc_out3_ep: endpoint { 2619 remote-endpoint = <&asrc_out3_ep>; 2620 }; 2621 }; 2622 2623 xbar_asrc_in4_port: port@69 { 2624 reg = <0x69>; 2625 2626 xbar_asrc_in4_ep: endpoint { 2627 remote-endpoint = <&asrc_in4_ep>; 2628 }; 2629 }; 2630 2631 port@6a { 2632 reg = <0x6a>; 2633 2634 xbar_asrc_out4_ep: endpoint { 2635 remote-endpoint = <&asrc_out4_ep>; 2636 }; 2637 }; 2638 2639 xbar_asrc_in5_port: port@6b { 2640 reg = <0x6b>; 2641 2642 xbar_asrc_in5_ep: endpoint { 2643 remote-endpoint = <&asrc_in5_ep>; 2644 }; 2645 }; 2646 2647 port@6c { 2648 reg = <0x6c>; 2649 2650 xbar_asrc_out5_ep: endpoint { 2651 remote-endpoint = <&asrc_out5_ep>; 2652 }; 2653 }; 2654 2655 xbar_asrc_in6_port: port@6d { 2656 reg = <0x6d>; 2657 2658 xbar_asrc_in6_ep: endpoint { 2659 remote-endpoint = <&asrc_in6_ep>; 2660 }; 2661 }; 2662 2663 port@6e { 2664 reg = <0x6e>; 2665 2666 xbar_asrc_out6_ep: endpoint { 2667 remote-endpoint = <&asrc_out6_ep>; 2668 }; 2669 }; 2670 2671 xbar_asrc_in7_port: port@6f { 2672 reg = <0x6f>; 2673 2674 xbar_asrc_in7_ep: endpoint { 2675 remote-endpoint = <&asrc_in7_ep>; 2676 }; 2677 }; 2678 2679 xbar_ope1_in_port: port@70 { 2680 reg = <0x70>; 2681 2682 xbar_ope1_in_ep: endpoint { 2683 remote-endpoint = <&ope1_cif_in_ep>; 2684 }; 2685 }; 2686 2687 port@71 { 2688 reg = <0x71>; 2689 2690 xbar_ope1_out_ep: endpoint { 2691 remote-endpoint = <&ope1_cif_out_ep>; 2692 }; 2693 }; 2694 }; 2695 }; 2696 2697 adma: dma-controller@2930000 { 2698 compatible = "nvidia,tegra234-adma", 2699 "nvidia,tegra186-adma"; 2700 reg = <0x0 0x02930000 0x0 0x20000>; 2701 interrupt-parent = <&agic>; 2702 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2729 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2734 #dma-cells = <1>; 2735 clocks = <&bpmp TEGRA234_CLK_AHUB>; 2736 clock-names = "d_audio"; 2737 status = "disabled"; 2738 }; 2739 2740 agic: interrupt-controller@2a40000 { 2741 compatible = "nvidia,tegra234-agic", 2742 "nvidia,tegra210-agic"; 2743 #interrupt-cells = <3>; 2744 interrupt-controller; 2745 reg = <0x0 0x02a41000 0x0 0x1000>, 2746 <0x0 0x02a42000 0x0 0x2000>; 2747 interrupts = <GIC_SPI 145 2748 (GIC_CPU_MASK_SIMPLE(4) | 2749 IRQ_TYPE_LEVEL_HIGH)>; 2750 clocks = <&bpmp TEGRA234_CLK_APE>; 2751 clock-names = "clk"; 2752 status = "disabled"; 2753 }; 2754 }; 2755 2756 mc: memory-controller@2c00000 { 2757 compatible = "nvidia,tegra234-mc"; 2758 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 2759 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 2760 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 2761 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 2762 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 2763 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 2764 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 2765 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 2766 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 2767 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 2768 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 2769 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 2770 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 2771 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 2772 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 2773 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 2774 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 2775 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 2776 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 2777 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 2778 "ch11", "ch12", "ch13", "ch14", "ch15"; 2779 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2780 #interconnect-cells = <1>; 2781 2782 #address-cells = <2>; 2783 #size-cells = <2>; 2784 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 2785 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 2786 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 2787 2788 /* 2789 * Bit 39 of addresses passing through the memory 2790 * controller selects the XBAR format used when memory 2791 * is accessed. This is used to transparently access 2792 * memory in the XBAR format used by the discrete GPU 2793 * (bit 39 set) or Tegra (bit 39 clear). 2794 * 2795 * As a consequence, the operating system must ensure 2796 * that bit 39 is never used implicitly, for example 2797 * via an I/O virtual address mapping of an IOMMU. If 2798 * devices require access to the XBAR switch, their 2799 * drivers must set this bit explicitly. 2800 * 2801 * Limit the DMA range for memory clients to [38:0]. 2802 */ 2803 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 2804 2805 emc: external-memory-controller@2c60000 { 2806 compatible = "nvidia,tegra234-emc"; 2807 reg = <0x0 0x02c60000 0x0 0x90000>, 2808 <0x0 0x01780000 0x0 0x80000>; 2809 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 2810 clocks = <&bpmp TEGRA234_CLK_EMC>; 2811 clock-names = "emc"; 2812 2813 #interconnect-cells = <0>; 2814 2815 nvidia,bpmp = <&bpmp>; 2816 }; 2817 }; 2818 2819 uarta: serial@3100000 { 2820 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2821 reg = <0x0 0x03100000 0x0 0x10000>; 2822 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2823 clocks = <&bpmp TEGRA234_CLK_UARTA>; 2824 resets = <&bpmp TEGRA234_RESET_UARTA>; 2825 dmas = <&gpcdma 8>, <&gpcdma 8>; 2826 dma-names = "rx", "tx"; 2827 status = "disabled"; 2828 }; 2829 2830 uarte: serial@3140000 { 2831 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2832 reg = <0x0 0x03140000 0x0 0x10000>; 2833 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2834 clocks = <&bpmp TEGRA234_CLK_UARTE>; 2835 resets = <&bpmp TEGRA234_RESET_UARTE>; 2836 dmas = <&gpcdma 20>, <&gpcdma 20>; 2837 dma-names = "rx", "tx"; 2838 status = "disabled"; 2839 }; 2840 2841 gen1_i2c: i2c@3160000 { 2842 compatible = "nvidia,tegra194-i2c"; 2843 reg = <0x0 0x3160000 0x0 0x100>; 2844 status = "disabled"; 2845 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2846 #address-cells = <1>; 2847 #size-cells = <0>; 2848 clock-frequency = <400000>; 2849 clocks = <&bpmp TEGRA234_CLK_I2C1>, 2850 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2851 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 2852 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2853 clock-names = "div-clk", "parent"; 2854 resets = <&bpmp TEGRA234_RESET_I2C1>; 2855 reset-names = "i2c"; 2856 dmas = <&gpcdma 21>, <&gpcdma 21>; 2857 dma-names = "rx", "tx"; 2858 }; 2859 2860 cam_i2c: i2c@3180000 { 2861 compatible = "nvidia,tegra194-i2c"; 2862 reg = <0x0 0x3180000 0x0 0x100>; 2863 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2864 #address-cells = <1>; 2865 #size-cells = <0>; 2866 status = "disabled"; 2867 clock-frequency = <400000>; 2868 clocks = <&bpmp TEGRA234_CLK_I2C3>, 2869 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2870 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 2871 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2872 clock-names = "div-clk", "parent"; 2873 resets = <&bpmp TEGRA234_RESET_I2C3>; 2874 reset-names = "i2c"; 2875 dmas = <&gpcdma 23>, <&gpcdma 23>; 2876 dma-names = "rx", "tx"; 2877 }; 2878 2879 dp_aux_ch1_i2c: i2c@3190000 { 2880 compatible = "nvidia,tegra194-i2c"; 2881 reg = <0x0 0x3190000 0x0 0x100>; 2882 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2883 #address-cells = <1>; 2884 #size-cells = <0>; 2885 status = "disabled"; 2886 clock-frequency = <100000>; 2887 clocks = <&bpmp TEGRA234_CLK_I2C4>, 2888 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2889 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 2890 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2891 clock-names = "div-clk", "parent"; 2892 resets = <&bpmp TEGRA234_RESET_I2C4>; 2893 reset-names = "i2c"; 2894 dmas = <&gpcdma 26>, <&gpcdma 26>; 2895 dma-names = "rx", "tx"; 2896 }; 2897 2898 dp_aux_ch0_i2c: i2c@31b0000 { 2899 compatible = "nvidia,tegra194-i2c"; 2900 reg = <0x0 0x31b0000 0x0 0x100>; 2901 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 status = "disabled"; 2905 clock-frequency = <100000>; 2906 clocks = <&bpmp TEGRA234_CLK_I2C6>, 2907 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2908 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 2909 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2910 clock-names = "div-clk", "parent"; 2911 resets = <&bpmp TEGRA234_RESET_I2C6>; 2912 reset-names = "i2c"; 2913 dmas = <&gpcdma 30>, <&gpcdma 30>; 2914 dma-names = "rx", "tx"; 2915 }; 2916 2917 dp_aux_ch2_i2c: i2c@31c0000 { 2918 compatible = "nvidia,tegra194-i2c"; 2919 reg = <0x0 0x31c0000 0x0 0x100>; 2920 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 status = "disabled"; 2924 clock-frequency = <100000>; 2925 clocks = <&bpmp TEGRA234_CLK_I2C7>, 2926 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2927 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 2928 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2929 clock-names = "div-clk", "parent"; 2930 resets = <&bpmp TEGRA234_RESET_I2C7>; 2931 reset-names = "i2c"; 2932 dmas = <&gpcdma 27>, <&gpcdma 27>; 2933 dma-names = "rx", "tx"; 2934 }; 2935 2936 uarti: serial@31d0000 { 2937 compatible = "arm,sbsa-uart"; 2938 reg = <0x0 0x31d0000 0x0 0x10000>; 2939 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 2940 status = "disabled"; 2941 }; 2942 2943 dp_aux_ch3_i2c: i2c@31e0000 { 2944 compatible = "nvidia,tegra194-i2c"; 2945 reg = <0x0 0x31e0000 0x0 0x100>; 2946 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2947 #address-cells = <1>; 2948 #size-cells = <0>; 2949 status = "disabled"; 2950 clock-frequency = <100000>; 2951 clocks = <&bpmp TEGRA234_CLK_I2C9>, 2952 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2953 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 2954 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2955 clock-names = "div-clk", "parent"; 2956 resets = <&bpmp TEGRA234_RESET_I2C9>; 2957 reset-names = "i2c"; 2958 dmas = <&gpcdma 31>, <&gpcdma 31>; 2959 dma-names = "rx", "tx"; 2960 }; 2961 2962 spi@3210000 { 2963 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2964 reg = <0x0 0x03210000 0x0 0x1000>; 2965 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 clocks = <&bpmp TEGRA234_CLK_SPI1>; 2969 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; 2970 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2971 clock-names = "spi"; 2972 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2973 resets = <&bpmp TEGRA234_RESET_SPI1>; 2974 reset-names = "spi"; 2975 dmas = <&gpcdma 15>, <&gpcdma 15>; 2976 dma-names = "rx", "tx"; 2977 dma-coherent; 2978 status = "disabled"; 2979 }; 2980 2981 spi@3230000 { 2982 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2983 reg = <0x0 0x03230000 0x0 0x1000>; 2984 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2985 #address-cells = <1>; 2986 #size-cells = <0>; 2987 clocks = <&bpmp TEGRA234_CLK_SPI3>; 2988 clock-names = "spi"; 2989 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2990 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; 2991 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2992 resets = <&bpmp TEGRA234_RESET_SPI3>; 2993 reset-names = "spi"; 2994 dmas = <&gpcdma 17>, <&gpcdma 17>; 2995 dma-names = "rx", "tx"; 2996 dma-coherent; 2997 status = "disabled"; 2998 }; 2999 3000 spi@3270000 { 3001 compatible = "nvidia,tegra234-qspi"; 3002 reg = <0x0 0x3270000 0x0 0x1000>; 3003 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3004 #address-cells = <1>; 3005 #size-cells = <0>; 3006 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 3007 <&bpmp TEGRA234_CLK_QSPI0_PM>; 3008 clock-names = "qspi", "qspi_out"; 3009 resets = <&bpmp TEGRA234_RESET_QSPI0>; 3010 iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; 3011 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 3012 <&bpmp TEGRA234_CLK_QSPI0_PM>; 3013 assigned-clock-rates = <199999999 99999999>; 3014 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 3015 status = "disabled"; 3016 }; 3017 3018 pwm1: pwm@3280000 { 3019 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3020 reg = <0x0 0x3280000 0x0 0x10000>; 3021 clocks = <&bpmp TEGRA234_CLK_PWM1>; 3022 resets = <&bpmp TEGRA234_RESET_PWM1>; 3023 reset-names = "pwm"; 3024 status = "disabled"; 3025 #pwm-cells = <2>; 3026 }; 3027 3028 pwm2: pwm@3290000 { 3029 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3030 reg = <0x0 0x3290000 0x0 0x10000>; 3031 clocks = <&bpmp TEGRA234_CLK_PWM2>; 3032 resets = <&bpmp TEGRA234_RESET_PWM2>; 3033 reset-names = "pwm"; 3034 status = "disabled"; 3035 #pwm-cells = <2>; 3036 }; 3037 3038 pwm3: pwm@32a0000 { 3039 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3040 reg = <0x0 0x32a0000 0x0 0x10000>; 3041 clocks = <&bpmp TEGRA234_CLK_PWM3>; 3042 resets = <&bpmp TEGRA234_RESET_PWM3>; 3043 reset-names = "pwm"; 3044 status = "disabled"; 3045 #pwm-cells = <2>; 3046 }; 3047 3048 pwm5: pwm@32c0000 { 3049 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3050 reg = <0x0 0x32c0000 0x0 0x10000>; 3051 clocks = <&bpmp TEGRA234_CLK_PWM5>; 3052 resets = <&bpmp TEGRA234_RESET_PWM5>; 3053 reset-names = "pwm"; 3054 status = "disabled"; 3055 #pwm-cells = <2>; 3056 }; 3057 3058 pwm6: pwm@32d0000 { 3059 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3060 reg = <0x0 0x32d0000 0x0 0x10000>; 3061 clocks = <&bpmp TEGRA234_CLK_PWM6>; 3062 resets = <&bpmp TEGRA234_RESET_PWM6>; 3063 reset-names = "pwm"; 3064 status = "disabled"; 3065 #pwm-cells = <2>; 3066 }; 3067 3068 pwm7: pwm@32e0000 { 3069 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3070 reg = <0x0 0x32e0000 0x0 0x10000>; 3071 clocks = <&bpmp TEGRA234_CLK_PWM7>; 3072 resets = <&bpmp TEGRA234_RESET_PWM7>; 3073 reset-names = "pwm"; 3074 status = "disabled"; 3075 #pwm-cells = <2>; 3076 }; 3077 3078 pwm8: pwm@32f0000 { 3079 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3080 reg = <0x0 0x32f0000 0x0 0x10000>; 3081 clocks = <&bpmp TEGRA234_CLK_PWM8>; 3082 resets = <&bpmp TEGRA234_RESET_PWM8>; 3083 reset-names = "pwm"; 3084 status = "disabled"; 3085 #pwm-cells = <2>; 3086 }; 3087 3088 spi@3300000 { 3089 compatible = "nvidia,tegra234-qspi"; 3090 reg = <0x0 0x3300000 0x0 0x1000>; 3091 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3092 #address-cells = <1>; 3093 #size-cells = <0>; 3094 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3095 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3096 clock-names = "qspi", "qspi_out"; 3097 resets = <&bpmp TEGRA234_RESET_QSPI1>; 3098 iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; 3099 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3100 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3101 assigned-clock-rates = <199999999 99999999>; 3102 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 3103 status = "disabled"; 3104 }; 3105 3106 mmc@3400000 { 3107 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3108 reg = <0x0 0x03400000 0x0 0x20000>; 3109 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3110 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3111 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3112 clock-names = "sdhci", "tmclk"; 3113 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3114 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 3115 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 3116 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 3117 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 3118 reset-names = "sdhci"; 3119 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 3120 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 3121 interconnect-names = "dma-mem", "write"; 3122 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 3123 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 3124 pinctrl-0 = <&sdmmc1_3v3>; 3125 pinctrl-1 = <&sdmmc1_1v8>; 3126 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 3127 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 3128 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3129 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3130 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3131 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3132 nvidia,default-tap = <14>; 3133 nvidia,default-trim = <0x8>; 3134 sd-uhs-sdr25; 3135 sd-uhs-sdr50; 3136 sd-uhs-ddr50; 3137 sd-uhs-sdr104; 3138 status = "disabled"; 3139 }; 3140 3141 mmc@3460000 { 3142 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3143 reg = <0x0 0x03460000 0x0 0x20000>; 3144 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 3145 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3146 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3147 clock-names = "sdhci", "tmclk"; 3148 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3149 <&bpmp TEGRA234_CLK_PLLC4>; 3150 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 3151 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 3152 reset-names = "sdhci"; 3153 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 3154 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 3155 interconnect-names = "dma-mem", "write"; 3156 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 3157 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 3158 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 3159 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 3160 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3161 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3162 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 3163 nvidia,default-tap = <0x8>; 3164 nvidia,default-trim = <0x14>; 3165 nvidia,dqs-trim = <40>; 3166 supports-cqe; 3167 status = "disabled"; 3168 }; 3169 3170 hda@3510000 { 3171 compatible = "nvidia,tegra234-hda"; 3172 reg = <0x0 0x3510000 0x0 0x10000>; 3173 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 3174 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 3175 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 3176 clock-names = "hda", "hda2codec_2x"; 3177 resets = <&bpmp TEGRA234_RESET_HDA>, 3178 <&bpmp TEGRA234_RESET_HDACODEC>; 3179 reset-names = "hda", "hda2codec_2x"; 3180 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 3181 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 3182 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 3183 interconnect-names = "dma-mem", "write"; 3184 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 3185 status = "disabled"; 3186 }; 3187 3188 xusb_padctl: padctl@3520000 { 3189 compatible = "nvidia,tegra234-xusb-padctl"; 3190 reg = <0x0 0x03520000 0x0 0x20000>, 3191 <0x0 0x03540000 0x0 0x10000>; 3192 reg-names = "padctl", "ao"; 3193 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 3194 3195 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 3196 reset-names = "padctl"; 3197 3198 status = "disabled"; 3199 3200 pads { 3201 usb2 { 3202 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 3203 clock-names = "trk"; 3204 3205 lanes { 3206 usb2-0 { 3207 nvidia,function = "xusb"; 3208 status = "disabled"; 3209 #phy-cells = <0>; 3210 }; 3211 3212 usb2-1 { 3213 nvidia,function = "xusb"; 3214 status = "disabled"; 3215 #phy-cells = <0>; 3216 }; 3217 3218 usb2-2 { 3219 nvidia,function = "xusb"; 3220 status = "disabled"; 3221 #phy-cells = <0>; 3222 }; 3223 3224 usb2-3 { 3225 nvidia,function = "xusb"; 3226 status = "disabled"; 3227 #phy-cells = <0>; 3228 }; 3229 }; 3230 }; 3231 3232 usb3 { 3233 lanes { 3234 usb3-0 { 3235 nvidia,function = "xusb"; 3236 status = "disabled"; 3237 #phy-cells = <0>; 3238 }; 3239 3240 usb3-1 { 3241 nvidia,function = "xusb"; 3242 status = "disabled"; 3243 #phy-cells = <0>; 3244 }; 3245 3246 usb3-2 { 3247 nvidia,function = "xusb"; 3248 status = "disabled"; 3249 #phy-cells = <0>; 3250 }; 3251 3252 usb3-3 { 3253 nvidia,function = "xusb"; 3254 status = "disabled"; 3255 #phy-cells = <0>; 3256 }; 3257 }; 3258 }; 3259 }; 3260 3261 ports { 3262 usb2-0 { 3263 status = "disabled"; 3264 }; 3265 3266 usb2-1 { 3267 status = "disabled"; 3268 }; 3269 3270 usb2-2 { 3271 status = "disabled"; 3272 }; 3273 3274 usb2-3 { 3275 status = "disabled"; 3276 }; 3277 3278 usb3-0 { 3279 status = "disabled"; 3280 }; 3281 3282 usb3-1 { 3283 status = "disabled"; 3284 }; 3285 3286 usb3-2 { 3287 status = "disabled"; 3288 }; 3289 3290 usb3-3 { 3291 status = "disabled"; 3292 }; 3293 }; 3294 }; 3295 3296 usb@3550000 { 3297 compatible = "nvidia,tegra234-xudc"; 3298 reg = <0x0 0x03550000 0x0 0x8000>, 3299 <0x0 0x03558000 0x0 0x8000>; 3300 reg-names = "base", "fpci"; 3301 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 3302 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 3303 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3304 <&bpmp TEGRA234_CLK_XUSB_SS>, 3305 <&bpmp TEGRA234_CLK_XUSB_FS>; 3306 clock-names = "dev", "ss", "ss_src", "fs_src"; 3307 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 3308 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 3309 interconnect-names = "dma-mem", "write"; 3310 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 3311 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 3312 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3313 power-domain-names = "dev", "ss"; 3314 nvidia,xusb-padctl = <&xusb_padctl>; 3315 dma-coherent; 3316 status = "disabled"; 3317 }; 3318 3319 usb@3610000 { 3320 compatible = "nvidia,tegra234-xusb"; 3321 reg = <0x0 0x03610000 0x0 0x40000>, 3322 <0x0 0x03600000 0x0 0x10000>, 3323 <0x0 0x03650000 0x0 0x10000>; 3324 reg-names = "hcd", "fpci", "bar2"; 3325 3326 interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 3327 <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 3328 <&pmc 76 IRQ_TYPE_LEVEL_HIGH>, 3329 <&pmc 77 IRQ_TYPE_LEVEL_HIGH>, 3330 <&pmc 78 IRQ_TYPE_LEVEL_HIGH>, 3331 <&pmc 79 IRQ_TYPE_LEVEL_HIGH>, 3332 <&pmc 80 IRQ_TYPE_LEVEL_HIGH>, 3333 <&pmc 81 IRQ_TYPE_LEVEL_HIGH>, 3334 <&pmc 82 IRQ_TYPE_LEVEL_HIGH>; 3335 3336 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 3337 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 3338 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3339 <&bpmp TEGRA234_CLK_XUSB_SS>, 3340 <&bpmp TEGRA234_CLK_CLK_M>, 3341 <&bpmp TEGRA234_CLK_XUSB_FS>, 3342 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 3343 <&bpmp TEGRA234_CLK_CLK_M>, 3344 <&bpmp TEGRA234_CLK_PLLE>; 3345 clock-names = "xusb_host", "xusb_falcon_src", 3346 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 3347 "xusb_fs_src", "pll_u_480m", "clk_m", 3348 "pll_e"; 3349 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 3350 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 3351 interconnect-names = "dma-mem", "write"; 3352 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 3353 3354 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 3355 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3356 power-domain-names = "xusb_host", "xusb_ss"; 3357 3358 nvidia,xusb-padctl = <&xusb_padctl>; 3359 dma-coherent; 3360 status = "disabled"; 3361 }; 3362 3363 fuse@3810000 { 3364 compatible = "nvidia,tegra234-efuse"; 3365 reg = <0x0 0x03810000 0x0 0x10000>; 3366 clocks = <&bpmp TEGRA234_CLK_FUSE>; 3367 clock-names = "fuse"; 3368 }; 3369 3370 hte_lic: hardware-timestamp@3aa0000 { 3371 compatible = "nvidia,tegra234-gte-lic"; 3372 reg = <0x0 0x3aa0000 0x0 0x10000>; 3373 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3374 nvidia,int-threshold = <1>; 3375 #timestamp-cells = <1>; 3376 }; 3377 3378 hsp_top0: hsp@3c00000 { 3379 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3380 reg = <0x0 0x03c00000 0x0 0xa0000>; 3381 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3390 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 3391 "shared3", "shared4", "shared5", "shared6", 3392 "shared7"; 3393 #mbox-cells = <2>; 3394 }; 3395 3396 p2u_hsio_0: phy@3e00000 { 3397 compatible = "nvidia,tegra234-p2u"; 3398 reg = <0x0 0x03e00000 0x0 0x10000>; 3399 reg-names = "ctl"; 3400 3401 #phy-cells = <0>; 3402 }; 3403 3404 p2u_hsio_1: phy@3e10000 { 3405 compatible = "nvidia,tegra234-p2u"; 3406 reg = <0x0 0x03e10000 0x0 0x10000>; 3407 reg-names = "ctl"; 3408 3409 #phy-cells = <0>; 3410 }; 3411 3412 p2u_hsio_2: phy@3e20000 { 3413 compatible = "nvidia,tegra234-p2u"; 3414 reg = <0x0 0x03e20000 0x0 0x10000>; 3415 reg-names = "ctl"; 3416 3417 #phy-cells = <0>; 3418 }; 3419 3420 p2u_hsio_3: phy@3e30000 { 3421 compatible = "nvidia,tegra234-p2u"; 3422 reg = <0x0 0x03e30000 0x0 0x10000>; 3423 reg-names = "ctl"; 3424 3425 #phy-cells = <0>; 3426 }; 3427 3428 p2u_hsio_4: phy@3e40000 { 3429 compatible = "nvidia,tegra234-p2u"; 3430 reg = <0x0 0x03e40000 0x0 0x10000>; 3431 reg-names = "ctl"; 3432 3433 #phy-cells = <0>; 3434 }; 3435 3436 p2u_hsio_5: phy@3e50000 { 3437 compatible = "nvidia,tegra234-p2u"; 3438 reg = <0x0 0x03e50000 0x0 0x10000>; 3439 reg-names = "ctl"; 3440 3441 #phy-cells = <0>; 3442 }; 3443 3444 p2u_hsio_6: phy@3e60000 { 3445 compatible = "nvidia,tegra234-p2u"; 3446 reg = <0x0 0x03e60000 0x0 0x10000>; 3447 reg-names = "ctl"; 3448 3449 #phy-cells = <0>; 3450 }; 3451 3452 p2u_hsio_7: phy@3e70000 { 3453 compatible = "nvidia,tegra234-p2u"; 3454 reg = <0x0 0x03e70000 0x0 0x10000>; 3455 reg-names = "ctl"; 3456 3457 #phy-cells = <0>; 3458 }; 3459 3460 p2u_nvhs_0: phy@3e90000 { 3461 compatible = "nvidia,tegra234-p2u"; 3462 reg = <0x0 0x03e90000 0x0 0x10000>; 3463 reg-names = "ctl"; 3464 3465 #phy-cells = <0>; 3466 }; 3467 3468 p2u_nvhs_1: phy@3ea0000 { 3469 compatible = "nvidia,tegra234-p2u"; 3470 reg = <0x0 0x03ea0000 0x0 0x10000>; 3471 reg-names = "ctl"; 3472 3473 #phy-cells = <0>; 3474 }; 3475 3476 p2u_nvhs_2: phy@3eb0000 { 3477 compatible = "nvidia,tegra234-p2u"; 3478 reg = <0x0 0x03eb0000 0x0 0x10000>; 3479 reg-names = "ctl"; 3480 3481 #phy-cells = <0>; 3482 }; 3483 3484 p2u_nvhs_3: phy@3ec0000 { 3485 compatible = "nvidia,tegra234-p2u"; 3486 reg = <0x0 0x03ec0000 0x0 0x10000>; 3487 reg-names = "ctl"; 3488 3489 #phy-cells = <0>; 3490 }; 3491 3492 p2u_nvhs_4: phy@3ed0000 { 3493 compatible = "nvidia,tegra234-p2u"; 3494 reg = <0x0 0x03ed0000 0x0 0x10000>; 3495 reg-names = "ctl"; 3496 3497 #phy-cells = <0>; 3498 }; 3499 3500 p2u_nvhs_5: phy@3ee0000 { 3501 compatible = "nvidia,tegra234-p2u"; 3502 reg = <0x0 0x03ee0000 0x0 0x10000>; 3503 reg-names = "ctl"; 3504 3505 #phy-cells = <0>; 3506 }; 3507 3508 p2u_nvhs_6: phy@3ef0000 { 3509 compatible = "nvidia,tegra234-p2u"; 3510 reg = <0x0 0x03ef0000 0x0 0x10000>; 3511 reg-names = "ctl"; 3512 3513 #phy-cells = <0>; 3514 }; 3515 3516 p2u_nvhs_7: phy@3f00000 { 3517 compatible = "nvidia,tegra234-p2u"; 3518 reg = <0x0 0x03f00000 0x0 0x10000>; 3519 reg-names = "ctl"; 3520 3521 #phy-cells = <0>; 3522 }; 3523 3524 p2u_gbe_0: phy@3f20000 { 3525 compatible = "nvidia,tegra234-p2u"; 3526 reg = <0x0 0x03f20000 0x0 0x10000>; 3527 reg-names = "ctl"; 3528 3529 #phy-cells = <0>; 3530 }; 3531 3532 p2u_gbe_1: phy@3f30000 { 3533 compatible = "nvidia,tegra234-p2u"; 3534 reg = <0x0 0x03f30000 0x0 0x10000>; 3535 reg-names = "ctl"; 3536 3537 #phy-cells = <0>; 3538 }; 3539 3540 p2u_gbe_2: phy@3f40000 { 3541 compatible = "nvidia,tegra234-p2u"; 3542 reg = <0x0 0x03f40000 0x0 0x10000>; 3543 reg-names = "ctl"; 3544 3545 #phy-cells = <0>; 3546 }; 3547 3548 p2u_gbe_3: phy@3f50000 { 3549 compatible = "nvidia,tegra234-p2u"; 3550 reg = <0x0 0x03f50000 0x0 0x10000>; 3551 reg-names = "ctl"; 3552 3553 #phy-cells = <0>; 3554 }; 3555 3556 p2u_gbe_4: phy@3f60000 { 3557 compatible = "nvidia,tegra234-p2u"; 3558 reg = <0x0 0x03f60000 0x0 0x10000>; 3559 reg-names = "ctl"; 3560 3561 #phy-cells = <0>; 3562 }; 3563 3564 p2u_gbe_5: phy@3f70000 { 3565 compatible = "nvidia,tegra234-p2u"; 3566 reg = <0x0 0x03f70000 0x0 0x10000>; 3567 reg-names = "ctl"; 3568 3569 #phy-cells = <0>; 3570 }; 3571 3572 p2u_gbe_6: phy@3f80000 { 3573 compatible = "nvidia,tegra234-p2u"; 3574 reg = <0x0 0x03f80000 0x0 0x10000>; 3575 reg-names = "ctl"; 3576 3577 #phy-cells = <0>; 3578 }; 3579 3580 p2u_gbe_7: phy@3f90000 { 3581 compatible = "nvidia,tegra234-p2u"; 3582 reg = <0x0 0x03f90000 0x0 0x10000>; 3583 reg-names = "ctl"; 3584 3585 #phy-cells = <0>; 3586 }; 3587 3588 ethernet@6800000 { 3589 compatible = "nvidia,tegra234-mgbe"; 3590 reg = <0x0 0x06800000 0x0 0x10000>, 3591 <0x0 0x06810000 0x0 0x10000>, 3592 <0x0 0x068a0000 0x0 0x10000>; 3593 reg-names = "hypervisor", "mac", "xpcs"; 3594 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 3595 interrupt-names = "common"; 3596 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 3597 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 3598 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 3599 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 3600 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 3601 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 3602 <&bpmp TEGRA234_CLK_MGBE0_TX>, 3603 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 3604 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 3605 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 3606 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 3607 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 3608 clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", 3609 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3610 "rx-pcs", "tx-pcs"; 3611 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 3612 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 3613 reset-names = "mac", "pcs"; 3614 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 3615 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 3616 interconnect-names = "dma-mem", "write"; 3617 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 3618 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 3619 status = "disabled"; 3620 3621 snps,axi-config = <&mgbe0_axi_setup>; 3622 3623 mgbe0_axi_setup: stmmac-axi-config { 3624 snps,blen = <256 128 64 32 0 0 0>; 3625 snps,rd_osr_lmt = <63>; 3626 snps,wr_osr_lmt = <63>; 3627 }; 3628 }; 3629 3630 ethernet@6900000 { 3631 compatible = "nvidia,tegra234-mgbe"; 3632 reg = <0x0 0x06900000 0x0 0x10000>, 3633 <0x0 0x06910000 0x0 0x10000>, 3634 <0x0 0x069a0000 0x0 0x10000>; 3635 reg-names = "hypervisor", "mac", "xpcs"; 3636 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 3637 interrupt-names = "common"; 3638 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 3639 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 3640 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 3641 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 3642 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 3643 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 3644 <&bpmp TEGRA234_CLK_MGBE1_TX>, 3645 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 3646 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 3647 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 3648 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 3649 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 3650 clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", 3651 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3652 "rx-pcs", "tx-pcs"; 3653 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 3654 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 3655 reset-names = "mac", "pcs"; 3656 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 3657 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 3658 interconnect-names = "dma-mem", "write"; 3659 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 3660 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 3661 status = "disabled"; 3662 3663 snps,axi-config = <&mgbe1_axi_setup>; 3664 3665 mgbe1_axi_setup: stmmac-axi-config { 3666 snps,blen = <256 128 64 32 0 0 0>; 3667 snps,rd_osr_lmt = <63>; 3668 snps,wr_osr_lmt = <63>; 3669 }; 3670 }; 3671 3672 ethernet@6a00000 { 3673 compatible = "nvidia,tegra234-mgbe"; 3674 reg = <0x0 0x06a00000 0x0 0x10000>, 3675 <0x0 0x06a10000 0x0 0x10000>, 3676 <0x0 0x06aa0000 0x0 0x10000>; 3677 reg-names = "hypervisor", "mac", "xpcs"; 3678 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 3679 interrupt-names = "common"; 3680 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 3681 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 3682 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 3683 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 3684 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 3685 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 3686 <&bpmp TEGRA234_CLK_MGBE2_TX>, 3687 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 3688 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 3689 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 3690 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 3691 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 3692 clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", 3693 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3694 "rx-pcs", "tx-pcs"; 3695 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 3696 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 3697 reset-names = "mac", "pcs"; 3698 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 3699 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 3700 interconnect-names = "dma-mem", "write"; 3701 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 3702 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3703 status = "disabled"; 3704 3705 snps,axi-config = <&mgbe2_axi_setup>; 3706 3707 mgbe2_axi_setup: stmmac-axi-config { 3708 snps,blen = <256 128 64 32 0 0 0>; 3709 snps,rd_osr_lmt = <63>; 3710 snps,wr_osr_lmt = <63>; 3711 }; 3712 }; 3713 3714 ethernet@6b00000 { 3715 compatible = "nvidia,tegra234-mgbe"; 3716 reg = <0x0 0x06b00000 0x0 0x10000>, 3717 <0x0 0x06b10000 0x0 0x10000>, 3718 <0x0 0x06ba0000 0x0 0x10000>; 3719 reg-names = "hypervisor", "mac", "xpcs"; 3720 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3721 interrupt-names = "common"; 3722 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 3723 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 3724 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 3725 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 3726 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 3727 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 3728 <&bpmp TEGRA234_CLK_MGBE3_TX>, 3729 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 3730 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 3731 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 3732 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 3733 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 3734 clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", 3735 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3736 "rx-pcs", "tx-pcs"; 3737 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 3738 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 3739 reset-names = "mac", "pcs"; 3740 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 3741 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 3742 interconnect-names = "dma-mem", "write"; 3743 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 3744 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3745 status = "disabled"; 3746 }; 3747 3748 smmu_niso1: iommu@8000000 { 3749 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 3750 reg = <0x0 0x8000000 0x0 0x1000000>, 3751 <0x0 0x7000000 0x0 0x1000000>; 3752 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3882 stream-match-mask = <0x7f80>; 3883 #global-interrupts = <2>; 3884 #iommu-cells = <1>; 3885 3886 nvidia,memory-controller = <&mc>; 3887 }; 3888 3889 sce-fabric@b600000 { 3890 compatible = "nvidia,tegra234-sce-fabric"; 3891 reg = <0x0 0xb600000 0x0 0x40000>; 3892 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 3893 status = "disabled"; 3894 }; 3895 3896 rce-fabric@be00000 { 3897 compatible = "nvidia,tegra234-rce-fabric"; 3898 reg = <0x0 0xbe00000 0x0 0x40000>; 3899 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 3900 }; 3901 3902 hsp_aon: hsp@c150000 { 3903 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3904 reg = <0x0 0x0c150000 0x0 0x90000>; 3905 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3909 /* 3910 * Shared interrupt 0 is routed only to AON/SPE, so 3911 * we only have 4 shared interrupts for the CCPLEX. 3912 */ 3913 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 3914 #mbox-cells = <2>; 3915 }; 3916 3917 hte_aon: hardware-timestamp@c1e0000 { 3918 compatible = "nvidia,tegra234-gte-aon"; 3919 reg = <0x0 0xc1e0000 0x0 0x10000>; 3920 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3921 nvidia,int-threshold = <1>; 3922 nvidia,gpio-controller = <&gpio_aon>; 3923 #timestamp-cells = <1>; 3924 }; 3925 3926 gen2_i2c: i2c@c240000 { 3927 compatible = "nvidia,tegra194-i2c"; 3928 reg = <0x0 0xc240000 0x0 0x100>; 3929 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 3930 #address-cells = <1>; 3931 #size-cells = <0>; 3932 status = "disabled"; 3933 clock-frequency = <100000>; 3934 clocks = <&bpmp TEGRA234_CLK_I2C2>, 3935 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3936 clock-names = "div-clk", "parent"; 3937 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 3938 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3939 resets = <&bpmp TEGRA234_RESET_I2C2>; 3940 reset-names = "i2c"; 3941 dmas = <&gpcdma 22>, <&gpcdma 22>; 3942 dma-names = "rx", "tx"; 3943 }; 3944 3945 gen8_i2c: i2c@c250000 { 3946 compatible = "nvidia,tegra194-i2c"; 3947 reg = <0x0 0xc250000 0x0 0x100>; 3948 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3949 #address-cells = <1>; 3950 #size-cells = <0>; 3951 status = "disabled"; 3952 clock-frequency = <400000>; 3953 clocks = <&bpmp TEGRA234_CLK_I2C8>, 3954 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3955 clock-names = "div-clk", "parent"; 3956 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 3957 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3958 resets = <&bpmp TEGRA234_RESET_I2C8>; 3959 reset-names = "i2c"; 3960 dmas = <&gpcdma 0>, <&gpcdma 0>; 3961 dma-names = "rx", "tx"; 3962 }; 3963 3964 spi@c260000 { 3965 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 3966 reg = <0x0 0x0c260000 0x0 0x1000>; 3967 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3968 #address-cells = <1>; 3969 #size-cells = <0>; 3970 clocks = <&bpmp TEGRA234_CLK_SPI2>; 3971 clock-names = "spi"; 3972 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 3973 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; 3974 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3975 resets = <&bpmp TEGRA234_RESET_SPI2>; 3976 reset-names = "spi"; 3977 dmas = <&gpcdma 16>, <&gpcdma 16>; 3978 dma-names = "rx", "tx"; 3979 dma-coherent; 3980 status = "disabled"; 3981 }; 3982 3983 rtc@c2a0000 { 3984 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 3985 reg = <0x0 0x0c2a0000 0x0 0x10000>; 3986 interrupt-parent = <&pmc>; 3987 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 3988 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 3989 clock-names = "rtc"; 3990 status = "disabled"; 3991 }; 3992 3993 gpio_aon: gpio@c2f0000 { 3994 compatible = "nvidia,tegra234-gpio-aon"; 3995 reg-names = "security", "gpio"; 3996 reg = <0x0 0x0c2f0000 0x0 0x1000>, 3997 <0x0 0x0c2f1000 0x0 0x1000>; 3998 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 4002 #interrupt-cells = <2>; 4003 interrupt-controller; 4004 #gpio-cells = <2>; 4005 gpio-controller; 4006 gpio-ranges = <&pinmux_aon 0 0 32>; 4007 }; 4008 4009 pinmux_aon: pinmux@c300000 { 4010 compatible = "nvidia,tegra234-pinmux-aon"; 4011 reg = <0x0 0xc300000 0x0 0x4000>; 4012 }; 4013 4014 pwm4: pwm@c340000 { 4015 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 4016 reg = <0x0 0xc340000 0x0 0x10000>; 4017 clocks = <&bpmp TEGRA234_CLK_PWM4>; 4018 resets = <&bpmp TEGRA234_RESET_PWM4>; 4019 reset-names = "pwm"; 4020 status = "disabled"; 4021 #pwm-cells = <2>; 4022 }; 4023 4024 pmc: pmc@c360000 { 4025 compatible = "nvidia,tegra234-pmc"; 4026 reg = <0x0 0x0c360000 0x0 0x10000>, 4027 <0x0 0x0c370000 0x0 0x10000>, 4028 <0x0 0x0c380000 0x0 0x10000>, 4029 <0x0 0x0c390000 0x0 0x10000>, 4030 <0x0 0x0c3a0000 0x0 0x10000>; 4031 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 4032 4033 #interrupt-cells = <2>; 4034 interrupt-controller; 4035 4036 sdmmc1_1v8: sdmmc1-1v8 { 4037 pins = "sdmmc1-hv"; 4038 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 4039 }; 4040 4041 sdmmc1_3v3: sdmmc1-3v3 { 4042 pins = "sdmmc1-hv"; 4043 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 4044 }; 4045 4046 sdmmc3_1v8: sdmmc3-1v8 { 4047 pins = "sdmmc3-hv"; 4048 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 4049 }; 4050 4051 sdmmc3_3v3: sdmmc3-3v3 { 4052 pins = "sdmmc3-hv"; 4053 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 4054 }; 4055 }; 4056 4057 aon-fabric@c600000 { 4058 compatible = "nvidia,tegra234-aon-fabric"; 4059 reg = <0x0 0xc600000 0x0 0x40000>; 4060 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 4061 }; 4062 4063 bpmp-fabric@d600000 { 4064 compatible = "nvidia,tegra234-bpmp-fabric"; 4065 reg = <0x0 0xd600000 0x0 0x40000>; 4066 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4067 }; 4068 4069 dce-fabric@de00000 { 4070 compatible = "nvidia,tegra234-dce-fabric"; 4071 reg = <0x0 0xde00000 0x0 0x40000>; 4072 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 4073 }; 4074 4075 ccplex@e000000 { 4076 compatible = "nvidia,tegra234-ccplex-cluster"; 4077 reg = <0x0 0x0e000000 0x0 0x5ffff>; 4078 nvidia,bpmp = <&bpmp>; 4079 }; 4080 4081 gic: interrupt-controller@f400000 { 4082 compatible = "arm,gic-v3"; 4083 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 4084 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 4085 interrupt-parent = <&gic>; 4086 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4087 4088 #redistributor-regions = <1>; 4089 #interrupt-cells = <3>; 4090 interrupt-controller; 4091 4092 #address-cells = <0>; 4093 }; 4094 4095 smmu_iso: iommu@10000000 { 4096 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4097 reg = <0x0 0x10000000 0x0 0x1000000>; 4098 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4227 stream-match-mask = <0x7f80>; 4228 #global-interrupts = <1>; 4229 #iommu-cells = <1>; 4230 4231 nvidia,memory-controller = <&mc>; 4232 }; 4233 4234 smmu_niso0: iommu@12000000 { 4235 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4236 reg = <0x0 0x12000000 0x0 0x1000000>, 4237 <0x0 0x11000000 0x0 0x1000000>; 4238 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4368 stream-match-mask = <0x7f80>; 4369 #global-interrupts = <2>; 4370 #iommu-cells = <1>; 4371 4372 nvidia,memory-controller = <&mc>; 4373 }; 4374 4375 cbb-fabric@13a00000 { 4376 compatible = "nvidia,tegra234-cbb-fabric"; 4377 reg = <0x0 0x13a00000 0x0 0x400000>; 4378 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 4379 }; 4380 4381 host1x@13e00000 { 4382 compatible = "nvidia,tegra234-host1x"; 4383 reg = <0x0 0x13e00000 0x0 0x10000>, 4384 <0x0 0x13e10000 0x0 0x10000>, 4385 <0x0 0x13e40000 0x0 0x10000>; 4386 reg-names = "common", "hypervisor", "vm"; 4387 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4396 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 4397 "syncpt5", "syncpt6", "syncpt7", "host1x"; 4398 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 4399 clock-names = "host1x"; 4400 4401 #address-cells = <2>; 4402 #size-cells = <2>; 4403 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 4404 4405 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 4406 interconnect-names = "dma-mem"; 4407 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 4408 dma-coherent; 4409 4410 /* Context isolation domains */ 4411 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 4412 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 4413 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 4414 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 4415 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 4416 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 4417 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 4418 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 4419 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 4420 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 4421 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 4422 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 4423 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 4424 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 4425 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 4426 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 4427 4428 vic@15340000 { 4429 compatible = "nvidia,tegra234-vic"; 4430 reg = <0x0 0x15340000 0x0 0x00040000>; 4431 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 4432 clocks = <&bpmp TEGRA234_CLK_VIC>; 4433 clock-names = "vic"; 4434 resets = <&bpmp TEGRA234_RESET_VIC>; 4435 reset-names = "vic"; 4436 4437 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 4438 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 4439 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 4440 interconnect-names = "dma-mem", "write"; 4441 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 4442 dma-coherent; 4443 }; 4444 4445 nvdec@15480000 { 4446 compatible = "nvidia,tegra234-nvdec"; 4447 reg = <0x0 0x15480000 0x0 0x00040000>; 4448 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 4449 <&bpmp TEGRA234_CLK_FUSE>, 4450 <&bpmp TEGRA234_CLK_TSEC_PKA>; 4451 clock-names = "nvdec", "fuse", "tsec_pka"; 4452 resets = <&bpmp TEGRA234_RESET_NVDEC>; 4453 reset-names = "nvdec"; 4454 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 4455 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 4456 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 4457 interconnect-names = "dma-mem", "write"; 4458 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 4459 dma-coherent; 4460 4461 nvidia,memory-controller = <&mc>; 4462 4463 /* 4464 * Placeholder values that firmware needs to update with the real 4465 * offsets parsed from the microcode headers. 4466 */ 4467 nvidia,bl-manifest-offset = <0>; 4468 nvidia,bl-data-offset = <0>; 4469 nvidia,bl-code-offset = <0>; 4470 nvidia,os-manifest-offset = <0>; 4471 nvidia,os-data-offset = <0>; 4472 nvidia,os-code-offset = <0>; 4473 4474 /* 4475 * Firmware needs to set this to "okay" once the above values have 4476 * been updated. 4477 */ 4478 status = "disabled"; 4479 }; 4480 4481 crypto@15820000 { 4482 compatible = "nvidia,tegra234-se-aes"; 4483 reg = <0x00 0x15820000 0x00 0x10000>; 4484 clocks = <&bpmp TEGRA234_CLK_SE>; 4485 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>; 4486 dma-coherent; 4487 }; 4488 4489 crypto@15840000 { 4490 compatible = "nvidia,tegra234-se-hash"; 4491 reg = <0x00 0x15840000 0x00 0x10000>; 4492 clocks = <&bpmp TEGRA234_CLK_SE>; 4493 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>; 4494 dma-coherent; 4495 }; 4496 }; 4497 4498 pcie@140a0000 { 4499 compatible = "nvidia,tegra234-pcie"; 4500 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 4501 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 4502 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 4503 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4504 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4505 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4506 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4507 4508 #address-cells = <3>; 4509 #size-cells = <2>; 4510 device_type = "pci"; 4511 num-lanes = <4>; 4512 num-viewport = <8>; 4513 linux,pci-domain = <8>; 4514 4515 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 4516 clock-names = "core"; 4517 4518 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 4519 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 4520 reset-names = "apb", "core"; 4521 4522 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4523 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4524 interrupt-names = "intr", "msi"; 4525 4526 #interrupt-cells = <1>; 4527 interrupt-map-mask = <0 0 0 0>; 4528 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 4529 4530 nvidia,bpmp = <&bpmp 8>; 4531 4532 nvidia,aspm-cmrt-us = <60>; 4533 nvidia,aspm-pwr-on-t-us = <20>; 4534 nvidia,aspm-l0s-entrance-latency-us = <3>; 4535 aspm-l1-entry-delay-ns = <16000>; 4536 4537 bus-range = <0x0 0xff>; 4538 4539 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4540 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4541 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4542 4543 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 4544 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 4545 interconnect-names = "dma-mem", "write"; 4546 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 4547 iommu-map-mask = <0x0>; 4548 dma-coherent; 4549 4550 status = "disabled"; 4551 }; 4552 4553 pcie@140c0000 { 4554 compatible = "nvidia,tegra234-pcie"; 4555 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 4556 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 4557 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 4558 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4559 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4560 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4561 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4562 4563 #address-cells = <3>; 4564 #size-cells = <2>; 4565 device_type = "pci"; 4566 num-lanes = <4>; 4567 num-viewport = <8>; 4568 linux,pci-domain = <9>; 4569 4570 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 4571 clock-names = "core"; 4572 4573 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 4574 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 4575 reset-names = "apb", "core"; 4576 4577 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4578 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4579 interrupt-names = "intr", "msi"; 4580 4581 #interrupt-cells = <1>; 4582 interrupt-map-mask = <0 0 0 0>; 4583 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 4584 4585 nvidia,bpmp = <&bpmp 9>; 4586 4587 nvidia,aspm-cmrt-us = <60>; 4588 nvidia,aspm-pwr-on-t-us = <20>; 4589 nvidia,aspm-l0s-entrance-latency-us = <3>; 4590 aspm-l1-entry-delay-ns = <16000>; 4591 4592 bus-range = <0x0 0xff>; 4593 4594 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 4595 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4596 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4597 4598 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 4599 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 4600 interconnect-names = "dma-mem", "write"; 4601 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 4602 iommu-map-mask = <0x0>; 4603 dma-coherent; 4604 4605 status = "disabled"; 4606 }; 4607 4608 pcie@140e0000 { 4609 compatible = "nvidia,tegra234-pcie"; 4610 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4611 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4612 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 4613 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4614 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4615 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4616 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4617 4618 #address-cells = <3>; 4619 #size-cells = <2>; 4620 device_type = "pci"; 4621 num-lanes = <4>; 4622 num-viewport = <8>; 4623 linux,pci-domain = <10>; 4624 4625 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4626 clock-names = "core"; 4627 4628 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4629 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4630 reset-names = "apb", "core"; 4631 4632 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4633 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4634 interrupt-names = "intr", "msi"; 4635 4636 #interrupt-cells = <1>; 4637 interrupt-map-mask = <0 0 0 0>; 4638 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4639 4640 nvidia,bpmp = <&bpmp 10>; 4641 4642 nvidia,aspm-cmrt-us = <60>; 4643 nvidia,aspm-pwr-on-t-us = <20>; 4644 nvidia,aspm-l0s-entrance-latency-us = <3>; 4645 aspm-l1-entry-delay-ns = <16000>; 4646 4647 bus-range = <0x0 0xff>; 4648 4649 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4650 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4651 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4652 4653 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4654 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4655 interconnect-names = "dma-mem", "write"; 4656 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 4657 iommu-map-mask = <0x0>; 4658 dma-coherent; 4659 4660 status = "disabled"; 4661 }; 4662 4663 pcie-ep@140e0000 { 4664 compatible = "nvidia,tegra234-pcie-ep"; 4665 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4666 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4667 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4668 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 4669 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4670 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4671 4672 num-lanes = <4>; 4673 4674 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4675 clock-names = "core"; 4676 4677 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4678 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4679 reset-names = "apb", "core"; 4680 4681 pinctrl-names = "default"; 4682 pinctrl-0 = <&pex_rst_c10_in_state>; 4683 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4684 interrupt-names = "intr"; 4685 4686 nvidia,bpmp = <&bpmp 10>; 4687 4688 nvidia,enable-ext-refclk; 4689 nvidia,aspm-cmrt-us = <60>; 4690 nvidia,aspm-pwr-on-t-us = <20>; 4691 nvidia,aspm-l0s-entrance-latency-us = <3>; 4692 aspm-l1-entry-delay-ns = <32000>; 4693 4694 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4695 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4696 interconnect-names = "dma-mem", "write"; 4697 iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>; 4698 dma-coherent; 4699 4700 status = "disabled"; 4701 }; 4702 4703 pcie@14100000 { 4704 compatible = "nvidia,tegra234-pcie"; 4705 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4706 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 4707 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 4708 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4709 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4710 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4711 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4712 4713 #address-cells = <3>; 4714 #size-cells = <2>; 4715 device_type = "pci"; 4716 num-lanes = <1>; 4717 num-viewport = <8>; 4718 linux,pci-domain = <1>; 4719 4720 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 4721 clock-names = "core"; 4722 4723 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 4724 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 4725 reset-names = "apb", "core"; 4726 4727 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4728 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4729 interrupt-names = "intr", "msi"; 4730 4731 #interrupt-cells = <1>; 4732 interrupt-map-mask = <0 0 0 0>; 4733 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 4734 4735 nvidia,bpmp = <&bpmp 1>; 4736 4737 nvidia,aspm-cmrt-us = <60>; 4738 nvidia,aspm-pwr-on-t-us = <20>; 4739 nvidia,aspm-l0s-entrance-latency-us = <3>; 4740 aspm-l1-entry-delay-ns = <16000>; 4741 4742 bus-range = <0x0 0xff>; 4743 4744 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4745 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4746 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4747 4748 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 4749 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 4750 interconnect-names = "dma-mem", "write"; 4751 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 4752 iommu-map-mask = <0x0>; 4753 dma-coherent; 4754 4755 status = "disabled"; 4756 }; 4757 4758 pcie@14120000 { 4759 compatible = "nvidia,tegra234-pcie"; 4760 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4761 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 4762 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 4763 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4764 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4765 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4766 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4767 4768 #address-cells = <3>; 4769 #size-cells = <2>; 4770 device_type = "pci"; 4771 num-lanes = <1>; 4772 num-viewport = <8>; 4773 linux,pci-domain = <2>; 4774 4775 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 4776 clock-names = "core"; 4777 4778 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 4779 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 4780 reset-names = "apb", "core"; 4781 4782 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4783 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4784 interrupt-names = "intr", "msi"; 4785 4786 #interrupt-cells = <1>; 4787 interrupt-map-mask = <0 0 0 0>; 4788 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 4789 4790 nvidia,bpmp = <&bpmp 2>; 4791 4792 nvidia,aspm-cmrt-us = <60>; 4793 nvidia,aspm-pwr-on-t-us = <20>; 4794 nvidia,aspm-l0s-entrance-latency-us = <3>; 4795 aspm-l1-entry-delay-ns = <16000>; 4796 4797 bus-range = <0x0 0xff>; 4798 4799 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4800 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4801 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4802 4803 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 4804 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 4805 interconnect-names = "dma-mem", "write"; 4806 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 4807 iommu-map-mask = <0x0>; 4808 dma-coherent; 4809 4810 status = "disabled"; 4811 }; 4812 4813 pcie@14140000 { 4814 compatible = "nvidia,tegra234-pcie"; 4815 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4816 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 4817 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 4818 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4819 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4820 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4821 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4822 4823 #address-cells = <3>; 4824 #size-cells = <2>; 4825 device_type = "pci"; 4826 num-lanes = <1>; 4827 num-viewport = <8>; 4828 linux,pci-domain = <3>; 4829 4830 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 4831 clock-names = "core"; 4832 4833 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 4834 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 4835 reset-names = "apb", "core"; 4836 4837 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4838 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4839 interrupt-names = "intr", "msi"; 4840 4841 #interrupt-cells = <1>; 4842 interrupt-map-mask = <0 0 0 0>; 4843 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 4844 4845 nvidia,bpmp = <&bpmp 3>; 4846 4847 nvidia,aspm-cmrt-us = <60>; 4848 nvidia,aspm-pwr-on-t-us = <20>; 4849 nvidia,aspm-l0s-entrance-latency-us = <3>; 4850 aspm-l1-entry-delay-ns = <16000>; 4851 4852 bus-range = <0x0 0xff>; 4853 4854 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4855 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4856 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4857 4858 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 4859 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 4860 interconnect-names = "dma-mem", "write"; 4861 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 4862 iommu-map-mask = <0x0>; 4863 dma-coherent; 4864 4865 status = "disabled"; 4866 }; 4867 4868 pcie@14160000 { 4869 compatible = "nvidia,tegra234-pcie"; 4870 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4871 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 4872 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 4873 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4874 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4875 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4876 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4877 4878 #address-cells = <3>; 4879 #size-cells = <2>; 4880 device_type = "pci"; 4881 num-lanes = <4>; 4882 num-viewport = <8>; 4883 linux,pci-domain = <4>; 4884 4885 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4886 clock-names = "core"; 4887 4888 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4889 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4890 reset-names = "apb", "core"; 4891 4892 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4893 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4894 interrupt-names = "intr", "msi"; 4895 4896 #interrupt-cells = <1>; 4897 interrupt-map-mask = <0 0 0 0>; 4898 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 4899 4900 nvidia,bpmp = <&bpmp 4>; 4901 4902 nvidia,aspm-cmrt-us = <60>; 4903 nvidia,aspm-pwr-on-t-us = <20>; 4904 nvidia,aspm-l0s-entrance-latency-us = <3>; 4905 aspm-l1-entry-delay-ns = <16000>; 4906 4907 bus-range = <0x0 0xff>; 4908 4909 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4910 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4911 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4912 4913 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4914 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4915 interconnect-names = "dma-mem", "write"; 4916 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 4917 iommu-map-mask = <0x0>; 4918 dma-coherent; 4919 4920 status = "disabled"; 4921 }; 4922 4923 pcie-ep@14160000 { 4924 compatible = "nvidia,tegra234-pcie-ep"; 4925 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4926 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 4927 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 4928 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */ 4929 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4930 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4931 num-lanes = <4>; 4932 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4933 clock-names = "core"; 4934 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4935 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4936 reset-names = "apb", "core"; 4937 4938 pinctrl-names = "default"; 4939 pinctrl-0 = <&pex_rst_c4_in_state>; 4940 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4941 interrupt-names = "intr"; 4942 nvidia,bpmp = <&bpmp 4>; 4943 nvidia,enable-ext-refclk; 4944 nvidia,aspm-cmrt-us = <60>; 4945 nvidia,aspm-pwr-on-t-us = <20>; 4946 nvidia,aspm-l0s-entrance-latency-us = <3>; 4947 aspm-l1-entry-delay-ns = <32000>; 4948 4949 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4950 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4951 interconnect-names = "dma-mem", "write"; 4952 iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>; 4953 dma-coherent; 4954 status = "disabled"; 4955 }; 4956 4957 pcie@14180000 { 4958 compatible = "nvidia,tegra234-pcie"; 4959 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 4960 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 4961 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 4962 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4963 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4964 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4965 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4966 4967 #address-cells = <3>; 4968 #size-cells = <2>; 4969 device_type = "pci"; 4970 num-lanes = <4>; 4971 num-viewport = <8>; 4972 linux,pci-domain = <0>; 4973 4974 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 4975 clock-names = "core"; 4976 4977 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 4978 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 4979 reset-names = "apb", "core"; 4980 4981 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4982 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4983 interrupt-names = "intr", "msi"; 4984 4985 #interrupt-cells = <1>; 4986 interrupt-map-mask = <0 0 0 0>; 4987 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4988 4989 nvidia,bpmp = <&bpmp 0>; 4990 4991 nvidia,aspm-cmrt-us = <60>; 4992 nvidia,aspm-pwr-on-t-us = <20>; 4993 nvidia,aspm-l0s-entrance-latency-us = <3>; 4994 aspm-l1-entry-delay-ns = <16000>; 4995 4996 bus-range = <0x0 0xff>; 4997 4998 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4999 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5000 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5001 5002 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 5003 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 5004 interconnect-names = "dma-mem", "write"; 5005 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 5006 iommu-map-mask = <0x0>; 5007 dma-coherent; 5008 5009 status = "disabled"; 5010 }; 5011 5012 pcie@141a0000 { 5013 compatible = "nvidia,tegra234-pcie"; 5014 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 5015 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 5016 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 5017 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5018 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5019 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5020 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5021 5022 #address-cells = <3>; 5023 #size-cells = <2>; 5024 device_type = "pci"; 5025 num-lanes = <8>; 5026 num-viewport = <8>; 5027 linux,pci-domain = <5>; 5028 5029 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 5030 clock-names = "core"; 5031 5032 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 5033 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 5034 reset-names = "apb", "core"; 5035 5036 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5037 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5038 interrupt-names = "intr", "msi"; 5039 5040 #interrupt-cells = <1>; 5041 interrupt-map-mask = <0 0 0 0>; 5042 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 5043 5044 nvidia,bpmp = <&bpmp 5>; 5045 5046 nvidia,aspm-cmrt-us = <60>; 5047 nvidia,aspm-pwr-on-t-us = <20>; 5048 nvidia,aspm-l0s-entrance-latency-us = <3>; 5049 aspm-l1-entry-delay-ns = <16000>; 5050 5051 bus-range = <0x0 0xff>; 5052 5053 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 5054 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5055 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5056 5057 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 5058 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5059 interconnect-names = "dma-mem", "write"; 5060 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 5061 iommu-map-mask = <0x0>; 5062 dma-coherent; 5063 5064 status = "disabled"; 5065 }; 5066 5067 pcie-ep@141a0000 { 5068 compatible = "nvidia,tegra234-pcie-ep"; 5069 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 5070 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 5071 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5072 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5073 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5074 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5075 5076 num-lanes = <8>; 5077 5078 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 5079 clock-names = "core"; 5080 5081 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 5082 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 5083 reset-names = "apb", "core"; 5084 5085 pinctrl-names = "default"; 5086 pinctrl-0 = <&pex_rst_c5_in_state>; 5087 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5088 interrupt-names = "intr"; 5089 5090 nvidia,bpmp = <&bpmp 5>; 5091 5092 nvidia,enable-ext-refclk; 5093 nvidia,aspm-cmrt-us = <60>; 5094 nvidia,aspm-pwr-on-t-us = <20>; 5095 nvidia,aspm-l0s-entrance-latency-us = <3>; 5096 aspm-l1-entry-delay-ns = <32000>; 5097 5098 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 5099 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5100 interconnect-names = "dma-mem", "write"; 5101 iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>; 5102 dma-coherent; 5103 5104 status = "disabled"; 5105 }; 5106 5107 pcie@141c0000 { 5108 compatible = "nvidia,tegra234-pcie"; 5109 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5110 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5111 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 5112 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5113 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5114 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5115 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5116 5117 #address-cells = <3>; 5118 #size-cells = <2>; 5119 device_type = "pci"; 5120 num-lanes = <4>; 5121 num-viewport = <8>; 5122 linux,pci-domain = <6>; 5123 5124 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5125 clock-names = "core"; 5126 5127 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5128 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5129 reset-names = "apb", "core"; 5130 5131 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5132 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5133 interrupt-names = "intr", "msi"; 5134 5135 #interrupt-cells = <1>; 5136 interrupt-map-mask = <0 0 0 0>; 5137 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 5138 5139 nvidia,bpmp = <&bpmp 6>; 5140 5141 nvidia,aspm-cmrt-us = <60>; 5142 nvidia,aspm-pwr-on-t-us = <20>; 5143 nvidia,aspm-l0s-entrance-latency-us = <3>; 5144 aspm-l1-entry-delay-ns = <16000>; 5145 5146 bus-range = <0x0 0xff>; 5147 5148 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 5149 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5150 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5151 5152 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5153 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5154 interconnect-names = "dma-mem", "write"; 5155 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 5156 iommu-map-mask = <0x0>; 5157 dma-coherent; 5158 5159 status = "disabled"; 5160 }; 5161 5162 pcie-ep@141c0000 { 5163 compatible = "nvidia,tegra234-pcie-ep"; 5164 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5165 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5166 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5167 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 5168 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 5169 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5170 5171 num-lanes = <4>; 5172 5173 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5174 clock-names = "core"; 5175 5176 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5177 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5178 reset-names = "apb", "core"; 5179 5180 pinctrl-names = "default"; 5181 pinctrl-0 = <&pex_rst_c6_in_state>; 5182 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5183 interrupt-names = "intr"; 5184 5185 nvidia,bpmp = <&bpmp 6>; 5186 5187 nvidia,enable-ext-refclk; 5188 nvidia,aspm-cmrt-us = <60>; 5189 nvidia,aspm-pwr-on-t-us = <20>; 5190 nvidia,aspm-l0s-entrance-latency-us = <3>; 5191 aspm-l1-entry-delay-ns = <32000>; 5192 5193 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5194 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5195 interconnect-names = "dma-mem", "write"; 5196 iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>; 5197 dma-coherent; 5198 5199 status = "disabled"; 5200 }; 5201 5202 pcie@141e0000 { 5203 compatible = "nvidia,tegra234-pcie"; 5204 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5205 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5206 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 5207 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5208 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5209 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5210 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5211 5212 #address-cells = <3>; 5213 #size-cells = <2>; 5214 device_type = "pci"; 5215 num-lanes = <8>; 5216 num-viewport = <8>; 5217 linux,pci-domain = <7>; 5218 5219 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5220 clock-names = "core"; 5221 5222 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5223 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5224 reset-names = "apb", "core"; 5225 5226 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5227 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5228 interrupt-names = "intr", "msi"; 5229 5230 #interrupt-cells = <1>; 5231 interrupt-map-mask = <0 0 0 0>; 5232 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 5233 5234 nvidia,bpmp = <&bpmp 7>; 5235 5236 nvidia,aspm-cmrt-us = <60>; 5237 nvidia,aspm-pwr-on-t-us = <20>; 5238 nvidia,aspm-l0s-entrance-latency-us = <3>; 5239 aspm-l1-entry-delay-ns = <16000>; 5240 5241 bus-range = <0x0 0xff>; 5242 5243 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 5244 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5245 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5246 5247 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5248 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5249 interconnect-names = "dma-mem", "write"; 5250 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 5251 iommu-map-mask = <0x0>; 5252 dma-coherent; 5253 5254 status = "disabled"; 5255 }; 5256 5257 pcie-ep@141e0000 { 5258 compatible = "nvidia,tegra234-pcie-ep"; 5259 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5260 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5261 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5262 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 5263 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5264 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5265 5266 num-lanes = <8>; 5267 5268 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5269 clock-names = "core"; 5270 5271 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5272 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5273 reset-names = "apb", "core"; 5274 5275 pinctrl-names = "default"; 5276 pinctrl-0 = <&pex_rst_c7_in_state>; 5277 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5278 interrupt-names = "intr"; 5279 5280 nvidia,bpmp = <&bpmp 7>; 5281 5282 nvidia,enable-ext-refclk; 5283 nvidia,aspm-cmrt-us = <60>; 5284 nvidia,aspm-pwr-on-t-us = <20>; 5285 nvidia,aspm-l0s-entrance-latency-us = <3>; 5286 aspm-l1-entry-delay-ns = <32000>; 5287 5288 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5289 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5290 interconnect-names = "dma-mem", "write"; 5291 iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>; 5292 dma-coherent; 5293 5294 status = "disabled"; 5295 }; 5296 }; 5297 5298 sram@40000000 { 5299 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 5300 reg = <0x0 0x40000000 0x0 0x80000>; 5301 5302 #address-cells = <1>; 5303 #size-cells = <1>; 5304 ranges = <0x0 0x0 0x40000000 0x80000>; 5305 5306 no-memory-wc; 5307 5308 cpu_bpmp_tx: sram@70000 { 5309 reg = <0x70000 0x1000>; 5310 label = "cpu-bpmp-tx"; 5311 pool; 5312 }; 5313 5314 cpu_bpmp_rx: sram@71000 { 5315 reg = <0x71000 0x1000>; 5316 label = "cpu-bpmp-rx"; 5317 pool; 5318 }; 5319 }; 5320 5321 bpmp: bpmp { 5322 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 5323 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5324 TEGRA_HSP_DB_MASTER_BPMP>; 5325 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 5326 #clock-cells = <1>; 5327 #reset-cells = <1>; 5328 #power-domain-cells = <1>; 5329 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 5330 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 5331 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 5332 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 5333 interconnect-names = "read", "write", "dma-mem", "dma-write"; 5334 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 5335 5336 bpmp_i2c: i2c { 5337 compatible = "nvidia,tegra186-bpmp-i2c"; 5338 nvidia,bpmp-bus-id = <5>; 5339 #address-cells = <1>; 5340 #size-cells = <0>; 5341 }; 5342 5343 bpmp_thermal: thermal { 5344 compatible = "nvidia,tegra186-bpmp-thermal"; 5345 #thermal-sensor-cells = <1>; 5346 }; 5347 }; 5348 5349 cpus { 5350 #address-cells = <1>; 5351 #size-cells = <0>; 5352 5353 cpu0_0: cpu@0 { 5354 compatible = "arm,cortex-a78ae"; 5355 device_type = "cpu"; 5356 reg = <0x00000>; 5357 5358 enable-method = "psci"; 5359 5360 operating-points-v2 = <&cl0_opp_tbl>; 5361 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5362 5363 i-cache-size = <65536>; 5364 i-cache-line-size = <64>; 5365 i-cache-sets = <256>; 5366 d-cache-size = <65536>; 5367 d-cache-line-size = <64>; 5368 d-cache-sets = <256>; 5369 next-level-cache = <&l2c0_0>; 5370 }; 5371 5372 cpu0_1: cpu@100 { 5373 compatible = "arm,cortex-a78ae"; 5374 device_type = "cpu"; 5375 reg = <0x00100>; 5376 5377 enable-method = "psci"; 5378 5379 operating-points-v2 = <&cl0_opp_tbl>; 5380 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5381 5382 i-cache-size = <65536>; 5383 i-cache-line-size = <64>; 5384 i-cache-sets = <256>; 5385 d-cache-size = <65536>; 5386 d-cache-line-size = <64>; 5387 d-cache-sets = <256>; 5388 next-level-cache = <&l2c0_1>; 5389 }; 5390 5391 cpu0_2: cpu@200 { 5392 compatible = "arm,cortex-a78ae"; 5393 device_type = "cpu"; 5394 reg = <0x00200>; 5395 5396 enable-method = "psci"; 5397 5398 operating-points-v2 = <&cl0_opp_tbl>; 5399 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5400 5401 i-cache-size = <65536>; 5402 i-cache-line-size = <64>; 5403 i-cache-sets = <256>; 5404 d-cache-size = <65536>; 5405 d-cache-line-size = <64>; 5406 d-cache-sets = <256>; 5407 next-level-cache = <&l2c0_2>; 5408 }; 5409 5410 cpu0_3: cpu@300 { 5411 compatible = "arm,cortex-a78ae"; 5412 device_type = "cpu"; 5413 reg = <0x00300>; 5414 5415 enable-method = "psci"; 5416 5417 operating-points-v2 = <&cl0_opp_tbl>; 5418 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5419 5420 i-cache-size = <65536>; 5421 i-cache-line-size = <64>; 5422 i-cache-sets = <256>; 5423 d-cache-size = <65536>; 5424 d-cache-line-size = <64>; 5425 d-cache-sets = <256>; 5426 next-level-cache = <&l2c0_3>; 5427 }; 5428 5429 cpu1_0: cpu@10000 { 5430 compatible = "arm,cortex-a78ae"; 5431 device_type = "cpu"; 5432 reg = <0x10000>; 5433 5434 enable-method = "psci"; 5435 5436 operating-points-v2 = <&cl1_opp_tbl>; 5437 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5438 5439 i-cache-size = <65536>; 5440 i-cache-line-size = <64>; 5441 i-cache-sets = <256>; 5442 d-cache-size = <65536>; 5443 d-cache-line-size = <64>; 5444 d-cache-sets = <256>; 5445 next-level-cache = <&l2c1_0>; 5446 }; 5447 5448 cpu1_1: cpu@10100 { 5449 compatible = "arm,cortex-a78ae"; 5450 device_type = "cpu"; 5451 reg = <0x10100>; 5452 5453 enable-method = "psci"; 5454 5455 operating-points-v2 = <&cl1_opp_tbl>; 5456 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5457 5458 i-cache-size = <65536>; 5459 i-cache-line-size = <64>; 5460 i-cache-sets = <256>; 5461 d-cache-size = <65536>; 5462 d-cache-line-size = <64>; 5463 d-cache-sets = <256>; 5464 next-level-cache = <&l2c1_1>; 5465 }; 5466 5467 cpu1_2: cpu@10200 { 5468 compatible = "arm,cortex-a78ae"; 5469 device_type = "cpu"; 5470 reg = <0x10200>; 5471 5472 enable-method = "psci"; 5473 5474 operating-points-v2 = <&cl1_opp_tbl>; 5475 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5476 5477 i-cache-size = <65536>; 5478 i-cache-line-size = <64>; 5479 i-cache-sets = <256>; 5480 d-cache-size = <65536>; 5481 d-cache-line-size = <64>; 5482 d-cache-sets = <256>; 5483 next-level-cache = <&l2c1_2>; 5484 }; 5485 5486 cpu1_3: cpu@10300 { 5487 compatible = "arm,cortex-a78ae"; 5488 device_type = "cpu"; 5489 reg = <0x10300>; 5490 5491 enable-method = "psci"; 5492 5493 operating-points-v2 = <&cl1_opp_tbl>; 5494 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5495 5496 i-cache-size = <65536>; 5497 i-cache-line-size = <64>; 5498 i-cache-sets = <256>; 5499 d-cache-size = <65536>; 5500 d-cache-line-size = <64>; 5501 d-cache-sets = <256>; 5502 next-level-cache = <&l2c1_3>; 5503 }; 5504 5505 cpu2_0: cpu@20000 { 5506 compatible = "arm,cortex-a78ae"; 5507 device_type = "cpu"; 5508 reg = <0x20000>; 5509 5510 enable-method = "psci"; 5511 5512 operating-points-v2 = <&cl2_opp_tbl>; 5513 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5514 5515 i-cache-size = <65536>; 5516 i-cache-line-size = <64>; 5517 i-cache-sets = <256>; 5518 d-cache-size = <65536>; 5519 d-cache-line-size = <64>; 5520 d-cache-sets = <256>; 5521 next-level-cache = <&l2c2_0>; 5522 }; 5523 5524 cpu2_1: cpu@20100 { 5525 compatible = "arm,cortex-a78ae"; 5526 device_type = "cpu"; 5527 reg = <0x20100>; 5528 5529 enable-method = "psci"; 5530 5531 operating-points-v2 = <&cl2_opp_tbl>; 5532 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5533 5534 i-cache-size = <65536>; 5535 i-cache-line-size = <64>; 5536 i-cache-sets = <256>; 5537 d-cache-size = <65536>; 5538 d-cache-line-size = <64>; 5539 d-cache-sets = <256>; 5540 next-level-cache = <&l2c2_1>; 5541 }; 5542 5543 cpu2_2: cpu@20200 { 5544 compatible = "arm,cortex-a78ae"; 5545 device_type = "cpu"; 5546 reg = <0x20200>; 5547 5548 enable-method = "psci"; 5549 5550 operating-points-v2 = <&cl2_opp_tbl>; 5551 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5552 5553 i-cache-size = <65536>; 5554 i-cache-line-size = <64>; 5555 i-cache-sets = <256>; 5556 d-cache-size = <65536>; 5557 d-cache-line-size = <64>; 5558 d-cache-sets = <256>; 5559 next-level-cache = <&l2c2_2>; 5560 }; 5561 5562 cpu2_3: cpu@20300 { 5563 compatible = "arm,cortex-a78ae"; 5564 device_type = "cpu"; 5565 reg = <0x20300>; 5566 5567 enable-method = "psci"; 5568 5569 operating-points-v2 = <&cl2_opp_tbl>; 5570 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5571 5572 i-cache-size = <65536>; 5573 i-cache-line-size = <64>; 5574 i-cache-sets = <256>; 5575 d-cache-size = <65536>; 5576 d-cache-line-size = <64>; 5577 d-cache-sets = <256>; 5578 next-level-cache = <&l2c2_3>; 5579 }; 5580 5581 cpu-map { 5582 cluster0 { 5583 core0 { 5584 cpu = <&cpu0_0>; 5585 }; 5586 5587 core1 { 5588 cpu = <&cpu0_1>; 5589 }; 5590 5591 core2 { 5592 cpu = <&cpu0_2>; 5593 }; 5594 5595 core3 { 5596 cpu = <&cpu0_3>; 5597 }; 5598 }; 5599 5600 cluster1 { 5601 core0 { 5602 cpu = <&cpu1_0>; 5603 }; 5604 5605 core1 { 5606 cpu = <&cpu1_1>; 5607 }; 5608 5609 core2 { 5610 cpu = <&cpu1_2>; 5611 }; 5612 5613 core3 { 5614 cpu = <&cpu1_3>; 5615 }; 5616 }; 5617 5618 cluster2 { 5619 core0 { 5620 cpu = <&cpu2_0>; 5621 }; 5622 5623 core1 { 5624 cpu = <&cpu2_1>; 5625 }; 5626 5627 core2 { 5628 cpu = <&cpu2_2>; 5629 }; 5630 5631 core3 { 5632 cpu = <&cpu2_3>; 5633 }; 5634 }; 5635 }; 5636 5637 l2c0_0: l2-cache00 { 5638 compatible = "cache"; 5639 cache-size = <262144>; 5640 cache-line-size = <64>; 5641 cache-sets = <512>; 5642 cache-unified; 5643 cache-level = <2>; 5644 next-level-cache = <&l3c0>; 5645 }; 5646 5647 l2c0_1: l2-cache01 { 5648 compatible = "cache"; 5649 cache-size = <262144>; 5650 cache-line-size = <64>; 5651 cache-sets = <512>; 5652 cache-unified; 5653 cache-level = <2>; 5654 next-level-cache = <&l3c0>; 5655 }; 5656 5657 l2c0_2: l2-cache02 { 5658 compatible = "cache"; 5659 cache-size = <262144>; 5660 cache-line-size = <64>; 5661 cache-sets = <512>; 5662 cache-unified; 5663 cache-level = <2>; 5664 next-level-cache = <&l3c0>; 5665 }; 5666 5667 l2c0_3: l2-cache03 { 5668 compatible = "cache"; 5669 cache-size = <262144>; 5670 cache-line-size = <64>; 5671 cache-sets = <512>; 5672 cache-unified; 5673 cache-level = <2>; 5674 next-level-cache = <&l3c0>; 5675 }; 5676 5677 l2c1_0: l2-cache10 { 5678 compatible = "cache"; 5679 cache-size = <262144>; 5680 cache-line-size = <64>; 5681 cache-sets = <512>; 5682 cache-unified; 5683 cache-level = <2>; 5684 next-level-cache = <&l3c1>; 5685 }; 5686 5687 l2c1_1: l2-cache11 { 5688 compatible = "cache"; 5689 cache-size = <262144>; 5690 cache-line-size = <64>; 5691 cache-sets = <512>; 5692 cache-unified; 5693 cache-level = <2>; 5694 next-level-cache = <&l3c1>; 5695 }; 5696 5697 l2c1_2: l2-cache12 { 5698 compatible = "cache"; 5699 cache-size = <262144>; 5700 cache-line-size = <64>; 5701 cache-sets = <512>; 5702 cache-unified; 5703 cache-level = <2>; 5704 next-level-cache = <&l3c1>; 5705 }; 5706 5707 l2c1_3: l2-cache13 { 5708 compatible = "cache"; 5709 cache-size = <262144>; 5710 cache-line-size = <64>; 5711 cache-sets = <512>; 5712 cache-unified; 5713 cache-level = <2>; 5714 next-level-cache = <&l3c1>; 5715 }; 5716 5717 l2c2_0: l2-cache20 { 5718 compatible = "cache"; 5719 cache-size = <262144>; 5720 cache-line-size = <64>; 5721 cache-sets = <512>; 5722 cache-unified; 5723 cache-level = <2>; 5724 next-level-cache = <&l3c2>; 5725 }; 5726 5727 l2c2_1: l2-cache21 { 5728 compatible = "cache"; 5729 cache-size = <262144>; 5730 cache-line-size = <64>; 5731 cache-sets = <512>; 5732 cache-unified; 5733 cache-level = <2>; 5734 next-level-cache = <&l3c2>; 5735 }; 5736 5737 l2c2_2: l2-cache22 { 5738 compatible = "cache"; 5739 cache-size = <262144>; 5740 cache-line-size = <64>; 5741 cache-sets = <512>; 5742 cache-unified; 5743 cache-level = <2>; 5744 next-level-cache = <&l3c2>; 5745 }; 5746 5747 l2c2_3: l2-cache23 { 5748 compatible = "cache"; 5749 cache-size = <262144>; 5750 cache-line-size = <64>; 5751 cache-sets = <512>; 5752 cache-unified; 5753 cache-level = <2>; 5754 next-level-cache = <&l3c2>; 5755 }; 5756 5757 l3c0: l3-cache0 { 5758 compatible = "cache"; 5759 cache-unified; 5760 cache-size = <2097152>; 5761 cache-line-size = <64>; 5762 cache-sets = <2048>; 5763 cache-level = <3>; 5764 }; 5765 5766 l3c1: l3-cache1 { 5767 compatible = "cache"; 5768 cache-unified; 5769 cache-size = <2097152>; 5770 cache-line-size = <64>; 5771 cache-sets = <2048>; 5772 cache-level = <3>; 5773 }; 5774 5775 l3c2: l3-cache2 { 5776 compatible = "cache"; 5777 cache-unified; 5778 cache-size = <2097152>; 5779 cache-line-size = <64>; 5780 cache-sets = <2048>; 5781 cache-level = <3>; 5782 }; 5783 }; 5784 5785 dsu-pmu0 { 5786 compatible = "arm,dsu-pmu"; 5787 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 5788 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 5789 }; 5790 5791 dsu-pmu1 { 5792 compatible = "arm,dsu-pmu"; 5793 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 5794 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 5795 }; 5796 5797 dsu-pmu2 { 5798 compatible = "arm,dsu-pmu"; 5799 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 5800 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 5801 }; 5802 5803 pmu { 5804 compatible = "arm,cortex-a78-pmu"; 5805 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 5806 }; 5807 5808 psci { 5809 compatible = "arm,psci-1.0"; 5810 method = "smc"; 5811 }; 5812 5813 tcu: serial { 5814 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 5815 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 5816 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 5817 mbox-names = "rx", "tx"; 5818 status = "disabled"; 5819 }; 5820 5821 sound { 5822 status = "disabled"; 5823 5824 clocks = <&bpmp TEGRA234_CLK_PLLA>, 5825 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5826 clock-names = "pll_a", "plla_out0"; 5827 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 5828 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 5829 <&bpmp TEGRA234_CLK_AUD_MCLK>; 5830 assigned-clock-parents = <0>, 5831 <&bpmp TEGRA234_CLK_PLLA>, 5832 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5833 }; 5834 5835 thermal-zones { 5836 cpu-thermal { 5837 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 5838 status = "disabled"; 5839 }; 5840 5841 gpu-thermal { 5842 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 5843 status = "disabled"; 5844 }; 5845 5846 cv0-thermal { 5847 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 5848 status = "disabled"; 5849 }; 5850 5851 cv1-thermal { 5852 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 5853 status = "disabled"; 5854 }; 5855 5856 cv2-thermal { 5857 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 5858 status = "disabled"; 5859 }; 5860 5861 soc0-thermal { 5862 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 5863 status = "disabled"; 5864 }; 5865 5866 soc1-thermal { 5867 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 5868 status = "disabled"; 5869 }; 5870 5871 soc2-thermal { 5872 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 5873 status = "disabled"; 5874 }; 5875 5876 tj-thermal { 5877 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 5878 status = "disabled"; 5879 }; 5880 }; 5881 5882 timer { 5883 compatible = "arm,armv8-timer"; 5884 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5885 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5886 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5887 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5888 interrupt-parent = <&gic>; 5889 always-on; 5890 }; 5891 5892 cl0_opp_tbl: opp-table-cluster0 { 5893 compatible = "operating-points-v2"; 5894 opp-shared; 5895 5896 cl0_ch1_opp1: opp-115200000 { 5897 opp-hz = /bits/ 64 <115200000>; 5898 opp-peak-kBps = <816000>; 5899 }; 5900 5901 cl0_ch1_opp2: opp-192000000 { 5902 opp-hz = /bits/ 64 <192000000>; 5903 opp-peak-kBps = <816000>; 5904 }; 5905 5906 cl0_ch1_opp3: opp-268800000 { 5907 opp-hz = /bits/ 64 <268800000>; 5908 opp-peak-kBps = <816000>; 5909 }; 5910 5911 cl0_ch1_opp4: opp-345600000 { 5912 opp-hz = /bits/ 64 <345600000>; 5913 opp-peak-kBps = <816000>; 5914 }; 5915 5916 cl0_ch1_opp5: opp-422400000 { 5917 opp-hz = /bits/ 64 <422400000>; 5918 opp-peak-kBps = <816000>; 5919 }; 5920 5921 cl0_ch1_opp6: opp-499200000 { 5922 opp-hz = /bits/ 64 <499200000>; 5923 opp-peak-kBps = <816000>; 5924 }; 5925 5926 cl0_ch1_opp7: opp-576000000 { 5927 opp-hz = /bits/ 64 <576000000>; 5928 opp-peak-kBps = <816000>; 5929 }; 5930 5931 cl0_ch1_opp8: opp-652800000 { 5932 opp-hz = /bits/ 64 <652800000>; 5933 opp-peak-kBps = <816000>; 5934 }; 5935 5936 cl0_ch1_opp9: opp-729600000 { 5937 opp-hz = /bits/ 64 <729600000>; 5938 opp-peak-kBps = <816000>; 5939 }; 5940 5941 cl0_ch1_opp10: opp-806400000 { 5942 opp-hz = /bits/ 64 <806400000>; 5943 opp-peak-kBps = <816000>; 5944 }; 5945 5946 cl0_ch1_opp11: opp-883200000 { 5947 opp-hz = /bits/ 64 <883200000>; 5948 opp-peak-kBps = <816000>; 5949 }; 5950 5951 cl0_ch1_opp12: opp-960000000 { 5952 opp-hz = /bits/ 64 <960000000>; 5953 opp-peak-kBps = <816000>; 5954 }; 5955 5956 cl0_ch1_opp13: opp-1036800000 { 5957 opp-hz = /bits/ 64 <1036800000>; 5958 opp-peak-kBps = <816000>; 5959 }; 5960 5961 cl0_ch1_opp14: opp-1113600000 { 5962 opp-hz = /bits/ 64 <1113600000>; 5963 opp-peak-kBps = <1632000>; 5964 }; 5965 5966 cl0_ch1_opp15: opp-1190400000 { 5967 opp-hz = /bits/ 64 <1190400000>; 5968 opp-peak-kBps = <1632000>; 5969 }; 5970 5971 cl0_ch1_opp16: opp-1267200000 { 5972 opp-hz = /bits/ 64 <1267200000>; 5973 opp-peak-kBps = <1632000>; 5974 }; 5975 5976 cl0_ch1_opp17: opp-1344000000 { 5977 opp-hz = /bits/ 64 <1344000000>; 5978 opp-peak-kBps = <1632000>; 5979 }; 5980 5981 cl0_ch1_opp18: opp-1420800000 { 5982 opp-hz = /bits/ 64 <1420800000>; 5983 opp-peak-kBps = <1632000>; 5984 }; 5985 5986 cl0_ch1_opp19: opp-1497600000 { 5987 opp-hz = /bits/ 64 <1497600000>; 5988 opp-peak-kBps = <3200000>; 5989 }; 5990 5991 cl0_ch1_opp20: opp-1574400000 { 5992 opp-hz = /bits/ 64 <1574400000>; 5993 opp-peak-kBps = <3200000>; 5994 }; 5995 5996 cl0_ch1_opp21: opp-1651200000 { 5997 opp-hz = /bits/ 64 <1651200000>; 5998 opp-peak-kBps = <3200000>; 5999 }; 6000 6001 cl0_ch1_opp22: opp-1728000000 { 6002 opp-hz = /bits/ 64 <1728000000>; 6003 opp-peak-kBps = <3200000>; 6004 }; 6005 6006 cl0_ch1_opp23: opp-1804800000 { 6007 opp-hz = /bits/ 64 <1804800000>; 6008 opp-peak-kBps = <3200000>; 6009 }; 6010 6011 cl0_ch1_opp24: opp-1881600000 { 6012 opp-hz = /bits/ 64 <1881600000>; 6013 opp-peak-kBps = <3200000>; 6014 }; 6015 6016 cl0_ch1_opp25: opp-1958400000 { 6017 opp-hz = /bits/ 64 <1958400000>; 6018 opp-peak-kBps = <3200000>; 6019 }; 6020 6021 cl0_ch1_opp26: opp-2035200000 { 6022 opp-hz = /bits/ 64 <2035200000>; 6023 opp-peak-kBps = <3200000>; 6024 }; 6025 6026 cl0_ch1_opp27: opp-2112000000 { 6027 opp-hz = /bits/ 64 <2112000000>; 6028 opp-peak-kBps = <6400000>; 6029 }; 6030 6031 cl0_ch1_opp28: opp-2188800000 { 6032 opp-hz = /bits/ 64 <2188800000>; 6033 opp-peak-kBps = <6400000>; 6034 }; 6035 6036 cl0_ch1_opp29: opp-2201600000 { 6037 opp-hz = /bits/ 64 <2201600000>; 6038 opp-peak-kBps = <6400000>; 6039 }; 6040 }; 6041 6042 cl1_opp_tbl: opp-table-cluster1 { 6043 compatible = "operating-points-v2"; 6044 opp-shared; 6045 6046 cl1_ch1_opp1: opp-115200000 { 6047 opp-hz = /bits/ 64 <115200000>; 6048 opp-peak-kBps = <816000>; 6049 }; 6050 6051 cl1_ch1_opp2: opp-192000000 { 6052 opp-hz = /bits/ 64 <192000000>; 6053 opp-peak-kBps = <816000>; 6054 }; 6055 6056 cl1_ch1_opp3: opp-268800000 { 6057 opp-hz = /bits/ 64 <268800000>; 6058 opp-peak-kBps = <816000>; 6059 }; 6060 6061 cl1_ch1_opp4: opp-345600000 { 6062 opp-hz = /bits/ 64 <345600000>; 6063 opp-peak-kBps = <816000>; 6064 }; 6065 6066 cl1_ch1_opp5: opp-422400000 { 6067 opp-hz = /bits/ 64 <422400000>; 6068 opp-peak-kBps = <816000>; 6069 }; 6070 6071 cl1_ch1_opp6: opp-499200000 { 6072 opp-hz = /bits/ 64 <499200000>; 6073 opp-peak-kBps = <816000>; 6074 }; 6075 6076 cl1_ch1_opp7: opp-576000000 { 6077 opp-hz = /bits/ 64 <576000000>; 6078 opp-peak-kBps = <816000>; 6079 }; 6080 6081 cl1_ch1_opp8: opp-652800000 { 6082 opp-hz = /bits/ 64 <652800000>; 6083 opp-peak-kBps = <816000>; 6084 }; 6085 6086 cl1_ch1_opp9: opp-729600000 { 6087 opp-hz = /bits/ 64 <729600000>; 6088 opp-peak-kBps = <816000>; 6089 }; 6090 6091 cl1_ch1_opp10: opp-806400000 { 6092 opp-hz = /bits/ 64 <806400000>; 6093 opp-peak-kBps = <816000>; 6094 }; 6095 6096 cl1_ch1_opp11: opp-883200000 { 6097 opp-hz = /bits/ 64 <883200000>; 6098 opp-peak-kBps = <816000>; 6099 }; 6100 6101 cl1_ch1_opp12: opp-960000000 { 6102 opp-hz = /bits/ 64 <960000000>; 6103 opp-peak-kBps = <816000>; 6104 }; 6105 6106 cl1_ch1_opp13: opp-1036800000 { 6107 opp-hz = /bits/ 64 <1036800000>; 6108 opp-peak-kBps = <816000>; 6109 }; 6110 6111 cl1_ch1_opp14: opp-1113600000 { 6112 opp-hz = /bits/ 64 <1113600000>; 6113 opp-peak-kBps = <1632000>; 6114 }; 6115 6116 cl1_ch1_opp15: opp-1190400000 { 6117 opp-hz = /bits/ 64 <1190400000>; 6118 opp-peak-kBps = <1632000>; 6119 }; 6120 6121 cl1_ch1_opp16: opp-1267200000 { 6122 opp-hz = /bits/ 64 <1267200000>; 6123 opp-peak-kBps = <1632000>; 6124 }; 6125 6126 cl1_ch1_opp17: opp-1344000000 { 6127 opp-hz = /bits/ 64 <1344000000>; 6128 opp-peak-kBps = <1632000>; 6129 }; 6130 6131 cl1_ch1_opp18: opp-1420800000 { 6132 opp-hz = /bits/ 64 <1420800000>; 6133 opp-peak-kBps = <1632000>; 6134 }; 6135 6136 cl1_ch1_opp19: opp-1497600000 { 6137 opp-hz = /bits/ 64 <1497600000>; 6138 opp-peak-kBps = <3200000>; 6139 }; 6140 6141 cl1_ch1_opp20: opp-1574400000 { 6142 opp-hz = /bits/ 64 <1574400000>; 6143 opp-peak-kBps = <3200000>; 6144 }; 6145 6146 cl1_ch1_opp21: opp-1651200000 { 6147 opp-hz = /bits/ 64 <1651200000>; 6148 opp-peak-kBps = <3200000>; 6149 }; 6150 6151 cl1_ch1_opp22: opp-1728000000 { 6152 opp-hz = /bits/ 64 <1728000000>; 6153 opp-peak-kBps = <3200000>; 6154 }; 6155 6156 cl1_ch1_opp23: opp-1804800000 { 6157 opp-hz = /bits/ 64 <1804800000>; 6158 opp-peak-kBps = <3200000>; 6159 }; 6160 6161 cl1_ch1_opp24: opp-1881600000 { 6162 opp-hz = /bits/ 64 <1881600000>; 6163 opp-peak-kBps = <3200000>; 6164 }; 6165 6166 cl1_ch1_opp25: opp-1958400000 { 6167 opp-hz = /bits/ 64 <1958400000>; 6168 opp-peak-kBps = <3200000>; 6169 }; 6170 6171 cl1_ch1_opp26: opp-2035200000 { 6172 opp-hz = /bits/ 64 <2035200000>; 6173 opp-peak-kBps = <3200000>; 6174 }; 6175 6176 cl1_ch1_opp27: opp-2112000000 { 6177 opp-hz = /bits/ 64 <2112000000>; 6178 opp-peak-kBps = <6400000>; 6179 }; 6180 6181 cl1_ch1_opp28: opp-2188800000 { 6182 opp-hz = /bits/ 64 <2188800000>; 6183 opp-peak-kBps = <6400000>; 6184 }; 6185 6186 cl1_ch1_opp29: opp-2201600000 { 6187 opp-hz = /bits/ 64 <2201600000>; 6188 opp-peak-kBps = <6400000>; 6189 }; 6190 }; 6191 6192 cl2_opp_tbl: opp-table-cluster2 { 6193 compatible = "operating-points-v2"; 6194 opp-shared; 6195 6196 cl2_ch1_opp1: opp-115200000 { 6197 opp-hz = /bits/ 64 <115200000>; 6198 opp-peak-kBps = <816000>; 6199 }; 6200 6201 cl2_ch1_opp2: opp-192000000 { 6202 opp-hz = /bits/ 64 <192000000>; 6203 opp-peak-kBps = <816000>; 6204 }; 6205 6206 cl2_ch1_opp3: opp-268800000 { 6207 opp-hz = /bits/ 64 <268800000>; 6208 opp-peak-kBps = <816000>; 6209 }; 6210 6211 cl2_ch1_opp4: opp-345600000 { 6212 opp-hz = /bits/ 64 <345600000>; 6213 opp-peak-kBps = <816000>; 6214 }; 6215 6216 cl2_ch1_opp5: opp-422400000 { 6217 opp-hz = /bits/ 64 <422400000>; 6218 opp-peak-kBps = <816000>; 6219 }; 6220 6221 cl2_ch1_opp6: opp-499200000 { 6222 opp-hz = /bits/ 64 <499200000>; 6223 opp-peak-kBps = <816000>; 6224 }; 6225 6226 cl2_ch1_opp7: opp-576000000 { 6227 opp-hz = /bits/ 64 <576000000>; 6228 opp-peak-kBps = <816000>; 6229 }; 6230 6231 cl2_ch1_opp8: opp-652800000 { 6232 opp-hz = /bits/ 64 <652800000>; 6233 opp-peak-kBps = <816000>; 6234 }; 6235 6236 cl2_ch1_opp9: opp-729600000 { 6237 opp-hz = /bits/ 64 <729600000>; 6238 opp-peak-kBps = <816000>; 6239 }; 6240 6241 cl2_ch1_opp10: opp-806400000 { 6242 opp-hz = /bits/ 64 <806400000>; 6243 opp-peak-kBps = <816000>; 6244 }; 6245 6246 cl2_ch1_opp11: opp-883200000 { 6247 opp-hz = /bits/ 64 <883200000>; 6248 opp-peak-kBps = <816000>; 6249 }; 6250 6251 cl2_ch1_opp12: opp-960000000 { 6252 opp-hz = /bits/ 64 <960000000>; 6253 opp-peak-kBps = <816000>; 6254 }; 6255 6256 cl2_ch1_opp13: opp-1036800000 { 6257 opp-hz = /bits/ 64 <1036800000>; 6258 opp-peak-kBps = <816000>; 6259 }; 6260 6261 cl2_ch1_opp14: opp-1113600000 { 6262 opp-hz = /bits/ 64 <1113600000>; 6263 opp-peak-kBps = <1632000>; 6264 }; 6265 6266 cl2_ch1_opp15: opp-1190400000 { 6267 opp-hz = /bits/ 64 <1190400000>; 6268 opp-peak-kBps = <1632000>; 6269 }; 6270 6271 cl2_ch1_opp16: opp-1267200000 { 6272 opp-hz = /bits/ 64 <1267200000>; 6273 opp-peak-kBps = <1632000>; 6274 }; 6275 6276 cl2_ch1_opp17: opp-1344000000 { 6277 opp-hz = /bits/ 64 <1344000000>; 6278 opp-peak-kBps = <1632000>; 6279 }; 6280 6281 cl2_ch1_opp18: opp-1420800000 { 6282 opp-hz = /bits/ 64 <1420800000>; 6283 opp-peak-kBps = <1632000>; 6284 }; 6285 6286 cl2_ch1_opp19: opp-1497600000 { 6287 opp-hz = /bits/ 64 <1497600000>; 6288 opp-peak-kBps = <3200000>; 6289 }; 6290 6291 cl2_ch1_opp20: opp-1574400000 { 6292 opp-hz = /bits/ 64 <1574400000>; 6293 opp-peak-kBps = <3200000>; 6294 }; 6295 6296 cl2_ch1_opp21: opp-1651200000 { 6297 opp-hz = /bits/ 64 <1651200000>; 6298 opp-peak-kBps = <3200000>; 6299 }; 6300 6301 cl2_ch1_opp22: opp-1728000000 { 6302 opp-hz = /bits/ 64 <1728000000>; 6303 opp-peak-kBps = <3200000>; 6304 }; 6305 6306 cl2_ch1_opp23: opp-1804800000 { 6307 opp-hz = /bits/ 64 <1804800000>; 6308 opp-peak-kBps = <3200000>; 6309 }; 6310 6311 cl2_ch1_opp24: opp-1881600000 { 6312 opp-hz = /bits/ 64 <1881600000>; 6313 opp-peak-kBps = <3200000>; 6314 }; 6315 6316 cl2_ch1_opp25: opp-1958400000 { 6317 opp-hz = /bits/ 64 <1958400000>; 6318 opp-peak-kBps = <3200000>; 6319 }; 6320 6321 cl2_ch1_opp26: opp-2035200000 { 6322 opp-hz = /bits/ 64 <2035200000>; 6323 opp-peak-kBps = <3200000>; 6324 }; 6325 6326 cl2_ch1_opp27: opp-2112000000 { 6327 opp-hz = /bits/ 64 <2112000000>; 6328 opp-peak-kBps = <6400000>; 6329 }; 6330 6331 cl2_ch1_opp28: opp-2188800000 { 6332 opp-hz = /bits/ 64 <2188800000>; 6333 opp-peak-kBps = <6400000>; 6334 }; 6335 6336 cl2_ch1_opp29: opp-2201600000 { 6337 opp-hz = /bits/ 64 <2201600000>; 6338 opp-peak-kBps = <6400000>; 6339 }; 6340 }; 6341}; 6342