1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include "regs.h"
17 #include "rtl8xxxu.h"
18
19 static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
20 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
21 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
22 {0x430, 0x00}, {0x431, 0x00},
23 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
24 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
25 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
26 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
27 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
28 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
29 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
30 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
31 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
32 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
33 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
34 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
35 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
36 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
37 {0x516, 0x0a}, {0x525, 0x4f},
38 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
39 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
40 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
41 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
42 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
43 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
44 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
45 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
46 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
47 {0xffff, 0xff},
48 };
49
50 static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
51 {0x800, 0x80040000}, {0x804, 0x00000003},
52 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
53 {0x810, 0x10001331}, {0x814, 0x020c3d10},
54 {0x818, 0x02200385}, {0x81c, 0x00000000},
55 {0x820, 0x01000100}, {0x824, 0x00190204},
56 {0x828, 0x00000000}, {0x82c, 0x00000000},
57 {0x830, 0x00000000}, {0x834, 0x00000000},
58 {0x838, 0x00000000}, {0x83c, 0x00000000},
59 {0x840, 0x00010000}, {0x844, 0x00000000},
60 {0x848, 0x00000000}, {0x84c, 0x00000000},
61 {0x850, 0x00000000}, {0x854, 0x00000000},
62 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
63 {0x860, 0x66f60110}, {0x864, 0x061f0649},
64 {0x868, 0x00000000}, {0x86c, 0x27272700},
65 {0x870, 0x07000760}, {0x874, 0x25004000},
66 {0x878, 0x00000808}, {0x87c, 0x00000000},
67 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
68 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
69 {0x890, 0x00000800}, {0x894, 0xfffffffe},
70 {0x898, 0x40302010}, {0x89c, 0x00706050},
71 {0x900, 0x00000000}, {0x904, 0x00000023},
72 {0x908, 0x00000000}, {0x90c, 0x81121111},
73 {0x910, 0x00000002}, {0x914, 0x00000201},
74 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
75 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
76 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
77 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
78 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
79 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
80 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
81 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
82 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
83 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
84 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
85 {0xc10, 0x08800000}, {0xc14, 0x40000100},
86 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
87 {0xc20, 0x00000000}, {0xc24, 0x00000000},
88 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
89 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
90 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
91 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
92 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
93 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
94 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
95 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
96 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
97 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
98 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
99 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
100 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
101 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
102 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
103 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
104 {0xca8, 0x00000000}, {0xcac, 0x00000000},
105 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
106 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
107 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
108 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
109 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
110 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
111 {0xce0, 0x00222222}, {0xce4, 0x00000000},
112 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
113 {0xd00, 0x00000740}, {0xd04, 0x40020401},
114 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
115 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
116 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
117 {0xd30, 0x00000000}, {0xd34, 0x80608000},
118 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
119 {0xd40, 0x00000000}, {0xd44, 0x00000000},
120 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
121 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
122 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
123 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
124 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
125 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
126 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
127 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
128 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
129 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
130 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
131 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
132 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
133 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
134 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
135 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
136 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
137 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
138 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
139 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
140 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
141 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
142 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
143 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
144 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
145 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
146 {0xf00, 0x00000300},
147 {0x820, 0x01000100}, {0x800, 0x83040000},
148 {0xffff, 0xffffffff},
149 };
150
151 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
152 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
153 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
154 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
155 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
156 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
157 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
158 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
159 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
160 {0xc78, 0xed100001}, {0xc78, 0xec110001},
161 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
162 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
163 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
164 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
165 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
166 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
167 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
168 {0xc78, 0x65200001}, {0xc78, 0x64210001},
169 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
170 {0xc78, 0x49240001}, {0xc78, 0x48250001},
171 {0xc78, 0x47260001}, {0xc78, 0x46270001},
172 {0xc78, 0x45280001}, {0xc78, 0x44290001},
173 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
174 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
175 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
176 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
177 {0xc78, 0x08320001}, {0xc78, 0x07330001},
178 {0xc78, 0x06340001}, {0xc78, 0x05350001},
179 {0xc78, 0x04360001}, {0xc78, 0x03370001},
180 {0xc78, 0x02380001}, {0xc78, 0x01390001},
181 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
182 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
183 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
184 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
185 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
186 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
187 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
188 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
189 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
190 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
191 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
192 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
193 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
194 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
195 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
196 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
197 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
198 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
199 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
200 {0xc78, 0x65600001}, {0xc78, 0x64610001},
201 {0xc78, 0x63620001}, {0xc78, 0x62630001},
202 {0xc78, 0x61640001}, {0xc78, 0x48650001},
203 {0xc78, 0x47660001}, {0xc78, 0x46670001},
204 {0xc78, 0x45680001}, {0xc78, 0x44690001},
205 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
206 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
207 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
208 {0xc78, 0x24700001}, {0xc78, 0x09710001},
209 {0xc78, 0x08720001}, {0xc78, 0x07730001},
210 {0xc78, 0x06740001}, {0xc78, 0x05750001},
211 {0xc78, 0x04760001}, {0xc78, 0x03770001},
212 {0xc78, 0x02780001}, {0xc78, 0x01790001},
213 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
214 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
215 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
216 {0xc50, 0x69553422},
217 {0xc50, 0x69553420},
218 {0x824, 0x00390204},
219 {0xffff, 0xffffffff}
220 };
221
222 static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
223 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
224 {0xfe, 0x00000000}, {0xfe, 0x00000000},
225 {0xfe, 0x00000000}, {0xb1, 0x00000018},
226 {0xfe, 0x00000000}, {0xfe, 0x00000000},
227 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
228 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
229 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
230 {0x5c, 0x00000002}, {0x7c, 0x00000002},
231 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
232 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
233 {0x1e, 0x00000000}, {0xdf, 0x00000780},
234 {0x50, 0x00067435},
235 /*
236 * The 8723bu vendor driver indicates that bit 8 should be set in
237 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
238 * they never actually check the package type - and just default
239 * to not setting it.
240 */
241 {0x51, 0x0006b04e},
242 {0x52, 0x000007d2}, {0x53, 0x00000000},
243 {0x54, 0x00050400}, {0x55, 0x0004026e},
244 {0xdd, 0x0000004c}, {0x70, 0x00067435},
245 /*
246 * 0x71 has same package type condition as for register 0x51
247 */
248 {0x71, 0x0006b04e},
249 {0x72, 0x000007d2}, {0x73, 0x00000000},
250 {0x74, 0x00050400}, {0x75, 0x0004026e},
251 {0xef, 0x00000100}, {0x34, 0x0000add7},
252 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
253 {0x35, 0x00005000}, {0x34, 0x00008dd1},
254 {0x35, 0x00004400}, {0x34, 0x00007dce},
255 {0x35, 0x00003800}, {0x34, 0x00006cd1},
256 {0x35, 0x00004400}, {0x34, 0x00005cce},
257 {0x35, 0x00003800}, {0x34, 0x000048ce},
258 {0x35, 0x00004400}, {0x34, 0x000034ce},
259 {0x35, 0x00003800}, {0x34, 0x00002451},
260 {0x35, 0x00004400}, {0x34, 0x0000144e},
261 {0x35, 0x00003800}, {0x34, 0x00000051},
262 {0x35, 0x00004400}, {0xef, 0x00000000},
263 {0xef, 0x00000100}, {0xed, 0x00000010},
264 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
265 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
266 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
267 {0x44, 0x000044d1}, {0x44, 0x000034ce},
268 {0x44, 0x00002451}, {0x44, 0x0000144e},
269 {0x44, 0x00000051}, {0xef, 0x00000000},
270 {0xed, 0x00000000}, {0x7f, 0x00020080},
271 {0xef, 0x00002000}, {0x3b, 0x000380ef},
272 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
273 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
274 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
275 {0x3b, 0x00000900}, {0xef, 0x00000000},
276 {0xed, 0x00000001}, {0x40, 0x000380ef},
277 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
278 {0x40, 0x000200bc}, {0x40, 0x000188a5},
279 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
280 {0x40, 0x00000900}, {0xed, 0x00000000},
281 {0x82, 0x00080000}, {0x83, 0x00008000},
282 {0x84, 0x00048d80}, {0x85, 0x00068000},
283 {0xa2, 0x00080000}, {0xa3, 0x00008000},
284 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
285 {0xed, 0x00000002}, {0xef, 0x00000002},
286 {0x56, 0x00000032}, {0x76, 0x00000032},
287 {0x01, 0x00000780},
288 {0xff, 0xffffffff}
289 };
290
rtl8723bu_identify_chip(struct rtl8xxxu_priv * priv)291 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv)
292 {
293 struct device *dev = &priv->udev->dev;
294 u32 val32, sys_cfg, vendor;
295 int ret = 0;
296
297 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
298 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
299 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
300 dev_info(dev, "Unsupported test chip\n");
301 ret = -ENOTSUPP;
302 goto out;
303 }
304
305 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name));
306 priv->rtl_chip = RTL8723B;
307 priv->rf_paths = 1;
308 priv->rx_paths = 1;
309 priv->tx_paths = 1;
310
311 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
312 if (val32 & MULTI_WIFI_FUNC_EN)
313 priv->has_wifi = 1;
314 if (val32 & MULTI_BT_FUNC_EN)
315 priv->has_bluetooth = 1;
316 if (val32 & MULTI_GPS_FUNC_EN)
317 priv->has_gps = 1;
318 priv->is_multi_func = 1;
319
320 vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;
321 rtl8xxxu_identify_vendor_2bits(priv, vendor);
322
323 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
324 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
325
326 rtl8xxxu_config_endpoints_sie(priv);
327
328 /*
329 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
330 */
331 if (!priv->ep_tx_count)
332 ret = rtl8xxxu_config_endpoints_no_sie(priv);
333
334 out:
335 return ret;
336 }
337
rtl8723bu_write_btreg(struct rtl8xxxu_priv * priv,u8 reg,u8 data)338 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
339 {
340 struct h2c_cmd h2c;
341 int reqnum = 0;
342
343 memset(&h2c, 0, sizeof(struct h2c_cmd));
344 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
345 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
346 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
347 h2c.bt_mp_oper.data = data;
348 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
349
350 reqnum++;
351 memset(&h2c, 0, sizeof(struct h2c_cmd));
352 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
353 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
354 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
355 h2c.bt_mp_oper.addr = reg;
356 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
357 }
358
rtl8723bu_reset_8051(struct rtl8xxxu_priv * priv)359 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
360 {
361 u8 val8;
362 u16 sys_func;
363
364 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
365 val8 &= ~BIT(1);
366 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
367
368 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
369 val8 &= ~BIT(0);
370 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
371
372 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
373 sys_func &= ~SYS_FUNC_CPU_ENABLE;
374 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
375
376 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
377 val8 &= ~BIT(1);
378 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
379
380 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
381 val8 |= BIT(0);
382 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
383
384 sys_func |= SYS_FUNC_CPU_ENABLE;
385 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
386 }
387
388 static void
rtl8723b_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)389 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
390 {
391 u32 val32, ofdm, mcs;
392 u8 cck, ofdmbase, mcsbase;
393 int group, tx_idx;
394
395 tx_idx = 0;
396 group = rtl8xxxu_gen2_channel_to_group(channel);
397
398 cck = priv->cck_tx_power_index_B[group];
399 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
400 val32 &= 0xffff00ff;
401 val32 |= (cck << 8);
402 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
403
404 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
405 val32 &= 0xff;
406 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
407 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
408
409 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
410 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
411 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
412
413 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
414 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
415
416 mcsbase = priv->ht40_1s_tx_power_index_B[group];
417 if (ht40)
418 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
419 else
420 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
421 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
422
423 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
424 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
425 }
426
rtl8723bu_parse_efuse(struct rtl8xxxu_priv * priv)427 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
428 {
429 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
430 int i;
431
432 if (efuse->rtl_id != cpu_to_le16(0x8129))
433 return -EINVAL;
434
435 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
436
437 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
438 sizeof(efuse->tx_power_index_A.cck_base));
439 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
440 sizeof(efuse->tx_power_index_B.cck_base));
441
442 memcpy(priv->ht40_1s_tx_power_index_A,
443 efuse->tx_power_index_A.ht40_base,
444 sizeof(efuse->tx_power_index_A.ht40_base));
445 memcpy(priv->ht40_1s_tx_power_index_B,
446 efuse->tx_power_index_B.ht40_base,
447 sizeof(efuse->tx_power_index_B.ht40_base));
448
449 priv->ofdm_tx_power_diff[0].a =
450 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
451 priv->ofdm_tx_power_diff[0].b =
452 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
453
454 priv->ht20_tx_power_diff[0].a =
455 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
456 priv->ht20_tx_power_diff[0].b =
457 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
458
459 priv->ht40_tx_power_diff[0].a = 0;
460 priv->ht40_tx_power_diff[0].b = 0;
461
462 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
463 priv->ofdm_tx_power_diff[i].a =
464 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
465 priv->ofdm_tx_power_diff[i].b =
466 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
467
468 priv->ht20_tx_power_diff[i].a =
469 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
470 priv->ht20_tx_power_diff[i].b =
471 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
472
473 priv->ht40_tx_power_diff[i].a =
474 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
475 priv->ht40_tx_power_diff[i].b =
476 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
477 }
478
479 priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
480
481 return 0;
482 }
483
rtl8723bu_load_firmware(struct rtl8xxxu_priv * priv)484 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
485 {
486 return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8723bu_nic.bin");
487 }
488
rtl8723bu_init_phy_bb(struct rtl8xxxu_priv * priv)489 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
490 {
491 u8 val8;
492 u16 val16;
493
494 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
495 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
496 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
497
498 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
499
500 /* 6. 0x1f[7:0] = 0x07 */
501 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
502 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
503
504 /* Why? */
505 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
506 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
507 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
508
509 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
510 }
511
rtl8723bu_init_phy_rf(struct rtl8xxxu_priv * priv)512 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
513 {
514 int ret;
515
516 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
517 /*
518 * PHY LCK
519 */
520 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
521 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
522 msleep(200);
523 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
524
525 return ret;
526 }
527
rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv * priv)528 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
529 {
530 u32 val32;
531
532 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
533 val32 &= ~(BIT(20) | BIT(24));
534 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
535
536 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
537 val32 &= ~BIT(4);
538 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
539
540 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
541 val32 |= BIT(3);
542 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
543
544 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
545 val32 |= BIT(24);
546 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
547
548 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
549 val32 &= ~BIT(23);
550 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
551
552 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
553 val32 |= (BIT(0) | BIT(1));
554 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
555
556 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
557 val32 &= 0xffffff00;
558 val32 |= 0x77;
559 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
560
561 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
562 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
563 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
564 }
565
rtl8723bu_iqk_path_a(struct rtl8xxxu_priv * priv)566 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
567 {
568 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
569 int result = 0;
570
571 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
572
573 /*
574 * Leave IQK mode
575 */
576 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
577 val32 &= 0x000000ff;
578 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
579
580 /*
581 * Enable path A PA in TX IQK mode
582 */
583 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
584 val32 |= 0x80000;
585 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
586 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
587 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
588 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
589
590 /*
591 * Tx IQK setting
592 */
593 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
594 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
595
596 /* path-A IQK setting */
597 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
598 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
599 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
600 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
601
602 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
603 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
604 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
605 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
606
607 /* LO calibration setting */
608 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
609
610 /*
611 * Enter IQK mode
612 */
613 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
614 val32 &= 0x000000ff;
615 val32 |= 0x80800000;
616 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
617
618 /*
619 * The vendor driver indicates the USB module is always using
620 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
621 */
622 if (priv->rf_paths > 1)
623 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
624 else
625 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
626
627 /*
628 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
629 * No trace of this in the 8192eu or 8188eu vendor drivers.
630 */
631 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
632
633 /* One shot, path A LOK & IQK */
634 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
635 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
636
637 mdelay(1);
638
639 /* Restore Ant Path */
640 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
641 #ifdef RTL8723BU_BT
642 /* GNT_BT = 1 */
643 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
644 #endif
645
646 /*
647 * Leave IQK mode
648 */
649 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
650 val32 &= 0x000000ff;
651 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
652
653 /* Check failed */
654 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
655 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
656 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
657
658 val32 = (reg_e9c >> 16) & 0x3ff;
659 if (val32 & 0x200)
660 val32 = 0x400 - val32;
661
662 if (!(reg_eac & BIT(28)) &&
663 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
664 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
665 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
666 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
667 val32 < 0xf)
668 result |= 0x01;
669 else /* If TX not OK, ignore RX */
670 goto out;
671
672 out:
673 return result;
674 }
675
rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv * priv)676 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
677 {
678 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
679 int result = 0;
680
681 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
682
683 /*
684 * Leave IQK mode
685 */
686 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
687 val32 &= 0x000000ff;
688 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
689
690 /*
691 * Enable path A PA in TX IQK mode
692 */
693 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
694 val32 |= 0x80000;
695 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
696 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
697 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
698 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
699
700 /*
701 * Tx IQK setting
702 */
703 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
704 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
705
706 /* path-A IQK setting */
707 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
708 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
709 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
710 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
711
712 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
713 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
714 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
715 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
716
717 /* LO calibration setting */
718 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
719
720 /*
721 * Enter IQK mode
722 */
723 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
724 val32 &= 0x000000ff;
725 val32 |= 0x80800000;
726 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
727
728 /*
729 * The vendor driver indicates the USB module is always using
730 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
731 */
732 if (priv->rf_paths > 1)
733 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
734 else
735 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
736
737 /*
738 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
739 * No trace of this in the 8192eu or 8188eu vendor drivers.
740 */
741 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
742
743 /* One shot, path A LOK & IQK */
744 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
745 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
746
747 mdelay(1);
748
749 /* Restore Ant Path */
750 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
751 #ifdef RTL8723BU_BT
752 /* GNT_BT = 1 */
753 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
754 #endif
755
756 /*
757 * Leave IQK mode
758 */
759 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
760 val32 &= 0x000000ff;
761 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
762
763 /* Check failed */
764 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
765 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
766 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
767
768 val32 = (reg_e9c >> 16) & 0x3ff;
769 if (val32 & 0x200)
770 val32 = 0x400 - val32;
771
772 if (!(reg_eac & BIT(28)) &&
773 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
774 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
775 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
776 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
777 val32 < 0xf)
778 result |= 0x01;
779 else /* If TX not OK, ignore RX */
780 goto out;
781
782 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
783 ((reg_e9c & 0x3ff0000) >> 16);
784 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
785
786 /*
787 * Modify RX IQK mode
788 */
789 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
790 val32 &= 0x000000ff;
791 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
792 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
793 val32 |= 0x80000;
794 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
795 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
796 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
797 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
798
799 /*
800 * PA, PAD setting
801 */
802 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80);
803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
804
805 /*
806 * RX IQK setting
807 */
808 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
809
810 /* path-A IQK setting */
811 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
812 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
813 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
814 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
815
816 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
817 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
818 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
819 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
820
821 /* LO calibration setting */
822 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
823
824 /*
825 * Enter IQK mode
826 */
827 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
828 val32 &= 0x000000ff;
829 val32 |= 0x80800000;
830 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
831
832 if (priv->rf_paths > 1)
833 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
834 else
835 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
836
837 /*
838 * Disable BT
839 */
840 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
841
842 /* One shot, path A LOK & IQK */
843 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
844 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
845
846 mdelay(1);
847
848 /* Restore Ant Path */
849 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
850 #ifdef RTL8723BU_BT
851 /* GNT_BT = 1 */
852 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
853 #endif
854
855 /*
856 * Leave IQK mode
857 */
858 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
859 val32 &= 0x000000ff;
860 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
861
862 /* Check failed */
863 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
864 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
865
866 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780);
867
868 val32 = (reg_eac >> 16) & 0x3ff;
869 if (val32 & 0x200)
870 val32 = 0x400 - val32;
871
872 if (!(reg_eac & BIT(27)) &&
873 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
874 ((reg_eac & 0x03ff0000) != 0x00360000) &&
875 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
876 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
877 val32 < 0xf)
878 result |= 0x02;
879 else /* If TX not OK, ignore RX */
880 goto out;
881 out:
882 return result;
883 }
884
rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)885 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
886 int result[][8], int t)
887 {
888 struct device *dev = &priv->udev->dev;
889 u32 i, val32;
890 int path_a_ok /*, path_b_ok */;
891 int retry = 2;
892 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
893 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
894 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
895 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
896 REG_TX_OFDM_BBON, REG_TX_TO_RX,
897 REG_TX_TO_TX, REG_RX_CCK,
898 REG_RX_OFDM, REG_RX_WAIT_RIFS,
899 REG_RX_TO_RX, REG_STANDBY,
900 REG_SLEEP, REG_PMPD_ANAEN
901 };
902 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
903 REG_TXPAUSE, REG_BEACON_CTRL,
904 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
905 };
906 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
907 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
908 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
909 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
910 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
911 };
912 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
913 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
914
915 /*
916 * Note: IQ calibration must be performed after loading
917 * PHY_REG.txt , and radio_a, radio_b.txt
918 */
919
920 if (t == 0) {
921 /* Save ADDA parameters, turn Path A ADDA on */
922 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
923 RTL8XXXU_ADDA_REGS);
924 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
925 rtl8xxxu_save_regs(priv, iqk_bb_regs,
926 priv->bb_backup, RTL8XXXU_BB_REGS);
927 }
928
929 rtl8xxxu_path_adda_on(priv, adda_regs, true);
930
931 /* MAC settings */
932 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
933
934 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
935 val32 |= 0x0f000000;
936 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
937
938 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
939 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
940 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
941
942 /*
943 * RX IQ calibration setting for 8723B D cut large current issue
944 * when leaving IPS
945 */
946 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
947 val32 &= 0x000000ff;
948 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
949
950 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
951 val32 |= 0x80000;
952 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
953
954 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
955 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
956 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
957
958 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
959 val32 |= 0x20;
960 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
961
962 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
963
964 for (i = 0; i < retry; i++) {
965 path_a_ok = rtl8723bu_iqk_path_a(priv);
966 if (path_a_ok == 0x01) {
967 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
968 val32 &= 0x000000ff;
969 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
970
971 val32 = rtl8xxxu_read32(priv,
972 REG_TX_POWER_BEFORE_IQK_A);
973 result[t][0] = (val32 >> 16) & 0x3ff;
974 val32 = rtl8xxxu_read32(priv,
975 REG_TX_POWER_AFTER_IQK_A);
976 result[t][1] = (val32 >> 16) & 0x3ff;
977
978 break;
979 }
980 }
981
982 if (!path_a_ok)
983 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
984
985 for (i = 0; i < retry; i++) {
986 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
987 if (path_a_ok == 0x03) {
988 val32 = rtl8xxxu_read32(priv,
989 REG_RX_POWER_BEFORE_IQK_A_2);
990 result[t][2] = (val32 >> 16) & 0x3ff;
991 val32 = rtl8xxxu_read32(priv,
992 REG_RX_POWER_AFTER_IQK_A_2);
993 result[t][3] = (val32 >> 16) & 0x3ff;
994
995 break;
996 }
997 }
998
999 if (!path_a_ok)
1000 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1001
1002 if (priv->tx_paths > 1) {
1003 #if 1
1004 dev_warn(dev, "%s: Path B not supported\n", __func__);
1005 #else
1006
1007 /*
1008 * Path A into standby
1009 */
1010 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1011 val32 &= 0x000000ff;
1012 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1013 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1014
1015 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1016 val32 &= 0x000000ff;
1017 val32 |= 0x80800000;
1018 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1019
1020 /* Turn Path B ADDA on */
1021 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1022
1023 for (i = 0; i < retry; i++) {
1024 path_b_ok = rtl8xxxu_iqk_path_b(priv);
1025 if (path_b_ok == 0x03) {
1026 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1027 result[t][4] = (val32 >> 16) & 0x3ff;
1028 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1029 result[t][5] = (val32 >> 16) & 0x3ff;
1030 break;
1031 }
1032 }
1033
1034 if (!path_b_ok)
1035 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1036
1037 for (i = 0; i < retry; i++) {
1038 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
1039 if (path_a_ok == 0x03) {
1040 val32 = rtl8xxxu_read32(priv,
1041 REG_RX_POWER_BEFORE_IQK_B_2);
1042 result[t][6] = (val32 >> 16) & 0x3ff;
1043 val32 = rtl8xxxu_read32(priv,
1044 REG_RX_POWER_AFTER_IQK_B_2);
1045 result[t][7] = (val32 >> 16) & 0x3ff;
1046 break;
1047 }
1048 }
1049
1050 if (!path_b_ok)
1051 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1052 #endif
1053 }
1054
1055 /* Back to BB mode, load original value */
1056 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1057 val32 &= 0x000000ff;
1058 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1059
1060 if (t) {
1061 /* Reload ADDA power saving parameters */
1062 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1063 RTL8XXXU_ADDA_REGS);
1064
1065 /* Reload MAC parameters */
1066 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1067
1068 /* Reload BB parameters */
1069 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1070 priv->bb_backup, RTL8XXXU_BB_REGS);
1071
1072 /* Restore RX initial gain */
1073 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1074 val32 &= 0xffffff00;
1075 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1076 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1077
1078 if (priv->tx_paths > 1) {
1079 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1080 val32 &= 0xffffff00;
1081 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1082 val32 | 0x50);
1083 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1084 val32 | xb_agc);
1085 }
1086
1087 /* Load 0xe30 IQC default value */
1088 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1089 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1090 }
1091 }
1092
rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv * priv)1093 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1094 {
1095 struct device *dev = &priv->udev->dev;
1096 int result[4][8]; /* last is final result */
1097 int i, candidate;
1098 bool path_a_ok, path_b_ok;
1099 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1100 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1101 u32 val32, bt_control;
1102 s32 reg_tmp = 0;
1103 bool simu;
1104
1105 rtl8xxxu_gen2_prepare_calibrate(priv, 1);
1106
1107 memset(result, 0, sizeof(result));
1108 candidate = -1;
1109
1110 path_a_ok = false;
1111 path_b_ok = false;
1112
1113 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
1114
1115 for (i = 0; i < 3; i++) {
1116 rtl8723bu_phy_iqcalibrate(priv, result, i);
1117
1118 if (i == 1) {
1119 simu = rtl8xxxu_gen2_simularity_compare(priv,
1120 result, 0, 1);
1121 if (simu) {
1122 candidate = 0;
1123 break;
1124 }
1125 }
1126
1127 if (i == 2) {
1128 simu = rtl8xxxu_gen2_simularity_compare(priv,
1129 result, 0, 2);
1130 if (simu) {
1131 candidate = 0;
1132 break;
1133 }
1134
1135 simu = rtl8xxxu_gen2_simularity_compare(priv,
1136 result, 1, 2);
1137 if (simu) {
1138 candidate = 1;
1139 } else {
1140 for (i = 0; i < 8; i++)
1141 reg_tmp += result[3][i];
1142
1143 if (reg_tmp)
1144 candidate = 3;
1145 else
1146 candidate = -1;
1147 }
1148 }
1149 }
1150
1151 for (i = 0; i < 4; i++) {
1152 reg_e94 = result[i][0];
1153 reg_e9c = result[i][1];
1154 reg_ea4 = result[i][2];
1155 reg_eac = result[i][3];
1156 reg_eb4 = result[i][4];
1157 reg_ebc = result[i][5];
1158 reg_ec4 = result[i][6];
1159 reg_ecc = result[i][7];
1160 }
1161
1162 if (candidate >= 0) {
1163 reg_e94 = result[candidate][0];
1164 priv->rege94 = reg_e94;
1165 reg_e9c = result[candidate][1];
1166 priv->rege9c = reg_e9c;
1167 reg_ea4 = result[candidate][2];
1168 reg_eac = result[candidate][3];
1169 reg_eb4 = result[candidate][4];
1170 priv->regeb4 = reg_eb4;
1171 reg_ebc = result[candidate][5];
1172 priv->regebc = reg_ebc;
1173 reg_ec4 = result[candidate][6];
1174 reg_ecc = result[candidate][7];
1175 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1176 dev_dbg(dev,
1177 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1178 __func__, reg_e94, reg_e9c,
1179 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1180 path_a_ok = true;
1181 path_b_ok = true;
1182 } else {
1183 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1184 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1185 }
1186
1187 if (reg_e94 && candidate >= 0)
1188 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1189 candidate, (reg_ea4 == 0));
1190
1191 if (priv->tx_paths > 1 && reg_eb4)
1192 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1193 candidate, (reg_ec4 == 0));
1194
1195 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1196 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1197
1198 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
1199
1200 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1201 val32 |= 0x80000;
1202 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1203 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
1204 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
1205 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
1206 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
1207 val32 |= 0x20;
1208 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
1209 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
1210
1211 if (priv->rf_paths > 1)
1212 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
1213
1214 rtl8xxxu_gen2_prepare_calibrate(priv, 0);
1215 }
1216
rtl8723bu_active_to_emu(struct rtl8xxxu_priv * priv)1217 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
1218 {
1219 u8 val8;
1220 u16 val16;
1221 u32 val32;
1222 int count, ret = 0;
1223
1224 /* Turn off RF */
1225 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
1226
1227 /* Enable rising edge triggering interrupt */
1228 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
1229 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
1230 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
1231
1232 /* Release WLON reset 0x04[16]= 1*/
1233 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1234 val32 |= APS_FSMCO_WLON_RESET;
1235 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1236
1237 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1238 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1239 val8 |= BIT(1);
1240 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1241
1242 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1243 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1244 if ((val8 & BIT(1)) == 0)
1245 break;
1246 udelay(10);
1247 }
1248
1249 if (!count) {
1250 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1251 __func__);
1252 ret = -EBUSY;
1253 goto exit;
1254 }
1255
1256 /* Enable BT control XTAL setting */
1257 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1258 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
1259 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1260
1261 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
1262 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1263 val8 |= SYS_ISO_ANALOG_IPS;
1264 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1265
1266 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
1267 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1268 val8 &= ~LDOA15_ENABLE;
1269 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1270
1271 exit:
1272 return ret;
1273 }
1274
rtl8723b_emu_to_active(struct rtl8xxxu_priv * priv)1275 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
1276 {
1277 u8 val8;
1278 u32 val32;
1279 int count, ret = 0;
1280
1281 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
1282 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1283 val8 |= LDOA15_ENABLE;
1284 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1285
1286 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
1287 val8 = rtl8xxxu_read8(priv, 0x0067);
1288 val8 &= ~BIT(4);
1289 rtl8xxxu_write8(priv, 0x0067, val8);
1290
1291 mdelay(1);
1292
1293 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
1294 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1295 val8 &= ~SYS_ISO_ANALOG_IPS;
1296 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1297
1298 /* Disable SW LPS 0x04[10]= 0 */
1299 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
1300 val32 &= ~APS_FSMCO_SW_LPS;
1301 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1302
1303 /* Wait until 0x04[17] = 1 power ready */
1304 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1305 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1306 if (val32 & BIT(17))
1307 break;
1308
1309 udelay(10);
1310 }
1311
1312 if (!count) {
1313 ret = -EBUSY;
1314 goto exit;
1315 }
1316
1317 /* We should be able to optimize the following three entries into one */
1318
1319 /* Release WLON reset 0x04[16]= 1*/
1320 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1321 val32 |= APS_FSMCO_WLON_RESET;
1322 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1323
1324 /* Disable HWPDN 0x04[15]= 0*/
1325 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1326 val32 &= ~APS_FSMCO_HW_POWERDOWN;
1327 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1328
1329 /* Disable WL suspend*/
1330 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1331 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
1332 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1333
1334 /* Set, then poll until 0 */
1335 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1336 val32 |= APS_FSMCO_MAC_ENABLE;
1337 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1338
1339 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1340 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1341 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1342 ret = 0;
1343 break;
1344 }
1345 udelay(10);
1346 }
1347
1348 if (!count) {
1349 ret = -EBUSY;
1350 goto exit;
1351 }
1352
1353 /* Enable WL control XTAL setting */
1354 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1355 val8 |= AFE_MISC_WL_XTAL_CTRL;
1356 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1357
1358 /* Enable falling edge triggering interrupt */
1359 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
1360 val8 |= BIT(1);
1361 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
1362
1363 /* Enable GPIO9 interrupt mode */
1364 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
1365 val8 |= BIT(1);
1366 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
1367
1368 /* Enable GPIO9 input mode */
1369 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
1370 val8 &= ~BIT(1);
1371 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
1372
1373 /* Enable HSISR GPIO[C:0] interrupt */
1374 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
1375 val8 |= BIT(0);
1376 rtl8xxxu_write8(priv, REG_HSIMR, val8);
1377
1378 /* Enable HSISR GPIO9 interrupt */
1379 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
1380 val8 |= BIT(1);
1381 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
1382
1383 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
1384 val8 |= MULTI_WIFI_HW_ROF_EN;
1385 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
1386
1387 /* For GPIO9 internal pull high setting BIT(14) */
1388 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
1389 val8 |= BIT(6);
1390 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
1391
1392 exit:
1393 return ret;
1394 }
1395
rtl8723bu_power_on(struct rtl8xxxu_priv * priv)1396 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
1397 {
1398 u8 val8;
1399 u16 val16;
1400 u32 val32;
1401 int ret;
1402
1403 rtl8xxxu_disabled_to_emu(priv);
1404
1405 ret = rtl8723b_emu_to_active(priv);
1406 if (ret)
1407 goto exit;
1408
1409 /*
1410 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1411 * Set CR bit10 to enable 32k calibration.
1412 */
1413 val16 = rtl8xxxu_read16(priv, REG_CR);
1414 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1415 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1416 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1417 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1418 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1419 rtl8xxxu_write16(priv, REG_CR, val16);
1420
1421 /*
1422 * BT coexist power on settings. This is identical for 1 and 2
1423 * antenna parts.
1424 */
1425 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
1426
1427 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1428 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
1429 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1430
1431 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
1432 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1433 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
1434 /* Antenna inverse */
1435 rtl8xxxu_write8(priv, 0xfe08, 0x01);
1436
1437 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
1438 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1439 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
1440
1441 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1442 val32 |= LEDCFG0_DPDT_SELECT;
1443 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1444
1445 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1446 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
1447 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1448 exit:
1449 return ret;
1450 }
1451
rtl8723bu_power_off(struct rtl8xxxu_priv * priv)1452 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
1453 {
1454 u8 val8;
1455 u16 val16;
1456
1457 rtl8xxxu_flush_fifo(priv);
1458
1459 /*
1460 * Disable TX report timer
1461 */
1462 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1463 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1464 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1465
1466 rtl8xxxu_write8(priv, REG_CR, 0x0000);
1467
1468 rtl8xxxu_active_to_lps(priv);
1469
1470 /* Reset Firmware if running in RAM */
1471 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1472 rtl8xxxu_firmware_self_reset(priv);
1473
1474 /* Reset MCU */
1475 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1476 val16 &= ~SYS_FUNC_CPU_ENABLE;
1477 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1478
1479 /* Reset MCU ready status */
1480 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1481
1482 rtl8723bu_active_to_emu(priv);
1483
1484 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1485 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
1486 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1487
1488 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
1489 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
1490 val8 |= BIT(0);
1491 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
1492 }
1493
rtl8723b_enable_rf(struct rtl8xxxu_priv * priv)1494 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1495 {
1496 struct h2c_cmd h2c;
1497 u32 val32;
1498 u8 val8;
1499
1500 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1501 val32 |= (BIT(22) | BIT(23));
1502 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1503
1504 /*
1505 * No indication anywhere as to what 0x0790 does. The 2 antenna
1506 * vendor code preserves bits 6-7 here.
1507 */
1508 rtl8xxxu_write8(priv, 0x0790, 0x05);
1509 /*
1510 * 0x0778 seems to be related to enabling the number of antennas
1511 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
1512 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
1513 */
1514 rtl8xxxu_write8(priv, 0x0778, 0x01);
1515
1516 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1517 val8 |= BIT(5);
1518 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1519
1520 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
1521
1522 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
1523
1524 /*
1525 * Set BT grant to low
1526 */
1527 memset(&h2c, 0, sizeof(struct h2c_cmd));
1528 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
1529 h2c.bt_grant.data = 0;
1530 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
1531
1532 /*
1533 * WLAN action by PTA
1534 */
1535 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
1536
1537 /*
1538 * BT select S0/S1 controlled by WiFi
1539 */
1540 val8 = rtl8xxxu_read8(priv, 0x0067);
1541 val8 |= BIT(5);
1542 rtl8xxxu_write8(priv, 0x0067, val8);
1543
1544 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1545 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1546 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1547
1548 /*
1549 * Bits 6/7 are marked in/out ... but for what?
1550 */
1551 rtl8xxxu_write8(priv, 0x0974, 0xff);
1552
1553 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1554 val32 |= (BIT(0) | BIT(1));
1555 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1556
1557 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1558
1559 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1560 val32 &= ~BIT(24);
1561 val32 |= BIT(23);
1562 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1563
1564 /*
1565 * Fix external switch Main->S1, Aux->S0
1566 */
1567 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1568 val8 &= ~BIT(0);
1569 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1570
1571 memset(&h2c, 0, sizeof(struct h2c_cmd));
1572 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
1573 h2c.ant_sel_rsv.ant_inverse = 1;
1574 h2c.ant_sel_rsv.int_switch_type = 0;
1575 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
1576
1577 /*
1578 * Different settings per different antenna position.
1579 * Antenna Position: | Normal Inverse
1580 * --------------------------------------------------
1581 * Antenna switch to BT: | 0x280, 0x00
1582 * Antenna switch to WiFi: | 0x0, 0x280
1583 * Antenna switch to PTA: | 0x200, 0x80
1584 */
1585 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80);
1586
1587 /*
1588 * Software control, antenna at WiFi side
1589 */
1590 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
1591
1592 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
1593 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
1594 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
1595 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
1596
1597 memset(&h2c, 0, sizeof(struct h2c_cmd));
1598 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
1599 h2c.bt_info.data = BIT(0);
1600 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
1601
1602 memset(&h2c, 0, sizeof(struct h2c_cmd));
1603 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
1604 h2c.ignore_wlan.data = 0;
1605 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
1606 }
1607
rtl8723bu_init_aggregation(struct rtl8xxxu_priv * priv)1608 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
1609 {
1610 u32 agg_rx;
1611 u8 agg_ctrl;
1612
1613 /*
1614 * For now simply disable RX aggregation
1615 */
1616 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
1617 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
1618
1619 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
1620 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
1621 agg_rx &= ~0xff0f;
1622
1623 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
1624 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
1625 }
1626
rtl8723bu_init_statistics(struct rtl8xxxu_priv * priv)1627 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
1628 {
1629 u32 val32;
1630
1631 /* Time duration for NHM unit: 4us, 0x2710=40ms */
1632 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
1633 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
1634 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
1635 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
1636 /* TH8 */
1637 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1638 val32 |= 0xff;
1639 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1640 /* Enable CCK */
1641 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
1642 val32 |= BIT(8) | BIT(9) | BIT(10);
1643 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
1644 /* Max power amongst all RX antennas */
1645 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
1646 val32 |= BIT(7);
1647 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
1648 }
1649
rtl8723b_cck_rssi(struct rtl8xxxu_priv * priv,struct rtl8723au_phy_stats * phy_stats)1650 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
1651 {
1652 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
1653 s8 rx_pwr_all = 0x00;
1654 u8 vga_idx, lna_idx;
1655
1656 lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);
1657 vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);
1658
1659 switch (lna_idx) {
1660 case 6:
1661 rx_pwr_all = -34 - (2 * vga_idx);
1662 break;
1663 case 4:
1664 rx_pwr_all = -14 - (2 * vga_idx);
1665 break;
1666 case 1:
1667 rx_pwr_all = 6 - (2 * vga_idx);
1668 break;
1669 case 0:
1670 rx_pwr_all = 16 - (2 * vga_idx);
1671 break;
1672 default:
1673 break;
1674 }
1675
1676 return rx_pwr_all;
1677 }
1678
rtl8723bu_led_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)1679 static int rtl8723bu_led_brightness_set(struct led_classdev *led_cdev,
1680 enum led_brightness brightness)
1681 {
1682 struct rtl8xxxu_priv *priv = container_of(led_cdev,
1683 struct rtl8xxxu_priv,
1684 led_cdev);
1685 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2);
1686
1687 ledcfg &= LEDCFG2_DPDT_SELECT;
1688
1689 if (brightness == LED_OFF)
1690 ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;
1691 else if (brightness == LED_ON)
1692 ledcfg |= LEDCFG2_SW_LED_CONTROL;
1693 else if (brightness == RTL8XXXU_HW_LED_CONTROL)
1694 ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;
1695
1696 rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg);
1697
1698 return 0;
1699 }
1700
1701 struct rtl8xxxu_fileops rtl8723bu_fops = {
1702 .identify_chip = rtl8723bu_identify_chip,
1703 .parse_efuse = rtl8723bu_parse_efuse,
1704 .load_firmware = rtl8723bu_load_firmware,
1705 .power_on = rtl8723bu_power_on,
1706 .power_off = rtl8723bu_power_off,
1707 .read_efuse = rtl8xxxu_read_efuse,
1708 .reset_8051 = rtl8723bu_reset_8051,
1709 .llt_init = rtl8xxxu_auto_llt_table,
1710 .init_phy_bb = rtl8723bu_init_phy_bb,
1711 .init_phy_rf = rtl8723bu_init_phy_rf,
1712 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
1713 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
1714 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
1715 .config_channel = rtl8xxxu_gen2_config_channel,
1716 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1717 .parse_phystats = rtl8723au_rx_parse_phystats,
1718 .init_aggregation = rtl8723bu_init_aggregation,
1719 .init_statistics = rtl8723bu_init_statistics,
1720 .init_burst = rtl8xxxu_init_burst,
1721 .enable_rf = rtl8723b_enable_rf,
1722 .disable_rf = rtl8xxxu_gen2_disable_rf,
1723 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1724 .set_tx_power = rtl8723b_set_tx_power,
1725 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1726 .report_connect = rtl8xxxu_gen2_report_connect,
1727 .report_rssi = rtl8xxxu_gen2_report_rssi,
1728 .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1729 .set_crystal_cap = rtl8723a_set_crystal_cap,
1730 .cck_rssi = rtl8723b_cck_rssi,
1731 .led_classdev_brightness_set = rtl8723bu_led_brightness_set,
1732 .writeN_block_size = 1024,
1733 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1734 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1735 .has_s0s1 = 1,
1736 .has_tx_report = 1,
1737 .gen2_thermal_meter = 1,
1738 .needs_full_init = 1,
1739 .init_reg_hmtfr = 1,
1740 .hw_feature_report = 0,
1741 .ampdu_max_time = 0x5e,
1742 .ustime_tsf_edca = 0x50,
1743 .max_aggr_num = 0x0c14,
1744 .supports_ap = 1,
1745 .max_macid_num = 128,
1746 .max_sec_cam_num = 64,
1747 .adda_1t_init = 0x01c00014,
1748 .adda_1t_path_on = 0x01c00014,
1749 .adda_2t_path_on_a = 0x01c00014,
1750 .adda_2t_path_on_b = 0x01c00014,
1751 .trxff_boundary = 0x3f7f,
1752 .pbp_rx = PBP_PAGE_SIZE_256,
1753 .pbp_tx = PBP_PAGE_SIZE_256,
1754 .mactable = rtl8723b_mac_init_table,
1755 .total_page_num = TX_TOTAL_PAGE_NUM_8723B,
1756 .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,
1757 .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,
1758 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,
1759 };
1760