1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/G2L A/D Converter driver
4 *
5 * Copyright (c) 2021 Renesas Electronics Europe GmbH
6 *
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/cleanup.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/iio/adc-helpers.h>
15 #include <linux/iio/iio.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/reset.h>
24
25 #define DRIVER_NAME "rzg2l-adc"
26
27 #define RZG2L_ADM(n) ((n) * 0x4)
28 #define RZG2L_ADM0_ADCE BIT(0)
29 #define RZG2L_ADM0_ADBSY BIT(1)
30 #define RZG2L_ADM0_PWDWNB BIT(2)
31 #define RZG2L_ADM0_SRESB BIT(15)
32 #define RZG2L_ADM1_TRG BIT(0)
33 #define RZG2L_ADM1_MS BIT(2)
34 #define RZG2L_ADM1_BS BIT(4)
35 #define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
36 #define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
37 #define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
38
39 #define RZG2L_ADINT 0x20
40 #define RZG2L_ADINT_CSEEN BIT(16)
41 #define RZG2L_ADINT_INTS BIT(31)
42
43 #define RZG2L_ADSTS 0x24
44 #define RZG2L_ADSTS_CSEST BIT(16)
45
46 #define RZG2L_ADIVC 0x28
47 #define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
48 #define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
49
50 #define RZG2L_ADFIL 0x2c
51
52 #define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
53 #define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
54
55 #define RZG2L_ADC_MAX_CHANNELS 9
56 #define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
57
58 /**
59 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
60 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
61 * used for voltage channels, index 1 is used for temperature channel
62 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
63 * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
64 * @default_adcmp: default ADC cmp (see ADM3 register)
65 * @num_channels: number of supported channels
66 * @adivc: specifies if ADVIC register is available
67 */
68 struct rzg2l_adc_hw_params {
69 u16 default_adsmp[2];
70 u16 adsmp_mask;
71 u16 adint_inten_mask;
72 u8 default_adcmp;
73 u8 num_channels;
74 bool adivc;
75 };
76
77 struct rzg2l_adc_data {
78 const struct iio_chan_spec *channels;
79 u8 num_channels;
80 };
81
82 struct rzg2l_adc {
83 void __iomem *base;
84 struct reset_control *presetn;
85 struct reset_control *adrstn;
86 const struct rzg2l_adc_data *data;
87 const struct rzg2l_adc_hw_params *hw_params;
88 struct completion completion;
89 struct mutex lock;
90 u16 last_val[RZG2L_ADC_MAX_CHANNELS];
91 };
92
93 /**
94 * struct rzg2l_adc_channel - ADC channel descriptor
95 * @name: ADC channel name
96 * @type: ADC channel type
97 */
98 struct rzg2l_adc_channel {
99 const char * const name;
100 enum iio_chan_type type;
101 };
102
103 static const struct rzg2l_adc_channel rzg2l_adc_channels[] = {
104 { "adc0", IIO_VOLTAGE },
105 { "adc1", IIO_VOLTAGE },
106 { "adc2", IIO_VOLTAGE },
107 { "adc3", IIO_VOLTAGE },
108 { "adc4", IIO_VOLTAGE },
109 { "adc5", IIO_VOLTAGE },
110 { "adc6", IIO_VOLTAGE },
111 { "adc7", IIO_VOLTAGE },
112 { "adc8", IIO_TEMP },
113 };
114
rzg2l_adc_readl(struct rzg2l_adc * adc,u32 reg)115 static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
116 {
117 return readl(adc->base + reg);
118 }
119
rzg2l_adc_writel(struct rzg2l_adc * adc,unsigned int reg,u32 val)120 static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
121 {
122 writel(val, adc->base + reg);
123 }
124
rzg2l_adc_pwr(struct rzg2l_adc * adc,bool on)125 static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
126 {
127 u32 reg;
128
129 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
130 if (on)
131 reg |= RZG2L_ADM0_PWDWNB;
132 else
133 reg &= ~RZG2L_ADM0_PWDWNB;
134 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
135 udelay(2);
136 }
137
rzg2l_adc_start_stop(struct rzg2l_adc * adc,bool start)138 static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
139 {
140 int ret;
141 u32 reg;
142
143 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
144 if (start)
145 reg |= RZG2L_ADM0_ADCE;
146 else
147 reg &= ~RZG2L_ADM0_ADCE;
148 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
149
150 if (start)
151 return;
152
153 ret = read_poll_timeout(rzg2l_adc_readl, reg, !(reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)),
154 200, 1000, true, adc, RZG2L_ADM(0));
155 if (ret)
156 pr_err("%s stopping ADC timed out\n", __func__);
157 }
158
rzg2l_set_trigger(struct rzg2l_adc * adc)159 static void rzg2l_set_trigger(struct rzg2l_adc *adc)
160 {
161 u32 reg;
162
163 /*
164 * Setup ADM1 for SW trigger
165 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
166 * BS[4] - Enable 1-buffer mode
167 * MS[1] - Enable Select mode
168 * TRG[0] - Enable software trigger mode
169 */
170 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
171 reg &= ~RZG2L_ADM1_EGA_MASK;
172 reg &= ~RZG2L_ADM1_BS;
173 reg &= ~RZG2L_ADM1_TRG;
174 reg |= RZG2L_ADM1_MS;
175 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
176 }
177
rzg2l_adc_ch_to_adsmp_index(u8 ch)178 static u8 rzg2l_adc_ch_to_adsmp_index(u8 ch)
179 {
180 if (rzg2l_adc_channels[ch].type == IIO_VOLTAGE)
181 return 0;
182
183 return 1;
184 }
185
rzg2l_adc_conversion_setup(struct rzg2l_adc * adc,u8 ch)186 static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
187 {
188 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
189 u8 index = rzg2l_adc_ch_to_adsmp_index(ch);
190 u32 reg;
191
192 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
193 return -EBUSY;
194
195 rzg2l_set_trigger(adc);
196
197 /* Select analog input channel subjected to conversion. */
198 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
199 reg &= ~GENMASK(hw_params->num_channels - 1, 0);
200 reg |= BIT(ch);
201 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
202
203 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
204 reg &= ~hw_params->adsmp_mask;
205 reg |= hw_params->default_adsmp[index];
206 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
207
208 /*
209 * Setup ADINT
210 * INTS[31] - Select pulse signal
211 * CSEEN[16] - Enable channel select error interrupt
212 * INTEN[7:0] - Select channel interrupt
213 */
214 reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
215 reg &= ~RZG2L_ADINT_INTS;
216 reg &= ~hw_params->adint_inten_mask;
217 reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
218 rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
219
220 return 0;
221 }
222
rzg2l_adc_conversion(struct iio_dev * indio_dev,struct rzg2l_adc * adc,u8 ch)223 static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
224 {
225 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
226 struct device *dev = indio_dev->dev.parent;
227 int ret;
228
229 ret = pm_runtime_resume_and_get(dev);
230 if (ret)
231 return ret;
232
233 ret = rzg2l_adc_conversion_setup(adc, ch);
234 if (ret)
235 goto rpm_put;
236
237 reinit_completion(&adc->completion);
238
239 rzg2l_adc_start_stop(adc, true);
240
241 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
242 rzg2l_adc_writel(adc, RZG2L_ADINT,
243 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
244 ret = -ETIMEDOUT;
245 }
246
247 rzg2l_adc_start_stop(adc, false);
248
249 rpm_put:
250 pm_runtime_put_autosuspend(dev);
251 return ret;
252 }
253
rzg2l_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)254 static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
255 struct iio_chan_spec const *chan,
256 int *val, int *val2, long mask)
257 {
258 struct rzg2l_adc *adc = iio_priv(indio_dev);
259 int ret;
260
261 switch (mask) {
262 case IIO_CHAN_INFO_RAW: {
263 if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP)
264 return -EINVAL;
265
266 guard(mutex)(&adc->lock);
267
268 ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);
269 if (ret)
270 return ret;
271
272 *val = adc->last_val[chan->channel];
273
274 return IIO_VAL_INT;
275 }
276
277 default:
278 return -EINVAL;
279 }
280 }
281
rzg2l_adc_read_label(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,char * label)282 static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
283 const struct iio_chan_spec *chan,
284 char *label)
285 {
286 return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);
287 }
288
289 static const struct iio_info rzg2l_adc_iio_info = {
290 .read_raw = rzg2l_adc_read_raw,
291 .read_label = rzg2l_adc_read_label,
292 };
293
rzg2l_adc_isr(int irq,void * dev_id)294 static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
295 {
296 struct rzg2l_adc *adc = dev_id;
297 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
298 unsigned long intst;
299 u32 reg;
300 int ch;
301
302 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
303
304 /* A/D conversion channel select error interrupt */
305 if (reg & RZG2L_ADSTS_CSEST) {
306 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
307 return IRQ_HANDLED;
308 }
309
310 intst = reg & GENMASK(hw_params->num_channels - 1, 0);
311 if (!intst)
312 return IRQ_NONE;
313
314 for_each_set_bit(ch, &intst, hw_params->num_channels)
315 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
316
317 /* clear the channel interrupt */
318 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
319
320 complete(&adc->completion);
321
322 return IRQ_HANDLED;
323 }
324
325 static const struct iio_chan_spec rzg2l_adc_chan_template = {
326 .indexed = 1,
327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
328 };
329
rzg2l_adc_parse_properties(struct platform_device * pdev,struct rzg2l_adc * adc)330 static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
331 {
332 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
333 struct iio_chan_spec *chan_array;
334 struct rzg2l_adc_data *data;
335 int num_channels;
336 u8 i;
337
338 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
339 if (!data)
340 return -ENOMEM;
341
342 num_channels = devm_iio_adc_device_alloc_chaninfo_se(&pdev->dev,
343 &rzg2l_adc_chan_template,
344 hw_params->num_channels - 1,
345 &chan_array);
346 if (num_channels < 0)
347 return num_channels;
348
349 if (num_channels > hw_params->num_channels)
350 return dev_err_probe(&pdev->dev, -EINVAL,
351 "num of channel children out of range\n");
352
353 for (i = 0; i < num_channels; i++) {
354 int channel = chan_array[i].channel;
355
356 chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name;
357 chan_array[i].type = rzg2l_adc_channels[channel].type;
358 }
359
360 data->num_channels = num_channels;
361 data->channels = chan_array;
362 adc->data = data;
363
364 return 0;
365 }
366
rzg2l_adc_hw_init(struct device * dev,struct rzg2l_adc * adc)367 static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
368 {
369 const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
370 u32 reg;
371 int ret;
372
373 ret = pm_runtime_resume_and_get(dev);
374 if (ret)
375 return ret;
376
377 /* SW reset */
378 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
379 reg |= RZG2L_ADM0_SRESB;
380 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
381
382 ret = read_poll_timeout(rzg2l_adc_readl, reg, reg & RZG2L_ADM0_SRESB,
383 200, 1000, false, adc, RZG2L_ADM(0));
384 if (ret)
385 goto exit_hw_init;
386
387 if (hw_params->adivc) {
388 /* Only division by 4 can be set */
389 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
390 reg &= ~RZG2L_ADIVC_DIVADC_MASK;
391 reg |= RZG2L_ADIVC_DIVADC_4;
392 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
393 }
394
395 /*
396 * Setup AMD3
397 * ADIL[31:24] - Should be always set to 0
398 * ADCMP[23:16] - Should be always set to 0xe
399 * ADSMP[15:0] - Set default (0x578) sampling period
400 */
401 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
402 reg &= ~RZG2L_ADM3_ADIL_MASK;
403 reg &= ~RZG2L_ADM3_ADCMP_MASK;
404 reg &= ~hw_params->adsmp_mask;
405 reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
406 hw_params->default_adsmp[0];
407
408 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
409
410 exit_hw_init:
411 pm_runtime_put_autosuspend(dev);
412 return ret;
413 }
414
rzg2l_adc_probe(struct platform_device * pdev)415 static int rzg2l_adc_probe(struct platform_device *pdev)
416 {
417 struct device *dev = &pdev->dev;
418 struct iio_dev *indio_dev;
419 struct rzg2l_adc *adc;
420 int ret;
421 int irq;
422
423 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
424 if (!indio_dev)
425 return -ENOMEM;
426
427 platform_set_drvdata(pdev, indio_dev);
428
429 adc = iio_priv(indio_dev);
430
431 adc->hw_params = device_get_match_data(dev);
432 if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
433 return -EINVAL;
434
435 ret = rzg2l_adc_parse_properties(pdev, adc);
436 if (ret)
437 return ret;
438
439 mutex_init(&adc->lock);
440
441 adc->base = devm_platform_ioremap_resource(pdev, 0);
442 if (IS_ERR(adc->base))
443 return PTR_ERR(adc->base);
444
445 adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");
446 if (IS_ERR(adc->adrstn))
447 return dev_err_probe(dev, PTR_ERR(adc->adrstn),
448 "failed to get/deassert adrst-n\n");
449
450 adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn");
451 if (IS_ERR(adc->presetn))
452 return dev_err_probe(dev, PTR_ERR(adc->presetn),
453 "failed to get/deassert presetn\n");
454
455 pm_runtime_set_autosuspend_delay(dev, 300);
456 pm_runtime_use_autosuspend(dev);
457 ret = devm_pm_runtime_enable(dev);
458 if (ret)
459 return ret;
460
461 ret = rzg2l_adc_hw_init(dev, adc);
462 if (ret)
463 return dev_err_probe(&pdev->dev, ret,
464 "failed to initialize ADC HW\n");
465
466 irq = platform_get_irq(pdev, 0);
467 if (irq < 0)
468 return irq;
469
470 ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
471 0, dev_name(dev), adc);
472 if (ret < 0)
473 return ret;
474
475 init_completion(&adc->completion);
476
477 indio_dev->name = DRIVER_NAME;
478 indio_dev->info = &rzg2l_adc_iio_info;
479 indio_dev->modes = INDIO_DIRECT_MODE;
480 indio_dev->channels = adc->data->channels;
481 indio_dev->num_channels = adc->data->num_channels;
482
483 return devm_iio_device_register(dev, indio_dev);
484 }
485
486 static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
487 .num_channels = 8,
488 .default_adcmp = 0xe,
489 .default_adsmp = { 0x578 },
490 .adsmp_mask = GENMASK(15, 0),
491 .adint_inten_mask = GENMASK(7, 0),
492 .adivc = true
493 };
494
495 static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
496 .num_channels = 9,
497 .default_adcmp = 0x1d,
498 .default_adsmp = { 0x7f, 0xff },
499 .adsmp_mask = GENMASK(7, 0),
500 .adint_inten_mask = GENMASK(11, 0),
501 };
502
503 static const struct of_device_id rzg2l_adc_match[] = {
504 { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
505 { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
506 { }
507 };
508 MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
509
rzg2l_adc_pm_runtime_suspend(struct device * dev)510 static int rzg2l_adc_pm_runtime_suspend(struct device *dev)
511 {
512 struct iio_dev *indio_dev = dev_get_drvdata(dev);
513 struct rzg2l_adc *adc = iio_priv(indio_dev);
514
515 rzg2l_adc_pwr(adc, false);
516
517 return 0;
518 }
519
rzg2l_adc_pm_runtime_resume(struct device * dev)520 static int rzg2l_adc_pm_runtime_resume(struct device *dev)
521 {
522 struct iio_dev *indio_dev = dev_get_drvdata(dev);
523 struct rzg2l_adc *adc = iio_priv(indio_dev);
524
525 rzg2l_adc_pwr(adc, true);
526
527 return 0;
528 }
529
rzg2l_adc_suspend(struct device * dev)530 static int rzg2l_adc_suspend(struct device *dev)
531 {
532 struct iio_dev *indio_dev = dev_get_drvdata(dev);
533 struct rzg2l_adc *adc = iio_priv(indio_dev);
534 struct reset_control_bulk_data resets[] = {
535 { .rstc = adc->presetn },
536 { .rstc = adc->adrstn },
537 };
538 int ret;
539
540 ret = pm_runtime_force_suspend(dev);
541 if (ret)
542 return ret;
543
544 ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
545 if (ret)
546 goto rpm_restore;
547
548 return 0;
549
550 rpm_restore:
551 pm_runtime_force_resume(dev);
552 return ret;
553 }
554
rzg2l_adc_resume(struct device * dev)555 static int rzg2l_adc_resume(struct device *dev)
556 {
557 struct iio_dev *indio_dev = dev_get_drvdata(dev);
558 struct rzg2l_adc *adc = iio_priv(indio_dev);
559 struct reset_control_bulk_data resets[] = {
560 { .rstc = adc->adrstn },
561 { .rstc = adc->presetn },
562 };
563 int ret;
564
565 ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
566 if (ret)
567 return ret;
568
569 ret = pm_runtime_force_resume(dev);
570 if (ret)
571 goto resets_restore;
572
573 ret = rzg2l_adc_hw_init(dev, adc);
574 if (ret)
575 goto rpm_restore;
576
577 return 0;
578
579 rpm_restore:
580 pm_runtime_force_suspend(dev);
581 resets_restore:
582 reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
583 return ret;
584 }
585
586 static const struct dev_pm_ops rzg2l_adc_pm_ops = {
587 RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, rzg2l_adc_pm_runtime_resume, NULL)
588 SYSTEM_SLEEP_PM_OPS(rzg2l_adc_suspend, rzg2l_adc_resume)
589 };
590
591 static struct platform_driver rzg2l_adc_driver = {
592 .probe = rzg2l_adc_probe,
593 .driver = {
594 .name = DRIVER_NAME,
595 .of_match_table = rzg2l_adc_match,
596 .pm = pm_ptr(&rzg2l_adc_pm_ops),
597 },
598 };
599
600 module_platform_driver(rzg2l_adc_driver);
601
602 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
603 MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
604 MODULE_LICENSE("GPL v2");
605 MODULE_IMPORT_NS("IIO_DRIVER");
606