1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek HDMI v2 Display Data Channel Driver
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Copyright (c) 2021 BayLibre, SAS
7 * Copyright (c) 2024 Collabora Ltd.
8 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/types.h>
26
27 #include <drm/drm_edid.h>
28
29 #include "mtk_hdmi_common.h"
30 #include "mtk_hdmi_regs_v2.h"
31
32 #define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
33 #define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
34 #define SI2C_ADDR_READ 0xf4
35 #define SCDC_I2C_SLAVE_ADDRESS 0x54
36
37 struct mtk_hdmi_ddc {
38 struct device *dev;
39 struct regmap *regs;
40 struct clk *clk;
41 struct i2c_adapter adap;
42 };
43
mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc * ddc)44 static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
45 {
46 u32 val;
47
48 regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
49 if (val & DDC_I2C_BUS_LOW) {
50 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
51 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
52 usleep_range(250, 300);
53 }
54
55 if (val & DDC_I2C_NO_ACK) {
56 u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
57
58 regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
59 regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
60 regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
61 }
62
63 if (val & DDC_I2C_NO_ACK)
64 return -EIO;
65
66 return 0;
67 }
68
mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc * ddc,u16 addr_id,u16 offset_id,u16 data_cnt,u8 * wr_data)69 static int mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc *ddc, u16 addr_id,
70 u16 offset_id, u16 data_cnt, u8 *wr_data)
71 {
72 u32 val;
73 int ret, i;
74
75 /* Don't allow transfer with a size over than the transfer fifo size
76 * (16 byte)
77 */
78 if (data_cnt > 16) {
79 dev_err(ddc->dev, "Invalid DDCM write request\n");
80 return -EINVAL;
81 }
82
83 /* If down, rise bus for write operation */
84 mtk_ddc_check_and_rise_low_bus(ddc);
85
86 regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
87 FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
88
89 /* In case there is no payload data, just do a single write for the
90 * address only
91 */
92 if (wr_data) {
93 /* Fill transfer fifo with payload data */
94 for (i = 0; i < data_cnt; i++) {
95 regmap_write(ddc->regs, SI2C_CTRL,
96 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
97 FIELD_PREP(SI2C_WDATA, wr_data[i]) |
98 SI2C_WR);
99 }
100 }
101 regmap_write(ddc->regs, DDC_CTRL,
102 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
103 FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : data_cnt) |
104 FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
105 FIELD_PREP(DDC_CTRL_ADDR, addr_id));
106 usleep_range(1000, 1250);
107
108 ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
109 !(val & DDC_I2C_IN_PROG), 500, 1000);
110 if (ret) {
111 dev_err(ddc->dev, "DDC I2C write timeout\n");
112
113 /* Abort transfer if it is still in progress */
114 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
115 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));
116
117 return ret;
118 }
119
120 /* The I2C bus might be down after WR operation: rise it again */
121 ret = mtk_ddc_check_and_rise_low_bus(ddc);
122 if (ret) {
123 dev_err(ddc->dev, "Error during write operation: No ACK\n");
124 return ret;
125 }
126
127 return 0;
128 }
129
mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc * ddc,u16 uc_dev,u8 addr,u8 * puc_value,u16 data_cnt)130 static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
131 u8 addr, u8 *puc_value, u16 data_cnt)
132 {
133 u16 dly_cnt, i, uc_idx;
134 u32 rem, temp_length, uc_read_count, val;
135 u64 loop_counter;
136 int ret;
137
138 mtk_ddc_check_and_rise_low_bus(ddc);
139
140 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
141 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
142
143 if (data_cnt >= 16) {
144 temp_length = 16;
145 loop_counter = data_cnt;
146
147 rem = do_div(loop_counter, temp_length);
148 if (rem)
149 loop_counter++;
150 } else {
151 temp_length = data_cnt;
152 loop_counter = 1;
153 }
154
155 if (uc_dev >= DDC_ADDR)
156 dly_cnt = DDC2_DLY_CNT_EDID;
157 else
158 dly_cnt = DDC2_DLY_CNT;
159
160 regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
161 FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
162
163 for (i = 0; i < loop_counter; i++) {
164 rem = data_cnt % 16;
165
166 if (i > 0 && i == (loop_counter - 1) && rem)
167 temp_length = rem;
168
169 /* 0x51 - 0x53: Flow control */
170 if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
171 regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
172 FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
173
174 regmap_write(ddc->regs, DDC_CTRL,
175 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
176 FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
177 FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
178 FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
179 } else {
180 u16 offset;
181
182 if (addr != 0x43)
183 offset = i * 16;
184 else
185 offset = 0;
186
187 regmap_write(ddc->regs, DDC_CTRL,
188 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
189 FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
190 FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
191 FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
192 }
193 usleep_range(5000, 5500);
194
195 ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
196 !(val & DDC_I2C_IN_PROG), 1000,
197 500 * (temp_length + 5));
198 if (ret) {
199 dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
200
201 /* Abort transfer if it is still in progress */
202 regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
203 FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));
204
205 return ret;
206 }
207
208 ret = mtk_ddc_check_and_rise_low_bus(ddc);
209 if (ret) {
210 dev_err(ddc->dev, "Error during read operation: No ACK\n");
211 return ret;
212 }
213
214 for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
215 unsigned int read_idx = i * 16 + uc_idx;
216
217 regmap_write(ddc->regs, SI2C_CTRL,
218 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
219 SI2C_RD);
220
221 regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
222 puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
223
224 regmap_write(ddc->regs, SI2C_CTRL,
225 FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
226 SI2C_CONFIRM_READ);
227
228 /*
229 * If HDMI IP gets reset during EDID read, DDC read
230 * operation will fail and its delay counter will be
231 * reset to 400.
232 */
233 regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
234 if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
235 return 0;
236
237 uc_read_count = read_idx + 1;
238 }
239 }
240 if (uc_read_count > U8_MAX)
241 dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
242
243 return uc_read_count;
244 }
245
mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc * ddc,u16 b_dev,u8 data_addr,u16 data_cnt,u8 * pr_data)246 static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
247 u8 data_addr, u16 data_cnt, u8 *pr_data)
248 {
249 int read_data_cnt;
250 u16 req_data_cnt;
251
252 if (!data_cnt) {
253 dev_err(ddc->dev, "Invalid DDCM read request\n");
254 return -EINVAL;
255 }
256
257 req_data_cnt = U8_MAX - data_addr + 1;
258 if (req_data_cnt > data_cnt)
259 req_data_cnt = data_cnt;
260
261 regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
262
263 read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
264
265 if (read_data_cnt < 0)
266 return read_data_cnt;
267 else if (read_data_cnt != req_data_cnt)
268 return -EINVAL;
269
270 return 0;
271 }
272
mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc * ddc,u16 b_dev,u8 data_addr,u16 data_cnt,u8 * pr_data)273 static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
274 u8 data_addr, u16 data_cnt, u8 *pr_data)
275 {
276 regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
277
278 return mtk_ddcm_write_hdmi(ddc, b_dev, data_addr, data_cnt, pr_data);
279 }
280
mtk_hdmi_ddc_v2_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)281 static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
282 {
283 struct mtk_hdmi_ddc *ddc;
284 u8 offset = 0;
285 int i, ret;
286
287 ddc = adapter->algo_data;
288
289 for (i = 0; i < num; i++) {
290 struct i2c_msg *msg = &msgs[i];
291
292 if (!msg->buf) {
293 dev_err(ddc->dev, "No message buffer\n");
294 return -EINVAL;
295 }
296
297 if (msg->flags & I2C_M_RD) {
298 /*
299 * The underlying DDC hardware always issues a write request
300 * that assigns the read offset as part of the read operation,
301 * therefore, use the `offset` value assigned in the previous
302 * write request from drm_edid
303 */
304 ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
305 msg->len, &msg->buf[0]);
306 if (ret)
307 return ret;
308 } else {
309 /*
310 * The HW needs the data offset, found in buf[0], in the
311 * DDC_CTRL register, and each byte of data, starting at
312 * buf[1], goes in the SI2C_WDATA register.
313 */
314 ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
315 msg->len - 1, &msg->buf[1]);
316 if (ret)
317 return ret;
318
319 /*
320 * Store the offset value requested by drm_edid or by
321 * scdc to use in subsequent read requests.
322 */
323 if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
324 msg->len == 1) {
325 offset = msg->buf[0];
326 }
327 }
328 }
329
330 return i;
331 }
332
mtk_hdmi_ddc_v2_func(struct i2c_adapter * adapter)333 static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
334 {
335 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
336 }
337
338 static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
339 .master_xfer = mtk_hdmi_ddc_v2_xfer,
340 .functionality = mtk_hdmi_ddc_v2_func,
341 };
342
mtk_hdmi_ddc_v2_probe(struct platform_device * pdev)343 static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
344 {
345 struct device *dev = &pdev->dev;
346 struct mtk_hdmi_ddc *ddc;
347 int ret;
348
349 ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
350 if (!ddc)
351 return -ENOMEM;
352
353 ddc->dev = dev;
354 ddc->regs = device_node_to_regmap(dev->parent->of_node);
355 if (IS_ERR_OR_NULL(ddc->regs))
356 return dev_err_probe(dev,
357 IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
358 "Cannot get regmap\n");
359
360 ddc->clk = devm_clk_get_enabled(dev, NULL);
361 if (IS_ERR(ddc->clk))
362 return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
363
364 strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
365 ddc->adap.owner = THIS_MODULE;
366 ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
367 ddc->adap.retries = 3;
368 ddc->adap.dev.of_node = dev->of_node;
369 ddc->adap.algo_data = ddc;
370 ddc->adap.dev.parent = &pdev->dev;
371
372 ret = devm_pm_runtime_enable(&pdev->dev);
373 if (ret)
374 return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
375
376 pm_runtime_get_sync(dev);
377
378 ret = devm_i2c_add_adapter(dev, &ddc->adap);
379 if (ret < 0)
380 return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
381
382 platform_set_drvdata(pdev, ddc);
383 return 0;
384 }
385
386 static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
387 { .compatible = "mediatek,mt8195-hdmi-ddc" },
388 { /* sentinel */ }
389 };
390 MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
391
392 struct platform_driver mtk_hdmi_ddc_v2_driver = {
393 .probe = mtk_hdmi_ddc_v2_probe,
394 .driver = {
395 .name = "mediatek-hdmi-ddc-v2",
396 .of_match_table = mtk_hdmi_ddc_v2_match,
397 },
398 };
399 module_platform_driver(mtk_hdmi_ddc_v2_driver);
400
401 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
402 MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
403 MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
404 MODULE_LICENSE("GPL");
405