1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #include <linux/pci.h> 6 7 #include "mac.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "ser.h" 11 12 static bool rtw89_pci_disable_clkreq; 13 static bool rtw89_pci_disable_aspm_l1; 14 static bool rtw89_pci_disable_l1ss; 15 module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); 16 module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); 17 module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); 18 MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); 19 MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); 20 MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); 21 22 static int rtw89_pci_get_phy_offset_by_link_speed(struct rtw89_dev *rtwdev, 23 u32 *phy_offset) 24 { 25 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 26 struct pci_dev *pdev = rtwpci->pdev; 27 u32 val; 28 int ret; 29 30 ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val); 31 if (ret) 32 return ret; 33 34 val = u32_get_bits(val, RTW89_BCFG_LINK_SPEED_MASK); 35 if (val == RTW89_PCIE_GEN1_SPEED) { 36 *phy_offset = R_RAC_DIRECT_OFFSET_G1; 37 } else if (val == RTW89_PCIE_GEN2_SPEED) { 38 *phy_offset = R_RAC_DIRECT_OFFSET_G2; 39 } else { 40 rtw89_warn(rtwdev, "Unknown PCI link speed %d\n", val); 41 return -EFAULT; 42 } 43 44 return 0; 45 } 46 47 static int rtw89_pci_rst_bdram_ax(struct rtw89_dev *rtwdev) 48 { 49 u32 val; 50 int ret; 51 52 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RST_BDRAM); 53 54 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), 55 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, 56 rtwdev, R_AX_PCIE_INIT_CFG1); 57 58 return ret; 59 } 60 61 static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, 62 struct rtw89_pci_dma_ring *bd_ring, 63 u32 cur_idx, bool tx) 64 { 65 const struct rtw89_pci_info *info = rtwdev->pci_info; 66 u32 cnt, cur_rp, wp, rp, len; 67 68 rp = bd_ring->rp; 69 wp = bd_ring->wp; 70 len = bd_ring->len; 71 72 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 73 if (tx) { 74 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); 75 } else { 76 if (info->rx_ring_eq_is_full) 77 wp += 1; 78 79 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); 80 } 81 82 bd_ring->rp = cur_rp; 83 84 return cnt; 85 } 86 87 static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, 88 struct rtw89_pci_tx_ring *tx_ring) 89 { 90 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 91 u32 addr_idx = bd_ring->addr.idx; 92 u32 cnt, idx; 93 94 idx = rtw89_read32(rtwdev, addr_idx); 95 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); 96 97 return cnt; 98 } 99 100 static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, 101 struct rtw89_pci *rtwpci, 102 u32 cnt, bool release_all) 103 { 104 struct rtw89_pci_tx_data *tx_data; 105 struct sk_buff *skb; 106 u32 qlen; 107 108 while (cnt--) { 109 skb = skb_dequeue(&rtwpci->h2c_queue); 110 if (!skb) { 111 rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); 112 return; 113 } 114 skb_queue_tail(&rtwpci->h2c_release_queue, skb); 115 } 116 117 qlen = skb_queue_len(&rtwpci->h2c_release_queue); 118 if (!release_all) 119 qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; 120 121 while (qlen--) { 122 skb = skb_dequeue(&rtwpci->h2c_release_queue); 123 if (!skb) { 124 rtw89_err(rtwdev, "failed to release fwcmd\n"); 125 return; 126 } 127 tx_data = RTW89_PCI_TX_SKB_CB(skb); 128 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 129 DMA_TO_DEVICE); 130 dev_kfree_skb_any(skb); 131 } 132 } 133 134 static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, 135 struct rtw89_pci *rtwpci) 136 { 137 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[RTW89_TXCH_CH12]; 138 u32 cnt; 139 140 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 141 if (!cnt) 142 return; 143 rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); 144 } 145 146 static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, 147 struct rtw89_pci_rx_ring *rx_ring) 148 { 149 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 150 u32 addr_idx = bd_ring->addr.idx; 151 u32 cnt, idx; 152 153 idx = rtw89_read32(rtwdev, addr_idx); 154 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); 155 156 return cnt; 157 } 158 159 static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, 160 struct sk_buff *skb) 161 { 162 struct rtw89_pci_rx_info *rx_info; 163 dma_addr_t dma; 164 165 rx_info = RTW89_PCI_RX_SKB_CB(skb); 166 dma = rx_info->dma; 167 dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 168 DMA_FROM_DEVICE); 169 } 170 171 static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, 172 struct sk_buff *skb) 173 { 174 struct rtw89_pci_rx_info *rx_info; 175 dma_addr_t dma; 176 177 rx_info = RTW89_PCI_RX_SKB_CB(skb); 178 dma = rx_info->dma; 179 dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 180 DMA_FROM_DEVICE); 181 } 182 183 static void rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, 184 struct sk_buff *skb) 185 { 186 struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); 187 struct rtw89_pci_rxbd_info *rxbd_info; 188 __le32 info; 189 190 rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; 191 info = rxbd_info->dword; 192 193 rx_info->fs = le32_get_bits(info, RTW89_PCI_RXBD_FS); 194 rx_info->ls = le32_get_bits(info, RTW89_PCI_RXBD_LS); 195 rx_info->len = le32_get_bits(info, RTW89_PCI_RXBD_WRITE_SIZE); 196 rx_info->tag = le32_get_bits(info, RTW89_PCI_RXBD_TAG); 197 } 198 199 static int rtw89_pci_validate_rx_tag(struct rtw89_dev *rtwdev, 200 struct rtw89_pci_rx_ring *rx_ring, 201 struct sk_buff *skb) 202 { 203 struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); 204 const struct rtw89_pci_info *info = rtwdev->pci_info; 205 u32 target_rx_tag; 206 207 if (!info->check_rx_tag) 208 return 0; 209 210 /* valid range is 1 ~ 0x1FFF */ 211 if (rx_ring->target_rx_tag == 0) 212 target_rx_tag = 1; 213 else 214 target_rx_tag = rx_ring->target_rx_tag; 215 216 if (rx_info->tag != target_rx_tag) { 217 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "mismatch RX tag 0x%x 0x%x\n", 218 rx_info->tag, target_rx_tag); 219 return -EAGAIN; 220 } 221 222 return 0; 223 } 224 225 static 226 int rtw89_pci_sync_skb_for_device_and_validate_rx_info(struct rtw89_dev *rtwdev, 227 struct rtw89_pci_rx_ring *rx_ring, 228 struct sk_buff *skb) 229 { 230 struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); 231 int rx_tag_retry = 1000; 232 int ret; 233 234 do { 235 rtw89_pci_sync_skb_for_cpu(rtwdev, skb); 236 rtw89_pci_rxbd_info_update(rtwdev, skb); 237 238 ret = rtw89_pci_validate_rx_tag(rtwdev, rx_ring, skb); 239 if (ret != -EAGAIN) 240 break; 241 } while (rx_tag_retry--); 242 243 /* update target rx_tag for next RX */ 244 rx_ring->target_rx_tag = rx_info->tag + 1; 245 246 return ret; 247 } 248 249 static void rtw89_pci_ctrl_txdma_ch_ax(struct rtw89_dev *rtwdev, bool enable) 250 { 251 const struct rtw89_pci_info *info = rtwdev->pci_info; 252 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; 253 const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2; 254 255 if (enable) { 256 rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask); 257 if (dma_stop2->addr) 258 rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask); 259 } else { 260 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask); 261 if (dma_stop2->addr) 262 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask); 263 } 264 } 265 266 static void rtw89_pci_ctrl_txdma_fw_ch_ax(struct rtw89_dev *rtwdev, bool enable) 267 { 268 const struct rtw89_pci_info *info = rtwdev->pci_info; 269 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; 270 271 if (enable) 272 rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); 273 else 274 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); 275 } 276 277 static bool 278 rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, 279 struct sk_buff *new, 280 const struct sk_buff *skb, u32 offset, 281 const struct rtw89_pci_rx_info *rx_info, 282 const struct rtw89_rx_desc_info *desc_info) 283 { 284 u32 copy_len = rx_info->len - offset; 285 286 if (unlikely(skb_tailroom(new) < copy_len)) { 287 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 288 "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", 289 rx_info->len, desc_info->pkt_size, offset, fs, ls); 290 rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", 291 skb->data, rx_info->len); 292 /* length of a single segment skb is desc_info->pkt_size */ 293 if (fs && ls) { 294 copy_len = desc_info->pkt_size; 295 } else { 296 rtw89_info(rtwdev, "drop rx data due to invalid length\n"); 297 return false; 298 } 299 } 300 301 skb_put_data(new, skb->data + offset, copy_len); 302 303 return true; 304 } 305 306 static u32 rtw89_pci_get_rx_skb_idx(struct rtw89_dev *rtwdev, 307 struct rtw89_pci_dma_ring *bd_ring) 308 { 309 const struct rtw89_pci_info *info = rtwdev->pci_info; 310 u32 wp = bd_ring->wp; 311 312 if (!info->rx_ring_eq_is_full) 313 return wp; 314 315 if (++wp >= bd_ring->len) 316 wp = 0; 317 318 return wp; 319 } 320 321 static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, 322 struct rtw89_pci_rx_ring *rx_ring) 323 { 324 struct rtw89_rx_desc_info *desc_info = &rx_ring->deliver_desc; 325 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 326 const struct rtw89_pci_info *info = rtwdev->pci_info; 327 struct sk_buff *new = rx_ring->deliver_skb; 328 struct rtw89_pci_rx_info *rx_info; 329 struct sk_buff *skb; 330 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 331 u32 skb_idx; 332 u32 offset; 333 u32 cnt = 1; 334 bool fs, ls; 335 int ret; 336 337 skb_idx = rtw89_pci_get_rx_skb_idx(rtwdev, bd_ring); 338 skb = rx_ring->buf[skb_idx]; 339 340 ret = rtw89_pci_sync_skb_for_device_and_validate_rx_info(rtwdev, rx_ring, skb); 341 if (ret) { 342 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 343 bd_ring->wp, ret); 344 goto err_sync_device; 345 } 346 347 rx_info = RTW89_PCI_RX_SKB_CB(skb); 348 fs = info->no_rxbd_fs ? !new : rx_info->fs; 349 ls = rx_info->ls; 350 351 if (unlikely(!fs || !ls)) 352 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 353 "unexpected fs/ls=%d/%d tag=%u len=%u new->len=%u\n", 354 fs, ls, rx_info->tag, rx_info->len, new ? new->len : 0); 355 356 if (fs) { 357 if (new) { 358 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 359 "skb should not be ready before first segment start\n"); 360 goto err_sync_device; 361 } 362 if (desc_info->ready) { 363 rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); 364 goto err_sync_device; 365 } 366 367 rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); 368 369 new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size); 370 if (!new) 371 goto err_sync_device; 372 373 rx_ring->deliver_skb = new; 374 375 /* first segment has RX desc */ 376 offset = desc_info->offset + desc_info->rxd_len; 377 } else { 378 offset = sizeof(struct rtw89_pci_rxbd_info); 379 if (!new) { 380 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "no last skb\n"); 381 goto err_sync_device; 382 } 383 } 384 if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) 385 goto err_sync_device; 386 rtw89_pci_sync_skb_for_device(rtwdev, skb); 387 rtw89_pci_rxbd_increase(rx_ring, 1); 388 389 if (!desc_info->ready) { 390 rtw89_warn(rtwdev, "no rx desc information\n"); 391 goto err_free_resource; 392 } 393 if (ls) { 394 rtw89_core_rx(rtwdev, desc_info, new); 395 rx_ring->deliver_skb = NULL; 396 desc_info->ready = false; 397 } 398 399 return cnt; 400 401 err_sync_device: 402 rtw89_pci_sync_skb_for_device(rtwdev, skb); 403 rtw89_pci_rxbd_increase(rx_ring, 1); 404 err_free_resource: 405 if (new) 406 dev_kfree_skb_any(new); 407 rx_ring->deliver_skb = NULL; 408 desc_info->ready = false; 409 410 return cnt; 411 } 412 413 static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, 414 struct rtw89_pci_rx_ring *rx_ring, 415 u32 cnt) 416 { 417 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 418 u32 rx_cnt; 419 420 while (cnt && rtwdev->napi_budget_countdown > 0) { 421 rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); 422 if (!rx_cnt) { 423 rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); 424 425 /* skip the rest RXBD bufs */ 426 rtw89_pci_rxbd_increase(rx_ring, cnt); 427 break; 428 } 429 430 cnt -= rx_cnt; 431 } 432 433 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); 434 } 435 436 static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, 437 struct rtw89_pci *rtwpci, int budget) 438 { 439 struct rtw89_pci_rx_ring *rx_ring; 440 int countdown = rtwdev->napi_budget_countdown; 441 u32 cnt; 442 443 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RXQ]; 444 445 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 446 if (!cnt) 447 return 0; 448 449 cnt = min_t(u32, budget, cnt); 450 451 rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); 452 453 /* In case of flushing pending SKBs, the countdown may exceed. */ 454 if (rtwdev->napi_budget_countdown <= 0) 455 return budget; 456 457 return budget - countdown; 458 } 459 460 static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, 461 struct rtw89_pci_tx_ring *tx_ring, 462 struct sk_buff *skb, u8 tx_status) 463 { 464 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 465 struct ieee80211_tx_info *info; 466 467 if (rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status)) 468 return; 469 470 info = IEEE80211_SKB_CB(skb); 471 ieee80211_tx_info_clear_status(info); 472 473 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 474 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 475 if (tx_status == RTW89_TX_DONE) { 476 info->flags |= IEEE80211_TX_STAT_ACK; 477 tx_ring->tx_acked++; 478 } else { 479 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) 480 rtw89_debug(rtwdev, RTW89_DBG_FW, 481 "failed to TX of status %x\n", tx_status); 482 switch (tx_status) { 483 case RTW89_TX_RETRY_LIMIT: 484 tx_ring->tx_retry_lmt++; 485 break; 486 case RTW89_TX_LIFE_TIME: 487 tx_ring->tx_life_time++; 488 break; 489 case RTW89_TX_MACID_DROP: 490 tx_ring->tx_mac_id_drop++; 491 break; 492 default: 493 rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); 494 break; 495 } 496 } 497 498 ieee80211_tx_status_ni(rtwdev->hw, skb); 499 } 500 501 static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 502 { 503 struct rtw89_pci_tx_wd *txwd; 504 u32 cnt; 505 506 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 507 while (cnt--) { 508 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 509 if (!txwd) { 510 rtw89_warn(rtwdev, "No busy txwd pages available\n"); 511 break; 512 } 513 514 list_del_init(&txwd->list); 515 516 /* this skb has been freed by RPP */ 517 if (skb_queue_len(&txwd->queue) == 0) 518 rtw89_pci_enqueue_txwd(tx_ring, txwd); 519 } 520 } 521 522 static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, 523 struct rtw89_pci_tx_ring *tx_ring) 524 { 525 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 526 struct rtw89_pci_tx_wd *txwd; 527 int i; 528 529 for (i = 0; i < wd_ring->page_num; i++) { 530 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 531 if (!txwd) 532 break; 533 534 list_del_init(&txwd->list); 535 } 536 } 537 538 static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, 539 struct rtw89_pci_tx_ring *tx_ring, 540 struct rtw89_pci_tx_wd *txwd, u16 seq, 541 u8 tx_status) 542 { 543 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 544 struct rtw89_pci_tx_data *tx_data; 545 struct sk_buff *skb, *tmp; 546 u8 txch = tx_ring->txch; 547 548 if (!list_empty(&txwd->list)) { 549 rtw89_pci_reclaim_txbd(rtwdev, tx_ring); 550 /* In low power mode, RPP can receive before updating of TX BD. 551 * In normal mode, it should not happen so give it a warning. 552 */ 553 if (!rtwpci->low_power && !list_empty(&txwd->list)) 554 rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", 555 txch, seq); 556 } 557 558 skb_queue_walk_safe(&txwd->queue, skb, tmp) { 559 skb_unlink(skb, &txwd->queue); 560 561 tx_data = RTW89_PCI_TX_SKB_CB(skb); 562 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 563 DMA_TO_DEVICE); 564 565 rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); 566 } 567 568 if (list_empty(&txwd->list)) 569 rtw89_pci_enqueue_txwd(tx_ring, txwd); 570 } 571 572 void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp, 573 struct rtw89_pci_rpp_info *rpp_info) 574 { 575 const struct rtw89_pci_rpp_fmt *rpp = _rpp; 576 577 rpp_info->seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); 578 rpp_info->qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); 579 rpp_info->tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); 580 rpp_info->txch = rtw89_chip_get_ch_dma(rtwdev, rpp_info->qsel); 581 } 582 EXPORT_SYMBOL(rtw89_pci_parse_rpp); 583 584 void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp, 585 struct rtw89_pci_rpp_info *rpp_info) 586 { 587 const struct rtw89_pci_rpp_fmt_v1 *rpp = _rpp; 588 589 rpp_info->seq = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK); 590 rpp_info->qsel = le32_get_bits(rpp->w1, RTW89_PCI_RPP_W1_QSEL_V1_MASK); 591 rpp_info->tx_status = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK); 592 rpp_info->txch = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_DMA_CH_MASK); 593 } 594 EXPORT_SYMBOL(rtw89_pci_parse_rpp_v1); 595 596 static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp) 597 { 598 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 599 const struct rtw89_pci_info *info = rtwdev->pci_info; 600 struct rtw89_pci_rpp_info rpp_info = {}; 601 struct rtw89_pci_tx_wd_ring *wd_ring; 602 struct rtw89_pci_tx_ring *tx_ring; 603 struct rtw89_pci_tx_wd *txwd; 604 605 info->parse_rpp(rtwdev, rpp, &rpp_info); 606 607 if (unlikely(rpp_info.txch >= RTW89_TXCH_NUM || 608 info->tx_dma_ch_mask & BIT(rpp_info.txch))) { 609 rtw89_warn(rtwdev, "should no release report on txch %d\n", 610 rpp_info.txch); 611 return; 612 } 613 614 if (unlikely(rpp_info.seq >= RTW89_PCI_TXWD_NUM_MAX)) { 615 rtw89_warn(rtwdev, "invalid seq %d\n", rpp_info.seq); 616 return; 617 } 618 619 tx_ring = &rtwpci->tx.rings[rpp_info.txch]; 620 wd_ring = &tx_ring->wd_ring; 621 txwd = &wd_ring->pages[rpp_info.seq]; 622 623 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, rpp_info.seq, 624 rpp_info.tx_status); 625 } 626 627 static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, 628 struct rtw89_pci_tx_ring *tx_ring) 629 { 630 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 631 struct rtw89_pci_tx_wd *txwd; 632 int i; 633 634 for (i = 0; i < wd_ring->page_num; i++) { 635 txwd = &wd_ring->pages[i]; 636 637 if (!list_empty(&txwd->list)) 638 continue; 639 640 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); 641 } 642 } 643 644 static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, 645 struct rtw89_pci_rx_ring *rx_ring, 646 u32 max_cnt) 647 { 648 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 649 const struct rtw89_pci_info *info = rtwdev->pci_info; 650 struct rtw89_rx_desc_info desc_info = {}; 651 struct rtw89_pci_rx_info *rx_info; 652 struct sk_buff *skb; 653 void *rpp; 654 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 655 u32 rpp_size = info->rpp_fmt_size; 656 u32 cnt = 0; 657 u32 skb_idx; 658 u32 offset; 659 int ret; 660 661 skb_idx = rtw89_pci_get_rx_skb_idx(rtwdev, bd_ring); 662 skb = rx_ring->buf[skb_idx]; 663 664 ret = rtw89_pci_sync_skb_for_device_and_validate_rx_info(rtwdev, rx_ring, skb); 665 if (ret) { 666 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 667 bd_ring->wp, ret); 668 goto err_sync_device; 669 } 670 671 rx_info = RTW89_PCI_RX_SKB_CB(skb); 672 if (!rx_info->fs || !rx_info->ls) { 673 rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); 674 return cnt; 675 } 676 677 rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); 678 679 /* first segment has RX desc */ 680 offset = desc_info.offset + desc_info.rxd_len; 681 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { 682 rpp = skb->data + offset; 683 rtw89_pci_release_rpp(rtwdev, rpp); 684 } 685 686 rtw89_pci_sync_skb_for_device(rtwdev, skb); 687 rtw89_pci_rxbd_increase(rx_ring, 1); 688 cnt++; 689 690 return cnt; 691 692 err_sync_device: 693 rtw89_pci_sync_skb_for_device(rtwdev, skb); 694 return 0; 695 } 696 697 static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, 698 struct rtw89_pci_rx_ring *rx_ring, 699 u32 cnt) 700 { 701 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 702 u32 release_cnt; 703 704 while (cnt) { 705 release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); 706 if (!release_cnt) { 707 rtw89_err(rtwdev, "failed to release TX skbs\n"); 708 709 /* skip the rest RXBD bufs */ 710 rtw89_pci_rxbd_increase(rx_ring, cnt); 711 break; 712 } 713 714 cnt -= release_cnt; 715 } 716 717 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); 718 } 719 720 static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, 721 struct rtw89_pci *rtwpci, int budget) 722 { 723 struct rtw89_pci_rx_ring *rx_ring; 724 u32 cnt; 725 int work_done; 726 727 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 728 729 spin_lock_bh(&rtwpci->trx_lock); 730 731 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 732 if (cnt == 0) 733 goto out_unlock; 734 735 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 736 737 out_unlock: 738 spin_unlock_bh(&rtwpci->trx_lock); 739 740 /* always release all RPQ */ 741 work_done = min_t(int, cnt, budget); 742 rtwdev->napi_budget_countdown -= work_done; 743 744 return work_done; 745 } 746 747 static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, 748 struct rtw89_pci *rtwpci) 749 { 750 struct rtw89_pci_rx_ring *rx_ring; 751 struct rtw89_pci_dma_ring *bd_ring; 752 u32 reg_idx; 753 u16 hw_idx, hw_idx_next, host_idx; 754 int i; 755 756 for (i = 0; i < RTW89_RXCH_NUM; i++) { 757 rx_ring = &rtwpci->rx.rings[i]; 758 bd_ring = &rx_ring->bd_ring; 759 760 reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); 761 hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); 762 host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); 763 hw_idx_next = (hw_idx + 1) % bd_ring->len; 764 765 if (hw_idx_next == host_idx) 766 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "%d RXD unavailable\n", i); 767 768 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 769 "%d RXD unavailable, idx=0x%08x, len=%d\n", 770 i, reg_idx, bd_ring->len); 771 } 772 } 773 774 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, 775 struct rtw89_pci *rtwpci, 776 struct rtw89_pci_isrs *isrs) 777 { 778 isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; 779 isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; 780 isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; 781 782 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); 783 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); 784 rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); 785 } 786 EXPORT_SYMBOL(rtw89_pci_recognize_intrs); 787 788 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev, 789 struct rtw89_pci *rtwpci, 790 struct rtw89_pci_isrs *isrs) 791 { 792 isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs; 793 isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ? 794 rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0; 795 isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ? 796 rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0; 797 isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ? 798 rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0; 799 800 if (isrs->halt_c2h_isrs) 801 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); 802 if (isrs->isrs[0]) 803 rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]); 804 if (isrs->isrs[1]) 805 rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]); 806 } 807 EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1); 808 809 void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev, 810 struct rtw89_pci *rtwpci, 811 struct rtw89_pci_isrs *isrs) 812 { 813 isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs; 814 isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ? 815 rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0; 816 isrs->isrs[0] = isrs->ind_isrs & B_BE_HCI_AXIDMA_INT ? 817 rtw89_read32(rtwdev, R_BE_HAXI_HISR00) & rtwpci->intrs[0] : 0; 818 isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1]; 819 820 if (isrs->halt_c2h_isrs) 821 rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs); 822 if (isrs->isrs[0]) 823 rtw89_write32(rtwdev, R_BE_HAXI_HISR00, isrs->isrs[0]); 824 if (isrs->isrs[1]) 825 rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]); 826 rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs); 827 } 828 EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v2); 829 830 void rtw89_pci_recognize_intrs_v3(struct rtw89_dev *rtwdev, 831 struct rtw89_pci *rtwpci, 832 struct rtw89_pci_isrs *isrs) 833 { 834 isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs; 835 isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ? 836 rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0; 837 isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1]; 838 839 /* isrs[0] is not used, so borrow to store RDU status to share common 840 * flow in rtw89_pci_interrupt_threadfn(). 841 */ 842 isrs->isrs[0] = isrs->isrs[1] & (B_BE_PCIE_RDU_CH1_INT | 843 B_BE_PCIE_RDU_CH0_INT); 844 845 if (isrs->halt_c2h_isrs) 846 rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs); 847 if (isrs->isrs[1]) 848 rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]); 849 rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs); 850 } 851 EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v3); 852 853 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 854 { 855 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); 856 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); 857 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); 858 } 859 EXPORT_SYMBOL(rtw89_pci_enable_intr); 860 861 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 862 { 863 rtw89_write32(rtwdev, R_AX_HIMR0, 0); 864 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); 865 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); 866 } 867 EXPORT_SYMBOL(rtw89_pci_disable_intr); 868 869 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 870 { 871 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs); 872 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); 873 rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]); 874 rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]); 875 } 876 EXPORT_SYMBOL(rtw89_pci_enable_intr_v1); 877 878 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 879 { 880 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, 0); 881 } 882 EXPORT_SYMBOL(rtw89_pci_disable_intr_v1); 883 884 void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 885 { 886 rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs); 887 rtw89_write32(rtwdev, R_BE_HAXI_HIMR00, rtwpci->intrs[0]); 888 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]); 889 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs); 890 } 891 EXPORT_SYMBOL(rtw89_pci_enable_intr_v2); 892 893 void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 894 { 895 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, 0); 896 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, 0); 897 } 898 EXPORT_SYMBOL(rtw89_pci_disable_intr_v2); 899 900 void rtw89_pci_enable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 901 { 902 rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs); 903 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]); 904 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs); 905 } 906 EXPORT_SYMBOL(rtw89_pci_enable_intr_v3); 907 908 void rtw89_pci_disable_intr_v3(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 909 { 910 rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, 0); 911 rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, 0); 912 } 913 EXPORT_SYMBOL(rtw89_pci_disable_intr_v3); 914 915 static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev) 916 { 917 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 918 unsigned long flags; 919 920 spin_lock_irqsave(&rtwpci->irq_lock, flags); 921 rtw89_chip_disable_intr(rtwdev, rtwpci); 922 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_START); 923 rtw89_chip_enable_intr(rtwdev, rtwpci); 924 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 925 } 926 927 static void rtw89_pci_ops_recovery_complete(struct rtw89_dev *rtwdev) 928 { 929 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 930 unsigned long flags; 931 932 spin_lock_irqsave(&rtwpci->irq_lock, flags); 933 rtw89_chip_disable_intr(rtwdev, rtwpci); 934 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE); 935 rtw89_chip_enable_intr(rtwdev, rtwpci); 936 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 937 } 938 939 static void rtw89_pci_low_power_interrupt_handler(struct rtw89_dev *rtwdev) 940 { 941 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 942 int budget = NAPI_POLL_WEIGHT; 943 944 /* To prevent RXQ get stuck due to run out of budget. */ 945 rtwdev->napi_budget_countdown = budget; 946 947 rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, budget); 948 rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, budget); 949 } 950 951 static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) 952 { 953 struct rtw89_dev *rtwdev = dev; 954 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 955 const struct rtw89_pci_info *info = rtwdev->pci_info; 956 const struct rtw89_pci_isr_def *isr_def = info->isr_def; 957 struct rtw89_pci_isrs isrs; 958 unsigned long flags; 959 960 spin_lock_irqsave(&rtwpci->irq_lock, flags); 961 rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs); 962 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 963 964 if (unlikely(isrs.isrs[0] & isr_def->isr_rdu)) 965 rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); 966 967 if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_halt_c2h)) 968 rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); 969 970 if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_wdt_timeout)) 971 rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); 972 973 if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_sps_ocp)) 974 rtw89_warn(rtwdev, "SPS OCP alarm 0x%x\n", isrs.halt_c2h_isrs); 975 976 if (unlikely(rtwpci->under_recovery)) 977 goto enable_intr; 978 979 if (unlikely(rtwpci->low_power)) { 980 rtw89_pci_low_power_interrupt_handler(rtwdev); 981 goto enable_intr; 982 } 983 984 if (likely(rtwpci->running)) { 985 local_bh_disable(); 986 napi_schedule(&rtwdev->napi); 987 local_bh_enable(); 988 } 989 990 return IRQ_HANDLED; 991 992 enable_intr: 993 spin_lock_irqsave(&rtwpci->irq_lock, flags); 994 if (likely(rtwpci->running)) 995 rtw89_chip_enable_intr(rtwdev, rtwpci); 996 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 997 return IRQ_HANDLED; 998 } 999 1000 static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) 1001 { 1002 struct rtw89_dev *rtwdev = dev; 1003 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1004 unsigned long flags; 1005 irqreturn_t irqret = IRQ_WAKE_THREAD; 1006 1007 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1008 1009 /* If interrupt event is on the road, it is still trigger interrupt 1010 * even we have done pci_stop() to turn off IMR. 1011 */ 1012 if (unlikely(!rtwpci->running)) { 1013 irqret = IRQ_HANDLED; 1014 goto exit; 1015 } 1016 1017 rtw89_chip_disable_intr(rtwdev, rtwpci); 1018 exit: 1019 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1020 1021 return irqret; 1022 } 1023 1024 #define DEF_TXCHADDRS_TYPE3(gen, ch_idx, txch, v...) \ 1025 [RTW89_TXCH_##ch_idx] = { \ 1026 .num = R_##gen##_##txch##_TXBD_CFG, \ 1027 .idx = R_##gen##_##txch##_TXBD_IDX ##v, \ 1028 .bdram = 0, \ 1029 .desa_l = 0, \ 1030 .desa_h = 0, \ 1031 } 1032 1033 #define DEF_TXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, txch, grp, v...) \ 1034 [RTW89_TXCH_##ch_idx] = { \ 1035 .num = R_##gen##_##txch##_TXBD_CFG, \ 1036 .idx = R_##gen##_##txch##_TXBD_IDX ##v, \ 1037 .bdram = 0, \ 1038 .desa_l = R_##gen##_##grp##_TXBD_DESA_L, \ 1039 .desa_h = R_##gen##_##grp##_TXBD_DESA_H, \ 1040 } 1041 1042 #define DEF_TXCHADDRS_TYPE2(gen, ch_idx, txch, v...) \ 1043 [RTW89_TXCH_##ch_idx] = { \ 1044 .num = R_##gen##_##txch##_TXBD_NUM ##v, \ 1045 .idx = R_##gen##_##txch##_TXBD_IDX ##v, \ 1046 .bdram = 0, \ 1047 .desa_l = R_##gen##_##txch##_TXBD_DESA_L ##v, \ 1048 .desa_h = R_##gen##_##txch##_TXBD_DESA_H ##v, \ 1049 } 1050 1051 #define DEF_TXCHADDRS_TYPE1(info, txch, v...) \ 1052 [RTW89_TXCH_##txch] = { \ 1053 .num = R_AX_##txch##_TXBD_NUM ##v, \ 1054 .idx = R_AX_##txch##_TXBD_IDX ##v, \ 1055 .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ 1056 .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ 1057 .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ 1058 } 1059 1060 #define DEF_TXCHADDRS(info, txch, v...) \ 1061 [RTW89_TXCH_##txch] = { \ 1062 .num = R_AX_##txch##_TXBD_NUM, \ 1063 .idx = R_AX_##txch##_TXBD_IDX, \ 1064 .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ 1065 .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ 1066 .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ 1067 } 1068 1069 #define DEF_RXCHADDRS_TYPE3(gen, ch_idx, rxch, v...) \ 1070 [RTW89_RXCH_##ch_idx] = { \ 1071 .num = R_##gen##_RX_##rxch##_RXBD_CONFIG, \ 1072 .idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \ 1073 .desa_l = 0, \ 1074 .desa_h = 0, \ 1075 } 1076 1077 #define DEF_RXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, rxch, grp, v...) \ 1078 [RTW89_RXCH_##ch_idx] = { \ 1079 .num = R_##gen##_RX_##rxch##_RXBD_CONFIG, \ 1080 .idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \ 1081 .desa_l = R_##gen##_##grp##_RXBD_DESA_L, \ 1082 .desa_h = R_##gen##_##grp##_RXBD_DESA_H, \ 1083 } 1084 1085 #define DEF_RXCHADDRS(gen, ch_idx, rxch, v...) \ 1086 [RTW89_RXCH_##ch_idx] = { \ 1087 .num = R_##gen##_##rxch##_RXBD_NUM ##v, \ 1088 .idx = R_##gen##_##rxch##_RXBD_IDX ##v, \ 1089 .desa_l = R_##gen##_##rxch##_RXBD_DESA_L ##v, \ 1090 .desa_h = R_##gen##_##rxch##_RXBD_DESA_H ##v, \ 1091 } 1092 1093 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set = { 1094 .tx = { 1095 DEF_TXCHADDRS(info, ACH0), 1096 DEF_TXCHADDRS(info, ACH1), 1097 DEF_TXCHADDRS(info, ACH2), 1098 DEF_TXCHADDRS(info, ACH3), 1099 DEF_TXCHADDRS(info, ACH4), 1100 DEF_TXCHADDRS(info, ACH5), 1101 DEF_TXCHADDRS(info, ACH6), 1102 DEF_TXCHADDRS(info, ACH7), 1103 DEF_TXCHADDRS(info, CH8), 1104 DEF_TXCHADDRS(info, CH9), 1105 DEF_TXCHADDRS_TYPE1(info, CH10), 1106 DEF_TXCHADDRS_TYPE1(info, CH11), 1107 DEF_TXCHADDRS(info, CH12), 1108 }, 1109 .rx = { 1110 DEF_RXCHADDRS(AX, RXQ, RXQ), 1111 DEF_RXCHADDRS(AX, RPQ, RPQ), 1112 }, 1113 }; 1114 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set); 1115 1116 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1 = { 1117 .tx = { 1118 DEF_TXCHADDRS(info, ACH0, _V1), 1119 DEF_TXCHADDRS(info, ACH1, _V1), 1120 DEF_TXCHADDRS(info, ACH2, _V1), 1121 DEF_TXCHADDRS(info, ACH3, _V1), 1122 DEF_TXCHADDRS(info, ACH4, _V1), 1123 DEF_TXCHADDRS(info, ACH5, _V1), 1124 DEF_TXCHADDRS(info, ACH6, _V1), 1125 DEF_TXCHADDRS(info, ACH7, _V1), 1126 DEF_TXCHADDRS(info, CH8, _V1), 1127 DEF_TXCHADDRS(info, CH9, _V1), 1128 DEF_TXCHADDRS_TYPE1(info, CH10, _V1), 1129 DEF_TXCHADDRS_TYPE1(info, CH11, _V1), 1130 DEF_TXCHADDRS(info, CH12, _V1), 1131 }, 1132 .rx = { 1133 DEF_RXCHADDRS(AX, RXQ, RXQ, _V1), 1134 DEF_RXCHADDRS(AX, RPQ, RPQ, _V1), 1135 }, 1136 }; 1137 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_v1); 1138 1139 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be = { 1140 .tx = { 1141 DEF_TXCHADDRS_TYPE2(BE, ACH0, CH0, _V1), 1142 DEF_TXCHADDRS_TYPE2(BE, ACH1, CH1, _V1), 1143 DEF_TXCHADDRS_TYPE2(BE, ACH2, CH2, _V1), 1144 DEF_TXCHADDRS_TYPE2(BE, ACH3, CH3, _V1), 1145 DEF_TXCHADDRS_TYPE2(BE, ACH4, CH4, _V1), 1146 DEF_TXCHADDRS_TYPE2(BE, ACH5, CH5, _V1), 1147 DEF_TXCHADDRS_TYPE2(BE, ACH6, CH6, _V1), 1148 DEF_TXCHADDRS_TYPE2(BE, ACH7, CH7, _V1), 1149 DEF_TXCHADDRS_TYPE2(BE, CH8, CH8, _V1), 1150 DEF_TXCHADDRS_TYPE2(BE, CH9, CH9, _V1), 1151 DEF_TXCHADDRS_TYPE2(BE, CH10, CH10, _V1), 1152 DEF_TXCHADDRS_TYPE2(BE, CH11, CH11, _V1), 1153 DEF_TXCHADDRS_TYPE2(BE, CH12, CH12, _V1), 1154 }, 1155 .rx = { 1156 DEF_RXCHADDRS(BE, RXQ, RXQ0, _V1), 1157 DEF_RXCHADDRS(BE, RPQ, RPQ0, _V1), 1158 }, 1159 }; 1160 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_be); 1161 1162 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_be_v1 = { 1163 .tx = { 1164 DEF_TXCHADDRS_TYPE3_GRP_BASE(BE, ACH0, CH0, ACQ, _V1), 1165 /* no CH1 */ 1166 DEF_TXCHADDRS_TYPE3(BE, ACH2, CH2, _V1), 1167 /* no CH3 */ 1168 DEF_TXCHADDRS_TYPE3(BE, ACH4, CH4, _V1), 1169 /* no CH5 */ 1170 DEF_TXCHADDRS_TYPE3(BE, ACH6, CH6, _V1), 1171 /* no CH7 */ 1172 DEF_TXCHADDRS_TYPE3_GRP_BASE(BE, CH8, CH8, NACQ, _V1), 1173 /* no CH9 */ 1174 DEF_TXCHADDRS_TYPE3(BE, CH10, CH10, _V1), 1175 /* no CH11 */ 1176 DEF_TXCHADDRS_TYPE3(BE, CH12, CH12, _V1), 1177 }, 1178 .rx = { 1179 DEF_RXCHADDRS_TYPE3_GRP_BASE(BE, RXQ, CH0, HOST0, _V1), 1180 DEF_RXCHADDRS_TYPE3(BE, RPQ, CH1, _V1), 1181 }, 1182 }; 1183 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_be_v1); 1184 1185 #undef DEF_TXCHADDRS_TYPE3 1186 #undef DEF_TXCHADDRS_TYPE3_GRP_BASE 1187 #undef DEF_TXCHADDRS_TYPE2 1188 #undef DEF_TXCHADDRS_TYPE1 1189 #undef DEF_TXCHADDRS 1190 #undef DEF_RXCHADDRS_TYPE3 1191 #undef DEF_RXCHADDRS_TYPE3_GRP_BASE 1192 #undef DEF_RXCHADDRS 1193 1194 static int rtw89_pci_get_txch_addrs(struct rtw89_dev *rtwdev, 1195 enum rtw89_tx_channel txch, 1196 const struct rtw89_pci_ch_dma_addr **addr) 1197 { 1198 const struct rtw89_pci_info *info = rtwdev->pci_info; 1199 1200 if (txch >= RTW89_TXCH_NUM) 1201 return -EINVAL; 1202 1203 *addr = &info->dma_addr_set->tx[txch]; 1204 1205 return 0; 1206 } 1207 1208 static int rtw89_pci_get_rxch_addrs(struct rtw89_dev *rtwdev, 1209 enum rtw89_rx_channel rxch, 1210 const struct rtw89_pci_ch_dma_addr **addr) 1211 { 1212 const struct rtw89_pci_info *info = rtwdev->pci_info; 1213 1214 if (rxch >= RTW89_RXCH_NUM) 1215 return -EINVAL; 1216 1217 *addr = &info->dma_addr_set->rx[rxch]; 1218 1219 return 0; 1220 } 1221 1222 static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) 1223 { 1224 struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; 1225 1226 /* reserved 1 desc check ring is full or not */ 1227 if (bd_ring->rp > bd_ring->wp) 1228 return bd_ring->rp - bd_ring->wp - 1; 1229 1230 return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; 1231 } 1232 1233 static 1234 u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) 1235 { 1236 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1237 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[RTW89_TXCH_CH12]; 1238 u32 cnt; 1239 1240 spin_lock_bh(&rtwpci->trx_lock); 1241 rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); 1242 cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 1243 spin_unlock_bh(&rtwpci->trx_lock); 1244 1245 return cnt; 1246 } 1247 1248 static 1249 u32 __rtw89_pci_check_and_reclaim_tx_resource_noio(struct rtw89_dev *rtwdev, 1250 u8 txch) 1251 { 1252 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1253 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1254 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 1255 u32 cnt; 1256 1257 spin_lock_bh(&rtwpci->trx_lock); 1258 cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 1259 if (txch != RTW89_TXCH_CH12) 1260 cnt = min(cnt, wd_ring->curr_num); 1261 spin_unlock_bh(&rtwpci->trx_lock); 1262 1263 return cnt; 1264 } 1265 1266 static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 1267 u8 txch) 1268 { 1269 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1270 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1271 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 1272 const struct rtw89_chip_info *chip = rtwdev->chip; 1273 u32 bd_cnt, wd_cnt, min_cnt = 0; 1274 struct rtw89_pci_rx_ring *rx_ring; 1275 enum rtw89_debug_mask debug_mask; 1276 u32 cnt; 1277 1278 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ]; 1279 1280 spin_lock_bh(&rtwpci->trx_lock); 1281 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 1282 wd_cnt = wd_ring->curr_num; 1283 1284 if (wd_cnt == 0 || bd_cnt == 0) { 1285 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 1286 if (cnt) 1287 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 1288 else if (wd_cnt == 0) 1289 goto out_unlock; 1290 1291 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 1292 if (bd_cnt == 0) 1293 rtw89_pci_reclaim_txbd(rtwdev, tx_ring); 1294 } 1295 1296 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 1297 wd_cnt = wd_ring->curr_num; 1298 min_cnt = min(bd_cnt, wd_cnt); 1299 if (min_cnt == 0) { 1300 /* This message can be frequently shown in low power mode or 1301 * high traffic with small FIFO chips, and we have recognized it as normal 1302 * behavior, so print with mask RTW89_DBG_TXRX in these situations. 1303 */ 1304 if (rtwpci->low_power || chip->small_fifo_size) 1305 debug_mask = RTW89_DBG_TXRX; 1306 else 1307 debug_mask = RTW89_DBG_UNEXP; 1308 1309 rtw89_debug(rtwdev, debug_mask, 1310 "still no tx resource after reclaim: wd_cnt=%d bd_cnt=%d\n", 1311 wd_cnt, bd_cnt); 1312 } 1313 1314 out_unlock: 1315 spin_unlock_bh(&rtwpci->trx_lock); 1316 1317 return min_cnt; 1318 } 1319 1320 static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 1321 u8 txch) 1322 { 1323 if (rtwdev->hci.paused) 1324 return __rtw89_pci_check_and_reclaim_tx_resource_noio(rtwdev, txch); 1325 1326 if (txch == RTW89_TXCH_CH12) 1327 return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); 1328 1329 return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); 1330 } 1331 1332 static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 1333 { 1334 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1335 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1336 u32 host_idx, addr; 1337 1338 spin_lock_bh(&rtwpci->trx_lock); 1339 1340 addr = bd_ring->addr.idx; 1341 host_idx = bd_ring->wp; 1342 rtw89_write16(rtwdev, addr, host_idx); 1343 1344 spin_unlock_bh(&rtwpci->trx_lock); 1345 } 1346 1347 static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, 1348 int n_txbd) 1349 { 1350 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1351 u32 host_idx, len; 1352 1353 len = bd_ring->len; 1354 host_idx = bd_ring->wp + n_txbd; 1355 host_idx = host_idx < len ? host_idx : host_idx - len; 1356 1357 bd_ring->wp = host_idx; 1358 } 1359 1360 static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 1361 { 1362 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1363 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1364 1365 if (rtwdev->hci.paused) { 1366 set_bit(txch, rtwpci->kick_map); 1367 return; 1368 } 1369 1370 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 1371 } 1372 1373 static void rtw89_pci_tx_kick_off_pending(struct rtw89_dev *rtwdev) 1374 { 1375 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1376 struct rtw89_pci_tx_ring *tx_ring; 1377 int txch; 1378 1379 for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { 1380 if (!test_and_clear_bit(txch, rtwpci->kick_map)) 1381 continue; 1382 1383 tx_ring = &rtwpci->tx.rings[txch]; 1384 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 1385 } 1386 } 1387 1388 static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) 1389 { 1390 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1391 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx.rings[txch]; 1392 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1393 u32 cur_idx, cur_rp; 1394 u8 i; 1395 1396 /* Because the time taked by the I/O is a bit dynamic, it's hard to 1397 * define a reasonable fixed total timeout to use read_poll_timeout* 1398 * helper. Instead, we can ensure a reasonable polling times, so we 1399 * just use for loop with udelay here. 1400 */ 1401 for (i = 0; i < 60; i++) { 1402 cur_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); 1403 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 1404 if (cur_rp == bd_ring->wp) 1405 return; 1406 1407 udelay(1); 1408 } 1409 1410 if (!drop) 1411 rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); 1412 } 1413 1414 static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, 1415 bool drop) 1416 { 1417 const struct rtw89_pci_info *info = rtwdev->pci_info; 1418 u8 i; 1419 1420 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1421 /* It may be unnecessary to flush FWCMD queue. */ 1422 if (i == RTW89_TXCH_CH12) 1423 continue; 1424 if (info->tx_dma_ch_mask & BIT(i)) 1425 continue; 1426 1427 if (txchs & BIT(i)) 1428 __pci_flush_txch(rtwdev, i, drop); 1429 } 1430 } 1431 1432 static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 1433 bool drop) 1434 { 1435 __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); 1436 } 1437 1438 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev, 1439 void *txaddr_info_addr, u32 total_len, 1440 dma_addr_t dma, u8 *add_info_nr) 1441 { 1442 struct rtw89_pci_tx_addr_info_32 *txaddr_info = txaddr_info_addr; 1443 __le16 option; 1444 1445 txaddr_info->length = cpu_to_le16(total_len); 1446 option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | RTW89_PCI_ADDR_NUM(1)); 1447 option |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_ADDR_HIGH_MASK); 1448 txaddr_info->option = option; 1449 txaddr_info->dma = cpu_to_le32(dma); 1450 1451 *add_info_nr = 1; 1452 1453 return sizeof(*txaddr_info); 1454 } 1455 EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info); 1456 1457 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev, 1458 void *txaddr_info_addr, u32 total_len, 1459 dma_addr_t dma, u8 *add_info_nr) 1460 { 1461 struct rtw89_pci_tx_addr_info_32_v1 *txaddr_info = txaddr_info_addr; 1462 u32 remain = total_len; 1463 u32 len; 1464 u16 length_option; 1465 int n; 1466 1467 for (n = 0; n < RTW89_TXADDR_INFO_NR_V1 && remain; n++) { 1468 len = remain >= TXADDR_INFO_LENTHG_V1_MAX ? 1469 TXADDR_INFO_LENTHG_V1_MAX : remain; 1470 remain -= len; 1471 1472 length_option = FIELD_PREP(B_PCIADDR_LEN_V1_MASK, len) | 1473 FIELD_PREP(B_PCIADDR_HIGH_SEL_V1_MASK, 0) | 1474 FIELD_PREP(B_PCIADDR_LS_V1_MASK, remain == 0); 1475 length_option |= u16_encode_bits(upper_32_bits(dma), 1476 B_PCIADDR_HIGH_SEL_V1_MASK); 1477 txaddr_info->length_opt = cpu_to_le16(length_option); 1478 txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma)); 1479 txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma)); 1480 1481 dma += len; 1482 txaddr_info++; 1483 } 1484 1485 WARN_ONCE(remain, "length overflow remain=%u total_len=%u", 1486 remain, total_len); 1487 1488 *add_info_nr = n; 1489 1490 return n * sizeof(*txaddr_info); 1491 } 1492 EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info_v1); 1493 1494 static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, 1495 struct rtw89_pci_tx_ring *tx_ring, 1496 struct rtw89_pci_tx_wd *txwd, 1497 struct rtw89_core_tx_request *tx_req) 1498 { 1499 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1500 const struct rtw89_chip_info *chip = rtwdev->chip; 1501 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1502 struct rtw89_pci_tx_wp_info *txwp_info; 1503 void *txaddr_info_addr; 1504 struct pci_dev *pdev = rtwpci->pdev; 1505 struct sk_buff *skb = tx_req->skb; 1506 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 1507 bool en_wd_info = desc_info->en_wd_info; 1508 u32 txwd_len; 1509 u32 txwp_len; 1510 u32 txaddr_info_len; 1511 dma_addr_t dma; 1512 int ret; 1513 1514 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 1515 if (dma_mapping_error(&pdev->dev, dma)) { 1516 rtw89_err(rtwdev, "failed to map skb dma data\n"); 1517 ret = -EBUSY; 1518 goto err; 1519 } 1520 1521 tx_data->dma = dma; 1522 1523 txwp_len = sizeof(*txwp_info); 1524 txwd_len = chip->txwd_body_size; 1525 txwd_len += en_wd_info ? chip->txwd_info_size : 0; 1526 1527 txwp_info = txwd->vaddr + txwd_len; 1528 txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); 1529 txwp_info->seq1 = 0; 1530 txwp_info->seq2 = 0; 1531 txwp_info->seq3 = 0; 1532 1533 tx_ring->tx_cnt++; 1534 txaddr_info_addr = txwd->vaddr + txwd_len + txwp_len; 1535 txaddr_info_len = 1536 rtw89_chip_fill_txaddr_info(rtwdev, txaddr_info_addr, skb->len, 1537 dma, &desc_info->addr_info_nr); 1538 1539 txwd->len = txwd_len + txwp_len + txaddr_info_len; 1540 1541 rtw89_chip_fill_txdesc(rtwdev, desc_info, txwd->vaddr); 1542 1543 skb_queue_tail(&txwd->queue, skb); 1544 1545 return 0; 1546 1547 err: 1548 return ret; 1549 } 1550 1551 static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, 1552 struct rtw89_pci_tx_ring *tx_ring, 1553 struct rtw89_pci_tx_bd_32 *txbd, 1554 struct rtw89_core_tx_request *tx_req) 1555 { 1556 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1557 const struct rtw89_chip_info *chip = rtwdev->chip; 1558 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1559 void *txdesc; 1560 int txdesc_size = chip->h2c_desc_size; 1561 struct pci_dev *pdev = rtwpci->pdev; 1562 struct sk_buff *skb = tx_req->skb; 1563 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 1564 dma_addr_t dma; 1565 __le16 opt; 1566 1567 txdesc = skb_push(skb, txdesc_size); 1568 memset(txdesc, 0, txdesc_size); 1569 rtw89_chip_fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 1570 1571 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 1572 if (dma_mapping_error(&pdev->dev, dma)) { 1573 rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); 1574 return -EBUSY; 1575 } 1576 1577 tx_data->dma = dma; 1578 opt = cpu_to_le16(RTW89_PCI_TXBD_OPT_LS); 1579 opt |= le16_encode_bits(upper_32_bits(dma), RTW89_PCI_TXBD_OPT_DMA_HI); 1580 txbd->opt = opt; 1581 txbd->length = cpu_to_le16(skb->len); 1582 txbd->dma = cpu_to_le32(tx_data->dma); 1583 skb_queue_tail(&rtwpci->h2c_queue, skb); 1584 1585 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1586 1587 return 0; 1588 } 1589 1590 static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, 1591 struct rtw89_pci_tx_ring *tx_ring, 1592 struct rtw89_pci_tx_bd_32 *txbd, 1593 struct rtw89_core_tx_request *tx_req) 1594 { 1595 struct rtw89_pci_tx_wd *txwd; 1596 __le16 opt; 1597 int ret; 1598 1599 /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD 1600 * buffer with WD BODY only. So here we don't need to check the free 1601 * pages of the wd ring. 1602 */ 1603 if (tx_ring->txch == RTW89_TXCH_CH12) 1604 return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); 1605 1606 txwd = rtw89_pci_dequeue_txwd(tx_ring); 1607 if (!txwd) { 1608 rtw89_err(rtwdev, "no available TXWD\n"); 1609 ret = -ENOSPC; 1610 goto err; 1611 } 1612 1613 ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); 1614 if (ret) { 1615 rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); 1616 goto err_enqueue_wd; 1617 } 1618 1619 list_add_tail(&txwd->list, &tx_ring->busy_pages); 1620 1621 opt = cpu_to_le16(RTW89_PCI_TXBD_OPT_LS); 1622 opt |= le16_encode_bits(upper_32_bits(txwd->paddr), RTW89_PCI_TXBD_OPT_DMA_HI); 1623 txbd->opt = opt; 1624 txbd->length = cpu_to_le16(txwd->len); 1625 txbd->dma = cpu_to_le32(txwd->paddr); 1626 1627 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1628 1629 return 0; 1630 1631 err_enqueue_wd: 1632 rtw89_pci_enqueue_txwd(tx_ring, txwd); 1633 err: 1634 return ret; 1635 } 1636 1637 static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, 1638 u8 txch) 1639 { 1640 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1641 struct rtw89_pci_tx_ring *tx_ring; 1642 struct rtw89_pci_tx_bd_32 *txbd; 1643 u32 n_avail_txbd; 1644 int ret = 0; 1645 1646 /* check the tx type and dma channel for fw cmd queue */ 1647 if ((txch == RTW89_TXCH_CH12 || 1648 tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && 1649 (txch != RTW89_TXCH_CH12 || 1650 tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { 1651 rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); 1652 return -EINVAL; 1653 } 1654 1655 tx_ring = &rtwpci->tx.rings[txch]; 1656 spin_lock_bh(&rtwpci->trx_lock); 1657 1658 n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); 1659 if (n_avail_txbd == 0) { 1660 rtw89_err(rtwdev, "no available TXBD\n"); 1661 ret = -ENOSPC; 1662 goto err_unlock; 1663 } 1664 1665 txbd = rtw89_pci_get_next_txbd(tx_ring); 1666 ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); 1667 if (ret) { 1668 rtw89_err(rtwdev, "failed to submit TXBD\n"); 1669 goto err_unlock; 1670 } 1671 1672 spin_unlock_bh(&rtwpci->trx_lock); 1673 return 0; 1674 1675 err_unlock: 1676 spin_unlock_bh(&rtwpci->trx_lock); 1677 return ret; 1678 } 1679 1680 static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) 1681 { 1682 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1683 int ret; 1684 1685 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); 1686 if (ret) { 1687 rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); 1688 return ret; 1689 } 1690 1691 return 0; 1692 } 1693 1694 const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM] = { 1695 [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, 1696 [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, 1697 [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, 1698 [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, 1699 [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, 1700 [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, 1701 [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, 1702 [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, 1703 [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, 1704 [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, 1705 [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, 1706 [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, 1707 [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, 1708 }; 1709 EXPORT_SYMBOL(rtw89_bd_ram_table_dual); 1710 1711 const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM] = { 1712 [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, 1713 [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, 1714 [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, 1715 [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, 1716 [RTW89_TXCH_CH8] = {.start_idx = 20, .max_num = 4, .min_num = 1}, 1717 [RTW89_TXCH_CH9] = {.start_idx = 24, .max_num = 4, .min_num = 1}, 1718 [RTW89_TXCH_CH12] = {.start_idx = 28, .max_num = 4, .min_num = 1}, 1719 }; 1720 EXPORT_SYMBOL(rtw89_bd_ram_table_single); 1721 1722 static void rtw89_pci_init_wp_16sel(struct rtw89_dev *rtwdev) 1723 { 1724 const struct rtw89_pci_info *info = rtwdev->pci_info; 1725 u32 addr = info->wp_sel_addr; 1726 u32 val; 1727 int i; 1728 1729 if (!info->wp_sel_addr) 1730 return; 1731 1732 for (i = 0; i < 16; i += 4) { 1733 val = u32_encode_bits(i + 0, MASKBYTE0) | 1734 u32_encode_bits(i + 1, MASKBYTE1) | 1735 u32_encode_bits(i + 2, MASKBYTE2) | 1736 u32_encode_bits(i + 3, MASKBYTE3); 1737 rtw89_write32(rtwdev, addr + i, val); 1738 } 1739 } 1740 1741 static u16 rtw89_pci_enc_bd_cfg(struct rtw89_dev *rtwdev, u16 bd_num, 1742 u32 dma_offset) 1743 { 1744 u16 dma_offset_sel; 1745 u16 num_sel; 1746 1747 /* B_BE_TX_NUM_SEL_MASK, B_BE_RX_NUM_SEL_MASK: 1748 * 0 -> 0 1749 * 1 -> 64 = 2^6 1750 * 2 -> 128 = 2^7 1751 * ... 1752 * 7 -> 4096 = 2^12 1753 */ 1754 num_sel = ilog2(bd_num) - 5; 1755 1756 if (hweight16(bd_num) != 1) 1757 rtw89_warn(rtwdev, "bd_num %u is not power of 2\n", bd_num); 1758 1759 /* B_BE_TX_START_OFFSET_MASK, B_BE_RX_START_OFFSET_MASK: 1760 * 0 -> 0 = 0 * 2^9 1761 * 1 -> 512 = 1 * 2^9 1762 * 2 -> 1024 = 2 * 2^9 1763 * 3 -> 1536 = 3 * 2^9 1764 * ... 1765 * 255 -> 130560 = 255 * 2^9 1766 */ 1767 dma_offset_sel = dma_offset >> 9; 1768 1769 if (dma_offset % 512) 1770 rtw89_warn(rtwdev, "offset %u is not multiple of 512\n", dma_offset); 1771 1772 return u16_encode_bits(num_sel, B_BE_TX_NUM_SEL_MASK) | 1773 u16_encode_bits(dma_offset_sel, B_BE_TX_START_OFFSET_MASK); 1774 } 1775 1776 static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) 1777 { 1778 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1779 const struct rtw89_pci_info *info = rtwdev->pci_info; 1780 const struct rtw89_pci_bd_ram *bd_ram_table = *info->bd_ram_table; 1781 struct rtw89_pci_tx_ring *tx_ring; 1782 struct rtw89_pci_rx_ring *rx_ring; 1783 struct rtw89_pci_dma_ring *bd_ring; 1784 const struct rtw89_pci_bd_ram *bd_ram; 1785 dma_addr_t group_dma_base = 0; 1786 u16 num_or_offset; 1787 u32 addr_desa_l; 1788 u32 addr_bdram; 1789 u32 addr_num; 1790 u32 addr_idx; 1791 u32 val32; 1792 int i; 1793 1794 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1795 if (info->tx_dma_ch_mask & BIT(i)) 1796 continue; 1797 1798 tx_ring = &rtwpci->tx.rings[i]; 1799 bd_ring = &tx_ring->bd_ring; 1800 bd_ram = bd_ram_table ? &bd_ram_table[i] : NULL; 1801 addr_num = bd_ring->addr.num; 1802 addr_bdram = bd_ring->addr.bdram; 1803 addr_desa_l = bd_ring->addr.desa_l; 1804 bd_ring->wp = 0; 1805 bd_ring->rp = 0; 1806 1807 if (info->group_bd_addr) { 1808 if (addr_desa_l) 1809 group_dma_base = bd_ring->dma; 1810 1811 num_or_offset = 1812 rtw89_pci_enc_bd_cfg(rtwdev, bd_ring->len, 1813 bd_ring->dma - group_dma_base); 1814 } else { 1815 num_or_offset = bd_ring->len; 1816 } 1817 rtw89_write16(rtwdev, addr_num, num_or_offset); 1818 1819 if (addr_bdram && bd_ram) { 1820 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | 1821 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | 1822 FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); 1823 1824 rtw89_write32(rtwdev, addr_bdram, val32); 1825 } 1826 if (addr_desa_l) { 1827 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1828 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1829 } 1830 } 1831 1832 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1833 rx_ring = &rtwpci->rx.rings[i]; 1834 bd_ring = &rx_ring->bd_ring; 1835 addr_num = bd_ring->addr.num; 1836 addr_idx = bd_ring->addr.idx; 1837 addr_desa_l = bd_ring->addr.desa_l; 1838 if (info->rx_ring_eq_is_full) 1839 bd_ring->wp = bd_ring->len - 1; 1840 else 1841 bd_ring->wp = 0; 1842 bd_ring->rp = 0; 1843 rx_ring->deliver_skb = NULL; 1844 rx_ring->deliver_desc.ready = false; 1845 rx_ring->target_rx_tag = 0; 1846 1847 if (info->group_bd_addr) { 1848 if (addr_desa_l) 1849 group_dma_base = bd_ring->dma; 1850 1851 num_or_offset = 1852 rtw89_pci_enc_bd_cfg(rtwdev, bd_ring->len, 1853 bd_ring->dma - group_dma_base); 1854 } else { 1855 num_or_offset = bd_ring->len; 1856 } 1857 rtw89_write16(rtwdev, addr_num, num_or_offset); 1858 1859 if (addr_desa_l) { 1860 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1861 rtw89_write32(rtwdev, addr_desa_l + 4, upper_32_bits(bd_ring->dma)); 1862 } 1863 1864 if (info->rx_ring_eq_is_full) 1865 rtw89_write16(rtwdev, addr_idx, bd_ring->wp); 1866 } 1867 1868 rtw89_pci_init_wp_16sel(rtwdev); 1869 } 1870 1871 static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, 1872 struct rtw89_pci_tx_ring *tx_ring) 1873 { 1874 rtw89_pci_release_busy_txwd(rtwdev, tx_ring); 1875 rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); 1876 } 1877 1878 void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) 1879 { 1880 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1881 const struct rtw89_pci_info *info = rtwdev->pci_info; 1882 int txch; 1883 1884 rtw89_pci_reset_trx_rings(rtwdev); 1885 1886 spin_lock_bh(&rtwpci->trx_lock); 1887 for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { 1888 if (info->tx_dma_ch_mask & BIT(txch)) 1889 continue; 1890 if (txch == RTW89_TXCH_CH12) { 1891 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 1892 skb_queue_len(&rtwpci->h2c_queue), true); 1893 continue; 1894 } 1895 rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx.rings[txch]); 1896 } 1897 spin_unlock_bh(&rtwpci->trx_lock); 1898 } 1899 1900 static void rtw89_pci_enable_intr_lock(struct rtw89_dev *rtwdev) 1901 { 1902 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1903 unsigned long flags; 1904 1905 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1906 rtwpci->running = true; 1907 rtw89_chip_enable_intr(rtwdev, rtwpci); 1908 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1909 } 1910 1911 static void rtw89_pci_disable_intr_lock(struct rtw89_dev *rtwdev) 1912 { 1913 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1914 unsigned long flags; 1915 1916 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1917 rtwpci->running = false; 1918 rtw89_chip_disable_intr(rtwdev, rtwpci); 1919 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1920 } 1921 1922 static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) 1923 { 1924 rtw89_core_napi_start(rtwdev); 1925 rtw89_pci_enable_intr_lock(rtwdev); 1926 1927 return 0; 1928 } 1929 1930 static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) 1931 { 1932 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1933 struct pci_dev *pdev = rtwpci->pdev; 1934 1935 rtw89_pci_disable_intr_lock(rtwdev); 1936 synchronize_irq(pdev->irq); 1937 rtw89_core_napi_stop(rtwdev); 1938 } 1939 1940 static void rtw89_pci_ops_pause(struct rtw89_dev *rtwdev, bool pause) 1941 { 1942 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1943 struct pci_dev *pdev = rtwpci->pdev; 1944 1945 if (pause) { 1946 rtw89_pci_disable_intr_lock(rtwdev); 1947 synchronize_irq(pdev->irq); 1948 if (test_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1949 napi_synchronize(&rtwdev->napi); 1950 } else { 1951 rtw89_pci_enable_intr_lock(rtwdev); 1952 rtw89_pci_tx_kick_off_pending(rtwdev); 1953 } 1954 } 1955 1956 static 1957 void rtw89_pci_switch_bd_idx_addr(struct rtw89_dev *rtwdev, bool low_power) 1958 { 1959 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1960 const struct rtw89_pci_info *info = rtwdev->pci_info; 1961 const struct rtw89_pci_bd_idx_addr *bd_idx_addr = info->bd_idx_addr_low_power; 1962 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set = info->dma_addr_set; 1963 struct rtw89_pci_tx_ring *tx_ring; 1964 struct rtw89_pci_rx_ring *rx_ring; 1965 int i; 1966 1967 if (WARN(!bd_idx_addr, "only HCI with low power mode needs this\n")) 1968 return; 1969 1970 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1971 tx_ring = &rtwpci->tx.rings[i]; 1972 tx_ring->bd_ring.addr.idx = low_power ? 1973 bd_idx_addr->tx_bd_addrs[i] : 1974 dma_addr_set->tx[i].idx; 1975 } 1976 1977 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1978 rx_ring = &rtwpci->rx.rings[i]; 1979 rx_ring->bd_ring.addr.idx = low_power ? 1980 bd_idx_addr->rx_bd_addrs[i] : 1981 dma_addr_set->rx[i].idx; 1982 } 1983 } 1984 1985 static void rtw89_pci_ops_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 1986 { 1987 enum rtw89_pci_intr_mask_cfg cfg; 1988 1989 WARN(!rtwdev->hci.paused, "HCI isn't paused\n"); 1990 1991 cfg = low_power ? RTW89_PCI_INTR_MASK_LOW_POWER : RTW89_PCI_INTR_MASK_NORMAL; 1992 rtw89_chip_config_intr_mask(rtwdev, cfg); 1993 rtw89_pci_switch_bd_idx_addr(rtwdev, low_power); 1994 } 1995 1996 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); 1997 1998 static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) 1999 { 2000 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2001 u32 val = readl(rtwpci->mmap + addr); 2002 int count; 2003 2004 for (count = 0; ; count++) { 2005 if (val != RTW89_R32_DEAD) 2006 return val; 2007 if (count >= MAC_REG_POOL_COUNT) { 2008 rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); 2009 return RTW89_R32_DEAD; 2010 } 2011 rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); 2012 val = readl(rtwpci->mmap + addr); 2013 } 2014 2015 return val; 2016 } 2017 2018 static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) 2019 { 2020 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2021 u32 addr32, val32, shift; 2022 2023 if (!ACCESS_CMAC(addr)) 2024 return readb(rtwpci->mmap + addr); 2025 2026 addr32 = addr & ~0x3; 2027 shift = (addr & 0x3) * 8; 2028 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 2029 return val32 >> shift; 2030 } 2031 2032 static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) 2033 { 2034 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2035 u32 addr32, val32, shift; 2036 2037 if (!ACCESS_CMAC(addr)) 2038 return readw(rtwpci->mmap + addr); 2039 2040 addr32 = addr & ~0x3; 2041 shift = (addr & 0x3) * 8; 2042 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 2043 return val32 >> shift; 2044 } 2045 2046 static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) 2047 { 2048 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2049 2050 if (!ACCESS_CMAC(addr)) 2051 return readl(rtwpci->mmap + addr); 2052 2053 return rtw89_pci_ops_read32_cmac(rtwdev, addr); 2054 } 2055 2056 static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 2057 { 2058 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2059 2060 writeb(data, rtwpci->mmap + addr); 2061 } 2062 2063 static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 2064 { 2065 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2066 2067 writew(data, rtwpci->mmap + addr); 2068 } 2069 2070 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 2071 { 2072 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2073 2074 writel(data, rtwpci->mmap + addr); 2075 } 2076 2077 static u32 rtw89_pci_ops_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 2078 { 2079 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2080 struct pci_dev *pdev = rtwpci->pdev; 2081 u32 value; 2082 int ret; 2083 2084 ret = pci_read_config_dword(pdev, addr, &value); 2085 if (ret) 2086 return RTW89_R32_EA; 2087 2088 return value; 2089 } 2090 2091 static void rtw89_pci_ctrl_dma_trx(struct rtw89_dev *rtwdev, bool enable) 2092 { 2093 const struct rtw89_pci_info *info = rtwdev->pci_info; 2094 2095 if (enable) 2096 rtw89_write32_set(rtwdev, info->init_cfg_reg, 2097 info->rxhci_en_bit | info->txhci_en_bit); 2098 else 2099 rtw89_write32_clr(rtwdev, info->init_cfg_reg, 2100 info->rxhci_en_bit | info->txhci_en_bit); 2101 } 2102 2103 static void rtw89_pci_ctrl_dma_io(struct rtw89_dev *rtwdev, bool enable) 2104 { 2105 const struct rtw89_pci_info *info = rtwdev->pci_info; 2106 const struct rtw89_reg_def *reg = &info->dma_io_stop; 2107 2108 if (enable) 2109 rtw89_write32_clr(rtwdev, reg->addr, reg->mask); 2110 else 2111 rtw89_write32_set(rtwdev, reg->addr, reg->mask); 2112 } 2113 2114 void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) 2115 { 2116 rtw89_pci_ctrl_dma_io(rtwdev, enable); 2117 rtw89_pci_ctrl_dma_trx(rtwdev, enable); 2118 } 2119 2120 static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) 2121 { 2122 u16 val; 2123 2124 rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); 2125 2126 val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); 2127 switch (speed) { 2128 case PCIE_PHY_GEN1: 2129 if (addr < 0x20) 2130 val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); 2131 else 2132 val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); 2133 break; 2134 case PCIE_PHY_GEN2: 2135 if (addr < 0x20) 2136 val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); 2137 else 2138 val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); 2139 break; 2140 default: 2141 rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); 2142 return -EINVAL; 2143 } 2144 rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); 2145 rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); 2146 2147 return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, 2148 false, rtwdev, R_AX_MDIO_CFG); 2149 } 2150 2151 static int 2152 rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) 2153 { 2154 int ret; 2155 2156 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); 2157 if (ret) { 2158 rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); 2159 return ret; 2160 } 2161 *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); 2162 2163 return 0; 2164 } 2165 2166 static int 2167 rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) 2168 { 2169 int ret; 2170 2171 rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); 2172 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); 2173 if (ret) { 2174 rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); 2175 return ret; 2176 } 2177 2178 return 0; 2179 } 2180 2181 static int 2182 rtw89_write16_mdio_mask(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u16 data, u8 speed) 2183 { 2184 u32 shift; 2185 int ret; 2186 u16 val; 2187 2188 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 2189 if (ret) 2190 return ret; 2191 2192 shift = __ffs(mask); 2193 val &= ~mask; 2194 val |= ((data << shift) & mask); 2195 2196 ret = rtw89_write16_mdio(rtwdev, addr, val, speed); 2197 if (ret) 2198 return ret; 2199 2200 return 0; 2201 } 2202 2203 static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 2204 { 2205 int ret; 2206 u16 val; 2207 2208 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 2209 if (ret) 2210 return ret; 2211 ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); 2212 if (ret) 2213 return ret; 2214 2215 return 0; 2216 } 2217 2218 static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 2219 { 2220 int ret; 2221 u16 val; 2222 2223 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 2224 if (ret) 2225 return ret; 2226 ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); 2227 if (ret) 2228 return ret; 2229 2230 return 0; 2231 } 2232 2233 static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data) 2234 { 2235 u16 addr_2lsb = addr & B_AX_DBI_2LSB; 2236 u16 write_addr; 2237 u8 flag; 2238 int ret; 2239 2240 write_addr = addr & B_AX_DBI_ADDR_MSK; 2241 write_addr |= u16_encode_bits(BIT(addr_2lsb), B_AX_DBI_WREN_MSK); 2242 rtw89_write8(rtwdev, R_AX_DBI_WDATA + addr_2lsb, data); 2243 rtw89_write16(rtwdev, R_AX_DBI_FLAG, write_addr); 2244 rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16); 2245 2246 ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, 2247 10 * RTW89_PCI_WR_RETRY_CNT, false, 2248 rtwdev, R_AX_DBI_FLAG + 2); 2249 if (ret) 2250 rtw89_err(rtwdev, "failed to write DBI register, addr=0x%X\n", 2251 addr); 2252 2253 return ret; 2254 } 2255 2256 static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value) 2257 { 2258 u16 read_addr = addr & B_AX_DBI_ADDR_MSK; 2259 u8 flag; 2260 int ret; 2261 2262 rtw89_write16(rtwdev, R_AX_DBI_FLAG, read_addr); 2263 rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16); 2264 2265 ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, 2266 10 * RTW89_PCI_WR_RETRY_CNT, false, 2267 rtwdev, R_AX_DBI_FLAG + 2); 2268 if (ret) { 2269 rtw89_err(rtwdev, "failed to read DBI register, addr=0x%X\n", 2270 addr); 2271 return ret; 2272 } 2273 2274 read_addr = R_AX_DBI_RDATA + (addr & 3); 2275 *value = rtw89_read8(rtwdev, read_addr); 2276 2277 return 0; 2278 } 2279 2280 static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr, 2281 u8 data) 2282 { 2283 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2284 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2285 struct pci_dev *pdev = rtwpci->pdev; 2286 int ret; 2287 2288 ret = pci_write_config_byte(pdev, addr, data); 2289 if (!ret) 2290 return 0; 2291 2292 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2293 ret = rtw89_dbi_write8(rtwdev, addr, data); 2294 2295 return ret; 2296 } 2297 2298 static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr, 2299 u8 *value) 2300 { 2301 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2302 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2303 struct pci_dev *pdev = rtwpci->pdev; 2304 int ret; 2305 2306 ret = pci_read_config_byte(pdev, addr, value); 2307 if (!ret) 2308 return 0; 2309 2310 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2311 ret = rtw89_dbi_read8(rtwdev, addr, value); 2312 2313 return ret; 2314 } 2315 2316 static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr, 2317 u8 bit) 2318 { 2319 u8 value; 2320 int ret; 2321 2322 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 2323 if (ret) 2324 return ret; 2325 2326 value |= bit; 2327 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 2328 2329 return ret; 2330 } 2331 2332 static int rtw89_pci_config_byte_clr(struct rtw89_dev *rtwdev, u16 addr, 2333 u8 bit) 2334 { 2335 u8 value; 2336 int ret; 2337 2338 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 2339 if (ret) 2340 return ret; 2341 2342 value &= ~bit; 2343 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 2344 2345 return ret; 2346 } 2347 2348 static int 2349 __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) 2350 { 2351 u16 val, tar; 2352 int ret; 2353 2354 /* Enable counter */ 2355 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); 2356 if (ret) 2357 return ret; 2358 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 2359 phy_rate); 2360 if (ret) 2361 return ret; 2362 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, 2363 phy_rate); 2364 if (ret) 2365 return ret; 2366 2367 fsleep(300); 2368 2369 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); 2370 if (ret) 2371 return ret; 2372 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 2373 phy_rate); 2374 if (ret) 2375 return ret; 2376 2377 tar = tar & 0x0FFF; 2378 if (tar == 0 || tar == 0x0FFF) { 2379 rtw89_err(rtwdev, "[ERR]Get target failed.\n"); 2380 return -EINVAL; 2381 } 2382 2383 *target = tar; 2384 2385 return 0; 2386 } 2387 2388 static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev) 2389 { 2390 int ret; 2391 2392 if (!rtw89_is_rtl885xb(rtwdev)) 2393 return 0; 2394 2395 ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK, 2396 PCIE_AUTOK_4, PCIE_PHY_GEN1); 2397 return ret; 2398 } 2399 2400 static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) 2401 { 2402 enum rtw89_pcie_phy phy_rate; 2403 u16 val16, mgn_set, div_set, tar; 2404 u8 val8, bdr_ori; 2405 bool l1_flag = false; 2406 int ret = 0; 2407 2408 if (!rtw89_is_rtl885xb(rtwdev)) 2409 return 0; 2410 2411 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8); 2412 if (ret) { 2413 rtw89_err(rtwdev, "[ERR]pci config read %X\n", 2414 RTW89_PCIE_PHY_RATE); 2415 return ret; 2416 } 2417 2418 if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { 2419 phy_rate = PCIE_PHY_GEN1; 2420 } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { 2421 phy_rate = PCIE_PHY_GEN2; 2422 } else { 2423 rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); 2424 return -EOPNOTSUPP; 2425 } 2426 /* Disable L1BD */ 2427 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); 2428 if (ret) { 2429 rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_L1_CTRL); 2430 return ret; 2431 } 2432 2433 if (bdr_ori & RTW89_PCIE_BIT_L1) { 2434 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 2435 bdr_ori & ~RTW89_PCIE_BIT_L1); 2436 if (ret) { 2437 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 2438 RTW89_PCIE_L1_CTRL); 2439 return ret; 2440 } 2441 l1_flag = true; 2442 } 2443 2444 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 2445 if (ret) { 2446 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 2447 goto end; 2448 } 2449 2450 if (val16 & B_AX_CALIB_EN) { 2451 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, 2452 val16 & ~B_AX_CALIB_EN, phy_rate); 2453 if (ret) { 2454 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2455 goto end; 2456 } 2457 } 2458 2459 if (!autook_en) 2460 goto end; 2461 /* Set div */ 2462 ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); 2463 if (ret) { 2464 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2465 goto end; 2466 } 2467 2468 /* Obtain div and margin */ 2469 ret = __get_target(rtwdev, &tar, phy_rate); 2470 if (ret) { 2471 rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); 2472 goto end; 2473 } 2474 2475 mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; 2476 2477 if (mgn_set >= 128) { 2478 div_set = 0x0003; 2479 mgn_set = 0x000F; 2480 } else if (mgn_set >= 64) { 2481 div_set = 0x0003; 2482 mgn_set >>= 3; 2483 } else if (mgn_set >= 32) { 2484 div_set = 0x0002; 2485 mgn_set >>= 2; 2486 } else if (mgn_set >= 16) { 2487 div_set = 0x0001; 2488 mgn_set >>= 1; 2489 } else if (mgn_set == 0) { 2490 rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); 2491 goto end; 2492 } else { 2493 div_set = 0x0000; 2494 } 2495 2496 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 2497 if (ret) { 2498 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 2499 goto end; 2500 } 2501 2502 val16 |= u16_encode_bits(div_set, B_AX_DIV); 2503 2504 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); 2505 if (ret) { 2506 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2507 goto end; 2508 } 2509 2510 ret = __get_target(rtwdev, &tar, phy_rate); 2511 if (ret) { 2512 rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); 2513 goto end; 2514 } 2515 2516 rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", 2517 tar, div_set, mgn_set); 2518 ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, 2519 (tar & 0x0FFF) | (mgn_set << 12), phy_rate); 2520 if (ret) { 2521 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); 2522 goto end; 2523 } 2524 2525 /* Enable function */ 2526 ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); 2527 if (ret) { 2528 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2529 goto end; 2530 } 2531 2532 /* CLK delay = 0 */ 2533 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 2534 PCIE_CLKDLY_HW_0); 2535 2536 end: 2537 /* Set L1BD to ori */ 2538 if (l1_flag) { 2539 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 2540 bdr_ori); 2541 if (ret) { 2542 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 2543 RTW89_PCIE_L1_CTRL); 2544 return ret; 2545 } 2546 } 2547 2548 return ret; 2549 } 2550 2551 static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) 2552 { 2553 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2554 int ret; 2555 2556 if (chip_id == RTL8852A) { 2557 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 2558 PCIE_PHY_GEN1); 2559 if (ret) 2560 return ret; 2561 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 2562 PCIE_PHY_GEN2); 2563 if (ret) 2564 return ret; 2565 } else if (chip_id == RTL8852C) { 2566 rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA24 * 2, 2567 B_AX_DEGLITCH); 2568 rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA24 * 2, 2569 B_AX_DEGLITCH); 2570 } 2571 2572 return 0; 2573 } 2574 2575 static void rtw89_pci_disable_eq_ax(struct rtw89_dev *rtwdev) 2576 { 2577 u16 g1_oobs, g2_oobs; 2578 u32 backup_aspm; 2579 u32 phy_offset; 2580 u16 offset_cal; 2581 u16 oobs_val; 2582 int ret; 2583 u8 gen; 2584 2585 if (rtwdev->chip->chip_id != RTL8852C) 2586 return; 2587 2588 g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 + 2589 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL); 2590 g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G2 + 2591 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL); 2592 if (g1_oobs && g2_oobs) 2593 return; 2594 2595 backup_aspm = rtw89_read32(rtwdev, R_AX_PCIE_MIX_CFG_V1); 2596 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK); 2597 2598 ret = rtw89_pci_get_phy_offset_by_link_speed(rtwdev, &phy_offset); 2599 if (ret) 2600 goto out; 2601 2602 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, BAC_RX_TEST_EN); 2603 rtw89_write16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, ADDR_SEL_PINOUT_DIS_VAL); 2604 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, B_PCIE_BIT_RD_SEL); 2605 2606 oobs_val = rtw89_read16_mask(rtwdev, phy_offset + RAC_ANA1F * RAC_MULT, 2607 OOBS_LEVEL_MASK); 2608 2609 rtw89_write16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA03 * RAC_MULT, 2610 OOBS_SEN_MASK, oobs_val); 2611 rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA09 * RAC_MULT, 2612 BAC_OOBS_SEL); 2613 2614 rtw89_write16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA03 * RAC_MULT, 2615 OOBS_SEN_MASK, oobs_val); 2616 rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA09 * RAC_MULT, 2617 BAC_OOBS_SEL); 2618 2619 /* offset K */ 2620 for (gen = 1; gen <= 2; gen++) { 2621 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 : 2622 R_RAC_DIRECT_OFFSET_G2; 2623 2624 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, 2625 B_PCIE_BIT_RD_SEL); 2626 } 2627 2628 offset_cal = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 + 2629 RAC_ANA1F * RAC_MULT, OFFSET_CAL_MASK); 2630 2631 for (gen = 1; gen <= 2; gen++) { 2632 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_G1 : 2633 R_RAC_DIRECT_OFFSET_G2; 2634 2635 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT, 2636 MANUAL_LVL_MASK, offset_cal); 2637 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, 2638 OFFSET_CAL_MODE); 2639 } 2640 2641 out: 2642 rtw89_write32(rtwdev, R_AX_PCIE_MIX_CFG_V1, backup_aspm); 2643 } 2644 2645 static void rtw89_pci_ber(struct rtw89_dev *rtwdev) 2646 { 2647 u32 phy_offset; 2648 2649 if (!test_bit(RTW89_QUIRK_PCI_BER, rtwdev->quirks)) 2650 return; 2651 2652 phy_offset = R_RAC_DIRECT_OFFSET_G1; 2653 rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G1_VAL); 2654 rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL); 2655 2656 phy_offset = R_RAC_DIRECT_OFFSET_G2; 2657 rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G2_VAL); 2658 rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL); 2659 } 2660 2661 static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) 2662 { 2663 if (rtwdev->chip->chip_id != RTL8852A) 2664 return; 2665 2666 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); 2667 } 2668 2669 static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) 2670 { 2671 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2672 2673 if (chip_id != RTL8852A && !rtw89_is_rtl885xb(rtwdev)) 2674 return; 2675 2676 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); 2677 } 2678 2679 static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) 2680 { 2681 int ret; 2682 2683 if (rtwdev->chip->chip_id != RTL8852A) 2684 return 0; 2685 2686 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 2687 PCIE_PHY_GEN1); 2688 if (ret) 2689 return ret; 2690 2691 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 2692 PCIE_PHY_GEN2); 2693 if (ret) 2694 return ret; 2695 2696 return 0; 2697 } 2698 2699 static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) 2700 { 2701 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2702 2703 if (chip_id != RTL8852A && !rtw89_is_rtl885xb(rtwdev)) 2704 return; 2705 2706 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); 2707 } 2708 2709 static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) 2710 { 2711 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2712 2713 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2714 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 2715 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2716 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 2717 B_AX_PCIE_DIS_WLSUS_AFT_PDN); 2718 } else if (rtwdev->chip->chip_id == RTL8852C) { 2719 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 2720 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2721 } 2722 } 2723 2724 static int rtw89_pci_dphy_delay(struct rtw89_dev *rtwdev) 2725 { 2726 if (!rtw89_is_rtl885xb(rtwdev)) 2727 return 0; 2728 2729 return rtw89_write16_mdio_mask(rtwdev, RAC_REG_REV2, BAC_CMU_EN_DLY_MASK, 2730 PCIE_DPHY_DLY_25US, PCIE_PHY_GEN1); 2731 } 2732 2733 static void rtw89_pci_power_wake_ax(struct rtw89_dev *rtwdev, bool pwr_up) 2734 { 2735 if (pwr_up) 2736 rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); 2737 else 2738 rtw89_write32_clr(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); 2739 } 2740 2741 static void rtw89_pci_autoload_hang(struct rtw89_dev *rtwdev) 2742 { 2743 if (rtwdev->chip->chip_id != RTL8852C) 2744 return; 2745 2746 rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); 2747 rtw89_write32_clr(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); 2748 } 2749 2750 static void rtw89_pci_l12_vmain(struct rtw89_dev *rtwdev) 2751 { 2752 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) 2753 return; 2754 2755 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT); 2756 } 2757 2758 static void rtw89_pci_gen2_force_ib(struct rtw89_dev *rtwdev) 2759 { 2760 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) 2761 return; 2762 2763 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, 2764 B_AX_SYSON_DIS_PMCR_AX_WRMSK); 2765 rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3); 2766 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, 2767 B_AX_SYSON_DIS_PMCR_AX_WRMSK); 2768 } 2769 2770 static void rtw89_pci_l1_ent_lat(struct rtw89_dev *rtwdev) 2771 { 2772 if (rtwdev->chip->chip_id != RTL8852C) 2773 return; 2774 2775 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1); 2776 } 2777 2778 static void rtw89_pci_wd_exit_l1(struct rtw89_dev *rtwdev) 2779 { 2780 if (rtwdev->chip->chip_id != RTL8852C) 2781 return; 2782 2783 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN); 2784 } 2785 2786 static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) 2787 { 2788 if (rtwdev->chip->chip_id == RTL8852C) 2789 return; 2790 2791 rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, 2792 B_AX_SIC_EN_FORCE_CLKREQ); 2793 } 2794 2795 static void rtw89_pci_set_lbc(struct rtw89_dev *rtwdev) 2796 { 2797 const struct rtw89_pci_info *info = rtwdev->pci_info; 2798 u32 lbc; 2799 2800 if (rtwdev->chip->chip_id == RTL8852C) 2801 return; 2802 2803 lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); 2804 if (info->lbc_en == MAC_AX_PCIE_ENABLE) { 2805 lbc = u32_replace_bits(lbc, info->lbc_tmr, B_AX_LBC_TIMER); 2806 lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; 2807 rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); 2808 } else { 2809 lbc &= ~B_AX_LBC_EN; 2810 } 2811 rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc); 2812 } 2813 2814 static void rtw89_pci_set_io_rcy(struct rtw89_dev *rtwdev) 2815 { 2816 const struct rtw89_pci_info *info = rtwdev->pci_info; 2817 u32 val32; 2818 2819 if (rtwdev->chip->chip_id != RTL8852C) 2820 return; 2821 2822 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) { 2823 val32 = FIELD_PREP(B_AX_PCIE_WDT_TIMER_M1_MASK, 2824 info->io_rcy_tmr); 2825 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M1, val32); 2826 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M2, val32); 2827 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_E0, val32); 2828 2829 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); 2830 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); 2831 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); 2832 } else { 2833 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); 2834 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); 2835 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); 2836 } 2837 2838 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_S1, B_AX_PCIE_IO_RCY_WDT_MODE_S1); 2839 } 2840 2841 static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) 2842 { 2843 if (rtwdev->chip->chip_id == RTL8852C) 2844 return; 2845 2846 rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, 2847 B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); 2848 2849 rtw89_write32_mask(rtwdev, R_AX_PCIE_EXP_CTRL, 2850 B_AX_EN_STUCK_DBG | B_AX_ASFF_FULL_NO_STK, 2851 B_AX_EN_STUCK_DBG); 2852 2853 if (rtwdev->chip->chip_id == RTL8852A) 2854 rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, 2855 B_AX_EN_CHKDSC_NO_RX_STUCK); 2856 } 2857 2858 static void rtw89_pci_set_keep_reg(struct rtw89_dev *rtwdev) 2859 { 2860 if (rtwdev->chip->chip_id == RTL8852C) 2861 return; 2862 2863 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 2864 B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); 2865 } 2866 2867 static void rtw89_pci_clr_idx_all_ax(struct rtw89_dev *rtwdev) 2868 { 2869 const struct rtw89_pci_info *info = rtwdev->pci_info; 2870 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2871 u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | 2872 B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | 2873 B_AX_CLR_CH12_IDX; 2874 u32 rxbd_rwptr_clr = info->rxbd_rwptr_clr_reg; 2875 u32 txbd_rwptr_clr2 = info->txbd_rwptr_clr2_reg; 2876 2877 if (chip_id == RTL8852A || chip_id == RTL8852C) 2878 val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | 2879 B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; 2880 /* clear DMA indexes */ 2881 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); 2882 if (chip_id == RTL8852A || chip_id == RTL8852C) 2883 rtw89_write32_set(rtwdev, txbd_rwptr_clr2, 2884 B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); 2885 rtw89_write32_set(rtwdev, rxbd_rwptr_clr, 2886 B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); 2887 } 2888 2889 static int rtw89_pci_poll_txdma_ch_idle_ax(struct rtw89_dev *rtwdev) 2890 { 2891 const struct rtw89_pci_info *info = rtwdev->pci_info; 2892 u32 dma_busy1 = info->dma_busy1.addr; 2893 u32 dma_busy2 = info->dma_busy2_reg; 2894 u32 check, dma_busy; 2895 int ret; 2896 2897 check = info->dma_busy1.mask; 2898 2899 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2900 10, 100, false, rtwdev, dma_busy1); 2901 if (ret) 2902 return ret; 2903 2904 if (!dma_busy2) 2905 return 0; 2906 2907 check = B_AX_CH10_BUSY | B_AX_CH11_BUSY; 2908 2909 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2910 10, 100, false, rtwdev, dma_busy2); 2911 if (ret) 2912 return ret; 2913 2914 return 0; 2915 } 2916 2917 static int rtw89_pci_poll_rxdma_ch_idle_ax(struct rtw89_dev *rtwdev) 2918 { 2919 const struct rtw89_pci_info *info = rtwdev->pci_info; 2920 u32 dma_busy3 = info->dma_busy3_reg; 2921 u32 check, dma_busy; 2922 int ret; 2923 2924 check = B_AX_RXQ_BUSY | B_AX_RPQ_BUSY; 2925 2926 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2927 10, 100, false, rtwdev, dma_busy3); 2928 if (ret) 2929 return ret; 2930 2931 return 0; 2932 } 2933 2934 static int rtw89_pci_poll_dma_all_idle(struct rtw89_dev *rtwdev) 2935 { 2936 int ret; 2937 2938 ret = rtw89_pci_poll_txdma_ch_idle_ax(rtwdev); 2939 if (ret) { 2940 rtw89_err(rtwdev, "txdma ch busy\n"); 2941 return ret; 2942 } 2943 2944 ret = rtw89_pci_poll_rxdma_ch_idle_ax(rtwdev); 2945 if (ret) { 2946 rtw89_err(rtwdev, "rxdma ch busy\n"); 2947 return ret; 2948 } 2949 2950 return 0; 2951 } 2952 2953 static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev) 2954 { 2955 const struct rtw89_pci_info *info = rtwdev->pci_info; 2956 enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode; 2957 enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode; 2958 enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode; 2959 enum mac_ax_tag_mode tag_mode = info->tag_mode; 2960 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl; 2961 enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl; 2962 enum mac_ax_tx_burst tx_burst = info->tx_burst; 2963 enum mac_ax_rx_burst rx_burst = info->rx_burst; 2964 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2965 u8 cv = rtwdev->hal.cv; 2966 u32 val32; 2967 2968 if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { 2969 if (chip_id == RTL8852A && cv == CHIP_CBV) 2970 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); 2971 } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { 2972 if (chip_id == RTL8852A || chip_id == RTL8852B) 2973 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); 2974 } 2975 2976 if (rxbd_trunc_mode == MAC_AX_BD_TRUNC) { 2977 if (chip_id == RTL8852A && cv == CHIP_CBV) 2978 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); 2979 } else if (rxbd_trunc_mode == MAC_AX_BD_NORM) { 2980 if (chip_id == RTL8852A || chip_id == RTL8852B) 2981 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); 2982 } 2983 2984 if (rxbd_mode == MAC_AX_RXBD_PKT) { 2985 rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); 2986 } else if (rxbd_mode == MAC_AX_RXBD_SEP) { 2987 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); 2988 2989 if (chip_id == RTL8852A || chip_id == RTL8852B) 2990 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, 2991 B_AX_PCIE_RX_APPLEN_MASK, 0); 2992 } 2993 2994 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2995 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst); 2996 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst); 2997 } else if (chip_id == RTL8852C) { 2998 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst); 2999 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst); 3000 } 3001 3002 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 3003 if (tag_mode == MAC_AX_TAG_SGL) { 3004 val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) & 3005 ~B_AX_LATENCY_CONTROL; 3006 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 3007 } else if (tag_mode == MAC_AX_TAG_MULTI) { 3008 val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | 3009 B_AX_LATENCY_CONTROL; 3010 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 3011 } 3012 } 3013 3014 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask, 3015 info->multi_tag_num); 3016 3017 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 3018 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, 3019 wd_dma_idle_intvl); 3020 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, 3021 wd_dma_act_intvl); 3022 } else if (chip_id == RTL8852C) { 3023 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK, 3024 wd_dma_idle_intvl); 3025 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK, 3026 wd_dma_act_intvl); 3027 } 3028 3029 if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { 3030 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 3031 B_AX_HOST_ADDR_INFO_8B_SEL); 3032 rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 3033 } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { 3034 rtw89_write32_clr(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 3035 B_AX_HOST_ADDR_INFO_8B_SEL); 3036 rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 3037 } 3038 3039 return 0; 3040 } 3041 3042 static bool rtw89_pci_dev_ltr_enabled(struct rtw89_dev *rtwdev) 3043 { 3044 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3045 struct pci_dev *pdev = rtwpci->pdev; 3046 u16 cap; 3047 3048 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap); 3049 3050 return !!(cap & PCI_EXP_DEVCTL2_LTR_EN); 3051 } 3052 3053 static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) 3054 { 3055 const struct rtw89_pci_info *info = rtwdev->pci_info; 3056 3057 rtw89_pci_power_wake(rtwdev, false); 3058 3059 if (rtwdev->chip->chip_id == RTL8852A) { 3060 /* ltr sw trigger */ 3061 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); 3062 } 3063 info->ltr_set(rtwdev, false); 3064 rtw89_pci_ctrl_dma_all(rtwdev, false); 3065 rtw89_pci_clr_idx_all(rtwdev); 3066 3067 return 0; 3068 } 3069 3070 static int rtw89_pci_ops_mac_pre_init_ax(struct rtw89_dev *rtwdev) 3071 { 3072 const struct rtw89_pci_info *info = rtwdev->pci_info; 3073 int ret; 3074 3075 rtw89_pci_ber(rtwdev); 3076 rtw89_pci_rxdma_prefth(rtwdev); 3077 rtw89_pci_l1off_pwroff(rtwdev); 3078 rtw89_pci_deglitch_setting(rtwdev); 3079 ret = rtw89_pci_l2_rxen_lat(rtwdev); 3080 if (ret) { 3081 rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); 3082 return ret; 3083 } 3084 3085 rtw89_pci_aphy_pwrcut(rtwdev); 3086 rtw89_pci_hci_ldo(rtwdev); 3087 rtw89_pci_dphy_delay(rtwdev); 3088 3089 ret = rtw89_pci_autok_x(rtwdev); 3090 if (ret) { 3091 rtw89_err(rtwdev, "[ERR] pcie autok_x fail %d\n", ret); 3092 return ret; 3093 } 3094 3095 ret = rtw89_pci_auto_refclk_cal(rtwdev, false); 3096 if (ret) { 3097 rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); 3098 return ret; 3099 } 3100 3101 rtw89_pci_power_wake_ax(rtwdev, true); 3102 rtw89_pci_autoload_hang(rtwdev); 3103 rtw89_pci_l12_vmain(rtwdev); 3104 rtw89_pci_gen2_force_ib(rtwdev); 3105 rtw89_pci_l1_ent_lat(rtwdev); 3106 rtw89_pci_wd_exit_l1(rtwdev); 3107 rtw89_pci_set_sic(rtwdev); 3108 rtw89_pci_set_lbc(rtwdev); 3109 rtw89_pci_set_io_rcy(rtwdev); 3110 rtw89_pci_set_dbg(rtwdev); 3111 rtw89_pci_set_keep_reg(rtwdev); 3112 3113 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA); 3114 3115 /* stop DMA activities */ 3116 rtw89_pci_ctrl_dma_all(rtwdev, false); 3117 3118 ret = rtw89_pci_poll_dma_all_idle(rtwdev); 3119 if (ret) { 3120 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n"); 3121 return ret; 3122 } 3123 3124 rtw89_pci_clr_idx_all(rtwdev); 3125 rtw89_pci_mode_op(rtwdev); 3126 3127 /* fill TRX BD indexes */ 3128 rtw89_pci_ops_reset(rtwdev); 3129 3130 ret = rtw89_pci_rst_bdram_ax(rtwdev); 3131 if (ret) { 3132 rtw89_warn(rtwdev, "reset bdram busy\n"); 3133 return ret; 3134 } 3135 3136 /* disable all channels except to FW CMD channel to download firmware */ 3137 rtw89_pci_ctrl_txdma_ch_ax(rtwdev, false); 3138 rtw89_pci_ctrl_txdma_fw_ch_ax(rtwdev, true); 3139 3140 /* start DMA activities */ 3141 rtw89_pci_ctrl_dma_all(rtwdev, true); 3142 3143 return 0; 3144 } 3145 3146 static int rtw89_pci_ops_mac_pre_deinit_ax(struct rtw89_dev *rtwdev) 3147 { 3148 rtw89_pci_power_wake_ax(rtwdev, false); 3149 3150 return 0; 3151 } 3152 3153 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en) 3154 { 3155 u32 val; 3156 3157 if (!en || !rtw89_pci_dev_ltr_enabled(rtwdev)) 3158 return 0; 3159 3160 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); 3161 if (rtw89_pci_ltr_is_err_reg_val(val)) 3162 return -EINVAL; 3163 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); 3164 if (rtw89_pci_ltr_is_err_reg_val(val)) 3165 return -EINVAL; 3166 val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); 3167 if (rtw89_pci_ltr_is_err_reg_val(val)) 3168 return -EINVAL; 3169 val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); 3170 if (rtw89_pci_ltr_is_err_reg_val(val)) 3171 return -EINVAL; 3172 3173 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN | 3174 B_AX_LTR_WD_NOEMP_CHK); 3175 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, 3176 PCI_LTR_SPC_500US); 3177 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, 3178 PCI_LTR_IDLE_TIMER_3_2MS); 3179 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); 3180 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); 3181 rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x90039003); 3182 rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); 3183 3184 return 0; 3185 } 3186 EXPORT_SYMBOL(rtw89_pci_ltr_set); 3187 3188 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en) 3189 { 3190 u32 dec_ctrl; 3191 u32 val32; 3192 3193 if (!rtw89_pci_dev_ltr_enabled(rtwdev)) 3194 return 0; 3195 3196 val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); 3197 if (rtw89_pci_ltr_is_err_reg_val(val32)) 3198 return -EINVAL; 3199 val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); 3200 if (rtw89_pci_ltr_is_err_reg_val(val32)) 3201 return -EINVAL; 3202 dec_ctrl = rtw89_read32(rtwdev, R_AX_LTR_DEC_CTRL); 3203 if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl)) 3204 return -EINVAL; 3205 val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX3); 3206 if (rtw89_pci_ltr_is_err_reg_val(val32)) 3207 return -EINVAL; 3208 val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX0); 3209 if (rtw89_pci_ltr_is_err_reg_val(val32)) 3210 return -EINVAL; 3211 3212 if (!en) { 3213 dec_ctrl &= ~(LTR_EN_BITS | B_AX_LTR_IDX_DRV_MASK | B_AX_LTR_HW_DEC_EN); 3214 dec_ctrl |= FIELD_PREP(B_AX_LTR_IDX_DRV_MASK, PCIE_LTR_IDX_IDLE) | 3215 B_AX_LTR_REQ_DRV; 3216 } else { 3217 dec_ctrl |= B_AX_LTR_HW_DEC_EN; 3218 } 3219 3220 dec_ctrl &= ~B_AX_LTR_SPACE_IDX_V1_MASK; 3221 dec_ctrl |= FIELD_PREP(B_AX_LTR_SPACE_IDX_V1_MASK, PCI_LTR_SPC_500US); 3222 3223 if (en) 3224 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, 3225 B_AX_LTR_WD_NOEMP_CHK_V1 | B_AX_LTR_HW_EN); 3226 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, 3227 PCI_LTR_IDLE_TIMER_3_2MS); 3228 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); 3229 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); 3230 rtw89_write32(rtwdev, R_AX_LTR_DEC_CTRL, dec_ctrl); 3231 rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX3, 0x90039003); 3232 rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX0, 0x880b880b); 3233 3234 return 0; 3235 } 3236 EXPORT_SYMBOL(rtw89_pci_ltr_set_v1); 3237 3238 static int rtw89_pci_ops_mac_post_init_ax(struct rtw89_dev *rtwdev) 3239 { 3240 const struct rtw89_pci_info *info = rtwdev->pci_info; 3241 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3242 int ret; 3243 3244 ret = info->ltr_set(rtwdev, true); 3245 if (ret) { 3246 rtw89_err(rtwdev, "pci ltr set fail\n"); 3247 return ret; 3248 } 3249 if (chip_id == RTL8852A) { 3250 /* ltr sw trigger */ 3251 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); 3252 } 3253 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 3254 /* ADDR info 8-byte mode */ 3255 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 3256 B_AX_HOST_ADDR_INFO_8B_SEL); 3257 rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 3258 } 3259 3260 /* enable DMA for all queues */ 3261 rtw89_pci_ctrl_txdma_ch_ax(rtwdev, true); 3262 3263 /* Release PCI IO */ 3264 rtw89_write32_clr(rtwdev, info->dma_stop1.addr, 3265 B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); 3266 3267 return 0; 3268 } 3269 3270 static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, 3271 struct pci_dev *pdev) 3272 { 3273 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3274 int ret; 3275 3276 ret = pci_enable_device(pdev); 3277 if (ret) { 3278 rtw89_err(rtwdev, "failed to enable pci device\n"); 3279 return ret; 3280 } 3281 3282 pci_set_master(pdev); 3283 pci_set_drvdata(pdev, rtwdev->hw); 3284 3285 rtwpci->pdev = pdev; 3286 3287 return 0; 3288 } 3289 3290 static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, 3291 struct pci_dev *pdev) 3292 { 3293 pci_disable_device(pdev); 3294 } 3295 3296 static bool rtw89_pci_chip_is_manual_dac(struct rtw89_dev *rtwdev) 3297 { 3298 const struct rtw89_chip_info *chip = rtwdev->chip; 3299 3300 switch (chip->chip_id) { 3301 case RTL8852A: 3302 case RTL8852B: 3303 case RTL8851B: 3304 case RTL8852BT: 3305 return true; 3306 default: 3307 return false; 3308 } 3309 } 3310 3311 static bool rtw89_pci_is_dac_compatible_bridge(struct rtw89_dev *rtwdev) 3312 { 3313 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3314 struct pci_dev *bridge = pci_upstream_bridge(rtwpci->pdev); 3315 3316 if (!rtw89_pci_chip_is_manual_dac(rtwdev)) 3317 return true; 3318 3319 if (!bridge) 3320 return false; 3321 3322 switch (bridge->vendor) { 3323 case PCI_VENDOR_ID_INTEL: 3324 return true; 3325 case PCI_VENDOR_ID_ASMEDIA: 3326 if (bridge->device == 0x2806) 3327 return true; 3328 break; 3329 case PCI_VENDOR_ID_SPACEMIT: 3330 if (bridge->device == PCI_DEVICE_ID_SPACEMIT_K3) 3331 return true; 3332 break; 3333 } 3334 3335 return false; 3336 } 3337 3338 static int rtw89_pci_cfg_dac(struct rtw89_dev *rtwdev, bool force) 3339 { 3340 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3341 struct pci_dev *pdev = rtwpci->pdev; 3342 int ret; 3343 u8 val; 3344 3345 if (!rtwpci->enable_dac && !force) 3346 return 0; 3347 3348 if (!rtw89_pci_chip_is_manual_dac(rtwdev)) 3349 return 0; 3350 3351 /* Configure DAC only via PCI config API, not DBI interfaces */ 3352 ret = pci_read_config_byte(pdev, RTW89_PCIE_L1_CTRL, &val); 3353 if (ret) 3354 return ret; 3355 3356 val |= RTW89_PCIE_BIT_EN_64BITS; 3357 return pci_write_config_byte(pdev, RTW89_PCIE_L1_CTRL, val); 3358 } 3359 3360 static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, 3361 struct pci_dev *pdev) 3362 { 3363 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3364 unsigned long resource_len; 3365 u8 bar_id = 2; 3366 int ret; 3367 3368 ret = pci_request_regions(pdev, KBUILD_MODNAME); 3369 if (ret) { 3370 rtw89_err(rtwdev, "failed to request pci regions\n"); 3371 goto err; 3372 } 3373 3374 if (!rtw89_pci_is_dac_compatible_bridge(rtwdev)) 3375 goto try_dac_done; 3376 3377 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); 3378 if (!ret) { 3379 ret = rtw89_pci_cfg_dac(rtwdev, true); 3380 if (!ret) { 3381 rtwpci->enable_dac = true; 3382 goto try_dac_done; 3383 } 3384 3385 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3386 if (ret) { 3387 rtw89_err(rtwdev, 3388 "failed to set dma and consistent mask to 32/36-bit\n"); 3389 goto err_release_regions; 3390 } 3391 } 3392 try_dac_done: 3393 3394 resource_len = pci_resource_len(pdev, bar_id); 3395 rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); 3396 if (!rtwpci->mmap) { 3397 rtw89_err(rtwdev, "failed to map pci io\n"); 3398 ret = -EIO; 3399 goto err_release_regions; 3400 } 3401 3402 return 0; 3403 3404 err_release_regions: 3405 pci_release_regions(pdev); 3406 err: 3407 return ret; 3408 } 3409 3410 static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, 3411 struct pci_dev *pdev) 3412 { 3413 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3414 3415 if (rtwpci->mmap) { 3416 pci_iounmap(pdev, rtwpci->mmap); 3417 pci_release_regions(pdev); 3418 } 3419 } 3420 3421 static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, 3422 struct pci_dev *pdev, 3423 struct rtw89_pci_tx_ring *tx_ring) 3424 { 3425 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 3426 u8 *head = wd_ring->head; 3427 dma_addr_t dma = wd_ring->dma; 3428 u32 page_size = wd_ring->page_size; 3429 u32 page_num = wd_ring->page_num; 3430 u32 ring_sz = page_size * page_num; 3431 3432 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 3433 wd_ring->head = NULL; 3434 } 3435 3436 static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, 3437 struct pci_dev *pdev, 3438 struct rtw89_pci_tx_ring *tx_ring) 3439 { 3440 tx_ring->bd_ring.head = NULL; 3441 } 3442 3443 static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, 3444 struct pci_dev *pdev) 3445 { 3446 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3447 struct rtw89_pci_dma_pool *bd_pool = &rtwpci->tx.bd_pool; 3448 const struct rtw89_pci_info *info = rtwdev->pci_info; 3449 struct rtw89_pci_tx_ring *tx_ring; 3450 int i; 3451 3452 for (i = 0; i < RTW89_TXCH_NUM; i++) { 3453 if (info->tx_dma_ch_mask & BIT(i)) 3454 continue; 3455 tx_ring = &rtwpci->tx.rings[i]; 3456 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 3457 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 3458 } 3459 3460 dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3461 } 3462 3463 static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, 3464 struct pci_dev *pdev, 3465 struct rtw89_pci_rx_ring *rx_ring) 3466 { 3467 struct rtw89_pci_rx_info *rx_info; 3468 struct sk_buff *skb; 3469 dma_addr_t dma; 3470 u32 buf_sz; 3471 int i; 3472 3473 buf_sz = rx_ring->buf_sz; 3474 for (i = 0; i < rx_ring->bd_ring.len; i++) { 3475 skb = rx_ring->buf[i]; 3476 if (!skb) 3477 continue; 3478 3479 rx_info = RTW89_PCI_RX_SKB_CB(skb); 3480 dma = rx_info->dma; 3481 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 3482 dev_kfree_skb(skb); 3483 rx_ring->buf[i] = NULL; 3484 } 3485 3486 rx_ring->bd_ring.head = NULL; 3487 } 3488 3489 static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, 3490 struct pci_dev *pdev) 3491 { 3492 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3493 struct rtw89_pci_dma_pool *bd_pool = &rtwpci->rx.bd_pool; 3494 struct rtw89_pci_rx_ring *rx_ring; 3495 int i; 3496 3497 for (i = 0; i < RTW89_RXCH_NUM; i++) { 3498 rx_ring = &rtwpci->rx.rings[i]; 3499 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 3500 } 3501 3502 dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3503 } 3504 3505 static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, 3506 struct pci_dev *pdev) 3507 { 3508 rtw89_pci_free_rx_rings(rtwdev, pdev); 3509 rtw89_pci_free_tx_rings(rtwdev, pdev); 3510 } 3511 3512 static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, 3513 struct rtw89_pci_rx_ring *rx_ring, 3514 struct sk_buff *skb, int buf_sz, u32 idx) 3515 { 3516 struct rtw89_pci_rx_info *rx_info; 3517 struct rtw89_pci_rx_bd_32 *rx_bd; 3518 dma_addr_t dma; 3519 3520 if (!skb) 3521 return -EINVAL; 3522 3523 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 3524 if (dma_mapping_error(&pdev->dev, dma)) 3525 return -EBUSY; 3526 3527 rx_info = RTW89_PCI_RX_SKB_CB(skb); 3528 rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); 3529 3530 memset(rx_bd, 0, sizeof(*rx_bd)); 3531 rx_bd->buf_size = cpu_to_le16(buf_sz); 3532 rx_bd->dma = cpu_to_le32(dma); 3533 rx_bd->opt = le16_encode_bits(upper_32_bits(dma), RTW89_PCI_RXBD_OPT_DMA_HI); 3534 rx_info->dma = dma; 3535 3536 return 0; 3537 } 3538 3539 static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, 3540 struct pci_dev *pdev, 3541 struct rtw89_pci_tx_ring *tx_ring, 3542 enum rtw89_tx_channel txch) 3543 { 3544 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 3545 struct rtw89_pci_tx_wd *txwd; 3546 dma_addr_t dma; 3547 dma_addr_t cur_paddr; 3548 u8 *head; 3549 u8 *cur_vaddr; 3550 u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; 3551 u32 page_num = RTW89_PCI_TXWD_NUM_MAX; 3552 u32 ring_sz = page_size * page_num; 3553 u32 page_offset; 3554 int i; 3555 3556 /* FWCMD queue doesn't use txwd as pages */ 3557 if (txch == RTW89_TXCH_CH12) 3558 return 0; 3559 3560 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 3561 if (!head) 3562 return -ENOMEM; 3563 3564 INIT_LIST_HEAD(&wd_ring->free_pages); 3565 wd_ring->head = head; 3566 wd_ring->dma = dma; 3567 wd_ring->page_size = page_size; 3568 wd_ring->page_num = page_num; 3569 3570 page_offset = 0; 3571 for (i = 0; i < page_num; i++) { 3572 txwd = &wd_ring->pages[i]; 3573 cur_paddr = dma + page_offset; 3574 cur_vaddr = head + page_offset; 3575 3576 skb_queue_head_init(&txwd->queue); 3577 INIT_LIST_HEAD(&txwd->list); 3578 txwd->paddr = cur_paddr; 3579 txwd->vaddr = cur_vaddr; 3580 txwd->len = page_size; 3581 txwd->seq = i; 3582 rtw89_pci_enqueue_txwd(tx_ring, txwd); 3583 3584 page_offset += page_size; 3585 } 3586 3587 return 0; 3588 } 3589 3590 static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 3591 struct pci_dev *pdev, 3592 struct rtw89_pci_tx_ring *tx_ring, 3593 u32 desc_size, u32 len, 3594 enum rtw89_tx_channel txch, 3595 void *head, dma_addr_t dma) 3596 { 3597 const struct rtw89_pci_ch_dma_addr *txch_addr; 3598 int ret; 3599 3600 ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); 3601 if (ret) { 3602 rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); 3603 goto err; 3604 } 3605 3606 ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr); 3607 if (ret) { 3608 rtw89_err(rtwdev, "failed to get address of txch %d", txch); 3609 goto err_free_wd_ring; 3610 } 3611 3612 INIT_LIST_HEAD(&tx_ring->busy_pages); 3613 tx_ring->bd_ring.head = head; 3614 tx_ring->bd_ring.dma = dma; 3615 tx_ring->bd_ring.len = len; 3616 tx_ring->bd_ring.desc_size = desc_size; 3617 tx_ring->bd_ring.addr = *txch_addr; 3618 tx_ring->bd_ring.wp = 0; 3619 tx_ring->bd_ring.rp = 0; 3620 tx_ring->txch = txch; 3621 3622 return 0; 3623 3624 err_free_wd_ring: 3625 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 3626 err: 3627 return ret; 3628 } 3629 3630 static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, 3631 struct pci_dev *pdev) 3632 { 3633 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3634 struct rtw89_pci_dma_pool *bd_pool = &rtwpci->tx.bd_pool; 3635 const struct rtw89_pci_info *info = rtwdev->pci_info; 3636 struct rtw89_pci_tx_ring *tx_ring; 3637 u32 i, tx_allocated; 3638 dma_addr_t dma; 3639 u32 desc_size; 3640 u32 ring_sz; 3641 u32 pool_sz; 3642 u32 ch_num; 3643 void *head; 3644 u32 len; 3645 int ret; 3646 3647 BUILD_BUG_ON(RTW89_PCI_TXBD_NUM_MAX % 16); 3648 3649 desc_size = sizeof(struct rtw89_pci_tx_bd_32); 3650 len = RTW89_PCI_TXBD_NUM_MAX; 3651 ch_num = RTW89_TXCH_NUM - hweight32(info->tx_dma_ch_mask); 3652 ring_sz = desc_size * len; 3653 pool_sz = ring_sz * ch_num; 3654 3655 head = dma_alloc_coherent(&pdev->dev, pool_sz, &dma, GFP_KERNEL); 3656 if (!head) 3657 return -ENOMEM; 3658 3659 bd_pool->head = head; 3660 bd_pool->dma = dma; 3661 bd_pool->size = pool_sz; 3662 3663 for (i = 0; i < RTW89_TXCH_NUM; i++) { 3664 if (info->tx_dma_ch_mask & BIT(i)) 3665 continue; 3666 tx_ring = &rtwpci->tx.rings[i]; 3667 ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, 3668 desc_size, len, i, head, dma); 3669 if (ret) { 3670 rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); 3671 goto err_free; 3672 } 3673 3674 head += ring_sz; 3675 dma += ring_sz; 3676 } 3677 3678 return 0; 3679 3680 err_free: 3681 tx_allocated = i; 3682 for (i = 0; i < tx_allocated; i++) { 3683 tx_ring = &rtwpci->tx.rings[i]; 3684 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 3685 } 3686 3687 dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3688 3689 return ret; 3690 } 3691 3692 static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 3693 struct pci_dev *pdev, 3694 struct rtw89_pci_rx_ring *rx_ring, 3695 u32 desc_size, u32 len, u32 rxch, 3696 void *head, dma_addr_t dma) 3697 { 3698 const struct rtw89_pci_info *info = rtwdev->pci_info; 3699 const struct rtw89_pci_ch_dma_addr *rxch_addr; 3700 struct sk_buff *skb; 3701 int buf_sz = RTW89_PCI_RX_BUF_SIZE; 3702 int i, allocated; 3703 int ret; 3704 3705 ret = rtw89_pci_get_rxch_addrs(rtwdev, rxch, &rxch_addr); 3706 if (ret) { 3707 rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); 3708 return ret; 3709 } 3710 3711 rx_ring->bd_ring.head = head; 3712 rx_ring->bd_ring.dma = dma; 3713 rx_ring->bd_ring.len = len; 3714 rx_ring->bd_ring.desc_size = desc_size; 3715 rx_ring->bd_ring.addr = *rxch_addr; 3716 if (info->rx_ring_eq_is_full) 3717 rx_ring->bd_ring.wp = len - 1; 3718 else 3719 rx_ring->bd_ring.wp = 0; 3720 rx_ring->bd_ring.rp = 0; 3721 rx_ring->buf_sz = buf_sz; 3722 rx_ring->deliver_skb = NULL; 3723 rx_ring->deliver_desc.ready = false; 3724 rx_ring->target_rx_tag = 0; 3725 3726 for (i = 0; i < len; i++) { 3727 skb = dev_alloc_skb(buf_sz); 3728 if (!skb) { 3729 ret = -ENOMEM; 3730 goto err_free; 3731 } 3732 3733 memset(skb->data, 0, buf_sz); 3734 rx_ring->buf[i] = skb; 3735 ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, 3736 buf_sz, i); 3737 if (ret) { 3738 rtw89_err(rtwdev, "failed to init rx buf %d\n", i); 3739 dev_kfree_skb_any(skb); 3740 rx_ring->buf[i] = NULL; 3741 goto err_free; 3742 } 3743 } 3744 3745 return 0; 3746 3747 err_free: 3748 allocated = i; 3749 for (i = 0; i < allocated; i++) { 3750 skb = rx_ring->buf[i]; 3751 if (!skb) 3752 continue; 3753 dma = *((dma_addr_t *)skb->cb); 3754 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 3755 dev_kfree_skb(skb); 3756 rx_ring->buf[i] = NULL; 3757 } 3758 3759 rx_ring->bd_ring.head = NULL; 3760 3761 return ret; 3762 } 3763 3764 static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, 3765 struct pci_dev *pdev) 3766 { 3767 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3768 struct rtw89_pci_dma_pool *bd_pool = &rtwpci->rx.bd_pool; 3769 struct rtw89_pci_rx_ring *rx_ring; 3770 int i, rx_allocated; 3771 dma_addr_t dma; 3772 u32 desc_size; 3773 u32 ring_sz; 3774 u32 pool_sz; 3775 void *head; 3776 u32 len; 3777 int ret; 3778 3779 desc_size = sizeof(struct rtw89_pci_rx_bd_32); 3780 len = RTW89_PCI_RXBD_NUM_MAX; 3781 ring_sz = desc_size * len; 3782 pool_sz = ring_sz * RTW89_RXCH_NUM; 3783 3784 head = dma_alloc_coherent(&pdev->dev, pool_sz, &dma, GFP_KERNEL); 3785 if (!head) 3786 return -ENOMEM; 3787 3788 bd_pool->head = head; 3789 bd_pool->dma = dma; 3790 bd_pool->size = pool_sz; 3791 3792 for (i = 0; i < RTW89_RXCH_NUM; i++) { 3793 rx_ring = &rtwpci->rx.rings[i]; 3794 3795 ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, 3796 desc_size, len, i, 3797 head, dma); 3798 if (ret) { 3799 rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); 3800 goto err_free; 3801 } 3802 3803 head += ring_sz; 3804 dma += ring_sz; 3805 } 3806 3807 return 0; 3808 3809 err_free: 3810 rx_allocated = i; 3811 for (i = 0; i < rx_allocated; i++) { 3812 rx_ring = &rtwpci->rx.rings[i]; 3813 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 3814 } 3815 3816 dma_free_coherent(&pdev->dev, bd_pool->size, bd_pool->head, bd_pool->dma); 3817 3818 return ret; 3819 } 3820 3821 static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, 3822 struct pci_dev *pdev) 3823 { 3824 int ret; 3825 3826 ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); 3827 if (ret) { 3828 rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); 3829 goto err; 3830 } 3831 3832 ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); 3833 if (ret) { 3834 rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); 3835 goto err_free_tx_rings; 3836 } 3837 3838 return 0; 3839 3840 err_free_tx_rings: 3841 rtw89_pci_free_tx_rings(rtwdev, pdev); 3842 err: 3843 return ret; 3844 } 3845 3846 static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, 3847 struct rtw89_pci *rtwpci) 3848 { 3849 skb_queue_head_init(&rtwpci->h2c_queue); 3850 skb_queue_head_init(&rtwpci->h2c_release_queue); 3851 } 3852 3853 static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, 3854 struct pci_dev *pdev) 3855 { 3856 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3857 int ret; 3858 3859 ret = rtw89_pci_setup_mapping(rtwdev, pdev); 3860 if (ret) { 3861 rtw89_err(rtwdev, "failed to setup pci mapping\n"); 3862 goto err; 3863 } 3864 3865 ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); 3866 if (ret) { 3867 rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); 3868 goto err_pci_unmap; 3869 } 3870 3871 rtw89_pci_h2c_init(rtwdev, rtwpci); 3872 3873 spin_lock_init(&rtwpci->irq_lock); 3874 spin_lock_init(&rtwpci->trx_lock); 3875 3876 return 0; 3877 3878 err_pci_unmap: 3879 rtw89_pci_clear_mapping(rtwdev, pdev); 3880 err: 3881 return ret; 3882 } 3883 3884 static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, 3885 struct pci_dev *pdev) 3886 { 3887 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3888 3889 rtw89_pci_free_trx_rings(rtwdev, pdev); 3890 rtw89_pci_clear_mapping(rtwdev, pdev); 3891 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 3892 skb_queue_len(&rtwpci->h2c_queue), true); 3893 } 3894 3895 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev) 3896 { 3897 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3898 const struct rtw89_chip_info *chip = rtwdev->chip; 3899 u32 hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN; 3900 3901 if (chip->chip_id == RTL8851B) 3902 hs0isr_ind_int_en = B_AX_HS0ISR_IND_INT_EN_WKARND; 3903 3904 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; 3905 3906 if (rtwpci->under_recovery) { 3907 rtwpci->intrs[0] = hs0isr_ind_int_en; 3908 rtwpci->intrs[1] = 0; 3909 } else { 3910 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | 3911 B_AX_RXDMA_INT_EN | 3912 B_AX_RXP1DMA_INT_EN | 3913 B_AX_RPQDMA_INT_EN | 3914 B_AX_RXDMA_STUCK_INT_EN | 3915 B_AX_RDU_INT_EN | 3916 B_AX_RPQBD_FULL_INT_EN | 3917 hs0isr_ind_int_en; 3918 3919 rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; 3920 } 3921 } 3922 EXPORT_SYMBOL(rtw89_pci_config_intr_mask); 3923 3924 static void rtw89_pci_recovery_intr_mask_v1(struct rtw89_dev *rtwdev) 3925 { 3926 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3927 3928 rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN; 3929 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3930 rtwpci->intrs[0] = 0; 3931 rtwpci->intrs[1] = 0; 3932 } 3933 3934 static void rtw89_pci_default_intr_mask_v1(struct rtw89_dev *rtwdev) 3935 { 3936 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3937 3938 rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN | 3939 B_AX_HS1ISR_IND_INT_EN | 3940 B_AX_HS0ISR_IND_INT_EN; 3941 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3942 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | 3943 B_AX_RXDMA_INT_EN | 3944 B_AX_RXP1DMA_INT_EN | 3945 B_AX_RPQDMA_INT_EN | 3946 B_AX_RXDMA_STUCK_INT_EN | 3947 B_AX_RDU_INT_EN | 3948 B_AX_RPQBD_FULL_INT_EN; 3949 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; 3950 } 3951 3952 static void rtw89_pci_low_power_intr_mask_v1(struct rtw89_dev *rtwdev) 3953 { 3954 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3955 3956 rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN | 3957 B_AX_HS0ISR_IND_INT_EN; 3958 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3959 rtwpci->intrs[0] = 0; 3960 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; 3961 } 3962 3963 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev) 3964 { 3965 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3966 3967 if (rtwpci->under_recovery) 3968 rtw89_pci_recovery_intr_mask_v1(rtwdev); 3969 else if (rtwpci->low_power) 3970 rtw89_pci_low_power_intr_mask_v1(rtwdev); 3971 else 3972 rtw89_pci_default_intr_mask_v1(rtwdev); 3973 } 3974 EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v1); 3975 3976 static void rtw89_pci_recovery_intr_mask_v2(struct rtw89_dev *rtwdev) 3977 { 3978 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3979 3980 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 3981 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 3982 rtwpci->intrs[0] = 0; 3983 rtwpci->intrs[1] = 0; 3984 } 3985 3986 static void rtw89_pci_default_intr_mask_v2(struct rtw89_dev *rtwdev) 3987 { 3988 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3989 3990 rtwpci->ind_intrs = B_BE_HCI_AXIDMA_INT_EN0 | 3991 B_BE_HS0_IND_INT_EN0; 3992 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 3993 rtwpci->intrs[0] = B_BE_RDU_CH1_INT_IMR_V1 | 3994 B_BE_RDU_CH0_INT_IMR_V1; 3995 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 | 3996 B_BE_PCIE_RX_RPQ0_IMR0_V1; 3997 } 3998 3999 static void rtw89_pci_low_power_intr_mask_v2(struct rtw89_dev *rtwdev) 4000 { 4001 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4002 4003 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0 | 4004 B_BE_HS1_IND_INT_EN0; 4005 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN; 4006 rtwpci->intrs[0] = 0; 4007 rtwpci->intrs[1] = B_BE_PCIE_RX_RX0P2_IMR0_V1 | 4008 B_BE_PCIE_RX_RPQ0_IMR0_V1; 4009 } 4010 4011 void rtw89_pci_config_intr_mask_v2(struct rtw89_dev *rtwdev) 4012 { 4013 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4014 4015 if (rtwpci->under_recovery) 4016 rtw89_pci_recovery_intr_mask_v2(rtwdev); 4017 else if (rtwpci->low_power) 4018 rtw89_pci_low_power_intr_mask_v2(rtwdev); 4019 else 4020 rtw89_pci_default_intr_mask_v2(rtwdev); 4021 } 4022 EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v2); 4023 4024 static void rtw89_pci_recovery_intr_mask_v3(struct rtw89_dev *rtwdev) 4025 { 4026 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4027 4028 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 4029 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | 4030 B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; 4031 rtwpci->intrs[0] = 0; 4032 rtwpci->intrs[1] = 0; 4033 } 4034 4035 static void rtw89_pci_default_intr_mask_v3(struct rtw89_dev *rtwdev) 4036 { 4037 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4038 4039 rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0; 4040 rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN | 4041 B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN; 4042 rtwpci->intrs[0] = 0; 4043 rtwpci->intrs[1] = B_BE_PCIE_RDU_CH1_IMR | 4044 B_BE_PCIE_RDU_CH0_IMR | 4045 B_BE_PCIE_RX_RX0P2_IMR0_V1 | 4046 B_BE_PCIE_RX_RPQ0_IMR0_V1; 4047 } 4048 4049 void rtw89_pci_config_intr_mask_v3(struct rtw89_dev *rtwdev) 4050 { 4051 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4052 4053 if (rtwpci->under_recovery) 4054 rtw89_pci_recovery_intr_mask_v3(rtwdev); 4055 else 4056 rtw89_pci_default_intr_mask_v3(rtwdev); 4057 } 4058 EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v3); 4059 4060 static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, 4061 struct pci_dev *pdev) 4062 { 4063 unsigned long flags = 0; 4064 int ret; 4065 4066 flags |= PCI_IRQ_INTX | PCI_IRQ_MSI; 4067 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 4068 if (ret < 0) { 4069 rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); 4070 goto err; 4071 } 4072 4073 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 4074 rtw89_pci_interrupt_handler, 4075 rtw89_pci_interrupt_threadfn, 4076 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 4077 if (ret) { 4078 rtw89_err(rtwdev, "failed to request threaded irq\n"); 4079 goto err_free_vector; 4080 } 4081 4082 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RESET); 4083 4084 return 0; 4085 4086 err_free_vector: 4087 pci_free_irq_vectors(pdev); 4088 err: 4089 return ret; 4090 } 4091 4092 static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, 4093 struct pci_dev *pdev) 4094 { 4095 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 4096 pci_free_irq_vectors(pdev); 4097 } 4098 4099 static u16 gray_code_to_bin(u16 gray_code) 4100 { 4101 u16 binary = gray_code; 4102 4103 while (gray_code) { 4104 gray_code >>= 1; 4105 binary ^= gray_code; 4106 } 4107 4108 return binary; 4109 } 4110 4111 static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev) 4112 { 4113 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4114 struct pci_dev *pdev = rtwpci->pdev; 4115 u16 val16, filter_out_val; 4116 u32 val, phy_offset; 4117 int ret; 4118 4119 if (rtwdev->chip->chip_id != RTL8852C) 4120 return 0; 4121 4122 val = rtw89_read32_mask(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK); 4123 if (val == B_AX_ASPM_CTRL_L1) 4124 return 0; 4125 4126 ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val); 4127 if (ret) 4128 return ret; 4129 4130 val = FIELD_GET(RTW89_BCFG_LINK_SPEED_MASK, val); 4131 if (val == RTW89_PCIE_GEN1_SPEED) { 4132 phy_offset = R_RAC_DIRECT_OFFSET_G1; 4133 } else if (val == RTW89_PCIE_GEN2_SPEED) { 4134 phy_offset = R_RAC_DIRECT_OFFSET_G2; 4135 val16 = rtw89_read16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT); 4136 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, 4137 val16 | B_PCIE_BIT_PINOUT_DIS); 4138 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, 4139 val16 & ~B_PCIE_BIT_RD_SEL); 4140 4141 val16 = rtw89_read16_mask(rtwdev, 4142 phy_offset + RAC_ANA1F * RAC_MULT, 4143 FILTER_OUT_EQ_MASK); 4144 val16 = gray_code_to_bin(val16); 4145 filter_out_val = rtw89_read16(rtwdev, phy_offset + RAC_ANA24 * 4146 RAC_MULT); 4147 filter_out_val &= ~REG_FILTER_OUT_MASK; 4148 filter_out_val |= FIELD_PREP(REG_FILTER_OUT_MASK, val16); 4149 4150 rtw89_write16(rtwdev, phy_offset + RAC_ANA24 * RAC_MULT, 4151 filter_out_val); 4152 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0A * RAC_MULT, 4153 B_BAC_EQ_SEL); 4154 rtw89_write16_set(rtwdev, 4155 R_RAC_DIRECT_OFFSET_G1 + RAC_ANA0C * RAC_MULT, 4156 B_PCIE_BIT_PSAVE); 4157 } else { 4158 return -EOPNOTSUPP; 4159 } 4160 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0C * RAC_MULT, 4161 B_PCIE_BIT_PSAVE); 4162 4163 return 0; 4164 } 4165 4166 static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) 4167 { 4168 const struct rtw89_pci_info *info = rtwdev->pci_info; 4169 const struct rtw89_pci_gen_def *gen_def = info->gen_def; 4170 4171 if (rtw89_pci_disable_clkreq) 4172 return; 4173 4174 gen_def->clkreq_set(rtwdev, enable); 4175 } 4176 4177 static void rtw89_pci_clkreq_set_ax(struct rtw89_dev *rtwdev, bool enable) 4178 { 4179 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4180 int ret; 4181 4182 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 4183 PCIE_CLKDLY_HW_30US); 4184 if (ret) 4185 rtw89_err(rtwdev, "failed to set CLKREQ Delay\n"); 4186 4187 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 4188 if (enable) 4189 ret = rtw89_pci_config_byte_set(rtwdev, 4190 RTW89_PCIE_L1_CTRL, 4191 RTW89_PCIE_BIT_CLK); 4192 else 4193 ret = rtw89_pci_config_byte_clr(rtwdev, 4194 RTW89_PCIE_L1_CTRL, 4195 RTW89_PCIE_BIT_CLK); 4196 if (ret) 4197 rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", 4198 enable ? "set" : "unset", ret); 4199 } else if (chip_id == RTL8852C) { 4200 rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL, 4201 B_AX_CLK_REQ_SEL_OPT | B_AX_CLK_REQ_SEL); 4202 if (enable) 4203 rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL, 4204 B_AX_CLK_REQ_N); 4205 else 4206 rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL, 4207 B_AX_CLK_REQ_N); 4208 } 4209 } 4210 4211 static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) 4212 { 4213 const struct rtw89_pci_info *info = rtwdev->pci_info; 4214 const struct rtw89_pci_gen_def *gen_def = info->gen_def; 4215 4216 if (rtw89_pci_disable_aspm_l1) 4217 return; 4218 4219 gen_def->aspm_set(rtwdev, enable); 4220 } 4221 4222 static void rtw89_pci_aspm_set_ax(struct rtw89_dev *rtwdev, bool enable) 4223 { 4224 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4225 u8 value = 0; 4226 int ret; 4227 4228 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); 4229 if (ret) 4230 rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); 4231 4232 u8p_replace_bits(&value, PCIE_L1DLY_16US, RTW89_L1DLY_MASK); 4233 u8p_replace_bits(&value, PCIE_L0SDLY_4US, RTW89_L0DLY_MASK); 4234 4235 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value); 4236 if (ret) 4237 rtw89_warn(rtwdev, "failed to read ASPM Delay\n"); 4238 4239 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 4240 if (enable) 4241 ret = rtw89_pci_config_byte_set(rtwdev, 4242 RTW89_PCIE_L1_CTRL, 4243 RTW89_PCIE_BIT_L1); 4244 else 4245 ret = rtw89_pci_config_byte_clr(rtwdev, 4246 RTW89_PCIE_L1_CTRL, 4247 RTW89_PCIE_BIT_L1); 4248 } else if (chip_id == RTL8852C) { 4249 if (enable) 4250 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, 4251 B_AX_ASPM_CTRL_L1); 4252 else 4253 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, 4254 B_AX_ASPM_CTRL_L1); 4255 } 4256 if (ret) 4257 rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", 4258 enable ? "set" : "unset", ret); 4259 } 4260 4261 static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) 4262 { 4263 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 4264 const struct rtw89_pci_info *info = rtwdev->pci_info; 4265 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4266 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 4267 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 4268 u32 val = 0; 4269 4270 if (rtwdev->scanning || 4271 (tx_tfc_lv < RTW89_TFC_HIGH && rx_tfc_lv < RTW89_TFC_HIGH)) 4272 goto out; 4273 4274 if (chip_gen == RTW89_CHIP_BE) 4275 val = B_BE_PCIE_MIT_RX0P2_EN | B_BE_PCIE_MIT_RX0P1_EN; 4276 else 4277 val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | 4278 FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | 4279 FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | 4280 FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); 4281 4282 out: 4283 rtw89_write32(rtwdev, info->mit_addr, val); 4284 } 4285 4286 static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) 4287 { 4288 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4289 struct pci_dev *pdev = rtwpci->pdev; 4290 u16 link_ctrl; 4291 int ret; 4292 4293 /* Though there is standard PCIE configuration space to set the 4294 * link control register, but by Realtek's design, driver should 4295 * check if host supports CLKREQ/ASPM to enable the HW module. 4296 * 4297 * These functions are implemented by two HW modules associated, 4298 * one is responsible to access PCIE configuration space to 4299 * follow the host settings, and another is in charge of doing 4300 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 4301 * the host does not support it, and due to some reasons or wrong 4302 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 4303 * loss if HW misbehaves on the link. 4304 * 4305 * Hence it's designed that driver should first check the PCIE 4306 * configuration space is sync'ed and enabled, then driver can turn 4307 * on the other module that is actually working on the mechanism. 4308 */ 4309 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 4310 if (ret) { 4311 rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 4312 return; 4313 } 4314 4315 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 4316 rtw89_pci_clkreq_set(rtwdev, true); 4317 4318 if (link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) 4319 rtw89_pci_aspm_set(rtwdev, true); 4320 } 4321 4322 static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) 4323 { 4324 const struct rtw89_pci_info *info = rtwdev->pci_info; 4325 const struct rtw89_pci_gen_def *gen_def = info->gen_def; 4326 4327 if (rtw89_pci_disable_l1ss) 4328 return; 4329 4330 gen_def->l1ss_set(rtwdev, enable); 4331 } 4332 4333 static void rtw89_pci_l1ss_set_ax(struct rtw89_dev *rtwdev, bool enable) 4334 { 4335 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4336 int ret; 4337 4338 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 4339 if (enable) 4340 ret = rtw89_pci_config_byte_set(rtwdev, 4341 RTW89_PCIE_TIMER_CTRL, 4342 RTW89_PCIE_BIT_L1SUB); 4343 else 4344 ret = rtw89_pci_config_byte_clr(rtwdev, 4345 RTW89_PCIE_TIMER_CTRL, 4346 RTW89_PCIE_BIT_L1SUB); 4347 if (ret) 4348 rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", 4349 enable ? "set" : "unset", ret); 4350 } else if (chip_id == RTL8852C) { 4351 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1, 4352 RTW89_PCIE_BIT_ASPM_L11 | 4353 RTW89_PCIE_BIT_PCI_L11); 4354 if (ret) 4355 rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret); 4356 if (enable) 4357 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, 4358 B_AX_L1SUB_DISABLE); 4359 else 4360 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, 4361 B_AX_L1SUB_DISABLE); 4362 } 4363 } 4364 4365 static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) 4366 { 4367 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4368 struct pci_dev *pdev = rtwpci->pdev; 4369 u32 l1ss_cap_ptr, l1ss_ctrl; 4370 4371 if (rtw89_pci_disable_l1ss) 4372 return; 4373 4374 l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 4375 if (!l1ss_cap_ptr) 4376 return; 4377 4378 pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); 4379 4380 if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) 4381 rtw89_pci_l1ss_set(rtwdev, true); 4382 } 4383 4384 static void rtw89_pci_cpl_timeout_cfg(struct rtw89_dev *rtwdev) 4385 { 4386 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4387 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4388 struct rtw89_hal *hal = &rtwdev->hal; 4389 struct pci_dev *pdev = rtwpci->pdev; 4390 bool dis = true; 4391 4392 if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090) 4393 dis = false; 4394 4395 if (dis) 4396 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 4397 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 4398 else 4399 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2, 4400 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 4401 } 4402 4403 static int rtw89_pci_poll_io_idle_ax(struct rtw89_dev *rtwdev) 4404 { 4405 int ret = 0; 4406 u32 sts; 4407 u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; 4408 4409 ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, 4410 10, 1000, false, rtwdev, 4411 R_AX_PCIE_DMA_BUSY1); 4412 if (ret) { 4413 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", 4414 rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); 4415 return -EINVAL; 4416 } 4417 return ret; 4418 } 4419 4420 static int rtw89_pci_lv1rst_stop_dma_ax(struct rtw89_dev *rtwdev) 4421 { 4422 u32 val; 4423 int ret; 4424 4425 if (rtwdev->chip->chip_id == RTL8852C) 4426 return 0; 4427 4428 rtw89_pci_ctrl_dma_all(rtwdev, false); 4429 ret = rtw89_pci_poll_io_idle_ax(rtwdev); 4430 if (ret) { 4431 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 4432 rtw89_debug(rtwdev, RTW89_DBG_HCI, 4433 "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", 4434 R_AX_DBG_ERR_FLAG, val); 4435 if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) 4436 rtw89_mac_ctrl_hci_dma_tx(rtwdev, false); 4437 if (val & B_AX_RX_STUCK) 4438 rtw89_mac_ctrl_hci_dma_rx(rtwdev, false); 4439 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4440 ret = rtw89_pci_poll_io_idle_ax(rtwdev); 4441 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 4442 rtw89_debug(rtwdev, RTW89_DBG_HCI, 4443 "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", 4444 R_AX_DBG_ERR_FLAG, val); 4445 } 4446 4447 return ret; 4448 } 4449 4450 static int rtw89_pci_lv1rst_start_dma_ax(struct rtw89_dev *rtwdev) 4451 { 4452 int ret; 4453 4454 if (rtwdev->chip->chip_id == RTL8852C) 4455 return 0; 4456 4457 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 4458 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4459 rtw89_pci_clr_idx_all(rtwdev); 4460 4461 ret = rtw89_pci_rst_bdram_ax(rtwdev); 4462 if (ret) 4463 return ret; 4464 4465 rtw89_pci_ctrl_dma_all(rtwdev, true); 4466 return 0; 4467 } 4468 4469 static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, 4470 enum rtw89_lv1_rcvy_step step) 4471 { 4472 const struct rtw89_pci_info *info = rtwdev->pci_info; 4473 const struct rtw89_pci_gen_def *gen_def = info->gen_def; 4474 int ret; 4475 4476 switch (step) { 4477 case RTW89_LV1_RCVY_STEP_1: 4478 ret = gen_def->lv1rst_stop_dma(rtwdev); 4479 if (ret) 4480 rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); 4481 4482 break; 4483 4484 case RTW89_LV1_RCVY_STEP_2: 4485 ret = gen_def->lv1rst_start_dma(rtwdev); 4486 if (ret) 4487 rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); 4488 break; 4489 4490 default: 4491 return -EINVAL; 4492 } 4493 4494 return ret; 4495 } 4496 4497 static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) 4498 { 4499 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 4500 return; 4501 4502 if (rtwdev->chip->chip_id == RTL8852C) { 4503 rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", 4504 rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG_V1)); 4505 rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", 4506 rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG_V1)); 4507 } else { 4508 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", 4509 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 4510 rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", 4511 rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); 4512 rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", 4513 rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); 4514 } 4515 } 4516 4517 static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) 4518 { 4519 struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); 4520 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 4521 const struct rtw89_pci_info *info = rtwdev->pci_info; 4522 const struct rtw89_pci_isr_def *isr_def = info->isr_def; 4523 unsigned long flags; 4524 int work_done; 4525 4526 rtwdev->napi_budget_countdown = budget; 4527 4528 rtw89_write32(rtwdev, isr_def->isr_clear_rpq.addr, isr_def->isr_clear_rpq.data); 4529 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 4530 if (work_done == budget) 4531 return budget; 4532 4533 rtw89_write32(rtwdev, isr_def->isr_clear_rxq.addr, isr_def->isr_clear_rxq.data); 4534 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 4535 if (work_done < budget && napi_complete_done(napi, work_done)) { 4536 spin_lock_irqsave(&rtwpci->irq_lock, flags); 4537 if (likely(rtwpci->running)) 4538 rtw89_chip_enable_intr(rtwdev, rtwpci); 4539 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 4540 } 4541 4542 return work_done; 4543 } 4544 4545 static 4546 void rtw89_check_pci_ssid_quirks(struct rtw89_dev *rtwdev, 4547 struct pci_dev *pdev, 4548 const struct rtw89_pci_ssid_quirk *ssid_quirks) 4549 { 4550 int i; 4551 4552 if (!ssid_quirks) 4553 return; 4554 4555 for (i = 0; i < 200; i++, ssid_quirks++) { 4556 if (ssid_quirks->vendor == 0 && ssid_quirks->device == 0) 4557 break; 4558 4559 if (ssid_quirks->vendor != pdev->vendor || 4560 ssid_quirks->device != pdev->device || 4561 ssid_quirks->subsystem_vendor != pdev->subsystem_vendor || 4562 ssid_quirks->subsystem_device != pdev->subsystem_device) 4563 continue; 4564 4565 bitmap_or(rtwdev->quirks, rtwdev->quirks, &ssid_quirks->bitmap, 4566 NUM_OF_RTW89_QUIRKS); 4567 rtwdev->custid = ssid_quirks->custid; 4568 break; 4569 } 4570 4571 rtw89_debug(rtwdev, RTW89_DBG_HCI, "quirks=%*ph custid=%d\n", 4572 (int)sizeof(rtwdev->quirks), rtwdev->quirks, rtwdev->custid); 4573 } 4574 4575 static int __maybe_unused rtw89_pci_suspend(struct device *dev) 4576 { 4577 struct ieee80211_hw *hw = dev_get_drvdata(dev); 4578 struct rtw89_dev *rtwdev = hw->priv; 4579 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4580 4581 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 4582 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 4583 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 4584 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 4585 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 4586 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 4587 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 4588 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 4589 } else { 4590 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, 4591 B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); 4592 } 4593 4594 return 0; 4595 } 4596 4597 static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) 4598 { 4599 if (rtwdev->chip->chip_id == RTL8852C) 4600 return; 4601 4602 /* Hardware need write the reg twice to ensure the setting work */ 4603 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 4604 RTW89_PCIE_BIT_CFG_RST_MSTATE); 4605 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 4606 RTW89_PCIE_BIT_CFG_RST_MSTATE); 4607 } 4608 4609 void rtw89_pci_basic_cfg(struct rtw89_dev *rtwdev, bool resume) 4610 { 4611 if (resume) 4612 rtw89_pci_cfg_dac(rtwdev, false); 4613 4614 rtw89_pci_disable_eq(rtwdev); 4615 rtw89_pci_filter_out(rtwdev); 4616 rtw89_pci_cpl_timeout_cfg(rtwdev); 4617 rtw89_pci_link_cfg(rtwdev); 4618 rtw89_pci_l1ss_cfg(rtwdev); 4619 } 4620 4621 static int __maybe_unused rtw89_pci_resume(struct device *dev) 4622 { 4623 struct ieee80211_hw *hw = dev_get_drvdata(dev); 4624 struct rtw89_dev *rtwdev = hw->priv; 4625 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4626 4627 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 4628 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 4629 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 4630 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 4631 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 4632 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 4633 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, 4634 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 4635 } else { 4636 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, 4637 B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); 4638 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, 4639 B_AX_SEL_REQ_ENTR_L1); 4640 } 4641 rtw89_pci_hci_ldo(rtwdev); 4642 rtw89_pci_l2_hci_ldo(rtwdev); 4643 4644 rtw89_pci_basic_cfg(rtwdev, true); 4645 4646 return 0; 4647 } 4648 4649 SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); 4650 EXPORT_SYMBOL(rtw89_pm_ops); 4651 4652 static pci_ers_result_t rtw89_pci_io_error_detected(struct pci_dev *pdev, 4653 pci_channel_state_t state) 4654 { 4655 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 4656 4657 ieee80211_stop_queues(hw); 4658 4659 return PCI_ERS_RESULT_NEED_RESET; 4660 } 4661 4662 static pci_ers_result_t rtw89_pci_io_slot_reset(struct pci_dev *pdev) 4663 { 4664 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 4665 struct rtw89_dev *rtwdev = hw->priv; 4666 4667 rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION); 4668 4669 return PCI_ERS_RESULT_RECOVERED; 4670 } 4671 4672 static void rtw89_pci_io_resume(struct pci_dev *pdev) 4673 { 4674 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 4675 4676 /* ack any pending wake events, disable PME */ 4677 pci_enable_wake(pdev, PCI_D0, 0); 4678 4679 ieee80211_wake_queues(hw); 4680 } 4681 4682 const struct pci_error_handlers rtw89_pci_err_handler = { 4683 .error_detected = rtw89_pci_io_error_detected, 4684 .slot_reset = rtw89_pci_io_slot_reset, 4685 .resume = rtw89_pci_io_resume, 4686 }; 4687 EXPORT_SYMBOL(rtw89_pci_err_handler); 4688 4689 const struct rtw89_pci_isr_def rtw89_pci_isr_ax = { 4690 .isr_rdu = B_AX_RDU_INT, 4691 .isr_halt_c2h = B_AX_HALT_C2H_INT_EN, 4692 .isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN, 4693 .isr_sps_ocp = 0, 4694 .isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT}, 4695 .isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | 4696 B_AX_RDU_INT}, 4697 }; 4698 EXPORT_SYMBOL(rtw89_pci_isr_ax); 4699 4700 const struct rtw89_pci_gen_def rtw89_pci_gen_ax = { 4701 .mac_pre_init = rtw89_pci_ops_mac_pre_init_ax, 4702 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_ax, 4703 .mac_post_init = rtw89_pci_ops_mac_post_init_ax, 4704 4705 .clr_idx_all = rtw89_pci_clr_idx_all_ax, 4706 .rst_bdram = rtw89_pci_rst_bdram_ax, 4707 4708 .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_ax, 4709 .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_ax, 4710 4711 .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_ax, 4712 .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_ax, 4713 .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle_ax, 4714 4715 .aspm_set = rtw89_pci_aspm_set_ax, 4716 .clkreq_set = rtw89_pci_clkreq_set_ax, 4717 .l1ss_set = rtw89_pci_l1ss_set_ax, 4718 4719 .disable_eq = rtw89_pci_disable_eq_ax, 4720 .power_wake = rtw89_pci_power_wake_ax, 4721 }; 4722 EXPORT_SYMBOL(rtw89_pci_gen_ax); 4723 4724 static const struct rtw89_hci_ops rtw89_pci_ops = { 4725 .tx_write = rtw89_pci_ops_tx_write, 4726 .tx_kick_off = rtw89_pci_ops_tx_kick_off, 4727 .flush_queues = rtw89_pci_ops_flush_queues, 4728 .reset = rtw89_pci_ops_reset, 4729 .start = rtw89_pci_ops_start, 4730 .stop = rtw89_pci_ops_stop, 4731 .pause = rtw89_pci_ops_pause, 4732 .switch_mode = rtw89_pci_ops_switch_mode, 4733 .recalc_int_mit = rtw89_pci_recalc_int_mit, 4734 4735 .read8 = rtw89_pci_ops_read8, 4736 .read16 = rtw89_pci_ops_read16, 4737 .read32 = rtw89_pci_ops_read32, 4738 .write8 = rtw89_pci_ops_write8, 4739 .write16 = rtw89_pci_ops_write16, 4740 .write32 = rtw89_pci_ops_write32, 4741 4742 .read32_pci_cfg = rtw89_pci_ops_read32_pci_cfg, 4743 4744 .mac_pre_init = rtw89_pci_ops_mac_pre_init, 4745 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit, 4746 .mac_post_init = rtw89_pci_ops_mac_post_init, 4747 .deinit = rtw89_pci_ops_deinit, 4748 4749 .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, 4750 .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, 4751 .dump_err_status = rtw89_pci_ops_dump_err_status, 4752 .napi_poll = rtw89_pci_napi_poll, 4753 4754 .recovery_start = rtw89_pci_ops_recovery_start, 4755 .recovery_complete = rtw89_pci_ops_recovery_complete, 4756 4757 .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch, 4758 .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch, 4759 .ctrl_trxhci = rtw89_pci_ctrl_dma_trx, 4760 .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle, 4761 4762 .clr_idx_all = rtw89_pci_clr_idx_all, 4763 .clear = rtw89_pci_clear_resource, 4764 .disable_intr = rtw89_pci_disable_intr_lock, 4765 .enable_intr = rtw89_pci_enable_intr_lock, 4766 .rst_bdram = rtw89_pci_reset_bdram, 4767 }; 4768 4769 static void rtw89_pci_d3cold_quirks(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4770 { 4771 static const struct dmi_system_id d3cold_quirks[] = { 4772 { 4773 .ident = "ASUS EXPERTBOOK B3406CMA", 4774 .matches = { 4775 DMI_MATCH(DMI_BOARD_VENDOR, "ASUS"), 4776 DMI_MATCH(DMI_BOARD_NAME, "B3406CMA"), 4777 }, 4778 }, 4779 { 4780 .ident = "ASUS EXPERTBOOK B3606CMA", 4781 .matches = { 4782 DMI_MATCH(DMI_BOARD_VENDOR, "ASUS"), 4783 DMI_MATCH(DMI_BOARD_NAME, "B3606CMA"), 4784 }, 4785 }, 4786 { 4787 .ident = "ASUS EXPERTBOOK P3406CMA", 4788 .matches = { 4789 DMI_MATCH(DMI_BOARD_VENDOR, "ASUS"), 4790 DMI_MATCH(DMI_BOARD_NAME, "P3406CMA"), 4791 }, 4792 }, 4793 { 4794 .ident = "ASUS EXPERTBOOK P3606CMA", 4795 .matches = { 4796 DMI_MATCH(DMI_BOARD_VENDOR, "ASUS"), 4797 DMI_MATCH(DMI_BOARD_NAME, "P3606CMA"), 4798 }, 4799 }, 4800 {}, 4801 }; 4802 const struct dmi_system_id *match; 4803 4804 match = dmi_first_match(d3cold_quirks); 4805 if (!match) 4806 return; 4807 4808 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable D3Cold on %s\n", match->ident); 4809 pci_d3cold_disable(pdev); 4810 } 4811 4812 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 4813 { 4814 struct rtw89_dev *rtwdev; 4815 const struct rtw89_driver_info *info; 4816 const struct rtw89_pci_info *pci_info; 4817 int ret; 4818 4819 info = (const struct rtw89_driver_info *)id->driver_data; 4820 4821 rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev, 4822 sizeof(struct rtw89_pci), info); 4823 if (!rtwdev) { 4824 dev_err(&pdev->dev, "failed to allocate hw\n"); 4825 return -ENOMEM; 4826 } 4827 4828 pci_info = info->bus.pci; 4829 4830 rtwdev->pci_info = info->bus.pci; 4831 rtwdev->hci.ops = &rtw89_pci_ops; 4832 rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; 4833 rtwdev->hci.dle_type = RTW89_HCI_DLE_TYPE_PCIE; 4834 rtwdev->hci.rpwm_addr = pci_info->rpwm_addr; 4835 rtwdev->hci.cpwm_addr = pci_info->cpwm_addr; 4836 4837 rtw89_pci_d3cold_quirks(rtwdev, pdev); 4838 rtw89_check_quirks(rtwdev, info->quirks); 4839 rtw89_check_pci_ssid_quirks(rtwdev, pdev, pci_info->ssid_quirks); 4840 4841 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 4842 4843 ret = rtw89_core_init(rtwdev); 4844 if (ret) { 4845 rtw89_err(rtwdev, "failed to initialise core\n"); 4846 goto err_release_hw; 4847 } 4848 4849 ret = rtw89_pci_claim_device(rtwdev, pdev); 4850 if (ret) { 4851 rtw89_err(rtwdev, "failed to claim pci device\n"); 4852 goto err_core_deinit; 4853 } 4854 4855 ret = rtw89_pci_setup_resource(rtwdev, pdev); 4856 if (ret) { 4857 rtw89_err(rtwdev, "failed to setup pci resource\n"); 4858 goto err_declaim_pci; 4859 } 4860 4861 ret = rtw89_chip_info_setup(rtwdev); 4862 if (ret) { 4863 rtw89_err(rtwdev, "failed to setup chip information\n"); 4864 goto err_clear_resource; 4865 } 4866 4867 rtw89_pci_basic_cfg(rtwdev, false); 4868 4869 ret = rtw89_core_napi_init(rtwdev); 4870 if (ret) { 4871 rtw89_err(rtwdev, "failed to init napi\n"); 4872 goto err_clear_resource; 4873 } 4874 4875 ret = rtw89_pci_request_irq(rtwdev, pdev); 4876 if (ret) { 4877 rtw89_err(rtwdev, "failed to request pci irq\n"); 4878 goto err_deinit_napi; 4879 } 4880 4881 ret = rtw89_core_register(rtwdev); 4882 if (ret) { 4883 rtw89_err(rtwdev, "failed to register core\n"); 4884 goto err_free_irq; 4885 } 4886 4887 set_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags); 4888 4889 return 0; 4890 4891 err_free_irq: 4892 rtw89_pci_free_irq(rtwdev, pdev); 4893 err_deinit_napi: 4894 rtw89_core_napi_deinit(rtwdev); 4895 err_clear_resource: 4896 rtw89_pci_clear_resource(rtwdev, pdev); 4897 err_declaim_pci: 4898 rtw89_pci_declaim_device(rtwdev, pdev); 4899 err_core_deinit: 4900 rtw89_core_deinit(rtwdev); 4901 err_release_hw: 4902 rtw89_free_ieee80211_hw(rtwdev); 4903 4904 return ret; 4905 } 4906 EXPORT_SYMBOL(rtw89_pci_probe); 4907 4908 void rtw89_pci_remove(struct pci_dev *pdev) 4909 { 4910 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 4911 struct rtw89_dev *rtwdev; 4912 4913 rtwdev = hw->priv; 4914 4915 rtw89_pci_free_irq(rtwdev, pdev); 4916 rtw89_core_napi_deinit(rtwdev); 4917 rtw89_core_unregister(rtwdev); 4918 rtw89_pci_clear_resource(rtwdev, pdev); 4919 rtw89_pci_declaim_device(rtwdev, pdev); 4920 rtw89_core_deinit(rtwdev); 4921 rtw89_free_ieee80211_hw(rtwdev); 4922 } 4923 EXPORT_SYMBOL(rtw89_pci_remove); 4924 4925 void rtw89_pci_shutdown(struct pci_dev *pdev) 4926 { 4927 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 4928 struct rtw89_dev *rtwdev; 4929 4930 if (!hw) 4931 return; 4932 4933 rtwdev = hw->priv; 4934 set_bit(RTW89_FLAG_SHUTDOWN, rtwdev->flags); 4935 } 4936 EXPORT_SYMBOL(rtw89_pci_shutdown); 4937 4938 MODULE_AUTHOR("Realtek Corporation"); 4939 MODULE_DESCRIPTION("Realtek PCI 802.11ax wireless driver"); 4940 MODULE_LICENSE("Dual BSD/GPL"); 4941