1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4 * Copyright (c) 2014, Synopsys, Inc.
5 * All rights reserved
6 */
7
8 #include <linux/phy.h>
9 #include <linux/mdio.h>
10 #include <linux/clk.h>
11 #include <linux/bitrev.h>
12 #include <linux/crc32.h>
13 #include <linux/crc32poly.h>
14 #include <linux/pci.h>
15
16 #include "xgbe.h"
17 #include "xgbe-common.h"
18 #include "xgbe-smn.h"
19
xgbe_get_max_frame(struct xgbe_prv_data * pdata)20 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
21 {
22 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
23 }
24
xgbe_usec_to_riwt(struct xgbe_prv_data * pdata,unsigned int usec)25 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
26 unsigned int usec)
27 {
28 unsigned long rate;
29 unsigned int ret;
30
31 DBGPR("-->xgbe_usec_to_riwt\n");
32
33 rate = pdata->sysclk_rate;
34
35 /*
36 * Convert the input usec value to the watchdog timer value. Each
37 * watchdog timer value is equivalent to 256 clock cycles.
38 * Calculate the required value as:
39 * ( usec * ( system_clock_mhz / 10^6 ) / 256
40 */
41 ret = (usec * (rate / 1000000)) / 256;
42
43 DBGPR("<--xgbe_usec_to_riwt\n");
44
45 return ret;
46 }
47
xgbe_riwt_to_usec(struct xgbe_prv_data * pdata,unsigned int riwt)48 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
49 unsigned int riwt)
50 {
51 unsigned long rate;
52 unsigned int ret;
53
54 DBGPR("-->xgbe_riwt_to_usec\n");
55
56 rate = pdata->sysclk_rate;
57
58 /*
59 * Convert the input watchdog timer value to the usec value. Each
60 * watchdog timer value is equivalent to 256 clock cycles.
61 * Calculate the required value as:
62 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
63 */
64 ret = (riwt * 256) / (rate / 1000000);
65
66 DBGPR("<--xgbe_riwt_to_usec\n");
67
68 return ret;
69 }
70
xgbe_config_pbl_val(struct xgbe_prv_data * pdata)71 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata)
72 {
73 unsigned int pblx8, pbl;
74 unsigned int i;
75
76 pblx8 = DMA_PBL_X8_DISABLE;
77 pbl = pdata->pbl;
78
79 if (pdata->pbl > 32) {
80 pblx8 = DMA_PBL_X8_ENABLE;
81 pbl >>= 3;
82 }
83
84 for (i = 0; i < pdata->channel_count; i++) {
85 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8,
86 pblx8);
87
88 if (pdata->channel[i]->tx_ring)
89 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR,
90 PBL, pbl);
91
92 if (pdata->channel[i]->rx_ring)
93 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR,
94 PBL, pbl);
95 }
96
97 return 0;
98 }
99
xgbe_config_osp_mode(struct xgbe_prv_data * pdata)100 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
101 {
102 unsigned int i;
103
104 for (i = 0; i < pdata->channel_count; i++) {
105 if (!pdata->channel[i]->tx_ring)
106 break;
107
108 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP,
109 pdata->tx_osp_mode);
110 }
111
112 return 0;
113 }
114
xgbe_config_rsf_mode(struct xgbe_prv_data * pdata,unsigned int val)115 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
116 {
117 unsigned int i;
118
119 for (i = 0; i < pdata->rx_q_count; i++)
120 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
121
122 return 0;
123 }
124
xgbe_config_tsf_mode(struct xgbe_prv_data * pdata,unsigned int val)125 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
126 {
127 unsigned int i;
128
129 for (i = 0; i < pdata->tx_q_count; i++)
130 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
131
132 return 0;
133 }
134
xgbe_config_rx_threshold(struct xgbe_prv_data * pdata,unsigned int val)135 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
136 unsigned int val)
137 {
138 unsigned int i;
139
140 for (i = 0; i < pdata->rx_q_count; i++)
141 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
142
143 return 0;
144 }
145
xgbe_config_tx_threshold(struct xgbe_prv_data * pdata,unsigned int val)146 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
147 unsigned int val)
148 {
149 unsigned int i;
150
151 for (i = 0; i < pdata->tx_q_count; i++)
152 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
153
154 return 0;
155 }
156
xgbe_config_rx_coalesce(struct xgbe_prv_data * pdata)157 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
158 {
159 unsigned int i;
160
161 for (i = 0; i < pdata->channel_count; i++) {
162 if (!pdata->channel[i]->rx_ring)
163 break;
164
165 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT,
166 pdata->rx_riwt);
167 }
168
169 return 0;
170 }
171
xgbe_config_tx_coalesce(struct xgbe_prv_data * pdata)172 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
173 {
174 return 0;
175 }
176
xgbe_config_rx_buffer_size(struct xgbe_prv_data * pdata)177 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
178 {
179 unsigned int i;
180
181 for (i = 0; i < pdata->channel_count; i++) {
182 if (!pdata->channel[i]->rx_ring)
183 break;
184
185 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ,
186 pdata->rx_buf_size);
187 }
188 }
189
xgbe_config_tso_mode(struct xgbe_prv_data * pdata)190 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
191 {
192 unsigned int i;
193
194 for (i = 0; i < pdata->channel_count; i++) {
195 if (!pdata->channel[i]->tx_ring)
196 break;
197
198 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1);
199 }
200 }
201
xgbe_config_sph_mode(struct xgbe_prv_data * pdata)202 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
203 {
204 unsigned int i;
205
206 for (i = 0; i < pdata->channel_count; i++) {
207 if (!pdata->channel[i]->rx_ring)
208 break;
209
210 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1);
211 }
212
213 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
214 pdata->sph = true;
215 }
216
xgbe_disable_sph_mode(struct xgbe_prv_data * pdata)217 static void xgbe_disable_sph_mode(struct xgbe_prv_data *pdata)
218 {
219 unsigned int i;
220
221 for (i = 0; i < pdata->channel_count; i++) {
222 if (!pdata->channel[i]->rx_ring)
223 break;
224
225 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 0);
226 }
227 pdata->sph = false;
228 }
229
xgbe_write_rss_reg(struct xgbe_prv_data * pdata,unsigned int type,unsigned int index,unsigned int val)230 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
231 unsigned int index, unsigned int val)
232 {
233 unsigned int wait;
234 int ret = 0;
235
236 mutex_lock(&pdata->rss_mutex);
237
238 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
239 ret = -EBUSY;
240 goto unlock;
241 }
242
243 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
244
245 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
246 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
247 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
248 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
249
250 wait = 1000;
251 while (wait--) {
252 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
253 goto unlock;
254
255 usleep_range(1000, 1500);
256 }
257
258 ret = -EBUSY;
259
260 unlock:
261 mutex_unlock(&pdata->rss_mutex);
262
263 return ret;
264 }
265
xgbe_write_rss_hash_key(struct xgbe_prv_data * pdata)266 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
267 {
268 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
269 unsigned int *key = (unsigned int *)&pdata->rss_key;
270 int ret;
271
272 while (key_regs--) {
273 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
274 key_regs, *key++);
275 if (ret)
276 return ret;
277 }
278
279 return 0;
280 }
281
xgbe_write_rss_lookup_table(struct xgbe_prv_data * pdata)282 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
283 {
284 unsigned int i;
285 int ret;
286
287 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
288 ret = xgbe_write_rss_reg(pdata,
289 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
290 pdata->rss_table[i]);
291 if (ret)
292 return ret;
293 }
294
295 return 0;
296 }
297
xgbe_set_rss_hash_key(struct xgbe_prv_data * pdata,const u8 * key)298 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
299 {
300 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
301
302 return xgbe_write_rss_hash_key(pdata);
303 }
304
xgbe_set_rss_lookup_table(struct xgbe_prv_data * pdata,const u32 * table)305 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
306 const u32 *table)
307 {
308 unsigned int i;
309
310 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
311 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
312
313 return xgbe_write_rss_lookup_table(pdata);
314 }
315
xgbe_enable_rss(struct xgbe_prv_data * pdata)316 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
317 {
318 int ret;
319
320 if (!pdata->hw_feat.rss)
321 return -EOPNOTSUPP;
322
323 /* Program the hash key */
324 ret = xgbe_write_rss_hash_key(pdata);
325 if (ret)
326 return ret;
327
328 /* Program the lookup table */
329 ret = xgbe_write_rss_lookup_table(pdata);
330 if (ret)
331 return ret;
332
333 /* Set the RSS options */
334 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
335
336 /* Enable RSS */
337 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
338
339 return 0;
340 }
341
xgbe_disable_rss(struct xgbe_prv_data * pdata)342 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
343 {
344 if (!pdata->hw_feat.rss)
345 return -EOPNOTSUPP;
346
347 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
348
349 return 0;
350 }
351
xgbe_config_rss(struct xgbe_prv_data * pdata)352 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
353 {
354 int ret;
355
356 if (!pdata->hw_feat.rss)
357 return;
358
359 if (pdata->netdev->features & NETIF_F_RXHASH)
360 ret = xgbe_enable_rss(pdata);
361 else
362 ret = xgbe_disable_rss(pdata);
363
364 if (ret)
365 netdev_err(pdata->netdev,
366 "error configuring RSS, RSS disabled\n");
367 }
368
xgbe_is_pfc_queue(struct xgbe_prv_data * pdata,unsigned int queue)369 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
370 unsigned int queue)
371 {
372 unsigned int prio, tc;
373
374 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
375 /* Does this queue handle the priority? */
376 if (pdata->prio2q_map[prio] != queue)
377 continue;
378
379 /* Get the Traffic Class for this priority */
380 tc = pdata->ets->prio_tc[prio];
381
382 /* Check if PFC is enabled for this traffic class */
383 if (pdata->pfc->pfc_en & (1 << tc))
384 return true;
385 }
386
387 return false;
388 }
389
xgbe_set_vxlan_id(struct xgbe_prv_data * pdata)390 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata)
391 {
392 /* Program the VXLAN port */
393 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port);
394
395 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n",
396 pdata->vxlan_port);
397 }
398
xgbe_enable_vxlan(struct xgbe_prv_data * pdata)399 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata)
400 {
401 if (!pdata->hw_feat.vxn)
402 return;
403
404 /* Program the VXLAN port */
405 xgbe_set_vxlan_id(pdata);
406
407 /* Allow for IPv6/UDP zero-checksum VXLAN packets */
408 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1);
409
410 /* Enable VXLAN tunneling mode */
411 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0);
412 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1);
413
414 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n");
415 }
416
xgbe_disable_vxlan(struct xgbe_prv_data * pdata)417 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata)
418 {
419 if (!pdata->hw_feat.vxn)
420 return;
421
422 /* Disable tunneling mode */
423 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0);
424
425 /* Clear IPv6/UDP zero-checksum VXLAN packets setting */
426 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0);
427
428 /* Clear the VXLAN port */
429 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0);
430
431 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n");
432 }
433
xgbe_get_fc_queue_count(struct xgbe_prv_data * pdata)434 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata)
435 {
436 unsigned int max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
437
438 /* From MAC ver 30H the TFCR is per priority, instead of per queue */
439 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)
440 return max_q_count;
441 else
442 return min_t(unsigned int, pdata->tx_q_count, max_q_count);
443 }
444
xgbe_disable_tx_flow_control(struct xgbe_prv_data * pdata)445 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
446 {
447 unsigned int reg, reg_val;
448 unsigned int i, q_count;
449
450 /* Clear MTL flow control */
451 for (i = 0; i < pdata->rx_q_count; i++)
452 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
453
454 /* Clear MAC flow control */
455 q_count = xgbe_get_fc_queue_count(pdata);
456 reg = MAC_Q0TFCR;
457 for (i = 0; i < q_count; i++) {
458 reg_val = XGMAC_IOREAD(pdata, reg);
459 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
460 XGMAC_IOWRITE(pdata, reg, reg_val);
461
462 reg += MAC_QTFCR_INC;
463 }
464
465 return 0;
466 }
467
xgbe_enable_tx_flow_control(struct xgbe_prv_data * pdata)468 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
469 {
470 struct ieee_pfc *pfc = pdata->pfc;
471 struct ieee_ets *ets = pdata->ets;
472 unsigned int reg, reg_val;
473 unsigned int i, q_count;
474
475 /* Set MTL flow control */
476 for (i = 0; i < pdata->rx_q_count; i++) {
477 unsigned int ehfc = 0;
478
479 if (pdata->rx_rfd[i]) {
480 /* Flow control thresholds are established */
481 if (pfc && ets) {
482 if (xgbe_is_pfc_queue(pdata, i))
483 ehfc = 1;
484 } else {
485 ehfc = 1;
486 }
487 }
488
489 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
490
491 netif_dbg(pdata, drv, pdata->netdev,
492 "flow control %s for RXq%u\n",
493 ehfc ? "enabled" : "disabled", i);
494 }
495
496 /* Set MAC flow control */
497 q_count = xgbe_get_fc_queue_count(pdata);
498 reg = MAC_Q0TFCR;
499 for (i = 0; i < q_count; i++) {
500 reg_val = XGMAC_IOREAD(pdata, reg);
501
502 /* Enable transmit flow control */
503 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
504 /* Set pause time */
505 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
506
507 XGMAC_IOWRITE(pdata, reg, reg_val);
508
509 reg += MAC_QTFCR_INC;
510 }
511
512 return 0;
513 }
514
xgbe_disable_rx_flow_control(struct xgbe_prv_data * pdata)515 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
516 {
517 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
518
519 return 0;
520 }
521
xgbe_enable_rx_flow_control(struct xgbe_prv_data * pdata)522 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
523 {
524 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
525
526 return 0;
527 }
528
xgbe_config_tx_flow_control(struct xgbe_prv_data * pdata)529 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
530 {
531 struct ieee_pfc *pfc = pdata->pfc;
532
533 if (pdata->tx_pause || (pfc && pfc->pfc_en))
534 xgbe_enable_tx_flow_control(pdata);
535 else
536 xgbe_disable_tx_flow_control(pdata);
537
538 return 0;
539 }
540
xgbe_config_rx_flow_control(struct xgbe_prv_data * pdata)541 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
542 {
543 struct ieee_pfc *pfc = pdata->pfc;
544
545 if (pdata->rx_pause || (pfc && pfc->pfc_en))
546 xgbe_enable_rx_flow_control(pdata);
547 else
548 xgbe_disable_rx_flow_control(pdata);
549
550 return 0;
551 }
552
xgbe_config_flow_control(struct xgbe_prv_data * pdata)553 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
554 {
555 struct ieee_pfc *pfc = pdata->pfc;
556
557 xgbe_config_tx_flow_control(pdata);
558 xgbe_config_rx_flow_control(pdata);
559
560 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
561 (pfc && pfc->pfc_en) ? 1 : 0);
562 }
563
xgbe_enable_dma_interrupts(struct xgbe_prv_data * pdata)564 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
565 {
566 struct xgbe_channel *channel;
567 unsigned int i, ver;
568
569 /* Set the interrupt mode if supported */
570 if (pdata->channel_irq_mode)
571 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM,
572 pdata->channel_irq_mode);
573
574 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
575
576 for (i = 0; i < pdata->channel_count; i++) {
577 channel = pdata->channel[i];
578
579 /* Clear all the interrupts which are set */
580 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR,
581 XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
582
583 /* Clear all interrupt enable bits */
584 channel->curr_ier = 0;
585
586 /* Enable following interrupts
587 * NIE - Normal Interrupt Summary Enable
588 * AIE - Abnormal Interrupt Summary Enable
589 * FBEE - Fatal Bus Error Enable
590 */
591 if (ver < 0x21) {
592 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
593 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
594 } else {
595 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
596 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
597 }
598 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
599
600 if (channel->tx_ring) {
601 /* Enable the following Tx interrupts
602 * TIE - Transmit Interrupt Enable (unless using
603 * per channel interrupts in edge triggered
604 * mode)
605 */
606 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
607 XGMAC_SET_BITS(channel->curr_ier,
608 DMA_CH_IER, TIE, 1);
609 }
610 if (channel->rx_ring) {
611 /* Enable following Rx interrupts
612 * RBUE - Receive Buffer Unavailable Enable
613 * RIE - Receive Interrupt Enable (unless using
614 * per channel interrupts in edge triggered
615 * mode)
616 */
617 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
618 if (!pdata->per_channel_irq || pdata->channel_irq_mode)
619 XGMAC_SET_BITS(channel->curr_ier,
620 DMA_CH_IER, RIE, 1);
621 }
622
623 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
624 }
625 }
626
xgbe_enable_mtl_interrupts(struct xgbe_prv_data * pdata)627 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
628 {
629 unsigned int mtl_q_isr;
630 unsigned int q_count, i;
631
632 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
633 for (i = 0; i < q_count; i++) {
634 /* Clear all the interrupts which are set */
635 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
636 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
637
638 /* No MTL interrupts to be enabled */
639 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
640 }
641 }
642
xgbe_enable_mac_interrupts(struct xgbe_prv_data * pdata)643 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
644 {
645 unsigned int mac_ier = 0;
646
647 /* Enable Timestamp interrupt */
648 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
649
650 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
651
652 /* Enable all counter interrupts */
653 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
654 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
655
656 /* Enable MDIO single command completion interrupt */
657 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1);
658 }
659
xgbe_enable_ecc_interrupts(struct xgbe_prv_data * pdata)660 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
661 {
662 unsigned int ecc_isr, ecc_ier = 0;
663
664 if (!pdata->vdata->ecc_support)
665 return;
666
667 /* Clear all the interrupts which are set */
668 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
669 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
670
671 /* Enable ECC interrupts */
672 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1);
673 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1);
674 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1);
675 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1);
676 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1);
677 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1);
678
679 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
680 }
681
xgbe_disable_ecc_ded(struct xgbe_prv_data * pdata)682 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
683 {
684 unsigned int ecc_ier;
685
686 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
687
688 /* Disable ECC DED interrupts */
689 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0);
690 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0);
691 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0);
692
693 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
694 }
695
xgbe_disable_ecc_sec(struct xgbe_prv_data * pdata,enum xgbe_ecc_sec sec)696 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
697 enum xgbe_ecc_sec sec)
698 {
699 unsigned int ecc_ier;
700
701 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
702
703 /* Disable ECC SEC interrupt */
704 switch (sec) {
705 case XGBE_ECC_SEC_TX:
706 XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0);
707 break;
708 case XGBE_ECC_SEC_RX:
709 XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0);
710 break;
711 case XGBE_ECC_SEC_DESC:
712 XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0);
713 break;
714 }
715
716 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
717 }
718
xgbe_set_speed(struct xgbe_prv_data * pdata,int speed)719 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
720 {
721 unsigned int ss, ver;
722
723 switch (speed) {
724 case SPEED_10:
725 ss = XGBE_MAC_SS_10M;
726 break;
727 case SPEED_1000:
728 ss = XGBE_MAC_SS_1G;
729 break;
730 case SPEED_2500:
731 /* P100a uses XGMII mode for 2.5G, older platforms use GMII */
732 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
733 if (ver == XGBE_MAC_VER_33)
734 ss = XGBE_MAC_SS_2_5G_XGMII;
735 else
736 ss = XGBE_MAC_SS_2_5G_GMII;
737 break;
738 case SPEED_10000:
739 ss = XGBE_MAC_SS_10G;
740 break;
741 default:
742 return -EINVAL;
743 }
744
745 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss)
746 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss);
747
748 return 0;
749 }
750
xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data * pdata)751 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
752 {
753 /* Put the VLAN tag in the Rx descriptor */
754 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
755
756 /* Don't check the VLAN type */
757 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
758
759 /* Check only C-TAG (0x8100) packets */
760 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
761
762 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
763 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
764
765 /* Enable VLAN tag stripping */
766 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
767
768 return 0;
769 }
770
xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data * pdata)771 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
772 {
773 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
774
775 return 0;
776 }
777
xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data * pdata)778 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
779 {
780 /* Enable VLAN filtering */
781 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
782
783 /* Enable VLAN Hash Table filtering */
784 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
785
786 /* Disable VLAN tag inverse matching */
787 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
788
789 /* Only filter on the lower 12-bits of the VLAN tag */
790 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
791
792 /* In order for the VLAN Hash Table filtering to be effective,
793 * the VLAN tag identifier in the VLAN Tag Register must not
794 * be zero. Set the VLAN tag identifier to "1" to enable the
795 * VLAN Hash Table filtering. This implies that a VLAN tag of
796 * 1 will always pass filtering.
797 */
798 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
799
800 return 0;
801 }
802
xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data * pdata)803 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
804 {
805 /* Disable VLAN filtering */
806 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
807
808 return 0;
809 }
810
xgbe_vid_crc32_le(__le16 vid_le)811 static u32 xgbe_vid_crc32_le(__le16 vid_le)
812 {
813 u32 crc = ~0;
814 u32 temp = 0;
815 unsigned char *data = (unsigned char *)&vid_le;
816 unsigned char data_byte = 0;
817 int i, bits;
818
819 bits = get_bitmask_order(VLAN_VID_MASK);
820 for (i = 0; i < bits; i++) {
821 if ((i % 8) == 0)
822 data_byte = data[i / 8];
823
824 temp = ((crc & 1) ^ data_byte) & 1;
825 crc >>= 1;
826 data_byte >>= 1;
827
828 if (temp)
829 crc ^= CRC32_POLY_LE;
830 }
831
832 return crc;
833 }
834
xgbe_update_vlan_hash_table(struct xgbe_prv_data * pdata)835 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
836 {
837 u32 crc;
838 u16 vid;
839 __le16 vid_le;
840 u16 vlan_hash_table = 0;
841
842 /* Generate the VLAN Hash Table value */
843 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
844 /* Get the CRC32 value of the VLAN ID */
845 vid_le = cpu_to_le16(vid);
846 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
847
848 vlan_hash_table |= (1 << crc);
849 }
850
851 /* Set the VLAN Hash Table filtering register */
852 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
853
854 return 0;
855 }
856
xgbe_set_promiscuous_mode(struct xgbe_prv_data * pdata,unsigned int enable)857 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
858 unsigned int enable)
859 {
860 unsigned int val = enable ? 1 : 0;
861
862 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
863 return 0;
864
865 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
866 enable ? "entering" : "leaving");
867 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
868
869 /* Hardware will still perform VLAN filtering in promiscuous mode */
870 if (enable) {
871 xgbe_disable_rx_vlan_filtering(pdata);
872 } else {
873 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
874 xgbe_enable_rx_vlan_filtering(pdata);
875 }
876
877 return 0;
878 }
879
xgbe_set_all_multicast_mode(struct xgbe_prv_data * pdata,unsigned int enable)880 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
881 unsigned int enable)
882 {
883 unsigned int val = enable ? 1 : 0;
884
885 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
886 return 0;
887
888 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
889 enable ? "entering" : "leaving");
890 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
891
892 return 0;
893 }
894
xgbe_set_mac_reg(struct xgbe_prv_data * pdata,struct netdev_hw_addr * ha,unsigned int * mac_reg)895 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
896 struct netdev_hw_addr *ha, unsigned int *mac_reg)
897 {
898 unsigned int mac_addr_hi, mac_addr_lo;
899 u8 *mac_addr;
900
901 mac_addr_lo = 0;
902 mac_addr_hi = 0;
903
904 if (ha) {
905 mac_addr = (u8 *)&mac_addr_lo;
906 mac_addr[0] = ha->addr[0];
907 mac_addr[1] = ha->addr[1];
908 mac_addr[2] = ha->addr[2];
909 mac_addr[3] = ha->addr[3];
910 mac_addr = (u8 *)&mac_addr_hi;
911 mac_addr[0] = ha->addr[4];
912 mac_addr[1] = ha->addr[5];
913
914 netif_dbg(pdata, drv, pdata->netdev,
915 "adding mac address %pM at %#x\n",
916 ha->addr, *mac_reg);
917
918 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
919 }
920
921 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
922 *mac_reg += MAC_MACA_INC;
923 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
924 *mac_reg += MAC_MACA_INC;
925 }
926
xgbe_set_mac_addn_addrs(struct xgbe_prv_data * pdata)927 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
928 {
929 struct net_device *netdev = pdata->netdev;
930 struct netdev_hw_addr *ha;
931 unsigned int mac_reg;
932 unsigned int addn_macs;
933
934 mac_reg = MAC_MACA1HR;
935 addn_macs = pdata->hw_feat.addn_mac;
936
937 if (netdev_uc_count(netdev) > addn_macs) {
938 xgbe_set_promiscuous_mode(pdata, 1);
939 } else {
940 netdev_for_each_uc_addr(ha, netdev) {
941 xgbe_set_mac_reg(pdata, ha, &mac_reg);
942 addn_macs--;
943 }
944
945 if (netdev_mc_count(netdev) > addn_macs) {
946 xgbe_set_all_multicast_mode(pdata, 1);
947 } else {
948 netdev_for_each_mc_addr(ha, netdev) {
949 xgbe_set_mac_reg(pdata, ha, &mac_reg);
950 addn_macs--;
951 }
952 }
953 }
954
955 /* Clear remaining additional MAC address entries */
956 while (addn_macs--)
957 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
958 }
959
xgbe_set_mac_hash_table(struct xgbe_prv_data * pdata)960 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
961 {
962 struct net_device *netdev = pdata->netdev;
963 struct netdev_hw_addr *ha;
964 unsigned int hash_reg;
965 unsigned int hash_table_shift, hash_table_count;
966 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
967 u32 crc;
968 unsigned int i;
969
970 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
971 hash_table_count = pdata->hw_feat.hash_table_size / 32;
972 memset(hash_table, 0, sizeof(hash_table));
973
974 /* Build the MAC Hash Table register values */
975 netdev_for_each_uc_addr(ha, netdev) {
976 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
977 crc >>= hash_table_shift;
978 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
979 }
980
981 netdev_for_each_mc_addr(ha, netdev) {
982 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
983 crc >>= hash_table_shift;
984 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
985 }
986
987 /* Set the MAC Hash Table registers */
988 hash_reg = MAC_HTR0;
989 for (i = 0; i < hash_table_count; i++) {
990 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
991 hash_reg += MAC_HTR_INC;
992 }
993 }
994
xgbe_add_mac_addresses(struct xgbe_prv_data * pdata)995 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
996 {
997 if (pdata->hw_feat.hash_table_size)
998 xgbe_set_mac_hash_table(pdata);
999 else
1000 xgbe_set_mac_addn_addrs(pdata);
1001
1002 return 0;
1003 }
1004
xgbe_set_mac_address(struct xgbe_prv_data * pdata,const u8 * addr)1005 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr)
1006 {
1007 unsigned int mac_addr_hi, mac_addr_lo;
1008
1009 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
1010 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
1011 (addr[1] << 8) | (addr[0] << 0);
1012
1013 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
1014 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
1015
1016 return 0;
1017 }
1018
xgbe_config_rx_mode(struct xgbe_prv_data * pdata)1019 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
1020 {
1021 struct net_device *netdev = pdata->netdev;
1022 unsigned int pr_mode, am_mode;
1023
1024 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1025 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1026
1027 xgbe_set_promiscuous_mode(pdata, pr_mode);
1028 xgbe_set_all_multicast_mode(pdata, am_mode);
1029
1030 xgbe_add_mac_addresses(pdata);
1031
1032 return 0;
1033 }
1034
xgbe_clr_gpio(struct xgbe_prv_data * pdata,unsigned int gpio)1035 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1036 {
1037 unsigned int reg;
1038
1039 if (gpio > 15)
1040 return -EINVAL;
1041
1042 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1043
1044 reg &= ~(1 << (gpio + 16));
1045 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1046
1047 return 0;
1048 }
1049
xgbe_set_gpio(struct xgbe_prv_data * pdata,unsigned int gpio)1050 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio)
1051 {
1052 unsigned int reg;
1053
1054 if (gpio > 15)
1055 return -EINVAL;
1056
1057 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR);
1058
1059 reg |= (1 << (gpio + 16));
1060 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg);
1061
1062 return 0;
1063 }
1064
xgbe_get_mmd_address(struct xgbe_prv_data * pdata,int mmd_reg)1065 static unsigned int xgbe_get_mmd_address(struct xgbe_prv_data *pdata,
1066 int mmd_reg)
1067 {
1068 return (mmd_reg & XGBE_ADDR_C45) ?
1069 mmd_reg & ~XGBE_ADDR_C45 :
1070 (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
1071 }
1072
xgbe_get_pcs_index_and_offset(struct xgbe_prv_data * pdata,unsigned int mmd_address,unsigned int * index,unsigned int * offset)1073 static void xgbe_get_pcs_index_and_offset(struct xgbe_prv_data *pdata,
1074 unsigned int mmd_address,
1075 unsigned int *index,
1076 unsigned int *offset)
1077 {
1078 unsigned int ver;
1079
1080 /* The PCS registers are accessed using mmio. The underlying
1081 * management interface uses indirect addressing to access the MMD
1082 * register sets. This requires accessing of the PCS register in two
1083 * phases, an address phase and a data phase.
1084 *
1085 * The mmio interface is based on 16-bit offsets and values. All
1086 * register offsets must therefore be adjusted by left shifting the
1087 * offset 1 bit and reading 16 bits of data.
1088 */
1089 mmd_address <<= 1;
1090 *index = mmd_address & ~pdata->xpcs_window_mask;
1091
1092 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);
1093
1094 /* The P100a platform uses a different memory mapping scheme for XPCS
1095 * register access. The offset calculation differs between platforms:
1096 *
1097 * For P100a platforms: The offset is calculated by adding the
1098 * mmd_address to the xpcs_window and then applying the xpcs_window_mask
1099 * For older platforms: The offset is calculated by applying the
1100 * xpcs_window_mask to the mmd_address and then adding it to the
1101 * xpcs_window.
1102 *
1103 * This is critical because using the wrong calculation causes register
1104 * accesses to target the wrong registers, leading to incorrect behavior
1105 */
1106 if (ver == XGBE_MAC_VER_33)
1107 *offset = (pdata->xpcs_window + mmd_address) &
1108 pdata->xpcs_window_mask;
1109 else
1110 *offset = pdata->xpcs_window +
1111 (mmd_address & pdata->xpcs_window_mask);
1112 }
1113
xgbe_read_mmd_regs_v3(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)1114 static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
1115 int mmd_reg)
1116 {
1117 unsigned int mmd_address, index, offset;
1118 u32 smn_address;
1119 int mmd_data;
1120 int ret;
1121
1122 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1123
1124 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
1125
1126 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg;
1127 ret = amd_smn_write(0, smn_address, index);
1128 if (ret)
1129 return ret;
1130
1131 ret = amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
1132 if (ret)
1133 return ret;
1134
1135 mmd_data = (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) :
1136 FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
1137
1138 return mmd_data;
1139 }
1140
xgbe_write_mmd_regs_v3(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)1141 static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad,
1142 int mmd_reg, int mmd_data)
1143 {
1144 unsigned int pci_mmd_data, hi_mask, lo_mask;
1145 unsigned int mmd_address, index, offset;
1146 struct pci_dev *dev;
1147 u32 smn_address;
1148 int ret;
1149
1150 dev = pdata->pcidev;
1151 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1152
1153 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
1154
1155 smn_address = pdata->smn_base + pdata->xpcs_window_sel_reg;
1156 ret = amd_smn_write(0, smn_address, index);
1157 if (ret) {
1158 pci_err(dev, "Failed to write data 0x%x\n", index);
1159 return;
1160 }
1161
1162 ret = amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data);
1163 if (ret) {
1164 pci_err(dev, "Failed to read data\n");
1165 return;
1166 }
1167
1168 if (offset % 4) {
1169 hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data);
1170 lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, pci_mmd_data);
1171 } else {
1172 hi_mask = FIELD_PREP(XGBE_GEN_HI_MASK,
1173 FIELD_GET(XGBE_GEN_HI_MASK, pci_mmd_data));
1174 lo_mask = FIELD_GET(XGBE_GEN_LO_MASK, mmd_data);
1175 }
1176
1177 pci_mmd_data = hi_mask | lo_mask;
1178
1179 ret = amd_smn_write(0, smn_address, index);
1180 if (ret) {
1181 pci_err(dev, "Failed to write data 0x%x\n", index);
1182 return;
1183 }
1184
1185 ret = amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data);
1186 if (ret) {
1187 pci_err(dev, "Failed to write data 0x%x\n", pci_mmd_data);
1188 return;
1189 }
1190 }
1191
xgbe_read_mmd_regs_v2(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)1192 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1193 int mmd_reg)
1194 {
1195 unsigned int mmd_address, index, offset;
1196 unsigned long flags;
1197 int mmd_data;
1198
1199 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1200
1201 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
1202
1203 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1204 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1205 mmd_data = XPCS16_IOREAD(pdata, offset);
1206 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1207
1208 return mmd_data;
1209 }
1210
xgbe_write_mmd_regs_v2(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)1211 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad,
1212 int mmd_reg, int mmd_data)
1213 {
1214 unsigned long flags;
1215 unsigned int mmd_address, index, offset;
1216
1217 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1218
1219 xgbe_get_pcs_index_and_offset(pdata, mmd_address, &index, &offset);
1220
1221 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1222 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index);
1223 XPCS16_IOWRITE(pdata, offset, mmd_data);
1224 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1225 }
1226
xgbe_read_mmd_regs_v1(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)1227 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1228 int mmd_reg)
1229 {
1230 unsigned long flags;
1231 unsigned int mmd_address;
1232 int mmd_data;
1233
1234 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1235
1236 /* The PCS registers are accessed using mmio. The underlying APB3
1237 * management interface uses indirect addressing to access the MMD
1238 * register sets. This requires accessing of the PCS register in two
1239 * phases, an address phase and a data phase.
1240 *
1241 * The mmio interface is based on 32-bit offsets and values. All
1242 * register offsets must therefore be adjusted by left shifting the
1243 * offset 2 bits and reading 32 bits of data.
1244 */
1245 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1246 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1247 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2);
1248 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1249
1250 return mmd_data;
1251 }
1252
xgbe_write_mmd_regs_v1(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)1253 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad,
1254 int mmd_reg, int mmd_data)
1255 {
1256 unsigned int mmd_address;
1257 unsigned long flags;
1258
1259 mmd_address = xgbe_get_mmd_address(pdata, mmd_reg);
1260
1261 /* The PCS registers are accessed using mmio. The underlying APB3
1262 * management interface uses indirect addressing to access the MMD
1263 * register sets. This requires accessing of the PCS register in two
1264 * phases, an address phase and a data phase.
1265 *
1266 * The mmio interface is based on 32-bit offsets and values. All
1267 * register offsets must therefore be adjusted by left shifting the
1268 * offset 2 bits and writing 32 bits of data.
1269 */
1270 spin_lock_irqsave(&pdata->xpcs_lock, flags);
1271 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8);
1272 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
1273 spin_unlock_irqrestore(&pdata->xpcs_lock, flags);
1274 }
1275
xgbe_read_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)1276 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1277 int mmd_reg)
1278 {
1279 switch (pdata->vdata->xpcs_access) {
1280 case XGBE_XPCS_ACCESS_V1:
1281 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg);
1282
1283 case XGBE_XPCS_ACCESS_V2:
1284 default:
1285 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg);
1286
1287 case XGBE_XPCS_ACCESS_V3:
1288 return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg);
1289 }
1290 }
1291
xgbe_write_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)1292 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
1293 int mmd_reg, int mmd_data)
1294 {
1295 switch (pdata->vdata->xpcs_access) {
1296 case XGBE_XPCS_ACCESS_V1:
1297 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data);
1298
1299 case XGBE_XPCS_ACCESS_V3:
1300 return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data);
1301
1302 case XGBE_XPCS_ACCESS_V2:
1303 default:
1304 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data);
1305 }
1306 }
1307
xgbe_create_mdio_sca_c22(int port,int reg)1308 static unsigned int xgbe_create_mdio_sca_c22(int port, int reg)
1309 {
1310 unsigned int mdio_sca;
1311
1312 mdio_sca = 0;
1313 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
1314 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port);
1315
1316 return mdio_sca;
1317 }
1318
xgbe_create_mdio_sca_c45(int port,unsigned int da,int reg)1319 static unsigned int xgbe_create_mdio_sca_c45(int port, unsigned int da, int reg)
1320 {
1321 unsigned int mdio_sca;
1322
1323 mdio_sca = 0;
1324 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
1325 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port);
1326 XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da);
1327
1328 return mdio_sca;
1329 }
1330
xgbe_write_ext_mii_regs(struct xgbe_prv_data * pdata,unsigned int mdio_sca,u16 val)1331 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata,
1332 unsigned int mdio_sca, u16 val)
1333 {
1334 unsigned int mdio_sccd;
1335
1336 reinit_completion(&pdata->mdio_complete);
1337
1338 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1339
1340 mdio_sccd = 0;
1341 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
1342 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
1343 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
1344 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1345
1346 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1347 netdev_err(pdata->netdev, "mdio write operation timed out\n");
1348 return -ETIMEDOUT;
1349 }
1350
1351 return 0;
1352 }
1353
xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data * pdata,int addr,int reg,u16 val)1354 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr,
1355 int reg, u16 val)
1356 {
1357 unsigned int mdio_sca;
1358
1359 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg);
1360
1361 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val);
1362 }
1363
xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg,u16 val)1364 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr,
1365 int devad, int reg, u16 val)
1366 {
1367 unsigned int mdio_sca;
1368
1369 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg);
1370
1371 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val);
1372 }
1373
xgbe_read_ext_mii_regs(struct xgbe_prv_data * pdata,unsigned int mdio_sca)1374 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata,
1375 unsigned int mdio_sca)
1376 {
1377 unsigned int mdio_sccd;
1378
1379 reinit_completion(&pdata->mdio_complete);
1380
1381 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca);
1382
1383 mdio_sccd = 0;
1384 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
1385 XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
1386 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd);
1387
1388 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) {
1389 netdev_err(pdata->netdev, "mdio read operation timed out\n");
1390 return -ETIMEDOUT;
1391 }
1392
1393 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA);
1394 }
1395
xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data * pdata,int addr,int reg)1396 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr,
1397 int reg)
1398 {
1399 unsigned int mdio_sca;
1400
1401 mdio_sca = xgbe_create_mdio_sca_c22(addr, reg);
1402
1403 return xgbe_read_ext_mii_regs(pdata, mdio_sca);
1404 }
1405
xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data * pdata,int addr,int devad,int reg)1406 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr,
1407 int devad, int reg)
1408 {
1409 unsigned int mdio_sca;
1410
1411 mdio_sca = xgbe_create_mdio_sca_c45(addr, devad, reg);
1412
1413 return xgbe_read_ext_mii_regs(pdata, mdio_sca);
1414 }
1415
xgbe_set_ext_mii_mode(struct xgbe_prv_data * pdata,unsigned int port,enum xgbe_mdio_mode mode)1416 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port,
1417 enum xgbe_mdio_mode mode)
1418 {
1419 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);
1420
1421 switch (mode) {
1422 case XGBE_MDIO_MODE_CL22:
1423 if (port > XGMAC_MAX_C22_PORT)
1424 return -EINVAL;
1425 reg_val |= (1 << port);
1426 break;
1427 case XGBE_MDIO_MODE_CL45:
1428 break;
1429 default:
1430 return -EINVAL;
1431 }
1432
1433 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);
1434
1435 return 0;
1436 }
1437
xgbe_tx_complete(struct xgbe_ring_desc * rdesc)1438 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
1439 {
1440 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
1441 }
1442
xgbe_disable_rx_csum(struct xgbe_prv_data * pdata)1443 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
1444 {
1445 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
1446
1447 return 0;
1448 }
1449
xgbe_enable_rx_csum(struct xgbe_prv_data * pdata)1450 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
1451 {
1452 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
1453
1454 return 0;
1455 }
1456
xgbe_tx_desc_reset(struct xgbe_ring_data * rdata)1457 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1458 {
1459 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1460
1461 /* Reset the Tx descriptor
1462 * Set buffer 1 (lo) address to zero
1463 * Set buffer 1 (hi) address to zero
1464 * Reset all other control bits (IC, TTSE, B2L & B1L)
1465 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1466 */
1467 rdesc->desc0 = 0;
1468 rdesc->desc1 = 0;
1469 rdesc->desc2 = 0;
1470 rdesc->desc3 = 0;
1471
1472 /* Make sure ownership is written to the descriptor */
1473 dma_wmb();
1474 }
1475
xgbe_tx_desc_init(struct xgbe_channel * channel)1476 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1477 {
1478 struct xgbe_ring *ring = channel->tx_ring;
1479 struct xgbe_ring_data *rdata;
1480 int i;
1481 int start_index = ring->cur;
1482
1483 DBGPR("-->tx_desc_init\n");
1484
1485 /* Initialze all descriptors */
1486 for (i = 0; i < ring->rdesc_count; i++) {
1487 rdata = XGBE_GET_DESC_DATA(ring, i);
1488
1489 /* Initialize Tx descriptor */
1490 xgbe_tx_desc_reset(rdata);
1491 }
1492
1493 /* Update the total number of Tx descriptors */
1494 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1495
1496 /* Update the starting address of descriptor ring */
1497 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1498 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1499 upper_32_bits(rdata->rdesc_dma));
1500 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1501 lower_32_bits(rdata->rdesc_dma));
1502
1503 DBGPR("<--tx_desc_init\n");
1504 }
1505
xgbe_rx_desc_reset(struct xgbe_prv_data * pdata,struct xgbe_ring_data * rdata,unsigned int index)1506 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1507 struct xgbe_ring_data *rdata, unsigned int index)
1508 {
1509 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1510 unsigned int rx_usecs = pdata->rx_usecs;
1511 unsigned int rx_frames = pdata->rx_frames;
1512 unsigned int inte;
1513 dma_addr_t hdr_dma, buf_dma;
1514
1515 if (!rx_usecs && !rx_frames) {
1516 /* No coalescing, interrupt for every descriptor */
1517 inte = 1;
1518 } else {
1519 /* Set interrupt based on Rx frame coalescing setting */
1520 if (rx_frames && !((index + 1) % rx_frames))
1521 inte = 1;
1522 else
1523 inte = 0;
1524 }
1525
1526 /* Reset the Rx descriptor
1527 * Set buffer 1 (lo) address to header dma address (lo)
1528 * Set buffer 1 (hi) address to header dma address (hi)
1529 * Set buffer 2 (lo) address to buffer dma address (lo)
1530 * Set buffer 2 (hi) address to buffer dma address (hi) and
1531 * set control bits OWN and INTE
1532 */
1533 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off;
1534 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off;
1535 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma));
1536 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma));
1537 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma));
1538 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma));
1539
1540 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
1541
1542 /* Since the Rx DMA engine is likely running, make sure everything
1543 * is written to the descriptor(s) before setting the OWN bit
1544 * for the descriptor
1545 */
1546 dma_wmb();
1547
1548 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1549
1550 /* Make sure ownership is written to the descriptor */
1551 dma_wmb();
1552 }
1553
xgbe_rx_desc_init(struct xgbe_channel * channel)1554 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1555 {
1556 struct xgbe_prv_data *pdata = channel->pdata;
1557 struct xgbe_ring *ring = channel->rx_ring;
1558 struct xgbe_ring_data *rdata;
1559 unsigned int start_index = ring->cur;
1560 unsigned int i;
1561
1562 DBGPR("-->rx_desc_init\n");
1563
1564 /* Initialize all descriptors */
1565 for (i = 0; i < ring->rdesc_count; i++) {
1566 rdata = XGBE_GET_DESC_DATA(ring, i);
1567
1568 /* Initialize Rx descriptor */
1569 xgbe_rx_desc_reset(pdata, rdata, i);
1570 }
1571
1572 /* Update the total number of Rx descriptors */
1573 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1574
1575 /* Update the starting address of descriptor ring */
1576 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1577 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1578 upper_32_bits(rdata->rdesc_dma));
1579 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1580 lower_32_bits(rdata->rdesc_dma));
1581
1582 /* Update the Rx Descriptor Tail Pointer */
1583 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1584 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1585 lower_32_bits(rdata->rdesc_dma));
1586
1587 DBGPR("<--rx_desc_init\n");
1588 }
1589
xgbe_tx_start_xmit(struct xgbe_channel * channel,struct xgbe_ring * ring)1590 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1591 struct xgbe_ring *ring)
1592 {
1593 struct xgbe_prv_data *pdata = channel->pdata;
1594 struct xgbe_ring_data *rdata;
1595
1596 /* Make sure everything is written before the register write */
1597 wmb();
1598
1599 /* Issue a poll command to Tx DMA by writing address
1600 * of next immediate free descriptor */
1601 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1602 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1603 lower_32_bits(rdata->rdesc_dma));
1604
1605 /* Start the Tx timer */
1606 if (pdata->tx_usecs && !channel->tx_timer_active) {
1607 channel->tx_timer_active = 1;
1608 mod_timer(&channel->tx_timer,
1609 jiffies + usecs_to_jiffies(pdata->tx_usecs));
1610 }
1611
1612 ring->tx.xmit_more = 0;
1613 }
1614
xgbe_dev_xmit(struct xgbe_channel * channel)1615 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1616 {
1617 struct xgbe_prv_data *pdata = channel->pdata;
1618 struct xgbe_ring *ring = channel->tx_ring;
1619 struct xgbe_ring_data *rdata;
1620 struct xgbe_ring_desc *rdesc;
1621 struct xgbe_packet_data *packet = &ring->packet_data;
1622 unsigned int tx_packets, tx_bytes;
1623 unsigned int csum, tso, vlan, vxlan;
1624 unsigned int tso_context, vlan_context;
1625 unsigned int tx_set_ic;
1626 int start_index = ring->cur;
1627 int cur_index = ring->cur;
1628 int i;
1629
1630 DBGPR("-->xgbe_dev_xmit\n");
1631
1632 tx_packets = packet->tx_packets;
1633 tx_bytes = packet->tx_bytes;
1634
1635 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1636 CSUM_ENABLE);
1637 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1638 TSO_ENABLE);
1639 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1640 VLAN_CTAG);
1641 vxlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1642 VXLAN);
1643
1644 if (tso && (packet->mss != ring->tx.cur_mss))
1645 tso_context = 1;
1646 else
1647 tso_context = 0;
1648
1649 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1650 vlan_context = 1;
1651 else
1652 vlan_context = 0;
1653
1654 /* Determine if an interrupt should be generated for this Tx:
1655 * Interrupt:
1656 * - Tx frame count exceeds the frame count setting
1657 * - Addition of Tx frame count to the frame count since the
1658 * last interrupt was set exceeds the frame count setting
1659 * No interrupt:
1660 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1661 * - Addition of Tx frame count to the frame count since the
1662 * last interrupt was set does not exceed the frame count setting
1663 */
1664 ring->coalesce_count += tx_packets;
1665 if (!pdata->tx_frames)
1666 tx_set_ic = 0;
1667 else if (tx_packets > pdata->tx_frames)
1668 tx_set_ic = 1;
1669 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets)
1670 tx_set_ic = 1;
1671 else
1672 tx_set_ic = 0;
1673
1674 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1675 rdesc = rdata->rdesc;
1676
1677 /* Create a context descriptor if this is a TSO packet */
1678 if (tso_context || vlan_context) {
1679 if (tso_context) {
1680 netif_dbg(pdata, tx_queued, pdata->netdev,
1681 "TSO context descriptor, mss=%u\n",
1682 packet->mss);
1683
1684 /* Set the MSS size */
1685 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1686 MSS, packet->mss);
1687
1688 /* Mark it as a CONTEXT descriptor */
1689 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1690 CTXT, 1);
1691
1692 /* Indicate this descriptor contains the MSS */
1693 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1694 TCMSSV, 1);
1695
1696 ring->tx.cur_mss = packet->mss;
1697 }
1698
1699 if (vlan_context) {
1700 netif_dbg(pdata, tx_queued, pdata->netdev,
1701 "VLAN context descriptor, ctag=%u\n",
1702 packet->vlan_ctag);
1703
1704 /* Mark it as a CONTEXT descriptor */
1705 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1706 CTXT, 1);
1707
1708 /* Set the VLAN tag */
1709 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1710 VT, packet->vlan_ctag);
1711
1712 /* Indicate this descriptor contains the VLAN tag */
1713 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1714 VLTV, 1);
1715
1716 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1717 }
1718
1719 cur_index++;
1720 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1721 rdesc = rdata->rdesc;
1722 }
1723
1724 /* Update buffer address (for TSO this is the header) */
1725 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1726 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1727
1728 /* Update the buffer length */
1729 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1730 rdata->skb_dma_len);
1731
1732 /* VLAN tag insertion check */
1733 if (vlan)
1734 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1735 TX_NORMAL_DESC2_VLAN_INSERT);
1736
1737 /* Timestamp enablement check */
1738 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1739 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1740
1741 /* Mark it as First Descriptor */
1742 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1743
1744 /* Mark it as a NORMAL descriptor */
1745 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1746
1747 /* Set OWN bit if not the first descriptor */
1748 if (cur_index != start_index)
1749 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1750
1751 if (tso) {
1752 /* Enable TSO */
1753 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1754 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1755 packet->tcp_payload_len);
1756 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1757 packet->tcp_header_len / 4);
1758
1759 pdata->ext_stats.tx_tso_packets += tx_packets;
1760 } else {
1761 /* Enable CRC and Pad Insertion */
1762 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1763
1764 /* Enable HW CSUM */
1765 if (csum)
1766 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1767 CIC, 0x3);
1768
1769 /* Set the total length to be transmitted */
1770 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1771 packet->length);
1772 }
1773
1774 if (vxlan) {
1775 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, VNP,
1776 TX_NORMAL_DESC3_VXLAN_PACKET);
1777
1778 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets;
1779 }
1780
1781 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1782 cur_index++;
1783 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1784 rdesc = rdata->rdesc;
1785
1786 /* Update buffer address */
1787 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1788 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1789
1790 /* Update the buffer length */
1791 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1792 rdata->skb_dma_len);
1793
1794 /* Set OWN bit */
1795 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1796
1797 /* Mark it as NORMAL descriptor */
1798 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1799
1800 /* Enable HW CSUM */
1801 if (csum)
1802 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1803 CIC, 0x3);
1804 }
1805
1806 /* Set LAST bit for the last descriptor */
1807 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1808
1809 /* Set IC bit based on Tx coalescing settings */
1810 if (tx_set_ic)
1811 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1812
1813 /* Save the Tx info to report back during cleanup */
1814 rdata->tx.packets = tx_packets;
1815 rdata->tx.bytes = tx_bytes;
1816
1817 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets;
1818 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes;
1819
1820 /* In case the Tx DMA engine is running, make sure everything
1821 * is written to the descriptor(s) before setting the OWN bit
1822 * for the first descriptor
1823 */
1824 dma_wmb();
1825
1826 /* Set OWN bit for the first descriptor */
1827 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1828 rdesc = rdata->rdesc;
1829 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1830
1831 if (netif_msg_tx_queued(pdata))
1832 xgbe_dump_tx_desc(pdata, ring, start_index,
1833 packet->rdesc_count, 1);
1834
1835 /* Make sure ownership is written to the descriptor */
1836 smp_wmb();
1837
1838 ring->cur = cur_index + 1;
1839 if (!netdev_xmit_more() ||
1840 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1841 channel->queue_index)))
1842 xgbe_tx_start_xmit(channel, ring);
1843 else
1844 ring->tx.xmit_more = 1;
1845
1846 DBGPR(" %s: descriptors %u to %u written\n",
1847 channel->name, start_index & (ring->rdesc_count - 1),
1848 (ring->cur - 1) & (ring->rdesc_count - 1));
1849
1850 DBGPR("<--xgbe_dev_xmit\n");
1851 }
1852
xgbe_dev_read(struct xgbe_channel * channel)1853 static int xgbe_dev_read(struct xgbe_channel *channel)
1854 {
1855 struct xgbe_prv_data *pdata = channel->pdata;
1856 struct xgbe_ring *ring = channel->rx_ring;
1857 struct xgbe_ring_data *rdata;
1858 struct xgbe_ring_desc *rdesc;
1859 struct xgbe_packet_data *packet = &ring->packet_data;
1860 struct net_device *netdev = pdata->netdev;
1861 unsigned int err, etlt, l34t;
1862
1863 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1864
1865 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1866 rdesc = rdata->rdesc;
1867
1868 /* Check for data availability */
1869 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1870 return 1;
1871
1872 /* Make sure descriptor fields are read after reading the OWN bit */
1873 dma_rmb();
1874
1875 if (netif_msg_rx_status(pdata))
1876 xgbe_dump_rx_desc(pdata, ring, ring->cur);
1877
1878 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1879 /* Timestamp Context Descriptor */
1880 xgbe_get_rx_tstamp(packet, rdesc);
1881
1882 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1883 CONTEXT, 1);
1884 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1885 CONTEXT_NEXT, 0);
1886 return 0;
1887 }
1888
1889 /* Normal Descriptor, be sure Context Descriptor bit is off */
1890 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1891
1892 /* Indicate if a Context Descriptor is next */
1893 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1894 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1895 CONTEXT_NEXT, 1);
1896
1897 /* Get the header length */
1898 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
1899 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1900 FIRST, 1);
1901 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1902 RX_NORMAL_DESC2, HL);
1903 if (rdata->rx.hdr_len)
1904 pdata->ext_stats.rx_split_header_packets++;
1905 } else {
1906 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1907 FIRST, 0);
1908 }
1909
1910 /* Get the RSS hash */
1911 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1912 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1913 RSS_HASH, 1);
1914
1915 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1916
1917 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1918 switch (l34t) {
1919 case RX_DESC3_L34T_IPV4_TCP:
1920 case RX_DESC3_L34T_IPV4_UDP:
1921 case RX_DESC3_L34T_IPV6_TCP:
1922 case RX_DESC3_L34T_IPV6_UDP:
1923 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1924 break;
1925 default:
1926 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1927 }
1928 }
1929
1930 /* Not all the data has been transferred for this packet */
1931 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD))
1932 return 0;
1933
1934 /* This is the last of the data for this packet */
1935 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1936 LAST, 1);
1937
1938 /* Get the packet length */
1939 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1940
1941 /* Set checksum done indicator as appropriate */
1942 if (netdev->features & NETIF_F_RXCSUM) {
1943 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1944 CSUM_DONE, 1);
1945 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1946 TNPCSUM_DONE, 1);
1947 }
1948
1949 /* Set the tunneled packet indicator */
1950 if (XGMAC_GET_BITS_LE(rdesc->desc2, RX_NORMAL_DESC2, TNP)) {
1951 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1952 TNP, 1);
1953 pdata->ext_stats.rx_vxlan_packets++;
1954
1955 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1956 switch (l34t) {
1957 case RX_DESC3_L34T_IPV4_UNKNOWN:
1958 case RX_DESC3_L34T_IPV6_UNKNOWN:
1959 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1960 TNPCSUM_DONE, 0);
1961 break;
1962 }
1963 }
1964
1965 /* Check for errors (only valid in last descriptor) */
1966 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1967 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1968 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
1969
1970 if (!err || !etlt) {
1971 /* No error if err is 0 or etlt is 0 */
1972 if ((etlt == 0x09) &&
1973 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1974 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1975 VLAN_CTAG, 1);
1976 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1977 RX_NORMAL_DESC0,
1978 OVT);
1979 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
1980 packet->vlan_ctag);
1981 }
1982 } else {
1983 unsigned int tnp = XGMAC_GET_BITS(packet->attributes,
1984 RX_PACKET_ATTRIBUTES, TNP);
1985
1986 if ((etlt == 0x05) || (etlt == 0x06)) {
1987 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1988 CSUM_DONE, 0);
1989 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1990 TNPCSUM_DONE, 0);
1991 pdata->ext_stats.rx_csum_errors++;
1992 } else if (tnp && ((etlt == 0x09) || (etlt == 0x0a))) {
1993 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1994 CSUM_DONE, 0);
1995 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1996 TNPCSUM_DONE, 0);
1997 pdata->ext_stats.rx_vxlan_csum_errors++;
1998 } else {
1999 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
2000 FRAME, 1);
2001 }
2002 }
2003
2004 pdata->ext_stats.rxq_packets[channel->queue_index]++;
2005 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len;
2006
2007 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
2008 ring->cur & (ring->rdesc_count - 1), ring->cur);
2009
2010 return 0;
2011 }
2012
xgbe_is_context_desc(struct xgbe_ring_desc * rdesc)2013 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
2014 {
2015 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
2016 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
2017 }
2018
xgbe_is_last_desc(struct xgbe_ring_desc * rdesc)2019 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
2020 {
2021 /* Rx and Tx share LD bit, so check TDES3.LD bit */
2022 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
2023 }
2024
xgbe_enable_int(struct xgbe_channel * channel,enum xgbe_int int_id)2025 static int xgbe_enable_int(struct xgbe_channel *channel,
2026 enum xgbe_int int_id)
2027 {
2028 switch (int_id) {
2029 case XGMAC_INT_DMA_CH_SR_TI:
2030 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2031 break;
2032 case XGMAC_INT_DMA_CH_SR_TPS:
2033 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
2034 break;
2035 case XGMAC_INT_DMA_CH_SR_TBU:
2036 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
2037 break;
2038 case XGMAC_INT_DMA_CH_SR_RI:
2039 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2040 break;
2041 case XGMAC_INT_DMA_CH_SR_RBU:
2042 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
2043 break;
2044 case XGMAC_INT_DMA_CH_SR_RPS:
2045 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
2046 break;
2047 case XGMAC_INT_DMA_CH_SR_TI_RI:
2048 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
2049 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
2050 break;
2051 case XGMAC_INT_DMA_CH_SR_FBE:
2052 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
2053 break;
2054 case XGMAC_INT_DMA_ALL:
2055 channel->curr_ier |= channel->saved_ier;
2056 break;
2057 default:
2058 return -1;
2059 }
2060
2061 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2062
2063 return 0;
2064 }
2065
xgbe_disable_int(struct xgbe_channel * channel,enum xgbe_int int_id)2066 static int xgbe_disable_int(struct xgbe_channel *channel,
2067 enum xgbe_int int_id)
2068 {
2069 switch (int_id) {
2070 case XGMAC_INT_DMA_CH_SR_TI:
2071 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2072 break;
2073 case XGMAC_INT_DMA_CH_SR_TPS:
2074 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
2075 break;
2076 case XGMAC_INT_DMA_CH_SR_TBU:
2077 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
2078 break;
2079 case XGMAC_INT_DMA_CH_SR_RI:
2080 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2081 break;
2082 case XGMAC_INT_DMA_CH_SR_RBU:
2083 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
2084 break;
2085 case XGMAC_INT_DMA_CH_SR_RPS:
2086 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
2087 break;
2088 case XGMAC_INT_DMA_CH_SR_TI_RI:
2089 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
2090 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
2091 break;
2092 case XGMAC_INT_DMA_CH_SR_FBE:
2093 XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
2094 break;
2095 case XGMAC_INT_DMA_ALL:
2096 channel->saved_ier = channel->curr_ier;
2097 channel->curr_ier = 0;
2098 break;
2099 default:
2100 return -1;
2101 }
2102
2103 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, channel->curr_ier);
2104
2105 return 0;
2106 }
2107
__xgbe_exit(struct xgbe_prv_data * pdata)2108 static int __xgbe_exit(struct xgbe_prv_data *pdata)
2109 {
2110 unsigned int count = 2000;
2111
2112 DBGPR("-->xgbe_exit\n");
2113
2114 /* Issue a software reset */
2115 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
2116 usleep_range(10, 15);
2117
2118 /* Poll Until Poll Condition */
2119 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
2120 usleep_range(500, 600);
2121
2122 if (!count)
2123 return -EBUSY;
2124
2125 DBGPR("<--xgbe_exit\n");
2126
2127 return 0;
2128 }
2129
xgbe_exit(struct xgbe_prv_data * pdata)2130 static int xgbe_exit(struct xgbe_prv_data *pdata)
2131 {
2132 int ret;
2133
2134 /* To guard against possible incorrectly generated interrupts,
2135 * issue the software reset twice.
2136 */
2137 ret = __xgbe_exit(pdata);
2138 if (ret)
2139 return ret;
2140
2141 return __xgbe_exit(pdata);
2142 }
2143
xgbe_flush_tx_queues(struct xgbe_prv_data * pdata)2144 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
2145 {
2146 unsigned int i, count;
2147
2148 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
2149 return 0;
2150
2151 for (i = 0; i < pdata->tx_q_count; i++)
2152 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
2153
2154 /* Poll Until Poll Condition */
2155 for (i = 0; i < pdata->tx_q_count; i++) {
2156 count = 2000;
2157 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
2158 MTL_Q_TQOMR, FTQ))
2159 usleep_range(500, 600);
2160
2161 if (!count)
2162 return -EBUSY;
2163 }
2164
2165 return 0;
2166 }
2167
xgbe_config_dma_bus(struct xgbe_prv_data * pdata)2168 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
2169 {
2170 unsigned int sbmr;
2171
2172 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
2173
2174 /* Set enhanced addressing mode */
2175 XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);
2176
2177 /* Set the System Bus mode */
2178 XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);
2179 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
2180 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
2181 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
2182 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
2183
2184 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
2185
2186 /* Set descriptor fetching threshold */
2187 if (pdata->vdata->tx_desc_prefetch)
2188 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
2189 pdata->vdata->tx_desc_prefetch);
2190
2191 if (pdata->vdata->rx_desc_prefetch)
2192 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
2193 pdata->vdata->rx_desc_prefetch);
2194 }
2195
xgbe_config_dma_cache(struct xgbe_prv_data * pdata)2196 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
2197 {
2198 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
2199 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
2200 if (pdata->awarcr)
2201 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
2202 }
2203
xgbe_config_mtl_mode(struct xgbe_prv_data * pdata)2204 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
2205 {
2206 unsigned int i;
2207
2208 /* Set Tx to weighted round robin scheduling algorithm */
2209 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
2210
2211 /* Set Tx traffic classes to use WRR algorithm with equal weights */
2212 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2213 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2214 MTL_TSA_ETS);
2215 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
2216 }
2217
2218 /* Set Rx to strict priority algorithm */
2219 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
2220 }
2221
xgbe_queue_flow_control_threshold(struct xgbe_prv_data * pdata,unsigned int queue,unsigned int q_fifo_size)2222 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
2223 unsigned int queue,
2224 unsigned int q_fifo_size)
2225 {
2226 unsigned int frame_fifo_size;
2227 unsigned int rfa, rfd;
2228
2229 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
2230
2231 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
2232 /* PFC is active for this queue */
2233 rfa = pdata->pfc_rfa;
2234 rfd = rfa + frame_fifo_size;
2235 if (rfd > XGMAC_FLOW_CONTROL_MAX)
2236 rfd = XGMAC_FLOW_CONTROL_MAX;
2237 if (rfa >= XGMAC_FLOW_CONTROL_MAX)
2238 rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT;
2239 } else {
2240 /* This path deals with just maximum frame sizes which are
2241 * limited to a jumbo frame of 9,000 (plus headers, etc.)
2242 * so we can never exceed the maximum allowable RFA/RFD
2243 * values.
2244 */
2245 if (q_fifo_size <= 2048) {
2246 /* rx_rfd to zero to signal no flow control */
2247 pdata->rx_rfa[queue] = 0;
2248 pdata->rx_rfd[queue] = 0;
2249 return;
2250 }
2251
2252 if (q_fifo_size <= 4096) {
2253 /* Between 2048 and 4096 */
2254 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
2255 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
2256 return;
2257 }
2258
2259 if (q_fifo_size <= frame_fifo_size) {
2260 /* Between 4096 and max-frame */
2261 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
2262 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
2263 return;
2264 }
2265
2266 if (q_fifo_size <= (frame_fifo_size * 3)) {
2267 /* Between max-frame and 3 max-frames,
2268 * trigger if we get just over a frame of data and
2269 * resume when we have just under half a frame left.
2270 */
2271 rfa = q_fifo_size - frame_fifo_size;
2272 rfd = rfa + (frame_fifo_size / 2);
2273 } else {
2274 /* Above 3 max-frames - trigger when just over
2275 * 2 frames of space available
2276 */
2277 rfa = frame_fifo_size * 2;
2278 rfa += XGMAC_FLOW_CONTROL_UNIT;
2279 rfd = rfa + frame_fifo_size;
2280 }
2281 }
2282
2283 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
2284 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
2285 }
2286
xgbe_calculate_flow_control_threshold(struct xgbe_prv_data * pdata,unsigned int * fifo)2287 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
2288 unsigned int *fifo)
2289 {
2290 unsigned int q_fifo_size;
2291 unsigned int i;
2292
2293 for (i = 0; i < pdata->rx_q_count; i++) {
2294 q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
2295
2296 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
2297 }
2298 }
2299
xgbe_config_flow_control_threshold(struct xgbe_prv_data * pdata)2300 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2301 {
2302 unsigned int i;
2303
2304 for (i = 0; i < pdata->rx_q_count; i++) {
2305 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
2306 pdata->rx_rfa[i]);
2307 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
2308 pdata->rx_rfd[i]);
2309 }
2310 }
2311
xgbe_get_tx_fifo_size(struct xgbe_prv_data * pdata)2312 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
2313 {
2314 /* The configured value may not be the actual amount of fifo RAM */
2315 return min_t(unsigned int, pdata->tx_max_fifo_size,
2316 pdata->hw_feat.tx_fifo_size);
2317 }
2318
xgbe_get_rx_fifo_size(struct xgbe_prv_data * pdata)2319 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata)
2320 {
2321 /* The configured value may not be the actual amount of fifo RAM */
2322 return min_t(unsigned int, pdata->rx_max_fifo_size,
2323 pdata->hw_feat.rx_fifo_size);
2324 }
2325
xgbe_calculate_equal_fifo(unsigned int fifo_size,unsigned int queue_count,unsigned int * fifo)2326 static void xgbe_calculate_equal_fifo(unsigned int fifo_size,
2327 unsigned int queue_count,
2328 unsigned int *fifo)
2329 {
2330 unsigned int q_fifo_size;
2331 unsigned int p_fifo;
2332 unsigned int i;
2333
2334 q_fifo_size = fifo_size / queue_count;
2335
2336 /* Calculate the fifo setting by dividing the queue's fifo size
2337 * by the fifo allocation increment (with 0 representing the
2338 * base allocation increment so decrement the result by 1).
2339 */
2340 p_fifo = q_fifo_size / XGMAC_FIFO_UNIT;
2341 if (p_fifo)
2342 p_fifo--;
2343
2344 /* Distribute the fifo equally amongst the queues */
2345 for (i = 0; i < queue_count; i++)
2346 fifo[i] = p_fifo;
2347 }
2348
xgbe_set_nonprio_fifos(unsigned int fifo_size,unsigned int queue_count,unsigned int * fifo)2349 static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size,
2350 unsigned int queue_count,
2351 unsigned int *fifo)
2352 {
2353 unsigned int i;
2354
2355 BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC);
2356
2357 if (queue_count <= IEEE_8021QAZ_MAX_TCS)
2358 return fifo_size;
2359
2360 /* Rx queues 9 and up are for specialized packets,
2361 * such as PTP or DCB control packets, etc. and
2362 * don't require a large fifo
2363 */
2364 for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) {
2365 fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
2366 fifo_size -= XGMAC_FIFO_MIN_ALLOC;
2367 }
2368
2369 return fifo_size;
2370 }
2371
xgbe_get_pfc_delay(struct xgbe_prv_data * pdata)2372 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata)
2373 {
2374 unsigned int delay;
2375
2376 /* If a delay has been provided, use that */
2377 if (pdata->pfc->delay)
2378 return pdata->pfc->delay / 8;
2379
2380 /* Allow for two maximum size frames */
2381 delay = xgbe_get_max_frame(pdata);
2382 delay += XGMAC_ETH_PREAMBLE;
2383 delay *= 2;
2384
2385 /* Allow for PFC frame */
2386 delay += XGMAC_PFC_DATA_LEN;
2387 delay += ETH_HLEN + ETH_FCS_LEN;
2388 delay += XGMAC_ETH_PREAMBLE;
2389
2390 /* Allow for miscellaneous delays (LPI exit, cable, etc.) */
2391 delay += XGMAC_PFC_DELAYS;
2392
2393 return delay;
2394 }
2395
xgbe_get_pfc_queues(struct xgbe_prv_data * pdata)2396 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata)
2397 {
2398 unsigned int count, prio_queues;
2399 unsigned int i;
2400
2401 if (!pdata->pfc->pfc_en)
2402 return 0;
2403
2404 count = 0;
2405 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2406 for (i = 0; i < prio_queues; i++) {
2407 if (!xgbe_is_pfc_queue(pdata, i))
2408 continue;
2409
2410 pdata->pfcq[i] = 1;
2411 count++;
2412 }
2413
2414 return count;
2415 }
2416
xgbe_calculate_dcb_fifo(struct xgbe_prv_data * pdata,unsigned int fifo_size,unsigned int * fifo)2417 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata,
2418 unsigned int fifo_size,
2419 unsigned int *fifo)
2420 {
2421 unsigned int q_fifo_size, rem_fifo, addn_fifo;
2422 unsigned int prio_queues;
2423 unsigned int pfc_count;
2424 unsigned int i;
2425
2426 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata));
2427 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2428 pfc_count = xgbe_get_pfc_queues(pdata);
2429
2430 if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) {
2431 /* No traffic classes with PFC enabled or can't do lossless */
2432 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2433 return;
2434 }
2435
2436 /* Calculate how much fifo we have to play with */
2437 rem_fifo = fifo_size - (q_fifo_size * prio_queues);
2438
2439 /* Calculate how much more than base fifo PFC needs, which also
2440 * becomes the threshold activation point (RFA)
2441 */
2442 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata);
2443 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa);
2444
2445 if (pdata->pfc_rfa > q_fifo_size) {
2446 addn_fifo = pdata->pfc_rfa - q_fifo_size;
2447 addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo);
2448 } else {
2449 addn_fifo = 0;
2450 }
2451
2452 /* Calculate DCB fifo settings:
2453 * - distribute remaining fifo between the VLAN priority
2454 * queues based on traffic class PFC enablement and overall
2455 * priority (0 is lowest priority, so start at highest)
2456 */
2457 i = prio_queues;
2458 while (i > 0) {
2459 i--;
2460
2461 fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
2462
2463 if (!pdata->pfcq[i] || !addn_fifo)
2464 continue;
2465
2466 if (addn_fifo > rem_fifo) {
2467 netdev_warn(pdata->netdev,
2468 "RXq%u cannot set needed fifo size\n", i);
2469 if (!rem_fifo)
2470 continue;
2471
2472 addn_fifo = rem_fifo;
2473 }
2474
2475 fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
2476 rem_fifo -= addn_fifo;
2477 }
2478
2479 if (rem_fifo) {
2480 unsigned int inc_fifo = rem_fifo / prio_queues;
2481
2482 /* Distribute remaining fifo across queues */
2483 for (i = 0; i < prio_queues; i++)
2484 fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
2485 }
2486 }
2487
xgbe_config_tx_fifo_size(struct xgbe_prv_data * pdata)2488 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
2489 {
2490 unsigned int fifo_size;
2491 unsigned int fifo[XGBE_MAX_QUEUES];
2492 unsigned int i;
2493
2494 fifo_size = xgbe_get_tx_fifo_size(pdata);
2495
2496 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo);
2497
2498 for (i = 0; i < pdata->tx_q_count; i++)
2499 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]);
2500
2501 netif_info(pdata, drv, pdata->netdev,
2502 "%d Tx hardware queues, %d byte fifo per queue\n",
2503 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2504 }
2505
xgbe_config_rx_fifo_size(struct xgbe_prv_data * pdata)2506 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2507 {
2508 unsigned int fifo_size;
2509 unsigned int fifo[XGBE_MAX_QUEUES];
2510 unsigned int prio_queues;
2511 unsigned int i;
2512
2513 /* Clear any DCB related fifo/queue information */
2514 memset(pdata->pfcq, 0, sizeof(pdata->pfcq));
2515 pdata->pfc_rfa = 0;
2516
2517 fifo_size = xgbe_get_rx_fifo_size(pdata);
2518 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2519
2520 /* Assign a minimum fifo to the non-VLAN priority queues */
2521 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
2522
2523 if (pdata->pfc && pdata->ets)
2524 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
2525 else
2526 xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
2527
2528 for (i = 0; i < pdata->rx_q_count; i++)
2529 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
2530
2531 xgbe_calculate_flow_control_threshold(pdata, fifo);
2532 xgbe_config_flow_control_threshold(pdata);
2533
2534 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) {
2535 netif_info(pdata, drv, pdata->netdev,
2536 "%u Rx hardware queues\n", pdata->rx_q_count);
2537 for (i = 0; i < pdata->rx_q_count; i++)
2538 netif_info(pdata, drv, pdata->netdev,
2539 "RxQ%u, %u byte fifo queue\n", i,
2540 ((fifo[i] + 1) * XGMAC_FIFO_UNIT));
2541 } else {
2542 netif_info(pdata, drv, pdata->netdev,
2543 "%u Rx hardware queues, %u byte fifo per queue\n",
2544 pdata->rx_q_count,
2545 ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
2546 }
2547 }
2548
xgbe_config_queue_mapping(struct xgbe_prv_data * pdata)2549 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2550 {
2551 unsigned int qptc, qptc_extra, queue;
2552 unsigned int prio_queues;
2553 unsigned int ppq, ppq_extra, prio;
2554 unsigned int mask;
2555 unsigned int i, j, reg, reg_val;
2556
2557 /* Map the MTL Tx Queues to Traffic Classes
2558 * Note: Tx Queues >= Traffic Classes
2559 */
2560 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2561 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2562
2563 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2564 for (j = 0; j < qptc; j++) {
2565 netif_dbg(pdata, drv, pdata->netdev,
2566 "TXq%u mapped to TC%u\n", queue, i);
2567 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2568 Q2TCMAP, i);
2569 pdata->q2tc_map[queue++] = i;
2570 }
2571
2572 if (i < qptc_extra) {
2573 netif_dbg(pdata, drv, pdata->netdev,
2574 "TXq%u mapped to TC%u\n", queue, i);
2575 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2576 Q2TCMAP, i);
2577 pdata->q2tc_map[queue++] = i;
2578 }
2579 }
2580
2581 /* Map the 8 VLAN priority values to available MTL Rx queues */
2582 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
2583 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2584 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2585
2586 reg = MAC_RQC2R;
2587 reg_val = 0;
2588 for (i = 0, prio = 0; i < prio_queues;) {
2589 mask = 0;
2590 for (j = 0; j < ppq; j++) {
2591 netif_dbg(pdata, drv, pdata->netdev,
2592 "PRIO%u mapped to RXq%u\n", prio, i);
2593 mask |= (1 << prio);
2594 pdata->prio2q_map[prio++] = i;
2595 }
2596
2597 if (i < ppq_extra) {
2598 netif_dbg(pdata, drv, pdata->netdev,
2599 "PRIO%u mapped to RXq%u\n", prio, i);
2600 mask |= (1 << prio);
2601 pdata->prio2q_map[prio++] = i;
2602 }
2603
2604 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2605
2606 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2607 continue;
2608
2609 XGMAC_IOWRITE(pdata, reg, reg_val);
2610 reg += MAC_RQC2_INC;
2611 reg_val = 0;
2612 }
2613
2614 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2615 reg = MTL_RQDCM0R;
2616 reg_val = 0;
2617 for (i = 0; i < pdata->rx_q_count;) {
2618 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2619
2620 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2621 continue;
2622
2623 XGMAC_IOWRITE(pdata, reg, reg_val);
2624
2625 reg += MTL_RQDCM_INC;
2626 reg_val = 0;
2627 }
2628 }
2629
xgbe_config_tc(struct xgbe_prv_data * pdata)2630 static void xgbe_config_tc(struct xgbe_prv_data *pdata)
2631 {
2632 unsigned int offset, queue, prio;
2633 u8 i;
2634
2635 netdev_reset_tc(pdata->netdev);
2636 if (!pdata->num_tcs)
2637 return;
2638
2639 netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
2640
2641 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
2642 while ((queue < pdata->tx_q_count) &&
2643 (pdata->q2tc_map[queue] == i))
2644 queue++;
2645
2646 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
2647 i, offset, queue - 1);
2648 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
2649 offset = queue;
2650 }
2651
2652 if (!pdata->ets)
2653 return;
2654
2655 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
2656 netdev_set_prio_tc_map(pdata->netdev, prio,
2657 pdata->ets->prio_tc[prio]);
2658 }
2659
xgbe_config_dcb_tc(struct xgbe_prv_data * pdata)2660 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
2661 {
2662 struct ieee_ets *ets = pdata->ets;
2663 unsigned int total_weight, min_weight, weight;
2664 unsigned int mask, reg, reg_val;
2665 unsigned int i, prio;
2666
2667 if (!ets)
2668 return;
2669
2670 /* Set Tx to deficit weighted round robin scheduling algorithm (when
2671 * traffic class is using ETS algorithm)
2672 */
2673 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
2674
2675 /* Set Traffic Class algorithms */
2676 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
2677 min_weight = total_weight / 100;
2678 if (!min_weight)
2679 min_weight = 1;
2680
2681 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
2682 /* Map the priorities to the traffic class */
2683 mask = 0;
2684 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
2685 if (ets->prio_tc[prio] == i)
2686 mask |= (1 << prio);
2687 }
2688 mask &= 0xff;
2689
2690 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
2691 i, mask);
2692 reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG));
2693 reg_val = XGMAC_IOREAD(pdata, reg);
2694
2695 reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));
2696 reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));
2697
2698 XGMAC_IOWRITE(pdata, reg, reg_val);
2699
2700 /* Set the traffic class algorithm */
2701 switch (ets->tc_tsa[i]) {
2702 case IEEE_8021QAZ_TSA_STRICT:
2703 netif_dbg(pdata, drv, pdata->netdev,
2704 "TC%u using SP\n", i);
2705 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2706 MTL_TSA_SP);
2707 break;
2708 case IEEE_8021QAZ_TSA_ETS:
2709 weight = total_weight * ets->tc_tx_bw[i] / 100;
2710 weight = clamp(weight, min_weight, total_weight);
2711
2712 netif_dbg(pdata, drv, pdata->netdev,
2713 "TC%u using DWRR (weight %u)\n", i, weight);
2714 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
2715 MTL_TSA_ETS);
2716 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
2717 weight);
2718 break;
2719 }
2720 }
2721
2722 xgbe_config_tc(pdata);
2723 }
2724
xgbe_config_dcb_pfc(struct xgbe_prv_data * pdata)2725 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
2726 {
2727 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2728 /* Just stop the Tx queues while Rx fifo is changed */
2729 netif_tx_stop_all_queues(pdata->netdev);
2730
2731 /* Suspend Rx so that fifo's can be adjusted */
2732 pdata->hw_if.disable_rx(pdata);
2733 }
2734
2735 xgbe_config_rx_fifo_size(pdata);
2736 xgbe_config_flow_control(pdata);
2737
2738 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
2739 /* Resume Rx */
2740 pdata->hw_if.enable_rx(pdata);
2741
2742 /* Resume Tx queues */
2743 netif_tx_start_all_queues(pdata->netdev);
2744 }
2745 }
2746
xgbe_config_mac_address(struct xgbe_prv_data * pdata)2747 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2748 {
2749 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2750
2751 /* Filtering is done using perfect filtering and hash filtering */
2752 if (pdata->hw_feat.hash_table_size) {
2753 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2754 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2755 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2756 }
2757 }
2758
xgbe_config_jumbo_enable(struct xgbe_prv_data * pdata)2759 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2760 {
2761 unsigned int val;
2762
2763 if (pdata->netdev->mtu > XGMAC_JUMBO_PACKET_MTU) {
2764 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSL,
2765 XGMAC_GIANT_PACKET_MTU);
2766 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 1);
2767 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 1);
2768 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 1);
2769 } else {
2770 val = pdata->netdev->mtu > XGMAC_STD_PACKET_MTU ? 1 : 0;
2771 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 0);
2772 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 0);
2773 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 0);
2774 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2775 }
2776 }
2777
xgbe_config_mac_speed(struct xgbe_prv_data * pdata)2778 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2779 {
2780 xgbe_set_speed(pdata, pdata->phy_speed);
2781 }
2782
xgbe_config_checksum_offload(struct xgbe_prv_data * pdata)2783 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2784 {
2785 if (pdata->netdev->features & NETIF_F_RXCSUM)
2786 xgbe_enable_rx_csum(pdata);
2787 else
2788 xgbe_disable_rx_csum(pdata);
2789 }
2790
xgbe_config_vlan_support(struct xgbe_prv_data * pdata)2791 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2792 {
2793 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2794 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2795 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2796
2797 /* Set the current VLAN Hash Table register value */
2798 xgbe_update_vlan_hash_table(pdata);
2799
2800 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2801 xgbe_enable_rx_vlan_filtering(pdata);
2802 else
2803 xgbe_disable_rx_vlan_filtering(pdata);
2804
2805 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2806 xgbe_enable_rx_vlan_stripping(pdata);
2807 else
2808 xgbe_disable_rx_vlan_stripping(pdata);
2809 }
2810
xgbe_mmc_read(struct xgbe_prv_data * pdata,unsigned int reg_lo)2811 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2812 {
2813 bool read_hi;
2814 u64 val;
2815
2816 if (pdata->vdata->mmc_64bit) {
2817 switch (reg_lo) {
2818 /* These registers are always 32 bit */
2819 case MMC_RXRUNTERROR:
2820 case MMC_RXJABBERERROR:
2821 case MMC_RXUNDERSIZE_G:
2822 case MMC_RXOVERSIZE_G:
2823 case MMC_RXWATCHDOGERROR:
2824 case MMC_RXALIGNMENTERROR:
2825 read_hi = false;
2826 break;
2827
2828 default:
2829 read_hi = true;
2830 }
2831 } else {
2832 switch (reg_lo) {
2833 /* These registers are always 64 bit */
2834 case MMC_TXOCTETCOUNT_GB_LO:
2835 case MMC_TXOCTETCOUNT_G_LO:
2836 case MMC_RXOCTETCOUNT_GB_LO:
2837 case MMC_RXOCTETCOUNT_G_LO:
2838 read_hi = true;
2839 break;
2840
2841 default:
2842 read_hi = false;
2843 }
2844 }
2845
2846 val = XGMAC_IOREAD(pdata, reg_lo);
2847
2848 if (read_hi)
2849 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2850
2851 return val;
2852 }
2853
xgbe_tx_mmc_int(struct xgbe_prv_data * pdata)2854 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2855 {
2856 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2857 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2858
2859 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2860 stats->txoctetcount_gb +=
2861 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2862
2863 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2864 stats->txframecount_gb +=
2865 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2866
2867 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2868 stats->txbroadcastframes_g +=
2869 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2870
2871 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2872 stats->txmulticastframes_g +=
2873 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2874
2875 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2876 stats->tx64octets_gb +=
2877 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2878
2879 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2880 stats->tx65to127octets_gb +=
2881 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2882
2883 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2884 stats->tx128to255octets_gb +=
2885 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2886
2887 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2888 stats->tx256to511octets_gb +=
2889 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2890
2891 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2892 stats->tx512to1023octets_gb +=
2893 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2894
2895 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2896 stats->tx1024tomaxoctets_gb +=
2897 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2898
2899 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2900 stats->txunicastframes_gb +=
2901 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2902
2903 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2904 stats->txmulticastframes_gb +=
2905 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2906
2907 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2908 stats->txbroadcastframes_g +=
2909 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2910
2911 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2912 stats->txunderflowerror +=
2913 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2914
2915 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2916 stats->txoctetcount_g +=
2917 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2918
2919 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2920 stats->txframecount_g +=
2921 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2922
2923 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2924 stats->txpauseframes +=
2925 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2926
2927 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2928 stats->txvlanframes_g +=
2929 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2930 }
2931
xgbe_rx_mmc_int(struct xgbe_prv_data * pdata)2932 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2933 {
2934 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2935 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2936
2937 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2938 stats->rxframecount_gb +=
2939 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2940
2941 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2942 stats->rxoctetcount_gb +=
2943 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2944
2945 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2946 stats->rxoctetcount_g +=
2947 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2948
2949 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2950 stats->rxbroadcastframes_g +=
2951 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2952
2953 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2954 stats->rxmulticastframes_g +=
2955 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2956
2957 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2958 stats->rxcrcerror +=
2959 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2960
2961 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2962 stats->rxrunterror +=
2963 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2964
2965 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2966 stats->rxjabbererror +=
2967 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2968
2969 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2970 stats->rxundersize_g +=
2971 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2972
2973 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2974 stats->rxoversize_g +=
2975 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2976
2977 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2978 stats->rx64octets_gb +=
2979 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2980
2981 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2982 stats->rx65to127octets_gb +=
2983 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2984
2985 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2986 stats->rx128to255octets_gb +=
2987 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2988
2989 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2990 stats->rx256to511octets_gb +=
2991 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2992
2993 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2994 stats->rx512to1023octets_gb +=
2995 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2996
2997 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2998 stats->rx1024tomaxoctets_gb +=
2999 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3000
3001 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
3002 stats->rxunicastframes_g +=
3003 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3004
3005 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
3006 stats->rxlengtherror +=
3007 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3008
3009 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
3010 stats->rxoutofrangetype +=
3011 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3012
3013 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
3014 stats->rxpauseframes +=
3015 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3016
3017 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
3018 stats->rxfifooverflow +=
3019 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3020
3021 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
3022 stats->rxvlanframes_gb +=
3023 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3024
3025 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
3026 stats->rxwatchdogerror +=
3027 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3028
3029 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXALIGNMENTERROR))
3030 stats->rxalignmenterror +=
3031 xgbe_mmc_read(pdata, MMC_RXALIGNMENTERROR);
3032 }
3033
xgbe_read_mmc_stats(struct xgbe_prv_data * pdata)3034 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
3035 {
3036 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
3037
3038 /* Freeze counters */
3039 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
3040
3041 stats->txoctetcount_gb +=
3042 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
3043
3044 stats->txframecount_gb +=
3045 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
3046
3047 stats->txbroadcastframes_g +=
3048 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
3049
3050 stats->txmulticastframes_g +=
3051 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
3052
3053 stats->tx64octets_gb +=
3054 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
3055
3056 stats->tx65to127octets_gb +=
3057 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
3058
3059 stats->tx128to255octets_gb +=
3060 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
3061
3062 stats->tx256to511octets_gb +=
3063 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
3064
3065 stats->tx512to1023octets_gb +=
3066 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
3067
3068 stats->tx1024tomaxoctets_gb +=
3069 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
3070
3071 stats->txunicastframes_gb +=
3072 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
3073
3074 stats->txmulticastframes_gb +=
3075 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
3076
3077 stats->txbroadcastframes_g +=
3078 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
3079
3080 stats->txunderflowerror +=
3081 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
3082
3083 stats->txoctetcount_g +=
3084 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
3085
3086 stats->txframecount_g +=
3087 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
3088
3089 stats->txpauseframes +=
3090 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
3091
3092 stats->txvlanframes_g +=
3093 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
3094
3095 stats->rxframecount_gb +=
3096 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
3097
3098 stats->rxoctetcount_gb +=
3099 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
3100
3101 stats->rxoctetcount_g +=
3102 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
3103
3104 stats->rxbroadcastframes_g +=
3105 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
3106
3107 stats->rxmulticastframes_g +=
3108 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
3109
3110 stats->rxcrcerror +=
3111 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
3112
3113 stats->rxrunterror +=
3114 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
3115
3116 stats->rxjabbererror +=
3117 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
3118
3119 stats->rxundersize_g +=
3120 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
3121
3122 stats->rxoversize_g +=
3123 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
3124
3125 stats->rx64octets_gb +=
3126 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
3127
3128 stats->rx65to127octets_gb +=
3129 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
3130
3131 stats->rx128to255octets_gb +=
3132 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
3133
3134 stats->rx256to511octets_gb +=
3135 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
3136
3137 stats->rx512to1023octets_gb +=
3138 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
3139
3140 stats->rx1024tomaxoctets_gb +=
3141 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
3142
3143 stats->rxunicastframes_g +=
3144 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
3145
3146 stats->rxlengtherror +=
3147 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
3148
3149 stats->rxoutofrangetype +=
3150 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
3151
3152 stats->rxpauseframes +=
3153 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
3154
3155 stats->rxfifooverflow +=
3156 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
3157
3158 stats->rxvlanframes_gb +=
3159 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
3160
3161 stats->rxwatchdogerror +=
3162 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
3163
3164 stats->rxalignmenterror +=
3165 xgbe_mmc_read(pdata, MMC_RXALIGNMENTERROR);
3166
3167 /* Un-freeze counters */
3168 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
3169 }
3170
xgbe_config_mmc(struct xgbe_prv_data * pdata)3171 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
3172 {
3173 /* Set counters to reset on read */
3174 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
3175
3176 /* Reset the counters */
3177 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
3178 }
3179
xgbe_txq_prepare_tx_stop(struct xgbe_prv_data * pdata,unsigned int queue)3180 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata,
3181 unsigned int queue)
3182 {
3183 unsigned int tx_status;
3184 unsigned long tx_timeout;
3185
3186 /* The Tx engine cannot be stopped if it is actively processing
3187 * packets. Wait for the Tx queue to empty the Tx fifo. Don't
3188 * wait forever though...
3189 *
3190 * Optimization: Skip the wait when link is down. Hardware won't
3191 * complete TX processing, so waiting serves no purpose and only
3192 * delays interface shutdown. Descriptors will be reclaimed via
3193 * the force-cleanup path in tx_poll.
3194 */
3195
3196 if (!pdata->phy.link)
3197 return;
3198
3199 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3200 while (time_before(jiffies, tx_timeout)) {
3201 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR);
3202 if ((XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) &&
3203 (XGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0))
3204 break;
3205
3206 usleep_range(500, 1000);
3207 }
3208
3209 if (!time_before(jiffies, tx_timeout))
3210 netdev_info(pdata->netdev,
3211 "timed out waiting for Tx queue %u to empty\n",
3212 queue);
3213 }
3214
xgbe_prepare_tx_stop(struct xgbe_prv_data * pdata,unsigned int queue)3215 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
3216 unsigned int queue)
3217 {
3218 unsigned int tx_dsr, tx_pos, tx_qidx;
3219 unsigned int tx_status;
3220 unsigned long tx_timeout;
3221
3222 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20)
3223 return xgbe_txq_prepare_tx_stop(pdata, queue);
3224
3225 /* Calculate the status register to read and the position within */
3226 if (queue < DMA_DSRX_FIRST_QUEUE) {
3227 tx_dsr = DMA_DSR0;
3228 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START;
3229 } else {
3230 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE;
3231
3232 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
3233 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
3234 DMA_DSRX_TPS_START;
3235 }
3236
3237 /* The Tx engine cannot be stopped if it is actively processing
3238 * descriptors. Wait for the Tx engine to enter the stopped or
3239 * suspended state. Don't wait forever though...
3240 */
3241 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3242 while (time_before(jiffies, tx_timeout)) {
3243 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
3244 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
3245 if ((tx_status == DMA_TPS_STOPPED) ||
3246 (tx_status == DMA_TPS_SUSPENDED))
3247 break;
3248
3249 usleep_range(500, 1000);
3250 }
3251
3252 if (!time_before(jiffies, tx_timeout))
3253 netdev_info(pdata->netdev,
3254 "timed out waiting for Tx DMA channel %u to stop\n",
3255 queue);
3256 }
3257
xgbe_enable_tx(struct xgbe_prv_data * pdata)3258 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
3259 {
3260 unsigned int i;
3261
3262 /* Enable each Tx DMA channel */
3263 for (i = 0; i < pdata->channel_count; i++) {
3264 if (!pdata->channel[i]->tx_ring)
3265 break;
3266
3267 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3268 }
3269
3270 /* Enable each Tx queue */
3271 for (i = 0; i < pdata->tx_q_count; i++)
3272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
3273 MTL_Q_ENABLED);
3274
3275 /* Enable MAC Tx */
3276 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3277 }
3278
3279 /**
3280 * xgbe_wait_for_dma_tx_complete - Wait for DMA to complete pending TX
3281 * @pdata: driver private data
3282 *
3283 * Wait for the DMA TX channels to complete all pending descriptors.
3284 * This ensures no frames are in-flight before we disable the transmitter.
3285 * If link is down, return immediately as TX will never complete.
3286 *
3287 * Return: 0 on success, -ETIMEDOUT on timeout
3288 */
xgbe_wait_for_dma_tx_complete(struct xgbe_prv_data * pdata)3289 static int xgbe_wait_for_dma_tx_complete(struct xgbe_prv_data *pdata)
3290 {
3291 struct xgbe_channel *channel;
3292 struct xgbe_ring *ring;
3293 unsigned long timeout;
3294 unsigned int i;
3295 bool complete;
3296
3297 /* If link is down, TX will never complete - skip waiting */
3298 if (!pdata->phy.link)
3299 return 0;
3300
3301 timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3302
3303 do {
3304 complete = true;
3305
3306 for (i = 0; i < pdata->channel_count; i++) {
3307 channel = pdata->channel[i];
3308 ring = channel->tx_ring;
3309 if (!ring)
3310 continue;
3311
3312 /* Check if DMA has processed all descriptors */
3313 if (ring->dirty != ring->cur) {
3314 complete = false;
3315 break;
3316 }
3317 }
3318
3319 if (complete)
3320 return 0;
3321
3322 usleep_range(100, 200);
3323 } while (time_before(jiffies, timeout));
3324
3325 netif_warn(pdata, drv, pdata->netdev,
3326 "timeout waiting for DMA TX to complete\n");
3327 return -ETIMEDOUT;
3328 }
3329
xgbe_disable_tx(struct xgbe_prv_data * pdata)3330 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
3331 {
3332 unsigned int i;
3333
3334 /* Step 1: Wait for DMA to complete pending descriptors */
3335 xgbe_wait_for_dma_tx_complete(pdata);
3336
3337 /* Step 2: Disable each Tx DMA channel to stop
3338 * processing new descriptors
3339 */
3340 for (i = 0; i < pdata->channel_count; i++) {
3341 if (!pdata->channel[i]->tx_ring)
3342 break;
3343 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3344 }
3345
3346 /* Step 3: Wait for MTL TX queues to drain */
3347 for (i = 0; i < pdata->tx_q_count; i++)
3348 xgbe_prepare_tx_stop(pdata, i);
3349
3350 /* Step 4: Disable MTL TX queues */
3351 for (i = 0; i < pdata->tx_q_count; i++)
3352 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
3353
3354 /* Step 5: Disable MAC TX last */
3355 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3356 }
3357
xgbe_prepare_rx_stop(struct xgbe_prv_data * pdata,unsigned int queue)3358 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata,
3359 unsigned int queue)
3360 {
3361 unsigned int rx_status;
3362 unsigned long rx_timeout;
3363
3364 /* The Rx engine cannot be stopped if it is actively processing
3365 * packets. Wait for the Rx queue to empty the Rx fifo. Don't
3366 * wait forever though...
3367 */
3368 rx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
3369 while (time_before(jiffies, rx_timeout)) {
3370 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR);
3371 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) &&
3372 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0))
3373 break;
3374
3375 usleep_range(500, 1000);
3376 }
3377
3378 if (!time_before(jiffies, rx_timeout))
3379 netdev_info(pdata->netdev,
3380 "timed out waiting for Rx queue %u to empty\n",
3381 queue);
3382 }
3383
xgbe_enable_rx(struct xgbe_prv_data * pdata)3384 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
3385 {
3386 unsigned int reg_val, i;
3387
3388 /* Enable each Rx DMA channel */
3389 for (i = 0; i < pdata->channel_count; i++) {
3390 if (!pdata->channel[i]->rx_ring)
3391 break;
3392
3393 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3394 }
3395
3396 /* Enable each Rx queue */
3397 reg_val = 0;
3398 for (i = 0; i < pdata->rx_q_count; i++)
3399 reg_val |= (0x02 << (i << 1));
3400 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
3401
3402 /* Enable MAC Rx */
3403 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
3404 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
3405 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
3406 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
3407 }
3408
xgbe_disable_rx(struct xgbe_prv_data * pdata)3409 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
3410 {
3411 unsigned int i;
3412
3413 /* Disable MAC Rx */
3414 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
3415 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
3416 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
3417
3418 /* Prepare for Rx DMA channel stop */
3419 for (i = 0; i < pdata->rx_q_count; i++)
3420 xgbe_prepare_rx_stop(pdata, i);
3421
3422 /* Disable each Rx queue */
3423 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
3424
3425 /* Disable each Rx DMA channel */
3426 for (i = 0; i < pdata->channel_count; i++) {
3427 if (!pdata->channel[i]->rx_ring)
3428 break;
3429
3430 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3431 }
3432 }
3433
xgbe_powerup_tx(struct xgbe_prv_data * pdata)3434 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
3435 {
3436 unsigned int i;
3437
3438 /* Enable each Tx DMA channel */
3439 for (i = 0; i < pdata->channel_count; i++) {
3440 if (!pdata->channel[i]->tx_ring)
3441 break;
3442
3443 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1);
3444 }
3445
3446 /* Enable MAC Tx */
3447 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
3448 }
3449
xgbe_powerdown_tx(struct xgbe_prv_data * pdata)3450 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
3451 {
3452 unsigned int i;
3453
3454 /* Prepare for Tx DMA channel stop */
3455 for (i = 0; i < pdata->tx_q_count; i++)
3456 xgbe_prepare_tx_stop(pdata, i);
3457
3458 /* Disable MAC Tx */
3459 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
3460
3461 /* Disable each Tx DMA channel */
3462 for (i = 0; i < pdata->channel_count; i++) {
3463 if (!pdata->channel[i]->tx_ring)
3464 break;
3465
3466 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0);
3467 }
3468 }
3469
xgbe_powerup_rx(struct xgbe_prv_data * pdata)3470 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
3471 {
3472 unsigned int i;
3473
3474 /* Enable each Rx DMA channel */
3475 for (i = 0; i < pdata->channel_count; i++) {
3476 if (!pdata->channel[i]->rx_ring)
3477 break;
3478
3479 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1);
3480 }
3481 }
3482
xgbe_powerdown_rx(struct xgbe_prv_data * pdata)3483 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
3484 {
3485 unsigned int i;
3486
3487 /* Disable each Rx DMA channel */
3488 for (i = 0; i < pdata->channel_count; i++) {
3489 if (!pdata->channel[i]->rx_ring)
3490 break;
3491
3492 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0);
3493 }
3494 }
3495
xgbe_init(struct xgbe_prv_data * pdata)3496 static int xgbe_init(struct xgbe_prv_data *pdata)
3497 {
3498 struct xgbe_desc_if *desc_if = &pdata->desc_if;
3499 int ret;
3500
3501 DBGPR("-->xgbe_init\n");
3502
3503 /* Flush Tx queues */
3504 ret = xgbe_flush_tx_queues(pdata);
3505 if (ret) {
3506 netdev_err(pdata->netdev, "error flushing TX queues\n");
3507 return ret;
3508 }
3509
3510 /*
3511 * Initialize DMA related features
3512 */
3513 xgbe_config_dma_bus(pdata);
3514 xgbe_config_dma_cache(pdata);
3515 xgbe_config_osp_mode(pdata);
3516 xgbe_config_pbl_val(pdata);
3517 xgbe_config_rx_coalesce(pdata);
3518 xgbe_config_tx_coalesce(pdata);
3519 xgbe_config_rx_buffer_size(pdata);
3520 xgbe_config_tso_mode(pdata);
3521
3522 if (pdata->netdev->features & NETIF_F_RXCSUM) {
3523 xgbe_config_sph_mode(pdata);
3524 xgbe_config_rss(pdata);
3525 }
3526
3527 desc_if->wrapper_tx_desc_init(pdata);
3528 desc_if->wrapper_rx_desc_init(pdata);
3529 xgbe_enable_dma_interrupts(pdata);
3530
3531 /*
3532 * Initialize MTL related features
3533 */
3534 xgbe_config_mtl_mode(pdata);
3535 xgbe_config_queue_mapping(pdata);
3536 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
3537 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
3538 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
3539 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
3540 xgbe_config_tx_fifo_size(pdata);
3541 xgbe_config_rx_fifo_size(pdata);
3542 /*TODO: Error Packet and undersized good Packet forwarding enable
3543 (FEP and FUP)
3544 */
3545 xgbe_config_dcb_tc(pdata);
3546 xgbe_enable_mtl_interrupts(pdata);
3547
3548 /*
3549 * Initialize MAC related features
3550 */
3551 xgbe_config_mac_address(pdata);
3552 xgbe_config_rx_mode(pdata);
3553 xgbe_config_jumbo_enable(pdata);
3554 xgbe_config_flow_control(pdata);
3555 xgbe_config_mac_speed(pdata);
3556 xgbe_config_checksum_offload(pdata);
3557 xgbe_config_vlan_support(pdata);
3558 xgbe_config_mmc(pdata);
3559 xgbe_enable_mac_interrupts(pdata);
3560
3561 /*
3562 * Initialize ECC related features
3563 */
3564 xgbe_enable_ecc_interrupts(pdata);
3565
3566 DBGPR("<--xgbe_init\n");
3567
3568 return 0;
3569 }
3570
xgbe_init_function_ptrs_dev(struct xgbe_hw_if * hw_if)3571 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
3572 {
3573 DBGPR("-->xgbe_init_function_ptrs\n");
3574
3575 hw_if->tx_complete = xgbe_tx_complete;
3576
3577 hw_if->set_mac_address = xgbe_set_mac_address;
3578 hw_if->config_rx_mode = xgbe_config_rx_mode;
3579
3580 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
3581 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
3582
3583 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
3584 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
3585 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
3586 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
3587 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
3588
3589 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
3590 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
3591
3592 hw_if->set_speed = xgbe_set_speed;
3593
3594 hw_if->set_ext_mii_mode = xgbe_set_ext_mii_mode;
3595 hw_if->read_ext_mii_regs_c22 = xgbe_read_ext_mii_regs_c22;
3596 hw_if->write_ext_mii_regs_c22 = xgbe_write_ext_mii_regs_c22;
3597 hw_if->read_ext_mii_regs_c45 = xgbe_read_ext_mii_regs_c45;
3598 hw_if->write_ext_mii_regs_c45 = xgbe_write_ext_mii_regs_c45;
3599
3600 hw_if->set_gpio = xgbe_set_gpio;
3601 hw_if->clr_gpio = xgbe_clr_gpio;
3602
3603 hw_if->enable_tx = xgbe_enable_tx;
3604 hw_if->disable_tx = xgbe_disable_tx;
3605 hw_if->enable_rx = xgbe_enable_rx;
3606 hw_if->disable_rx = xgbe_disable_rx;
3607
3608 hw_if->powerup_tx = xgbe_powerup_tx;
3609 hw_if->powerdown_tx = xgbe_powerdown_tx;
3610 hw_if->powerup_rx = xgbe_powerup_rx;
3611 hw_if->powerdown_rx = xgbe_powerdown_rx;
3612
3613 hw_if->dev_xmit = xgbe_dev_xmit;
3614 hw_if->dev_read = xgbe_dev_read;
3615 hw_if->enable_int = xgbe_enable_int;
3616 hw_if->disable_int = xgbe_disable_int;
3617 hw_if->init = xgbe_init;
3618 hw_if->exit = xgbe_exit;
3619
3620 /* Descriptor related Sequences have to be initialized here */
3621 hw_if->tx_desc_init = xgbe_tx_desc_init;
3622 hw_if->rx_desc_init = xgbe_rx_desc_init;
3623 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
3624 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
3625 hw_if->is_last_desc = xgbe_is_last_desc;
3626 hw_if->is_context_desc = xgbe_is_context_desc;
3627 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
3628
3629 /* For FLOW ctrl */
3630 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
3631 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
3632
3633 /* For RX coalescing */
3634 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
3635 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
3636 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
3637 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
3638
3639 /* For RX and TX threshold config */
3640 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
3641 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
3642
3643 /* For RX and TX Store and Forward Mode config */
3644 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
3645 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
3646
3647 /* For TX DMA Operating on Second Frame config */
3648 hw_if->config_osp_mode = xgbe_config_osp_mode;
3649
3650 /* For MMC statistics support */
3651 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
3652 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
3653 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
3654
3655 /* For Data Center Bridging config */
3656 hw_if->config_tc = xgbe_config_tc;
3657 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
3658 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
3659
3660 /* For Receive Side Scaling */
3661 hw_if->enable_rss = xgbe_enable_rss;
3662 hw_if->disable_rss = xgbe_disable_rss;
3663 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
3664 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
3665
3666 /* For ECC */
3667 hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
3668 hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
3669
3670 /* For VXLAN */
3671 hw_if->enable_vxlan = xgbe_enable_vxlan;
3672 hw_if->disable_vxlan = xgbe_disable_vxlan;
3673 hw_if->set_vxlan_id = xgbe_set_vxlan_id;
3674
3675 /* For Split Header*/
3676 hw_if->enable_sph = xgbe_config_sph_mode;
3677 hw_if->disable_sph = xgbe_disable_sph_mode;
3678
3679 DBGPR("<--xgbe_init_function_ptrs\n");
3680 }
3681
xgbe_enable_mac_loopback(struct xgbe_prv_data * pdata)3682 int xgbe_enable_mac_loopback(struct xgbe_prv_data *pdata)
3683 {
3684 /* Enable MAC loopback mode */
3685 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, LM, 1);
3686
3687 /* Wait for loopback to stabilize */
3688 usleep_range(10, 15);
3689
3690 return 0;
3691 }
3692
xgbe_disable_mac_loopback(struct xgbe_prv_data * pdata)3693 void xgbe_disable_mac_loopback(struct xgbe_prv_data *pdata)
3694 {
3695 /* Disable MAC loopback mode */
3696 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, LM, 0);
3697 }
3698