1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/adi-axi-common.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 23 #include <linux/iio/backend.h> 24 #include <linux/iio/buffer-dmaengine.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/iio.h> 27 28 #include "ad7606_bus_iface.h" 29 /* 30 * Register definitions: 31 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 32 */ 33 34 /* ADC controls */ 35 36 #define ADI_AXI_REG_RSTN 0x0040 37 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 38 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 39 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 40 41 #define ADI_AXI_ADC_REG_CONFIG 0x000c 42 #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) 43 44 #define ADI_AXI_ADC_REG_CTRL 0x0044 45 #define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8) 46 #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3) 47 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) 48 49 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c 50 /* Bit 8 is common to all AXI ADC cores; bits 7-0 are per-HDL-project. */ 51 #define ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK BIT(8) 52 53 #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2) 54 #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0) 55 #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0 56 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1 57 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2 58 #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0) 59 #define AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(3, 2) 60 #define AXI_AD408X_PACKET_FORMAT_20BIT 0x0 61 #define AXI_AD408X_PACKET_FORMAT_16BIT 0x1 62 #define AXI_AD408X_PACKET_FORMAT_14BIT 0x2 63 64 #define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068 65 #define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0) 66 67 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 68 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) 69 70 /* ADC Channel controls */ 71 72 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 73 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 74 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 75 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 76 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 77 #define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4) 78 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 79 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 80 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 81 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 82 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 83 84 #define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40) 85 #define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1) 86 /* out of sync */ 87 #define ADI_AXI_ADC_CHAN_STAT_PN_OOS BIT(1) 88 /* spurious out of sync */ 89 #define ADI_AXI_ADC_CHAN_STAT_PN_ERR BIT(2) 90 91 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40) 92 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16) 93 94 #define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40) 95 #define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0) 96 97 /* IO Delays */ 98 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4) 99 #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0) 100 101 #define ADI_AXI_REG_CONFIG_WR 0x0080 102 #define ADI_AXI_REG_CONFIG_RD 0x0084 103 #define ADI_AXI_REG_CONFIG_CTRL 0x008c 104 #define ADI_AXI_REG_CONFIG_CTRL_READ 0x03 105 #define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01 106 107 #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15 108 109 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 110 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 111 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 112 ADI_AXI_REG_CHAN_CTRL_ENABLE) 113 114 #define ADI_AXI_REG_READ_BIT 0x8000 115 #define ADI_AXI_REG_ADDRESS_MASK 0xff00 116 #define ADI_AXI_REG_VALUE_MASK 0x00ff 117 118 struct axi_adc_info { 119 unsigned int version; 120 const struct iio_backend_info *backend_info; 121 bool has_child_nodes; 122 const void *pdata; 123 unsigned int pdata_sz; 124 }; 125 126 struct adi_axi_adc_state { 127 const struct axi_adc_info *info; 128 struct regmap *regmap; 129 struct device *dev; 130 /* lock to protect multiple accesses to the device registers */ 131 struct mutex lock; 132 }; 133 134 static int axi_adc_enable(struct iio_backend *back) 135 { 136 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 137 unsigned int __val; 138 int ret; 139 140 guard(mutex)(&st->lock); 141 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 142 ADI_AXI_REG_RSTN_MMCM_RSTN); 143 if (ret) 144 return ret; 145 146 /* 147 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all 148 * designs really use it but if they don't we still get the lock bit 149 * set. So let's do it all the time so the code is generic. 150 */ 151 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS, 152 __val, __val & ADI_AXI_ADC_DRP_LOCKED, 153 100, 1000); 154 if (ret) 155 return ret; 156 157 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, 158 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 159 } 160 161 static void axi_adc_disable(struct iio_backend *back) 162 { 163 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 164 165 guard(mutex)(&st->lock); 166 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 167 } 168 169 static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan, 170 const struct iio_backend_data_fmt *data) 171 { 172 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 173 u32 val; 174 175 if (!data->enable) 176 return regmap_clear_bits(st->regmap, 177 ADI_AXI_REG_CHAN_CTRL(chan), 178 ADI_AXI_REG_CHAN_CTRL_FMT_EN); 179 180 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true); 181 if (data->sign_extend) 182 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true); 183 if (data->type == IIO_BACKEND_OFFSET_BINARY) 184 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true); 185 186 return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 187 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val); 188 } 189 190 static int axi_adc_data_sample_trigger(struct iio_backend *back, 191 enum iio_backend_sample_trigger trigger) 192 { 193 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 194 195 switch (trigger) { 196 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING: 197 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 198 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 199 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING: 200 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 201 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK); 202 default: 203 return -EINVAL; 204 } 205 } 206 207 static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane, 208 unsigned int tap) 209 { 210 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 211 int ret; 212 u32 val; 213 214 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK)) 215 return -EINVAL; 216 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES) 217 return -EINVAL; 218 219 guard(mutex)(&st->lock); 220 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), tap); 221 if (ret) 222 return ret; 223 /* 224 * If readback is ~0, that means there are issues with the 225 * delay_clk. 226 */ 227 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), &val); 228 if (ret) 229 return ret; 230 if (val == U32_MAX) 231 return -EIO; 232 233 return 0; 234 } 235 236 static int axi_adc_test_pattern_set(struct iio_backend *back, 237 unsigned int chan, 238 enum iio_backend_test_pattern pattern) 239 { 240 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 241 242 switch (pattern) { 243 case IIO_BACKEND_NO_TEST_PATTERN: 244 /* nothing to do */ 245 return 0; 246 case IIO_BACKEND_ADI_PRBS_9A: 247 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 248 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 249 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0)); 250 case IIO_BACKEND_ADI_PRBS_23A: 251 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan), 252 ADI_AXI_ADC_CHAN_PN_SEL_MASK, 253 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 1)); 254 default: 255 return -EINVAL; 256 } 257 } 258 259 static int axi_adc_oversampling_ratio_set(struct iio_backend *back, 260 unsigned int chan, 261 unsigned int rate) 262 { 263 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 264 265 return regmap_update_bits(st->regmap, 266 ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan), 267 ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 268 FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, 269 rate)); 270 } 271 272 static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan, 273 unsigned int *status) 274 { 275 int ret; 276 277 guard(mutex)(&st->lock); 278 /* reset test bits by setting them */ 279 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 280 ADI_AXI_ADC_CHAN_STAT_PN_MASK); 281 if (ret) 282 return ret; 283 284 /* let's give enough time to validate or erroring the incoming pattern */ 285 fsleep(1000); 286 287 return regmap_read(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan), 288 status); 289 } 290 291 static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan, 292 bool *error) 293 { 294 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 295 u32 val; 296 int ret; 297 298 ret = axi_adc_read_chan_status(st, chan, &val); 299 if (ret) 300 return ret; 301 302 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val) 303 *error = true; 304 else 305 *error = false; 306 307 return 0; 308 } 309 310 static int axi_adc_debugfs_print_chan_status(struct iio_backend *back, 311 unsigned int chan, char *buf, 312 size_t len) 313 { 314 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 315 u32 val; 316 int ret; 317 318 ret = axi_adc_read_chan_status(st, chan, &val); 319 if (ret) 320 return ret; 321 322 /* 323 * PN_ERR is cleared in case out of sync is set. Hence, no point in 324 * checking both bits. 325 */ 326 if (val & ADI_AXI_ADC_CHAN_STAT_PN_OOS) 327 return scnprintf(buf, len, "CH%u: Out of Sync.\n", chan); 328 if (val & ADI_AXI_ADC_CHAN_STAT_PN_ERR) 329 return scnprintf(buf, len, "CH%u: Spurious Out of Sync.\n", chan); 330 331 return scnprintf(buf, len, "CH%u: OK.\n", chan); 332 } 333 334 static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan) 335 { 336 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 337 338 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 339 ADI_AXI_REG_CHAN_CTRL_ENABLE); 340 } 341 342 static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan) 343 { 344 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 345 346 return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), 347 ADI_AXI_REG_CHAN_CTRL_ENABLE); 348 } 349 350 static int axi_adc_interface_type_get(struct iio_backend *back, 351 enum iio_backend_interface_type *type) 352 { 353 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 354 unsigned int val; 355 int ret; 356 357 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val); 358 if (ret) 359 return ret; 360 361 if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N) 362 *type = IIO_BACKEND_INTERFACE_SERIAL_CMOS; 363 else 364 *type = IIO_BACKEND_INTERFACE_SERIAL_LVDS; 365 366 return 0; 367 } 368 369 static int axi_adc_ad485x_data_size_set(struct iio_backend *back, 370 unsigned int size) 371 { 372 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 373 unsigned int val; 374 375 switch (size) { 376 /* 377 * There are two different variants of the AXI AXI_AD485X IP block, a 378 * 16-bit and a 20-bit variant. 379 * The 0x0 value (AXI_AD485X_PACKET_FORMAT_20BIT) is corresponding also 380 * to the 16-bit variant of the IP block. 381 */ 382 case 16: 383 case 20: 384 val = AXI_AD485X_PACKET_FORMAT_20BIT; 385 break; 386 case 24: 387 val = AXI_AD485X_PACKET_FORMAT_24BIT; 388 break; 389 /* 390 * The 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) corresponds only to the 391 * 20-bit variant of the IP block. Setting this value properly is 392 * ensured by the upper layers of the drivers calling the axi-adc 393 * functions. 394 * Also, for 16-bit IP block, the 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) 395 * value is handled as maximum size available which is 24-bit for this 396 * configuration. 397 */ 398 case 32: 399 val = AXI_AD485X_PACKET_FORMAT_32BIT; 400 break; 401 default: 402 return -EINVAL; 403 } 404 405 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 406 AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, 407 FIELD_PREP(AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, val)); 408 } 409 410 static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back, 411 unsigned int chan, 412 unsigned int ratio) 413 { 414 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 415 416 /* The current state of the function enables or disables the 417 * oversampling in REG_CNTRL_3 register. A ratio equal to 1 implies no 418 * oversampling, while a value greater than 1 implies oversampling being 419 * enabled. 420 */ 421 switch (ratio) { 422 case 0: 423 return -EINVAL; 424 case 1: 425 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 426 AXI_AD485X_CNTRL_3_OS_EN_MSK); 427 default: 428 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 429 AXI_AD485X_CNTRL_3_OS_EN_MSK); 430 } 431 } 432 433 static int axi_adc_ad408x_filter_type_set(struct iio_backend *back, 434 enum iio_backend_filter_type type) 435 { 436 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 437 438 if (type) 439 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 440 AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 441 442 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 443 AXI_AD408X_CNTRL_3_FILTER_EN_MSK); 444 } 445 446 static int axi_adc_ad408x_data_size_set(struct iio_backend *back, 447 unsigned int size) 448 { 449 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 450 unsigned int val; 451 452 switch (size) { 453 case 20: 454 val = AXI_AD408X_PACKET_FORMAT_20BIT; 455 break; 456 case 16: 457 val = AXI_AD408X_PACKET_FORMAT_16BIT; 458 break; 459 case 14: 460 val = AXI_AD408X_PACKET_FORMAT_14BIT; 461 break; 462 default: 463 return -EINVAL; 464 } 465 466 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 467 AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK, 468 FIELD_PREP(AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK, val)); 469 } 470 471 static int axi_adc_ad408x_interface_data_align(struct iio_backend *back, 472 u32 timeout_us) 473 { 474 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 475 u32 val; 476 int ret; 477 478 ret = regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 479 ADI_AXI_ADC_CTRL_SYNC_MSK); 480 if (ret) 481 return ret; 482 483 return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS, 484 val, 485 FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val), 486 1, timeout_us); 487 } 488 489 static int axi_adc_num_lanes_set(struct iio_backend *back, 490 unsigned int num_lanes) 491 { 492 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 493 494 if (!num_lanes) 495 return -EINVAL; 496 497 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL, 498 ADI_AXI_ADC_CTRL_NUM_LANES_MSK, 499 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes)); 500 } 501 502 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, 503 struct iio_dev *indio_dev) 504 { 505 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 506 const char *dma_name; 507 508 if (device_property_read_string(st->dev, "dma-names", &dma_name)) 509 dma_name = "rx"; 510 511 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name); 512 } 513 514 static int axi_adc_raw_write(struct iio_backend *back, u32 val) 515 { 516 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 517 518 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, val); 519 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 520 ADI_AXI_REG_CONFIG_CTRL_WRITE); 521 fsleep(100); 522 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 523 fsleep(100); 524 525 return 0; 526 } 527 528 static int axi_adc_raw_read(struct iio_backend *back, u32 *val) 529 { 530 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 531 532 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 533 ADI_AXI_REG_CONFIG_CTRL_READ); 534 fsleep(100); 535 regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, val); 536 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00); 537 fsleep(100); 538 539 return 0; 540 } 541 542 static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val) 543 { 544 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 545 u32 addr, reg_val; 546 547 guard(mutex)(&st->lock); 548 549 /* 550 * The address is written on the highest weight byte, and the MSB set 551 * at 1 indicates a read operation. 552 */ 553 addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT; 554 axi_adc_raw_write(back, addr); 555 axi_adc_raw_read(back, ®_val); 556 557 *val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val); 558 559 /* Write 0x0 on the bus to get back to ADC mode */ 560 axi_adc_raw_write(back, 0); 561 562 return 0; 563 } 564 565 static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val) 566 { 567 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 568 u32 buf; 569 570 guard(mutex)(&st->lock); 571 572 /* Write any register to switch to register mode */ 573 axi_adc_raw_write(back, 0xaf00); 574 575 buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | 576 FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val); 577 axi_adc_raw_write(back, buf); 578 579 /* Write 0x0 on the bus to get back to ADC mode */ 580 axi_adc_raw_write(back, 0); 581 582 return 0; 583 } 584 585 static void axi_adc_free_buffer(struct iio_backend *back, 586 struct iio_buffer *buffer) 587 { 588 iio_dmaengine_buffer_teardown(buffer); 589 } 590 591 static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg, 592 unsigned int writeval, unsigned int *readval) 593 { 594 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 595 596 if (readval) 597 return regmap_read(st->regmap, reg, readval); 598 599 return regmap_write(st->regmap, reg, writeval); 600 } 601 602 static int axi_adc_crc_enable(struct iio_backend *back) 603 { 604 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 605 606 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 607 ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK); 608 } 609 610 static int axi_adc_crc_disable(struct iio_backend *back) 611 { 612 struct adi_axi_adc_state *st = iio_backend_get_priv(back); 613 614 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, 615 ADI_AXI_ADC_CNTRL_3_CRC_EN_MASK); 616 } 617 618 static const struct regmap_config axi_adc_regmap_config = { 619 .val_bits = 32, 620 .reg_bits = 32, 621 .reg_stride = 4, 622 }; 623 624 static void axi_adc_child_remove(void *data) 625 { 626 platform_device_unregister(data); 627 } 628 629 static int axi_adc_create_platform_device(struct adi_axi_adc_state *st, 630 struct fwnode_handle *child) 631 { 632 struct platform_device_info pi = { 633 .parent = st->dev, 634 .name = fwnode_get_name(child), 635 .id = PLATFORM_DEVID_AUTO, 636 .fwnode = child, 637 .data = st->info->pdata, 638 .size_data = st->info->pdata_sz, 639 }; 640 struct platform_device *pdev; 641 642 pdev = platform_device_register_full(&pi); 643 if (IS_ERR(pdev)) 644 return PTR_ERR(pdev); 645 646 return devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev); 647 } 648 649 static const struct iio_backend_ops adi_axi_adc_ops = { 650 .enable = axi_adc_enable, 651 .disable = axi_adc_disable, 652 .data_format_set = axi_adc_data_format_set, 653 .chan_enable = axi_adc_chan_enable, 654 .chan_disable = axi_adc_chan_disable, 655 .request_buffer = axi_adc_request_buffer, 656 .free_buffer = axi_adc_free_buffer, 657 .data_sample_trigger = axi_adc_data_sample_trigger, 658 .iodelay_set = axi_adc_iodelays_set, 659 .test_pattern_set = axi_adc_test_pattern_set, 660 .chan_status = axi_adc_chan_status, 661 .interface_type_get = axi_adc_interface_type_get, 662 .oversampling_ratio_set = axi_adc_oversampling_ratio_set, 663 .num_lanes_set = axi_adc_num_lanes_set, 664 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 665 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 666 .crc_enable = axi_adc_crc_enable, 667 .crc_disable = axi_adc_crc_disable, 668 }; 669 670 static const struct iio_backend_info adi_axi_adc_generic = { 671 .name = "axi-adc", 672 .ops = &adi_axi_adc_ops, 673 .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER | 674 IIO_BACKEND_CAP_ENABLE, 675 }; 676 677 static const struct iio_backend_ops adi_ad485x_ops = { 678 .enable = axi_adc_enable, 679 .disable = axi_adc_disable, 680 .data_format_set = axi_adc_data_format_set, 681 .chan_enable = axi_adc_chan_enable, 682 .chan_disable = axi_adc_chan_disable, 683 .request_buffer = axi_adc_request_buffer, 684 .free_buffer = axi_adc_free_buffer, 685 .data_sample_trigger = axi_adc_data_sample_trigger, 686 .iodelay_set = axi_adc_iodelays_set, 687 .chan_status = axi_adc_chan_status, 688 .interface_type_get = axi_adc_interface_type_get, 689 .data_size_set = axi_adc_ad485x_data_size_set, 690 .oversampling_ratio_set = axi_adc_ad485x_oversampling_ratio_set, 691 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 692 .debugfs_print_chan_status = 693 iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 694 }; 695 696 static const struct iio_backend_info axi_ad485x = { 697 .name = "axi-ad485x", 698 .ops = &adi_ad485x_ops, 699 .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER | 700 IIO_BACKEND_CAP_ENABLE, 701 }; 702 703 static const struct iio_backend_ops adi_ad408x_ops = { 704 .enable = axi_adc_enable, 705 .disable = axi_adc_disable, 706 .chan_enable = axi_adc_chan_enable, 707 .chan_disable = axi_adc_chan_disable, 708 .request_buffer = axi_adc_request_buffer, 709 .free_buffer = axi_adc_free_buffer, 710 .data_sample_trigger = axi_adc_data_sample_trigger, 711 .filter_type_set = axi_adc_ad408x_filter_type_set, 712 .data_size_set = axi_adc_ad408x_data_size_set, 713 .interface_data_align = axi_adc_ad408x_interface_data_align, 714 .num_lanes_set = axi_adc_num_lanes_set, 715 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access), 716 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status), 717 }; 718 719 static const struct iio_backend_info axi_ad408x = { 720 .name = "axi-ad408x", 721 .ops = &adi_ad408x_ops, 722 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE, 723 }; 724 725 static int adi_axi_adc_probe(struct platform_device *pdev) 726 { 727 struct device *dev = &pdev->dev; 728 struct adi_axi_adc_state *st; 729 void __iomem *base; 730 unsigned int ver; 731 struct clk *clk; 732 int ret; 733 734 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 735 if (!st) 736 return -ENOMEM; 737 738 ret = devm_mutex_init(dev, &st->lock); 739 if (ret) 740 return ret; 741 742 base = devm_platform_ioremap_resource(pdev, 0); 743 if (IS_ERR(base)) 744 return PTR_ERR(base); 745 746 st->dev = dev; 747 st->regmap = devm_regmap_init_mmio(dev, base, &axi_adc_regmap_config); 748 if (IS_ERR(st->regmap)) 749 return dev_err_probe(dev, PTR_ERR(st->regmap), 750 "failed to init register map\n"); 751 752 st->info = device_get_match_data(dev); 753 if (!st->info) 754 return -ENODEV; 755 756 clk = devm_clk_get_enabled(dev, NULL); 757 if (IS_ERR(clk)) 758 return dev_err_probe(dev, PTR_ERR(clk), 759 "failed to get clock\n"); 760 761 /* 762 * Force disable the core. Up to the frontend to enable us. And we can 763 * still read/write registers... 764 */ 765 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0); 766 if (ret) 767 return ret; 768 769 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); 770 if (ret) 771 return ret; 772 773 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version)) 774 return dev_err_probe(dev, -ENODEV, 775 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 776 ADI_AXI_PCORE_VER_MAJOR(st->info->version), 777 ADI_AXI_PCORE_VER_MINOR(st->info->version), 778 ADI_AXI_PCORE_VER_PATCH(st->info->version), 779 ADI_AXI_PCORE_VER_MAJOR(ver), 780 ADI_AXI_PCORE_VER_MINOR(ver), 781 ADI_AXI_PCORE_VER_PATCH(ver)); 782 783 ret = devm_iio_backend_register(dev, st->info->backend_info, st); 784 if (ret) 785 return dev_err_probe(dev, ret, "failed to register iio backend\n"); 786 787 device_for_each_child_node_scoped(dev, child) { 788 int val; 789 790 if (!st->info->has_child_nodes) 791 return dev_err_probe(dev, -EINVAL, 792 "invalid fdt axi-dac compatible."); 793 794 /* Processing only reg 0 node */ 795 ret = fwnode_property_read_u32(child, "reg", &val); 796 if (ret) 797 return dev_err_probe(dev, ret, "invalid reg property."); 798 if (val != 0) 799 return dev_err_probe(dev, -EINVAL, 800 "invalid node address."); 801 802 ret = axi_adc_create_platform_device(st, child); 803 if (ret) 804 return dev_err_probe(dev, -EINVAL, 805 "cannot create device."); 806 } 807 808 dev_info(dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 809 ADI_AXI_PCORE_VER_MAJOR(ver), 810 ADI_AXI_PCORE_VER_MINOR(ver), 811 ADI_AXI_PCORE_VER_PATCH(ver)); 812 813 return 0; 814 } 815 816 static const struct axi_adc_info adc_generic = { 817 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 818 .backend_info = &adi_axi_adc_generic, 819 }; 820 821 static const struct axi_adc_info adi_axi_ad485x = { 822 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 823 .backend_info = &axi_ad485x, 824 }; 825 826 static const struct ad7606_platform_data ad7606_pdata = { 827 .bus_reg_read = ad7606_bus_reg_read, 828 .bus_reg_write = ad7606_bus_reg_write, 829 }; 830 831 static const struct axi_adc_info adc_ad7606 = { 832 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 833 .backend_info = &adi_axi_adc_generic, 834 .pdata = &ad7606_pdata, 835 .pdata_sz = sizeof(ad7606_pdata), 836 .has_child_nodes = true, 837 }; 838 839 static const struct axi_adc_info adi_axi_ad408x = { 840 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 841 .backend_info = &axi_ad408x, 842 }; 843 844 /* Match table for of_platform binding */ 845 static const struct of_device_id adi_axi_adc_of_match[] = { 846 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic }, 847 { .compatible = "adi,axi-ad408x", .data = &adi_axi_ad408x }, 848 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x }, 849 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 }, 850 { } 851 }; 852 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 853 854 static struct platform_driver adi_axi_adc_driver = { 855 .driver = { 856 .name = KBUILD_MODNAME, 857 .of_match_table = adi_axi_adc_of_match, 858 }, 859 .probe = adi_axi_adc_probe, 860 }; 861 module_platform_driver(adi_axi_adc_driver); 862 863 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 864 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 865 MODULE_LICENSE("GPL v2"); 866 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 867 MODULE_IMPORT_NS("IIO_BACKEND"); 868