1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
5 *
6 * Copyright 2012-2020 Analog Devices Inc.
7 */
8
9 #include <linux/adi-axi-common.h>
10 #include <linux/bitfield.h>
11 #include <linux/cleanup.h>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22
23 #include <linux/iio/backend.h>
24 #include <linux/iio/buffer-dmaengine.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/iio.h>
27
28 #include "ad7606_bus_iface.h"
29 /*
30 * Register definitions:
31 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
32 */
33
34 /* ADC controls */
35
36 #define ADI_AXI_REG_RSTN 0x0040
37 #define ADI_AXI_REG_RSTN_CE_N BIT(2)
38 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
39 #define ADI_AXI_REG_RSTN_RSTN BIT(0)
40
41 #define ADI_AXI_ADC_REG_CONFIG 0x000c
42 #define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7)
43
44 #define ADI_AXI_ADC_REG_CTRL 0x0044
45 #define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8)
46 #define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3)
47 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1)
48
49 #define ADI_AXI_ADC_REG_CNTRL_3 0x004c
50 #define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2)
51 #define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0)
52 #define AXI_AD485X_PACKET_FORMAT_20BIT 0x0
53 #define AXI_AD485X_PACKET_FORMAT_24BIT 0x1
54 #define AXI_AD485X_PACKET_FORMAT_32BIT 0x2
55 #define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0)
56 #define AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(3, 2)
57 #define AXI_AD408X_PACKET_FORMAT_20BIT 0x0
58 #define AXI_AD408X_PACKET_FORMAT_16BIT 0x1
59 #define AXI_AD408X_PACKET_FORMAT_14BIT 0x2
60
61 #define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068
62 #define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0)
63
64 #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074
65 #define ADI_AXI_ADC_DRP_LOCKED BIT(17)
66
67 /* ADC Channel controls */
68
69 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
70 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
71 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
72 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
73 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
74 #define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4)
75 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
76 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
77 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
78 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
79 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
80
81 #define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40)
82 #define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1)
83 /* out of sync */
84 #define ADI_AXI_ADC_CHAN_STAT_PN_OOS BIT(1)
85 /* spurious out of sync */
86 #define ADI_AXI_ADC_CHAN_STAT_PN_ERR BIT(2)
87
88 #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40)
89 #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16)
90
91 #define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40)
92 #define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0)
93
94 /* IO Delays */
95 #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4)
96 #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0)
97
98 #define ADI_AXI_REG_CONFIG_WR 0x0080
99 #define ADI_AXI_REG_CONFIG_RD 0x0084
100 #define ADI_AXI_REG_CONFIG_CTRL 0x008c
101 #define ADI_AXI_REG_CONFIG_CTRL_READ 0x03
102 #define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01
103
104 #define ADI_AXI_ADC_MAX_IO_NUM_LANES 15
105
106 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
107 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
108 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
109 ADI_AXI_REG_CHAN_CTRL_ENABLE)
110
111 #define ADI_AXI_REG_READ_BIT 0x8000
112 #define ADI_AXI_REG_ADDRESS_MASK 0xff00
113 #define ADI_AXI_REG_VALUE_MASK 0x00ff
114
115 struct axi_adc_info {
116 unsigned int version;
117 const struct iio_backend_info *backend_info;
118 bool has_child_nodes;
119 const void *pdata;
120 unsigned int pdata_sz;
121 };
122
123 struct adi_axi_adc_state {
124 const struct axi_adc_info *info;
125 struct regmap *regmap;
126 struct device *dev;
127 /* lock to protect multiple accesses to the device registers */
128 struct mutex lock;
129 };
130
axi_adc_enable(struct iio_backend * back)131 static int axi_adc_enable(struct iio_backend *back)
132 {
133 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
134 unsigned int __val;
135 int ret;
136
137 guard(mutex)(&st->lock);
138 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,
139 ADI_AXI_REG_RSTN_MMCM_RSTN);
140 if (ret)
141 return ret;
142
143 /*
144 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
145 * designs really use it but if they don't we still get the lock bit
146 * set. So let's do it all the time so the code is generic.
147 */
148 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS,
149 __val, __val & ADI_AXI_ADC_DRP_LOCKED,
150 100, 1000);
151 if (ret)
152 return ret;
153
154 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN,
155 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
156 }
157
axi_adc_disable(struct iio_backend * back)158 static void axi_adc_disable(struct iio_backend *back)
159 {
160 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
161
162 guard(mutex)(&st->lock);
163 regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0);
164 }
165
axi_adc_data_format_set(struct iio_backend * back,unsigned int chan,const struct iio_backend_data_fmt * data)166 static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan,
167 const struct iio_backend_data_fmt *data)
168 {
169 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
170 u32 val;
171
172 if (!data->enable)
173 return regmap_clear_bits(st->regmap,
174 ADI_AXI_REG_CHAN_CTRL(chan),
175 ADI_AXI_REG_CHAN_CTRL_FMT_EN);
176
177 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true);
178 if (data->sign_extend)
179 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true);
180 if (data->type == IIO_BACKEND_OFFSET_BINARY)
181 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true);
182
183 return regmap_update_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
184 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val);
185 }
186
axi_adc_data_sample_trigger(struct iio_backend * back,enum iio_backend_sample_trigger trigger)187 static int axi_adc_data_sample_trigger(struct iio_backend *back,
188 enum iio_backend_sample_trigger trigger)
189 {
190 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
191
192 switch (trigger) {
193 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING:
194 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,
195 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK);
196 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING:
197 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,
198 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK);
199 default:
200 return -EINVAL;
201 }
202 }
203
axi_adc_iodelays_set(struct iio_backend * back,unsigned int lane,unsigned int tap)204 static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane,
205 unsigned int tap)
206 {
207 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
208 int ret;
209 u32 val;
210
211 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK))
212 return -EINVAL;
213 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES)
214 return -EINVAL;
215
216 guard(mutex)(&st->lock);
217 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), tap);
218 if (ret)
219 return ret;
220 /*
221 * If readback is ~0, that means there are issues with the
222 * delay_clk.
223 */
224 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_DELAY(lane), &val);
225 if (ret)
226 return ret;
227 if (val == U32_MAX)
228 return -EIO;
229
230 return 0;
231 }
232
axi_adc_test_pattern_set(struct iio_backend * back,unsigned int chan,enum iio_backend_test_pattern pattern)233 static int axi_adc_test_pattern_set(struct iio_backend *back,
234 unsigned int chan,
235 enum iio_backend_test_pattern pattern)
236 {
237 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
238
239 switch (pattern) {
240 case IIO_BACKEND_NO_TEST_PATTERN:
241 /* nothing to do */
242 return 0;
243 case IIO_BACKEND_ADI_PRBS_9A:
244 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan),
245 ADI_AXI_ADC_CHAN_PN_SEL_MASK,
246 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0));
247 case IIO_BACKEND_ADI_PRBS_23A:
248 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan),
249 ADI_AXI_ADC_CHAN_PN_SEL_MASK,
250 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 1));
251 default:
252 return -EINVAL;
253 }
254 }
255
axi_adc_oversampling_ratio_set(struct iio_backend * back,unsigned int chan,unsigned int rate)256 static int axi_adc_oversampling_ratio_set(struct iio_backend *back,
257 unsigned int chan,
258 unsigned int rate)
259 {
260 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
261
262 return regmap_update_bits(st->regmap,
263 ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan),
264 ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK,
265 FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK,
266 rate));
267 }
268
axi_adc_read_chan_status(struct adi_axi_adc_state * st,unsigned int chan,unsigned int * status)269 static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan,
270 unsigned int *status)
271 {
272 int ret;
273
274 guard(mutex)(&st->lock);
275 /* reset test bits by setting them */
276 ret = regmap_write(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan),
277 ADI_AXI_ADC_CHAN_STAT_PN_MASK);
278 if (ret)
279 return ret;
280
281 /* let's give enough time to validate or erroring the incoming pattern */
282 fsleep(1000);
283
284 return regmap_read(st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan),
285 status);
286 }
287
axi_adc_chan_status(struct iio_backend * back,unsigned int chan,bool * error)288 static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan,
289 bool *error)
290 {
291 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
292 u32 val;
293 int ret;
294
295 ret = axi_adc_read_chan_status(st, chan, &val);
296 if (ret)
297 return ret;
298
299 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val)
300 *error = true;
301 else
302 *error = false;
303
304 return 0;
305 }
306
axi_adc_debugfs_print_chan_status(struct iio_backend * back,unsigned int chan,char * buf,size_t len)307 static int axi_adc_debugfs_print_chan_status(struct iio_backend *back,
308 unsigned int chan, char *buf,
309 size_t len)
310 {
311 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
312 u32 val;
313 int ret;
314
315 ret = axi_adc_read_chan_status(st, chan, &val);
316 if (ret)
317 return ret;
318
319 /*
320 * PN_ERR is cleared in case out of sync is set. Hence, no point in
321 * checking both bits.
322 */
323 if (val & ADI_AXI_ADC_CHAN_STAT_PN_OOS)
324 return scnprintf(buf, len, "CH%u: Out of Sync.\n", chan);
325 if (val & ADI_AXI_ADC_CHAN_STAT_PN_ERR)
326 return scnprintf(buf, len, "CH%u: Spurious Out of Sync.\n", chan);
327
328 return scnprintf(buf, len, "CH%u: OK.\n", chan);
329 }
330
axi_adc_chan_enable(struct iio_backend * back,unsigned int chan)331 static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan)
332 {
333 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
334
335 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
336 ADI_AXI_REG_CHAN_CTRL_ENABLE);
337 }
338
axi_adc_chan_disable(struct iio_backend * back,unsigned int chan)339 static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan)
340 {
341 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
342
343 return regmap_clear_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
344 ADI_AXI_REG_CHAN_CTRL_ENABLE);
345 }
346
axi_adc_interface_type_get(struct iio_backend * back,enum iio_backend_interface_type * type)347 static int axi_adc_interface_type_get(struct iio_backend *back,
348 enum iio_backend_interface_type *type)
349 {
350 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
351 unsigned int val;
352 int ret;
353
354 ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val);
355 if (ret)
356 return ret;
357
358 if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N)
359 *type = IIO_BACKEND_INTERFACE_SERIAL_CMOS;
360 else
361 *type = IIO_BACKEND_INTERFACE_SERIAL_LVDS;
362
363 return 0;
364 }
365
axi_adc_ad485x_data_size_set(struct iio_backend * back,unsigned int size)366 static int axi_adc_ad485x_data_size_set(struct iio_backend *back,
367 unsigned int size)
368 {
369 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
370 unsigned int val;
371
372 switch (size) {
373 /*
374 * There are two different variants of the AXI AXI_AD485X IP block, a
375 * 16-bit and a 20-bit variant.
376 * The 0x0 value (AXI_AD485X_PACKET_FORMAT_20BIT) is corresponding also
377 * to the 16-bit variant of the IP block.
378 */
379 case 16:
380 case 20:
381 val = AXI_AD485X_PACKET_FORMAT_20BIT;
382 break;
383 case 24:
384 val = AXI_AD485X_PACKET_FORMAT_24BIT;
385 break;
386 /*
387 * The 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) corresponds only to the
388 * 20-bit variant of the IP block. Setting this value properly is
389 * ensured by the upper layers of the drivers calling the axi-adc
390 * functions.
391 * Also, for 16-bit IP block, the 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT)
392 * value is handled as maximum size available which is 24-bit for this
393 * configuration.
394 */
395 case 32:
396 val = AXI_AD485X_PACKET_FORMAT_32BIT;
397 break;
398 default:
399 return -EINVAL;
400 }
401
402 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
403 AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK,
404 FIELD_PREP(AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, val));
405 }
406
axi_adc_ad485x_oversampling_ratio_set(struct iio_backend * back,unsigned int chan,unsigned int ratio)407 static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back,
408 unsigned int chan,
409 unsigned int ratio)
410 {
411 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
412
413 /* The current state of the function enables or disables the
414 * oversampling in REG_CNTRL_3 register. A ratio equal to 1 implies no
415 * oversampling, while a value greater than 1 implies oversampling being
416 * enabled.
417 */
418 switch (ratio) {
419 case 0:
420 return -EINVAL;
421 case 1:
422 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
423 AXI_AD485X_CNTRL_3_OS_EN_MSK);
424 default:
425 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
426 AXI_AD485X_CNTRL_3_OS_EN_MSK);
427 }
428 }
429
axi_adc_ad408x_filter_type_set(struct iio_backend * back,enum iio_backend_filter_type type)430 static int axi_adc_ad408x_filter_type_set(struct iio_backend *back,
431 enum iio_backend_filter_type type)
432 {
433 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
434
435 if (type)
436 return regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
437 AXI_AD408X_CNTRL_3_FILTER_EN_MSK);
438
439 return regmap_clear_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
440 AXI_AD408X_CNTRL_3_FILTER_EN_MSK);
441 }
442
axi_adc_ad408x_data_size_set(struct iio_backend * back,unsigned int size)443 static int axi_adc_ad408x_data_size_set(struct iio_backend *back,
444 unsigned int size)
445 {
446 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
447 unsigned int val;
448
449 switch (size) {
450 case 20:
451 val = AXI_AD408X_PACKET_FORMAT_20BIT;
452 break;
453 case 16:
454 val = AXI_AD408X_PACKET_FORMAT_16BIT;
455 break;
456 case 14:
457 val = AXI_AD408X_PACKET_FORMAT_14BIT;
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
464 AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK,
465 FIELD_PREP(AXI_AD408X_CNTRL_3_PACKET_FORMAT_MSK, val));
466 }
467
axi_adc_ad408x_interface_data_align(struct iio_backend * back,u32 timeout_us)468 static int axi_adc_ad408x_interface_data_align(struct iio_backend *back,
469 u32 timeout_us)
470 {
471 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
472 u32 val;
473 int ret;
474
475 ret = regmap_set_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,
476 ADI_AXI_ADC_CTRL_SYNC_MSK);
477 if (ret)
478 return ret;
479
480 return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS,
481 val,
482 FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val),
483 1, timeout_us);
484 }
485
axi_adc_num_lanes_set(struct iio_backend * back,unsigned int num_lanes)486 static int axi_adc_num_lanes_set(struct iio_backend *back,
487 unsigned int num_lanes)
488 {
489 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
490
491 if (!num_lanes)
492 return -EINVAL;
493
494 return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CTRL,
495 ADI_AXI_ADC_CTRL_NUM_LANES_MSK,
496 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes));
497 }
498
axi_adc_request_buffer(struct iio_backend * back,struct iio_dev * indio_dev)499 static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
500 struct iio_dev *indio_dev)
501 {
502 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
503 const char *dma_name;
504
505 if (device_property_read_string(st->dev, "dma-names", &dma_name))
506 dma_name = "rx";
507
508 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name);
509 }
510
axi_adc_raw_write(struct iio_backend * back,u32 val)511 static int axi_adc_raw_write(struct iio_backend *back, u32 val)
512 {
513 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
514
515 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_WR, val);
516 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL,
517 ADI_AXI_REG_CONFIG_CTRL_WRITE);
518 fsleep(100);
519 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00);
520 fsleep(100);
521
522 return 0;
523 }
524
axi_adc_raw_read(struct iio_backend * back,u32 * val)525 static int axi_adc_raw_read(struct iio_backend *back, u32 *val)
526 {
527 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
528
529 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL,
530 ADI_AXI_REG_CONFIG_CTRL_READ);
531 fsleep(100);
532 regmap_read(st->regmap, ADI_AXI_REG_CONFIG_RD, val);
533 regmap_write(st->regmap, ADI_AXI_REG_CONFIG_CTRL, 0x00);
534 fsleep(100);
535
536 return 0;
537 }
538
ad7606_bus_reg_read(struct iio_backend * back,u32 reg,u32 * val)539 static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val)
540 {
541 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
542 u32 addr, reg_val;
543
544 guard(mutex)(&st->lock);
545
546 /*
547 * The address is written on the highest weight byte, and the MSB set
548 * at 1 indicates a read operation.
549 */
550 addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT;
551 axi_adc_raw_write(back, addr);
552 axi_adc_raw_read(back, ®_val);
553
554 *val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val);
555
556 /* Write 0x0 on the bus to get back to ADC mode */
557 axi_adc_raw_write(back, 0);
558
559 return 0;
560 }
561
ad7606_bus_reg_write(struct iio_backend * back,u32 reg,u32 val)562 static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val)
563 {
564 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
565 u32 buf;
566
567 guard(mutex)(&st->lock);
568
569 /* Write any register to switch to register mode */
570 axi_adc_raw_write(back, 0xaf00);
571
572 buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) |
573 FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val);
574 axi_adc_raw_write(back, buf);
575
576 /* Write 0x0 on the bus to get back to ADC mode */
577 axi_adc_raw_write(back, 0);
578
579 return 0;
580 }
581
axi_adc_free_buffer(struct iio_backend * back,struct iio_buffer * buffer)582 static void axi_adc_free_buffer(struct iio_backend *back,
583 struct iio_buffer *buffer)
584 {
585 iio_dmaengine_buffer_teardown(buffer);
586 }
587
axi_adc_reg_access(struct iio_backend * back,unsigned int reg,unsigned int writeval,unsigned int * readval)588 static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg,
589 unsigned int writeval, unsigned int *readval)
590 {
591 struct adi_axi_adc_state *st = iio_backend_get_priv(back);
592
593 if (readval)
594 return regmap_read(st->regmap, reg, readval);
595
596 return regmap_write(st->regmap, reg, writeval);
597 }
598
599 static const struct regmap_config axi_adc_regmap_config = {
600 .val_bits = 32,
601 .reg_bits = 32,
602 .reg_stride = 4,
603 };
604
axi_adc_child_remove(void * data)605 static void axi_adc_child_remove(void *data)
606 {
607 platform_device_unregister(data);
608 }
609
axi_adc_create_platform_device(struct adi_axi_adc_state * st,struct fwnode_handle * child)610 static int axi_adc_create_platform_device(struct adi_axi_adc_state *st,
611 struct fwnode_handle *child)
612 {
613 struct platform_device_info pi = {
614 .parent = st->dev,
615 .name = fwnode_get_name(child),
616 .id = PLATFORM_DEVID_AUTO,
617 .fwnode = child,
618 .data = st->info->pdata,
619 .size_data = st->info->pdata_sz,
620 };
621 struct platform_device *pdev;
622
623 pdev = platform_device_register_full(&pi);
624 if (IS_ERR(pdev))
625 return PTR_ERR(pdev);
626
627 return devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev);
628 }
629
630 static const struct iio_backend_ops adi_axi_adc_ops = {
631 .enable = axi_adc_enable,
632 .disable = axi_adc_disable,
633 .data_format_set = axi_adc_data_format_set,
634 .chan_enable = axi_adc_chan_enable,
635 .chan_disable = axi_adc_chan_disable,
636 .request_buffer = axi_adc_request_buffer,
637 .free_buffer = axi_adc_free_buffer,
638 .data_sample_trigger = axi_adc_data_sample_trigger,
639 .iodelay_set = axi_adc_iodelays_set,
640 .test_pattern_set = axi_adc_test_pattern_set,
641 .chan_status = axi_adc_chan_status,
642 .interface_type_get = axi_adc_interface_type_get,
643 .oversampling_ratio_set = axi_adc_oversampling_ratio_set,
644 .num_lanes_set = axi_adc_num_lanes_set,
645 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
646 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
647 };
648
649 static const struct iio_backend_info adi_axi_adc_generic = {
650 .name = "axi-adc",
651 .ops = &adi_axi_adc_ops,
652 .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER |
653 IIO_BACKEND_CAP_ENABLE,
654 };
655
656 static const struct iio_backend_ops adi_ad485x_ops = {
657 .enable = axi_adc_enable,
658 .disable = axi_adc_disable,
659 .data_format_set = axi_adc_data_format_set,
660 .chan_enable = axi_adc_chan_enable,
661 .chan_disable = axi_adc_chan_disable,
662 .request_buffer = axi_adc_request_buffer,
663 .free_buffer = axi_adc_free_buffer,
664 .data_sample_trigger = axi_adc_data_sample_trigger,
665 .iodelay_set = axi_adc_iodelays_set,
666 .chan_status = axi_adc_chan_status,
667 .interface_type_get = axi_adc_interface_type_get,
668 .data_size_set = axi_adc_ad485x_data_size_set,
669 .oversampling_ratio_set = axi_adc_ad485x_oversampling_ratio_set,
670 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
671 .debugfs_print_chan_status =
672 iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
673 };
674
675 static const struct iio_backend_info axi_ad485x = {
676 .name = "axi-ad485x",
677 .ops = &adi_ad485x_ops,
678 .caps = IIO_BACKEND_CAP_CALIBRATION | IIO_BACKEND_CAP_BUFFER |
679 IIO_BACKEND_CAP_ENABLE,
680 };
681
682 static const struct iio_backend_ops adi_ad408x_ops = {
683 .enable = axi_adc_enable,
684 .disable = axi_adc_disable,
685 .chan_enable = axi_adc_chan_enable,
686 .chan_disable = axi_adc_chan_disable,
687 .request_buffer = axi_adc_request_buffer,
688 .free_buffer = axi_adc_free_buffer,
689 .data_sample_trigger = axi_adc_data_sample_trigger,
690 .filter_type_set = axi_adc_ad408x_filter_type_set,
691 .data_size_set = axi_adc_ad408x_data_size_set,
692 .interface_data_align = axi_adc_ad408x_interface_data_align,
693 .num_lanes_set = axi_adc_num_lanes_set,
694 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
695 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
696 };
697
698 static const struct iio_backend_info axi_ad408x = {
699 .name = "axi-ad408x",
700 .ops = &adi_ad408x_ops,
701 .caps = IIO_BACKEND_CAP_BUFFER | IIO_BACKEND_CAP_ENABLE,
702 };
703
adi_axi_adc_probe(struct platform_device * pdev)704 static int adi_axi_adc_probe(struct platform_device *pdev)
705 {
706 struct device *dev = &pdev->dev;
707 struct adi_axi_adc_state *st;
708 void __iomem *base;
709 unsigned int ver;
710 struct clk *clk;
711 int ret;
712
713 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
714 if (!st)
715 return -ENOMEM;
716
717 base = devm_platform_ioremap_resource(pdev, 0);
718 if (IS_ERR(base))
719 return PTR_ERR(base);
720
721 st->dev = dev;
722 st->regmap = devm_regmap_init_mmio(dev, base, &axi_adc_regmap_config);
723 if (IS_ERR(st->regmap))
724 return dev_err_probe(dev, PTR_ERR(st->regmap),
725 "failed to init register map\n");
726
727 st->info = device_get_match_data(dev);
728 if (!st->info)
729 return -ENODEV;
730
731 clk = devm_clk_get_enabled(dev, NULL);
732 if (IS_ERR(clk))
733 return dev_err_probe(dev, PTR_ERR(clk),
734 "failed to get clock\n");
735
736 /*
737 * Force disable the core. Up to the frontend to enable us. And we can
738 * still read/write registers...
739 */
740 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0);
741 if (ret)
742 return ret;
743
744 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
745 if (ret)
746 return ret;
747
748 if (ADI_AXI_PCORE_VER_MAJOR(ver) != ADI_AXI_PCORE_VER_MAJOR(st->info->version))
749 return dev_err_probe(dev, -ENODEV,
750 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
751 ADI_AXI_PCORE_VER_MAJOR(st->info->version),
752 ADI_AXI_PCORE_VER_MINOR(st->info->version),
753 ADI_AXI_PCORE_VER_PATCH(st->info->version),
754 ADI_AXI_PCORE_VER_MAJOR(ver),
755 ADI_AXI_PCORE_VER_MINOR(ver),
756 ADI_AXI_PCORE_VER_PATCH(ver));
757
758 ret = devm_iio_backend_register(dev, st->info->backend_info, st);
759 if (ret)
760 return dev_err_probe(dev, ret, "failed to register iio backend\n");
761
762 device_for_each_child_node_scoped(dev, child) {
763 int val;
764
765 if (!st->info->has_child_nodes)
766 return dev_err_probe(dev, -EINVAL,
767 "invalid fdt axi-dac compatible.");
768
769 /* Processing only reg 0 node */
770 ret = fwnode_property_read_u32(child, "reg", &val);
771 if (ret)
772 return dev_err_probe(dev, ret, "invalid reg property.");
773 if (val != 0)
774 return dev_err_probe(dev, -EINVAL,
775 "invalid node address.");
776
777 ret = axi_adc_create_platform_device(st, child);
778 if (ret)
779 return dev_err_probe(dev, -EINVAL,
780 "cannot create device.");
781 }
782
783 dev_info(dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
784 ADI_AXI_PCORE_VER_MAJOR(ver),
785 ADI_AXI_PCORE_VER_MINOR(ver),
786 ADI_AXI_PCORE_VER_PATCH(ver));
787
788 return 0;
789 }
790
791 static const struct axi_adc_info adc_generic = {
792 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
793 .backend_info = &adi_axi_adc_generic,
794 };
795
796 static const struct axi_adc_info adi_axi_ad485x = {
797 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
798 .backend_info = &axi_ad485x,
799 };
800
801 static const struct ad7606_platform_data ad7606_pdata = {
802 .bus_reg_read = ad7606_bus_reg_read,
803 .bus_reg_write = ad7606_bus_reg_write,
804 };
805
806 static const struct axi_adc_info adc_ad7606 = {
807 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
808 .backend_info = &adi_axi_adc_generic,
809 .pdata = &ad7606_pdata,
810 .pdata_sz = sizeof(ad7606_pdata),
811 .has_child_nodes = true,
812 };
813
814 static const struct axi_adc_info adi_axi_ad408x = {
815 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
816 .backend_info = &axi_ad408x,
817 };
818
819 /* Match table for of_platform binding */
820 static const struct of_device_id adi_axi_adc_of_match[] = {
821 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic },
822 { .compatible = "adi,axi-ad408x", .data = &adi_axi_ad408x },
823 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x },
824 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 },
825 { }
826 };
827 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
828
829 static struct platform_driver adi_axi_adc_driver = {
830 .driver = {
831 .name = KBUILD_MODNAME,
832 .of_match_table = adi_axi_adc_of_match,
833 },
834 .probe = adi_axi_adc_probe,
835 };
836 module_platform_driver(adi_axi_adc_driver);
837
838 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
839 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
840 MODULE_LICENSE("GPL v2");
841 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
842 MODULE_IMPORT_NS("IIO_BACKEND");
843