1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include <dt-bindings/leds/leds-pca9532.h> 10#include <dt-bindings/thermal/thermal.h> 11#include "imx8mp-phycore-som.dtsi" 12 13/ { 14 model = "PHYTEC phyBOARD-Pollux i.MX8MP"; 15 compatible = "phytec,imx8mp-phyboard-pollux-rdk", 16 "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 17 18 chosen { 19 stdout-path = &uart1; 20 }; 21 22 backlight_lvds1: backlight1 { 23 compatible = "pwm-backlight"; 24 pinctrl-0 = <&pinctrl_lvds1>; 25 pinctrl-names = "default"; 26 power-supply = <®_lvds1_reg_en>; 27 status = "disabled"; 28 }; 29 30 fan0: fan { 31 compatible = "gpio-fan"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_fan>; 34 gpio-fan,speed-map = <0 0 35 13000 1>; 36 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 37 #cooling-cells = <2>; 38 }; 39 40 panel_lvds1: panel-lvds1 { 41 /* compatible panel in overlay */ 42 backlight = <&backlight_lvds1>; 43 power-supply = <®_vcc_3v3_sw>; 44 status = "disabled"; 45 46 port { 47 panel1_in: endpoint { 48 remote-endpoint = <&ldb_lvds_ch1>; 49 }; 50 }; 51 }; 52 53 reg_vcc_5v_sw: regulator-vcc-5v-sw { 54 compatible = "regulator-fixed"; 55 regulator-always-on; 56 regulator-boot-on; 57 regulator-max-microvolt = <5000000>; 58 regulator-min-microvolt = <5000000>; 59 regulator-name = "VCC_5V_SW"; 60 }; 61 62 reg_can1_stby: regulator-can1-stby { 63 compatible = "regulator-fixed"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_flexcan1_reg>; 66 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 67 regulator-max-microvolt = <3300000>; 68 regulator-min-microvolt = <3300000>; 69 regulator-name = "can1-stby"; 70 }; 71 72 reg_can2_stby: regulator-can2-stby { 73 compatible = "regulator-fixed"; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_flexcan2_reg>; 76 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; 77 regulator-max-microvolt = <3300000>; 78 regulator-min-microvolt = <3300000>; 79 regulator-name = "can2-stby"; 80 }; 81 82 reg_lvds1_reg_en: regulator-lvds1 { 83 compatible = "regulator-fixed"; 84 enable-active-high; 85 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 86 regulator-max-microvolt = <1200000>; 87 regulator-min-microvolt = <1200000>; 88 regulator-name = "lvds1_reg_en"; 89 }; 90 91 reg_usb1_vbus: regulator-usb1-vbus { 92 compatible = "regulator-fixed"; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_usb1_vbus>; 95 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; 96 regulator-max-microvolt = <5000000>; 97 regulator-min-microvolt = <5000000>; 98 regulator-name = "usb1_host_vbus"; 99 }; 100 101 reg_usdhc2_vmmc: regulator-usdhc2 { 102 compatible = "regulator-fixed"; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 105 regulator-name = "VSD_3V3"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 109 enable-active-high; 110 startup-delay-us = <100>; 111 off-on-delay-us = <12000>; 112 }; 113 114 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { 115 compatible = "regulator-fixed"; 116 regulator-name = "VCC_3V3_SW"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 }; 120 121 thermal-zones { 122 soc-thermal { 123 trips { 124 active1: trip2 { 125 temperature = <60000>; 126 hysteresis = <2000>; 127 type = "active"; 128 }; 129 }; 130 131 cooling-maps { 132 map1 { 133 trip = <&active1>; 134 cooling-device = <&fan0 1 THERMAL_NO_LIMIT>; 135 }; 136 }; 137 }; 138 }; 139}; 140 141/* TPM */ 142&ecspi1 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_ecspi1>; 148 status = "okay"; 149 150 tpm: tpm@0 { 151 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 152 reg = <0>; 153 spi-max-frequency = <38000000>; 154 }; 155}; 156 157&eqos { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_eqos>; 160 phy-mode = "rgmii-id"; 161 phy-handle = <ðphy0>; 162 status = "okay"; 163 164 mdio { 165 compatible = "snps,dwmac-mdio"; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 169 ethphy0: ethernet-phy@1 { 170 compatible = "ethernet-phy-ieee802.3-c22"; 171 reg = <0x1>; 172 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 173 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; 174 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 175 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 176 enet-phy-lane-no-swap; 177 }; 178 }; 179}; 180 181/* CAN FD */ 182&flexcan1 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_flexcan1>; 185 xceiver-supply = <®_can1_stby>; 186 status = "okay"; 187}; 188 189&flexcan2 { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_flexcan2>; 192 xceiver-supply = <®_can2_stby>; 193 status = "okay"; 194}; 195 196&i2c2 { 197 clock-frequency = <400000>; 198 pinctrl-names = "default", "gpio"; 199 pinctrl-0 = <&pinctrl_i2c2>; 200 pinctrl-1 = <&pinctrl_i2c2_gpio>; 201 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 202 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 203 status = "okay"; 204 205 eeprom@51 { 206 compatible = "atmel,24c02"; 207 reg = <0x51>; 208 pagesize = <16>; 209 vcc-supply = <®_vcc_3v3_sw>; 210 }; 211 212 leds@62 { 213 compatible = "nxp,pca9533"; 214 reg = <0x62>; 215 216 led-1 { 217 type = <PCA9532_TYPE_LED>; 218 }; 219 220 led-2 { 221 type = <PCA9532_TYPE_LED>; 222 }; 223 224 led-3 { 225 type = <PCA9532_TYPE_LED>; 226 }; 227 }; 228}; 229 230&ldb_lvds_ch1 { 231 remote-endpoint = <&panel1_in>; 232}; 233 234&snvs_pwrkey { 235 status = "okay"; 236}; 237 238&pcie_phy { 239 clocks = <&hsio_blk_ctrl>; 240 clock-names = "ref"; 241 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 242 fsl,clkreq-unsupported; 243 status = "okay"; 244}; 245 246/* Mini PCIe */ 247&pcie { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_pcie0>; 250 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; 251 vpcie-supply = <®_vcc_3v3_sw>; 252 status = "okay"; 253}; 254 255&pwm3 { 256 pinctrl-0 = <&pinctrl_pwm3>; 257 pinctrl-names = "default"; 258}; 259 260&rv3028 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_rtc>; 263 interrupt-parent = <&gpio4>; 264 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 265 aux-voltage-chargeable = <1>; 266 wakeup-source; 267 trickle-resistor-ohms = <3000>; 268}; 269 270/* debug console */ 271&uart1 { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_uart1>; 274 status = "okay"; 275}; 276 277/* USB1 Host mode Type-A */ 278&usb3_phy0 { 279 vbus-supply = <®_usb1_vbus>; 280 status = "okay"; 281}; 282 283&usb3_0 { 284 status = "okay"; 285}; 286 287&usb_dwc3_0 { 288 dr_mode = "host"; 289 status = "okay"; 290}; 291 292/* USB2 4-port USB3.0 HUB */ 293&usb3_phy1 { 294 vbus-supply = <®_vcc_5v_sw>; 295 status = "okay"; 296}; 297 298&usb3_1 { 299 fsl,permanently-attached; 300 fsl,disable-port-power-control; 301 status = "okay"; 302}; 303 304&usb_dwc3_1 { 305 dr_mode = "host"; 306 status = "okay"; 307}; 308 309/* RS232/RS485 */ 310&uart2 { 311 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 312 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_uart2>; 315 uart-has-rtscts; 316 status = "okay"; 317}; 318 319/* SD-Card */ 320&usdhc2 { 321 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 322 assigned-clock-rates = <200000000>; 323 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 324 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; 325 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; 326 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>; 327 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 328 disable-wp; 329 vmmc-supply = <®_usdhc2_vmmc>; 330 vqmmc-supply = <&ldo5>; 331 bus-width = <4>; 332 status = "okay"; 333}; 334 335&gpio1 { 336 gpio-line-names = "", "", "X_PMIC_WDOG_B", "", 337 "PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN", 338 "PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "", 339 "PCIe_nW_DISABLE"; 340}; 341 342&gpio2 { 343 gpio-line-names = "", "", "", "", 344 "", "", "", "", "", "", 345 "", "", "X_SD2_CD_B", "", "", "", 346 "", "", "", "SD2_RESET_B", "LVDS1_BL_EN"; 347}; 348 349&gpio3 { 350 gpio-line-names = "", "", "", "", 351 "", "", "", "", "", "", 352 "", "", "", "", "", "", 353 "", "", "", "", "nCAN1_EN", "nCAN2_EN"; 354}; 355 356&gpio4 { 357 gpio-line-names = "", "", "", "", 358 "", "", "", "", "", "", 359 "", "", "", "", "", "", 360 "", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN"; 361}; 362 363&gpio5 { 364 gpio-line-names = "", "", "", "", 365 "", "", "", "", "", "X_ECSPI1_SSO"; 366}; 367 368&iomuxc { 369 pinctrl_ecspi1: ecspi1grp { 370 fsl,pins = < 371 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80 372 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80 373 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80 374 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00 375 >; 376 }; 377 378 pinctrl_eqos: eqosgrp { 379 fsl,pins = < 380 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 381 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 382 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 383 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 384 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 385 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 386 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 387 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 388 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 389 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 390 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12 391 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12 392 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 393 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12 394 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 395 >; 396 }; 397 398 pinctrl_fan: fan0grp { 399 fsl,pins = < 400 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 401 >; 402 }; 403 404 pinctrl_flexcan1: flexcan1grp { 405 fsl,pins = < 406 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 407 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 408 >; 409 }; 410 411 pinctrl_flexcan2: flexcan2grp { 412 fsl,pins = < 413 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 414 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 415 >; 416 }; 417 418 pinctrl_flexcan1_reg: flexcan1reggrp { 419 fsl,pins = < 420 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 421 >; 422 }; 423 424 pinctrl_flexcan2_reg: flexcan2reggrp { 425 fsl,pins = < 426 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 427 >; 428 }; 429 430 pinctrl_i2c2: i2c2grp { 431 fsl,pins = < 432 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 433 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 434 >; 435 }; 436 437 pinctrl_i2c2_gpio: i2c2gpiogrp { 438 fsl,pins = < 439 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2 440 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2 441 >; 442 }; 443 444 pinctrl_lvds1: lvds1grp { 445 fsl,pins = < 446 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 447 >; 448 }; 449 450 pinctrl_pcie0: pcie0grp { 451 fsl,pins = < 452 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 453 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60 454 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */ 455 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 456 >; 457 }; 458 459 pinctrl_pwm3: pwm3grp { 460 fsl,pins = < 461 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12 462 >; 463 }; 464 465 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 466 fsl,pins = < 467 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 468 >; 469 }; 470 471 pinctrl_rtc: rtcgrp { 472 fsl,pins = < 473 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 474 >; 475 }; 476 477 pinctrl_uart1: uart1grp { 478 fsl,pins = < 479 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 480 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 481 >; 482 }; 483 484 pinctrl_usb1_vbus: usb1vbusgrp { 485 fsl,pins = < 486 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 487 >; 488 }; 489 490 pinctrl_uart2: uart2grp { 491 fsl,pins = < 492 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 493 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 494 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 495 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 496 >; 497 }; 498 499 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 500 fsl,pins = < 501 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40 502 >; 503 }; 504 505 pinctrl_usdhc2: usdhc2grp { 506 fsl,pins = < 507 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 508 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 509 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 510 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 511 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 512 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 513 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 514 >; 515 }; 516 517 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 518 fsl,pins = < 519 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 520 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 521 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 522 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 523 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 524 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 525 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 526 >; 527 }; 528 529 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 530 fsl,pins = < 531 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 532 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 533 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 534 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 535 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 536 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 537 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 538 >; 539 }; 540}; 541