1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4 #include <linux/ip.h>
5 #include <linux/sort.h>
6 #include <linux/udp.h>
7
8 #include "cam.h"
9 #include "chan.h"
10 #include "coex.h"
11 #include "core.h"
12 #include "efuse.h"
13 #include "fw.h"
14 #include "led.h"
15 #include "mac.h"
16 #include "phy.h"
17 #include "ps.h"
18 #include "reg.h"
19 #include "sar.h"
20 #include "ser.h"
21 #include "txrx.h"
22 #include "util.h"
23 #include "wow.h"
24
25 static bool rtw89_disable_ps_mode;
26 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
27 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
28
29 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
30 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
31 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
33 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
34 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
35 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
36 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
37 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
38 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
39
40 static struct ieee80211_channel rtw89_channels_2ghz[] = {
41 RTW89_DEF_CHAN_2G(2412, 1),
42 RTW89_DEF_CHAN_2G(2417, 2),
43 RTW89_DEF_CHAN_2G(2422, 3),
44 RTW89_DEF_CHAN_2G(2427, 4),
45 RTW89_DEF_CHAN_2G(2432, 5),
46 RTW89_DEF_CHAN_2G(2437, 6),
47 RTW89_DEF_CHAN_2G(2442, 7),
48 RTW89_DEF_CHAN_2G(2447, 8),
49 RTW89_DEF_CHAN_2G(2452, 9),
50 RTW89_DEF_CHAN_2G(2457, 10),
51 RTW89_DEF_CHAN_2G(2462, 11),
52 RTW89_DEF_CHAN_2G(2467, 12),
53 RTW89_DEF_CHAN_2G(2472, 13),
54 RTW89_DEF_CHAN_2G(2484, 14),
55 };
56
57 static struct ieee80211_channel rtw89_channels_5ghz[] = {
58 RTW89_DEF_CHAN_5G(5180, 36),
59 RTW89_DEF_CHAN_5G(5200, 40),
60 RTW89_DEF_CHAN_5G(5220, 44),
61 RTW89_DEF_CHAN_5G(5240, 48),
62 RTW89_DEF_CHAN_5G(5260, 52),
63 RTW89_DEF_CHAN_5G(5280, 56),
64 RTW89_DEF_CHAN_5G(5300, 60),
65 RTW89_DEF_CHAN_5G(5320, 64),
66 RTW89_DEF_CHAN_5G(5500, 100),
67 RTW89_DEF_CHAN_5G(5520, 104),
68 RTW89_DEF_CHAN_5G(5540, 108),
69 RTW89_DEF_CHAN_5G(5560, 112),
70 RTW89_DEF_CHAN_5G(5580, 116),
71 RTW89_DEF_CHAN_5G(5600, 120),
72 RTW89_DEF_CHAN_5G(5620, 124),
73 RTW89_DEF_CHAN_5G(5640, 128),
74 RTW89_DEF_CHAN_5G(5660, 132),
75 RTW89_DEF_CHAN_5G(5680, 136),
76 RTW89_DEF_CHAN_5G(5700, 140),
77 RTW89_DEF_CHAN_5G(5720, 144),
78 RTW89_DEF_CHAN_5G(5745, 149),
79 RTW89_DEF_CHAN_5G(5765, 153),
80 RTW89_DEF_CHAN_5G(5785, 157),
81 RTW89_DEF_CHAN_5G(5805, 161),
82 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
83 RTW89_DEF_CHAN_5G(5845, 169),
84 RTW89_DEF_CHAN_5G(5865, 173),
85 RTW89_DEF_CHAN_5G(5885, 177),
86 };
87
88 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
89 ARRAY_SIZE(rtw89_channels_5ghz));
90
91 static struct ieee80211_channel rtw89_channels_6ghz[] = {
92 RTW89_DEF_CHAN_6G(5955, 1),
93 RTW89_DEF_CHAN_6G(5975, 5),
94 RTW89_DEF_CHAN_6G(5995, 9),
95 RTW89_DEF_CHAN_6G(6015, 13),
96 RTW89_DEF_CHAN_6G(6035, 17),
97 RTW89_DEF_CHAN_6G(6055, 21),
98 RTW89_DEF_CHAN_6G(6075, 25),
99 RTW89_DEF_CHAN_6G(6095, 29),
100 RTW89_DEF_CHAN_6G(6115, 33),
101 RTW89_DEF_CHAN_6G(6135, 37),
102 RTW89_DEF_CHAN_6G(6155, 41),
103 RTW89_DEF_CHAN_6G(6175, 45),
104 RTW89_DEF_CHAN_6G(6195, 49),
105 RTW89_DEF_CHAN_6G(6215, 53),
106 RTW89_DEF_CHAN_6G(6235, 57),
107 RTW89_DEF_CHAN_6G(6255, 61),
108 RTW89_DEF_CHAN_6G(6275, 65),
109 RTW89_DEF_CHAN_6G(6295, 69),
110 RTW89_DEF_CHAN_6G(6315, 73),
111 RTW89_DEF_CHAN_6G(6335, 77),
112 RTW89_DEF_CHAN_6G(6355, 81),
113 RTW89_DEF_CHAN_6G(6375, 85),
114 RTW89_DEF_CHAN_6G(6395, 89),
115 RTW89_DEF_CHAN_6G(6415, 93),
116 RTW89_DEF_CHAN_6G(6435, 97),
117 RTW89_DEF_CHAN_6G(6455, 101),
118 RTW89_DEF_CHAN_6G(6475, 105),
119 RTW89_DEF_CHAN_6G(6495, 109),
120 RTW89_DEF_CHAN_6G(6515, 113),
121 RTW89_DEF_CHAN_6G(6535, 117),
122 RTW89_DEF_CHAN_6G(6555, 121),
123 RTW89_DEF_CHAN_6G(6575, 125),
124 RTW89_DEF_CHAN_6G(6595, 129),
125 RTW89_DEF_CHAN_6G(6615, 133),
126 RTW89_DEF_CHAN_6G(6635, 137),
127 RTW89_DEF_CHAN_6G(6655, 141),
128 RTW89_DEF_CHAN_6G(6675, 145),
129 RTW89_DEF_CHAN_6G(6695, 149),
130 RTW89_DEF_CHAN_6G(6715, 153),
131 RTW89_DEF_CHAN_6G(6735, 157),
132 RTW89_DEF_CHAN_6G(6755, 161),
133 RTW89_DEF_CHAN_6G(6775, 165),
134 RTW89_DEF_CHAN_6G(6795, 169),
135 RTW89_DEF_CHAN_6G(6815, 173),
136 RTW89_DEF_CHAN_6G(6835, 177),
137 RTW89_DEF_CHAN_6G(6855, 181),
138 RTW89_DEF_CHAN_6G(6875, 185),
139 RTW89_DEF_CHAN_6G(6895, 189),
140 RTW89_DEF_CHAN_6G(6915, 193),
141 RTW89_DEF_CHAN_6G(6935, 197),
142 RTW89_DEF_CHAN_6G(6955, 201),
143 RTW89_DEF_CHAN_6G(6975, 205),
144 RTW89_DEF_CHAN_6G(6995, 209),
145 RTW89_DEF_CHAN_6G(7015, 213),
146 RTW89_DEF_CHAN_6G(7035, 217),
147 RTW89_DEF_CHAN_6G(7055, 221),
148 RTW89_DEF_CHAN_6G(7075, 225),
149 RTW89_DEF_CHAN_6G(7095, 229),
150 RTW89_DEF_CHAN_6G(7115, 233),
151 };
152
153 static struct ieee80211_rate rtw89_bitrates[] = {
154 { .bitrate = 10, .hw_value = 0x00, },
155 { .bitrate = 20, .hw_value = 0x01, },
156 { .bitrate = 55, .hw_value = 0x02, },
157 { .bitrate = 110, .hw_value = 0x03, },
158 { .bitrate = 60, .hw_value = 0x04, },
159 { .bitrate = 90, .hw_value = 0x05, },
160 { .bitrate = 120, .hw_value = 0x06, },
161 { .bitrate = 180, .hw_value = 0x07, },
162 { .bitrate = 240, .hw_value = 0x08, },
163 { .bitrate = 360, .hw_value = 0x09, },
164 { .bitrate = 480, .hw_value = 0x0a, },
165 { .bitrate = 540, .hw_value = 0x0b, },
166 };
167
168 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
169 {
170 .max = 1,
171 .types = BIT(NL80211_IFTYPE_STATION),
172 },
173 {
174 .max = 1,
175 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
176 BIT(NL80211_IFTYPE_P2P_GO) |
177 BIT(NL80211_IFTYPE_AP),
178 },
179 };
180
181 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
182 {
183 .max = 1,
184 .types = BIT(NL80211_IFTYPE_STATION),
185 },
186 {
187 .max = 1,
188 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
189 BIT(NL80211_IFTYPE_P2P_GO),
190 },
191 };
192
193 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
194 {
195 .limits = rtw89_iface_limits,
196 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
197 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
198 .num_different_channels = 1,
199 },
200 {
201 .limits = rtw89_iface_limits_mcc,
202 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
203 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
204 .num_different_channels = 2,
205 },
206 };
207
208 static const u8 rtw89_ext_capa_sta[] = {
209 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
210 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
211 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
212 };
213
214 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = {
215 {
216 .iftype = NL80211_IFTYPE_STATION,
217 .extended_capabilities = rtw89_ext_capa_sta,
218 .extended_capabilities_mask = rtw89_ext_capa_sta,
219 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta),
220 /* relevant only if EHT is supported */
221 .eml_capabilities = 0,
222 .mld_capa_and_ops = 0,
223 },
224 };
225
226 #define RTW89_6GHZ_SPAN_HEAD 6145
227 #define RTW89_6GHZ_SPAN_IDX(center_freq) \
228 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2)
229
230 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \
231 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \
232 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \
233 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \
234 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \
235 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \
236 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \
237 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \
238 }
239
240 /* Since 6GHz subbands are not edge aligned, some cases span two subbands.
241 * In the following, we describe each of them with rtw89_6ghz_span.
242 */
243 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = {
244 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H),
245 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H),
246 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H),
247 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L),
248 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L),
249 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L),
250 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H),
251 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H),
252 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8),
253 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8),
254 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8),
255 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8),
256 };
257
258 const struct rtw89_6ghz_span *
rtw89_get_6ghz_span(struct rtw89_dev * rtwdev,u32 center_freq)259 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq)
260 {
261 int idx;
262
263 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) {
264 idx = RTW89_6GHZ_SPAN_IDX(center_freq);
265 /* To decrease size of rtw89_overlapping_6ghz[],
266 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs
267 * to make first span as index 0 of the table. So, if center
268 * frequency is less than the first one, it will get netative.
269 */
270 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz))
271 return &rtw89_overlapping_6ghz[idx];
272 }
273
274 return NULL;
275 }
276
rtw89_legacy_rate_to_bitrate(struct rtw89_dev * rtwdev,u8 legacy_rate,u16 * bitrate)277 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate)
278 {
279 const struct ieee80211_rate *rate;
280
281 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) {
282 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
283 "invalid legacy rate %d\n", legacy_rate);
284 return false;
285 }
286
287 rate = &rtw89_bitrates[legacy_rate];
288 *bitrate = rate->bitrate;
289
290 return true;
291 }
292
293 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
294 .band = NL80211_BAND_2GHZ,
295 .channels = rtw89_channels_2ghz,
296 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
297 .bitrates = rtw89_bitrates,
298 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
299 .ht_cap = {0},
300 .vht_cap = {0},
301 };
302
303 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
304 .band = NL80211_BAND_5GHZ,
305 .channels = rtw89_channels_5ghz,
306 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
307
308 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
309 .bitrates = rtw89_bitrates + 4,
310 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
311 .ht_cap = {0},
312 .vht_cap = {0},
313 };
314
315 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
316 .band = NL80211_BAND_6GHZ,
317 .channels = rtw89_channels_6ghz,
318 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
319
320 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
321 .bitrates = rtw89_bitrates + 4,
322 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
323 };
324
325 static const struct rtw89_hw_rate_def {
326 enum rtw89_hw_rate ht;
327 enum rtw89_hw_rate vht[RTW89_NSS_NUM];
328 } rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = {
329 [RTW89_CHIP_AX] = {
330 .ht = RTW89_HW_RATE_MCS0,
331 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0,
332 RTW89_HW_RATE_VHT_NSS2_MCS0,
333 RTW89_HW_RATE_VHT_NSS3_MCS0,
334 RTW89_HW_RATE_VHT_NSS4_MCS0},
335 },
336 [RTW89_CHIP_BE] = {
337 .ht = RTW89_HW_RATE_V1_MCS0,
338 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0,
339 RTW89_HW_RATE_V1_VHT_NSS2_MCS0,
340 RTW89_HW_RATE_V1_VHT_NSS3_MCS0,
341 RTW89_HW_RATE_V1_VHT_NSS4_MCS0},
342 },
343 };
344
rtw89_core_tx_skb_proto_stats(struct rtw89_traffic_stats * stats,struct sk_buff * skb)345 static void rtw89_core_tx_skb_proto_stats(struct rtw89_traffic_stats *stats,
346 struct sk_buff *skb)
347 {
348 switch (ip_hdr(skb)->protocol) {
349 case IPPROTO_TCP:
350 stats->tcp++;
351 break;
352 case IPPROTO_UDP:
353 stats->udp++;
354 break;
355 default:
356 break;
357 }
358 }
359
__rtw89_traffic_stats_accu(struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)360 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats,
361 struct sk_buff *skb, bool tx)
362 {
363 if (tx) {
364 rtw89_core_tx_skb_proto_stats(stats, skb);
365 stats->tx_cnt++;
366 stats->tx_unicast += skb->len;
367 } else {
368 stats->rx_cnt++;
369 stats->rx_unicast += skb->len;
370 }
371 }
372
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct sk_buff * skb,bool accu_dev,bool tx)373 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
374 struct rtw89_vif *rtwvif,
375 struct sk_buff *skb,
376 bool accu_dev, bool tx)
377 {
378 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
379
380 if (!ieee80211_is_data(hdr->frame_control))
381 return;
382
383 if (is_broadcast_ether_addr(hdr->addr1) ||
384 is_multicast_ether_addr(hdr->addr1))
385 return;
386
387 if (accu_dev)
388 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx);
389
390 if (rtwvif) {
391 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx);
392 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx);
393 }
394 }
395
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)396 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
397 {
398 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
399 NL80211_CHAN_NO_HT);
400 }
401
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)402 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
403 struct rtw89_chan *chan)
404 {
405 struct ieee80211_channel *channel = chandef->chan;
406 enum nl80211_chan_width width = chandef->width;
407 u32 primary_freq, center_freq;
408 u8 center_chan;
409 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
410 u32 offset;
411 u8 band;
412
413 center_chan = channel->hw_value;
414 primary_freq = channel->center_freq;
415 center_freq = chandef->center_freq1;
416
417 switch (width) {
418 case NL80211_CHAN_WIDTH_20_NOHT:
419 case NL80211_CHAN_WIDTH_20:
420 bandwidth = RTW89_CHANNEL_WIDTH_20;
421 break;
422 case NL80211_CHAN_WIDTH_40:
423 bandwidth = RTW89_CHANNEL_WIDTH_40;
424 if (primary_freq > center_freq) {
425 center_chan -= 2;
426 } else {
427 center_chan += 2;
428 }
429 break;
430 case NL80211_CHAN_WIDTH_80:
431 case NL80211_CHAN_WIDTH_160:
432 bandwidth = nl_to_rtw89_bandwidth(width);
433 if (primary_freq > center_freq) {
434 offset = (primary_freq - center_freq - 10) / 20;
435 center_chan -= 2 + offset * 4;
436 } else {
437 offset = (center_freq - primary_freq - 10) / 20;
438 center_chan += 2 + offset * 4;
439 }
440 break;
441 default:
442 center_chan = 0;
443 break;
444 }
445
446 switch (channel->band) {
447 default:
448 case NL80211_BAND_2GHZ:
449 band = RTW89_BAND_2G;
450 break;
451 case NL80211_BAND_5GHZ:
452 band = RTW89_BAND_5G;
453 break;
454 case NL80211_BAND_6GHZ:
455 band = RTW89_BAND_6G;
456 break;
457 }
458
459 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
460 }
461
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)462 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
463 const struct rtw89_chan *chan,
464 enum rtw89_phy_idx phy_idx)
465 {
466 const struct rtw89_chip_info *chip = rtwdev->chip;
467 bool entity_active;
468
469 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
470 if (!entity_active)
471 return;
472
473 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
474 }
475
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)476 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
477 {
478 struct rtw89_entity_conf conf;
479
480 rtw89_entity_get_conf(rtwdev, &conf);
481
482 __rtw89_core_set_chip_txpwr(rtwdev, conf.chans[0], RTW89_PHY_0);
483
484 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
485 return;
486
487 __rtw89_core_set_chip_txpwr(rtwdev, conf.chans[1], RTW89_PHY_1);
488 }
489
rtw89_core_rfk_record(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)490 static void rtw89_core_rfk_record(struct rtw89_dev *rtwdev,
491 struct rtw89_vif_link *rtwvif_link,
492 bool start)
493 {
494 struct rtw89_rfk_wait_info *info = &rtwdev->rfk_wait;
495 struct rtw89_rfk_record *record = &info->records[info->record_idx];
496 const struct rtw89_chip_info *chip = rtwdev->chip;
497 u8 path_num = min(chip->rf_path_num, RTW89_RFK_RECORD_PATH_NR);
498 int path;
499
500 if (!start)
501 goto end;
502
503 info->record_ptr = record;
504 record->phy_idx = rtwvif_link->phy_idx;
505
506 for (path = 0; path < path_num; path++) {
507 record->ch[path] = rtw89_read_rf(rtwdev, path, RR_CFGCH,
508 RR_CFGCH_BAND0 | RR_CFGCH_CH);
509 record->cv[path] = rtw89_read_rf(rtwdev, path, RR_VCO,
510 RR_VCO_SEL | RR_VCO_STS);
511 record->c5[path] = rtw89_read_rf(rtwdev, path, RR_SYNFB, RFREG_MASK);
512 }
513
514 return;
515
516 end:
517 info->record_idx = (info->record_idx + 1) % RTW89_RFK_RECORD_HISTORY_NR;
518 info->record_ptr = NULL;
519 }
520
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)521 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
522 struct rtw89_vif_link *rtwvif_link)
523 {
524 const struct rtw89_chip_info *chip = rtwdev->chip;
525 bool mon = !!rtwdev->pure_monitor_mode_vif;
526 bool prehdl_link = false;
527
528 if (chip->chip_gen != RTW89_CHIP_AX &&
529 !RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) &&
530 !mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx))
531 prehdl_link = true;
532
533 if (prehdl_link) {
534 rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx);
535 rtw89_set_channel(rtwdev);
536 }
537
538 if (chip->ops->rfk_channel) {
539 rtw89_core_rfk_record(rtwdev, rtwvif_link, true);
540
541 chip->ops->rfk_channel(rtwdev, rtwvif_link);
542
543 rtw89_core_rfk_record(rtwdev, rtwvif_link, false);
544 }
545
546 if (prehdl_link) {
547 rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM);
548 rtw89_set_channel(rtwdev);
549 }
550 }
551
rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)552 static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev,
553 enum rtw89_phy_idx phy_idx)
554 {
555 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif;
556 struct rtw89_vif_link *rtwvif_link;
557
558 if (!rtwvif)
559 return;
560
561 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx);
562 if (!rtwvif_link)
563 return;
564
565 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
566 }
567
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)568 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
569 const struct rtw89_chan *chan,
570 enum rtw89_mac_idx mac_idx,
571 enum rtw89_phy_idx phy_idx)
572 {
573 const struct rtw89_chip_info *chip = rtwdev->chip;
574 const struct rtw89_chan_rcd *chan_rcd;
575 struct rtw89_channel_help_params bak;
576 bool entity_active;
577
578 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
579
580 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
581
582 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
583
584 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
585
586 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
587
588 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
589
590 if (!entity_active || chan_rcd->band_changed) {
591 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
592 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
593 }
594
595 rtw89_set_entity_state(rtwdev, phy_idx, true);
596
597 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx);
598 }
599
rtw89_set_channel(struct rtw89_dev * rtwdev)600 int rtw89_set_channel(struct rtw89_dev *rtwdev)
601 {
602 struct rtw89_entity_conf conf;
603 enum rtw89_entity_mode mode;
604
605 mode = rtw89_entity_recalc(rtwdev);
606 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
607 WARN(1, "Invalid ent mode: %d\n", mode);
608 return -EINVAL;
609 }
610
611 rtw89_entity_get_conf(rtwdev, &conf);
612
613 __rtw89_set_channel(rtwdev, conf.chans[0], RTW89_MAC_0, RTW89_PHY_0);
614
615 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
616 return 0;
617
618 __rtw89_set_channel(rtwdev, conf.chans[1], RTW89_MAC_1, RTW89_PHY_1);
619
620 return 0;
621 }
622
623 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)624 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
625 struct sk_buff *skb)
626 {
627 struct ieee80211_hdr *hdr = (void *)skb->data;
628 __le16 fc = hdr->frame_control;
629
630 if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
631 return RTW89_CORE_TX_TYPE_MGMT;
632
633 return RTW89_CORE_TX_TYPE_DATA;
634 }
635
636 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)637 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
638 struct rtw89_core_tx_request *tx_req,
639 enum btc_pkt_type pkt_type)
640 {
641 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
642 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
643 struct ieee80211_link_sta *link_sta;
644 struct sk_buff *skb = tx_req->skb;
645 struct rtw89_sta *rtwsta;
646 u8 ampdu_num;
647 u8 tid;
648
649 if (pkt_type == PACKET_EAPOL) {
650 desc_info->bk = true;
651 return;
652 }
653
654 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
655 return;
656
657 if (!rtwsta_link) {
658 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
659 return;
660 }
661
662 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
663 rtwsta = rtwsta_link->rtwsta;
664
665 rcu_read_lock();
666
667 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
668 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
669 rtwsta->ampdu_params[tid].agg_num :
670 4 << link_sta->ht_cap.ampdu_factor) - 1);
671
672 desc_info->agg_en = true;
673 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
674 desc_info->ampdu_num = ampdu_num;
675
676 rcu_read_unlock();
677 }
678
679 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)680 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
681 struct rtw89_core_tx_request *tx_req)
682 {
683 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
684 const struct rtw89_chip_info *chip = rtwdev->chip;
685 const struct rtw89_sec_cam_entry *sec_cam;
686 struct ieee80211_tx_info *info;
687 struct ieee80211_key_conf *key;
688 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
689 struct sk_buff *skb = tx_req->skb;
690 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
691 u8 sec_cam_idx;
692 u64 pn64;
693
694 info = IEEE80211_SKB_CB(skb);
695 key = info->control.hw_key;
696 sec_cam_idx = key->hw_key_idx;
697 sec_cam = cam_info->sec_entries[sec_cam_idx];
698 if (!sec_cam) {
699 rtw89_warn(rtwdev, "sec cam entry is empty\n");
700 return;
701 }
702
703 switch (key->cipher) {
704 case WLAN_CIPHER_SUITE_WEP40:
705 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
706 break;
707 case WLAN_CIPHER_SUITE_WEP104:
708 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
709 break;
710 case WLAN_CIPHER_SUITE_TKIP:
711 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
712 break;
713 case WLAN_CIPHER_SUITE_CCMP:
714 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
715 break;
716 case WLAN_CIPHER_SUITE_CCMP_256:
717 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
718 break;
719 case WLAN_CIPHER_SUITE_GCMP:
720 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
721 break;
722 case WLAN_CIPHER_SUITE_GCMP_256:
723 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
724 break;
725 default:
726 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
727 return;
728 }
729
730 desc_info->sec_en = true;
731 desc_info->sec_keyid = key->keyidx;
732 desc_info->sec_type = sec_type;
733 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
734
735 if (!chip->hw_sec_hdr)
736 return;
737
738 pn64 = atomic64_inc_return(&key->tx_pn);
739 desc_info->sec_seq[0] = pn64;
740 desc_info->sec_seq[1] = pn64 >> 8;
741 desc_info->sec_seq[2] = pn64 >> 16;
742 desc_info->sec_seq[3] = pn64 >> 24;
743 desc_info->sec_seq[4] = pn64 >> 32;
744 desc_info->sec_seq[5] = pn64 >> 40;
745 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
746 }
747
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)748 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
749 struct rtw89_core_tx_request *tx_req,
750 const struct rtw89_chan *chan)
751 {
752 struct sk_buff *skb = tx_req->skb;
753 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
754 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
755 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
756 struct ieee80211_vif *vif = tx_info->control.vif;
757 struct ieee80211_bss_conf *bss_conf;
758 u16 lowest_rate;
759 u16 rate;
760
761 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
762 (vif && vif->p2p))
763 lowest_rate = RTW89_HW_RATE_OFDM6;
764 else if (chan->band_type == RTW89_BAND_2G)
765 lowest_rate = RTW89_HW_RATE_CCK1;
766 else
767 lowest_rate = RTW89_HW_RATE_OFDM6;
768
769 if (!rtwvif_link)
770 return lowest_rate;
771
772 rcu_read_lock();
773
774 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
775 if (!bss_conf->basic_rates || !rtwsta_link) {
776 rate = lowest_rate;
777 goto out;
778 }
779
780 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
781
782 out:
783 rcu_read_unlock();
784
785 return rate;
786 }
787
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)788 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
789 struct rtw89_core_tx_request *tx_req)
790 {
791 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
792 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
793 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
794
795 if (desc_info->mlo && !desc_info->sw_mld) {
796 if (rtwsta_link)
797 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta);
798 else
799 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif);
800 }
801
802 if (!rtwsta_link)
803 return rtwvif_link->mac_id;
804
805 return rtwsta_link->mac_id;
806 }
807
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)808 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
809 struct rtw89_tx_desc_info *desc_info,
810 struct sk_buff *skb)
811 {
812 struct ieee80211_hdr *hdr = (void *)skb->data;
813 __le16 fc = hdr->frame_control;
814
815 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
816 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
817 }
818
rtw89_core_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)819 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
820 {
821 switch (qsel) {
822 default:
823 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
824 fallthrough;
825 case RTW89_TX_QSEL_BE_0:
826 case RTW89_TX_QSEL_BE_1:
827 case RTW89_TX_QSEL_BE_2:
828 case RTW89_TX_QSEL_BE_3:
829 return RTW89_TXCH_ACH0;
830 case RTW89_TX_QSEL_BK_0:
831 case RTW89_TX_QSEL_BK_1:
832 case RTW89_TX_QSEL_BK_2:
833 case RTW89_TX_QSEL_BK_3:
834 return RTW89_TXCH_ACH1;
835 case RTW89_TX_QSEL_VI_0:
836 case RTW89_TX_QSEL_VI_1:
837 case RTW89_TX_QSEL_VI_2:
838 case RTW89_TX_QSEL_VI_3:
839 return RTW89_TXCH_ACH2;
840 case RTW89_TX_QSEL_VO_0:
841 case RTW89_TX_QSEL_VO_1:
842 case RTW89_TX_QSEL_VO_2:
843 case RTW89_TX_QSEL_VO_3:
844 return RTW89_TXCH_ACH3;
845 case RTW89_TX_QSEL_B0_MGMT:
846 return RTW89_TXCH_CH8;
847 case RTW89_TX_QSEL_B0_HI:
848 return RTW89_TXCH_CH9;
849 case RTW89_TX_QSEL_B1_MGMT:
850 return RTW89_TXCH_CH10;
851 case RTW89_TX_QSEL_B1_HI:
852 return RTW89_TXCH_CH11;
853 }
854 }
855 EXPORT_SYMBOL(rtw89_core_get_ch_dma);
856
rtw89_core_get_ch_dma_v1(struct rtw89_dev * rtwdev,u8 qsel)857 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel)
858 {
859 switch (qsel) {
860 default:
861 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel);
862 fallthrough;
863 case RTW89_TX_QSEL_BE_0:
864 case RTW89_TX_QSEL_BK_0:
865 return RTW89_TXCH_ACH0;
866 case RTW89_TX_QSEL_VI_0:
867 case RTW89_TX_QSEL_VO_0:
868 return RTW89_TXCH_ACH2;
869 case RTW89_TX_QSEL_B0_MGMT:
870 case RTW89_TX_QSEL_B0_HI:
871 return RTW89_TXCH_CH8;
872 case RTW89_TX_QSEL_B1_MGMT:
873 case RTW89_TX_QSEL_B1_HI:
874 return RTW89_TXCH_CH10;
875 }
876 }
877 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1);
878
rtw89_core_get_ch_dma_v2(struct rtw89_dev * rtwdev,u8 qsel)879 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel)
880 {
881 switch (qsel) {
882 default:
883 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel);
884 fallthrough;
885 case RTW89_TX_QSEL_BE_0:
886 case RTW89_TX_QSEL_VO_0:
887 return RTW89_TXCH_ACH0;
888 case RTW89_TX_QSEL_BK_0:
889 case RTW89_TX_QSEL_VI_0:
890 return RTW89_TXCH_ACH2;
891 case RTW89_TX_QSEL_B0_MGMT:
892 case RTW89_TX_QSEL_B0_HI:
893 return RTW89_TXCH_CH8;
894 case RTW89_TX_QSEL_B1_MGMT:
895 case RTW89_TX_QSEL_B1_HI:
896 return RTW89_TXCH_CH10;
897 }
898 }
899 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2);
900
901 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)902 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
903 struct rtw89_core_tx_request *tx_req)
904 {
905 const struct rtw89_chip_info *chip = rtwdev->chip;
906 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
907 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
908 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
909 rtwvif_link->chanctx_idx);
910 struct sk_buff *skb = tx_req->skb;
911 u8 qsel, ch_dma;
912
913 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req);
914 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
915
916 desc_info->qsel = qsel;
917 desc_info->ch_dma = ch_dma;
918 desc_info->sw_mld = true;
919 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
920 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
921 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
922 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
923
924 /* fixed data rate for mgmt frames */
925 desc_info->en_wd_info = true;
926 desc_info->use_rate = true;
927 desc_info->dis_data_fb = true;
928 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
929
930 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
931 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
932 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
933 }
934
935 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
936 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
937 desc_info->data_rate, chan->channel, chan->band_type,
938 chan->band_width);
939 }
940
941 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)942 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
943 struct rtw89_core_tx_request *tx_req)
944 {
945 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
946
947 desc_info->is_bmc = false;
948 desc_info->wd_page = false;
949 desc_info->ch_dma = RTW89_DMA_H2C;
950 }
951
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)952 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
953 const struct rtw89_chan *chan)
954 {
955 static const u8 rtw89_bandwidth_to_om[] = {
956 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
957 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
958 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
959 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
960 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
961 };
962 const struct rtw89_chip_info *chip = rtwdev->chip;
963 struct rtw89_hal *hal = &rtwdev->hal;
964 u8 om_bandwidth;
965
966 if (!chip->dis_2g_40m_ul_ofdma ||
967 chan->band_type != RTW89_BAND_2G ||
968 chan->band_width != RTW89_CHANNEL_WIDTH_40)
969 return;
970
971 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
972 rtw89_bandwidth_to_om[chan->band_width] : 0;
973 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
974 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
975 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
976 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
977 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
978 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
979 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
980 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
981 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
982 }
983
984 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)985 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
986 struct rtw89_core_tx_request *tx_req,
987 enum btc_pkt_type pkt_type)
988 {
989 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
990 struct ieee80211_vif *vif = tx_req->vif;
991 struct sk_buff *skb = tx_req->skb;
992 struct ieee80211_hdr *hdr = (void *)skb->data;
993 struct ieee80211_link_sta *link_sta;
994 __le16 fc = hdr->frame_control;
995
996 /* AP IOT issue with EAPoL, ARP and DHCP */
997 if (pkt_type < PACKET_MAX)
998 return false;
999
1000 if (!rtwsta_link)
1001 return false;
1002
1003 rcu_read_lock();
1004
1005 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
1006 if (!link_sta->he_cap.has_he) {
1007 rcu_read_unlock();
1008 return false;
1009 }
1010
1011 rcu_read_unlock();
1012
1013 if (!ieee80211_is_data_qos(fc))
1014 return false;
1015
1016 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
1017 return false;
1018
1019 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
1020 return false;
1021
1022 if (vif->type == NL80211_IFTYPE_AP)
1023 return false;
1024
1025 return true;
1026 }
1027
1028 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1029 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
1030 struct rtw89_core_tx_request *tx_req)
1031 {
1032 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1033 struct sk_buff *skb = tx_req->skb;
1034 struct ieee80211_hdr *hdr = (void *)skb->data;
1035 __le16 fc = hdr->frame_control;
1036 void *data;
1037 __le32 *htc;
1038 u8 *qc;
1039 int hdr_len;
1040
1041 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
1042 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
1043 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
1044
1045 hdr = data;
1046 htc = data + hdr_len;
1047 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
1048 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
1049 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
1050 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
1051
1052 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
1053 qc[0] |= IEEE80211_QOS_CTL_EOSP;
1054 }
1055
1056 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)1057 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
1058 struct rtw89_core_tx_request *tx_req,
1059 enum btc_pkt_type pkt_type)
1060 {
1061 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1062 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1063
1064 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
1065 goto desc_bk;
1066
1067 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
1068
1069 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
1070 desc_info->a_ctrl_bsr = true;
1071
1072 desc_bk:
1073 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
1074 return;
1075
1076 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
1077 desc_info->bk = true;
1078 }
1079
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1080 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
1081 struct rtw89_core_tx_request *tx_req)
1082 {
1083 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1084 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1085 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1086 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
1087 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
1088 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
1089 struct ieee80211_link_sta *link_sta;
1090 u16 lowest_rate;
1091 u16 rate;
1092
1093 if (rate_pattern->enable)
1094 return rate_pattern->rate;
1095
1096 if (vif->p2p)
1097 lowest_rate = RTW89_HW_RATE_OFDM6;
1098 else if (chan->band_type == RTW89_BAND_2G)
1099 lowest_rate = RTW89_HW_RATE_CCK1;
1100 else
1101 lowest_rate = RTW89_HW_RATE_OFDM6;
1102
1103 if (!rtwsta_link)
1104 return lowest_rate;
1105
1106 rcu_read_lock();
1107
1108 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
1109 if (!link_sta->supp_rates[chan->band_type]) {
1110 rate = lowest_rate;
1111 goto out;
1112 }
1113
1114 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
1115
1116 out:
1117 rcu_read_unlock();
1118
1119 return rate;
1120 }
1121
1122 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1123 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
1124 struct rtw89_core_tx_request *tx_req)
1125 {
1126 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1127 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1128 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1129 struct sk_buff *skb = tx_req->skb;
1130 u8 tid, tid_indicate;
1131 u8 qsel, ch_dma;
1132
1133 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
1134 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
1135 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
1136 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1137
1138 desc_info->ch_dma = ch_dma;
1139 desc_info->tid_indicate = tid_indicate;
1140 desc_info->qsel = qsel;
1141 desc_info->sw_mld = false;
1142 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
1143 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
1144 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
1145 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
1146 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
1147
1148 /* enable wd_info for AMPDU */
1149 desc_info->en_wd_info = true;
1150
1151 if (IEEE80211_SKB_CB(skb)->control.hw_key)
1152 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
1153
1154 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
1155 }
1156
1157 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1158 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
1159 struct rtw89_core_tx_request *tx_req)
1160 {
1161 struct wiphy *wiphy = rtwdev->hw->wiphy;
1162 struct sk_buff *skb = tx_req->skb;
1163 struct udphdr *udphdr;
1164
1165 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
1166 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work);
1167 return PACKET_EAPOL;
1168 }
1169
1170 if (skb->protocol == htons(ETH_P_ARP)) {
1171 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work);
1172 return PACKET_ARP;
1173 }
1174
1175 if (skb->protocol == htons(ETH_P_IP) &&
1176 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1177 udphdr = udp_hdr(skb);
1178 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
1179 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
1180 skb->len > 282) {
1181 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work);
1182 return PACKET_DHCP;
1183 }
1184 }
1185
1186 if (skb->protocol == htons(ETH_P_IP) &&
1187 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
1188 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work);
1189 return PACKET_ICMP;
1190 }
1191
1192 return PACKET_MAX;
1193 }
1194
1195 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1196 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
1197 struct rtw89_core_tx_request *tx_req)
1198 {
1199 const struct rtw89_chip_info *chip = rtwdev->chip;
1200
1201 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
1202 return;
1203
1204 switch (chip->chip_id) {
1205 case RTL8852BT:
1206 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags))
1207 goto notify;
1208 break;
1209 case RTL8852C:
1210 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
1211 goto notify;
1212 break;
1213 default:
1214 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) &&
1215 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT)
1216 goto notify;
1217 break;
1218 }
1219
1220 return;
1221
1222 notify:
1223 rtw89_mac_notify_wake(rtwdev);
1224 }
1225
rtw89_core_tx_update_injection(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,struct ieee80211_tx_info * info)1226 static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev,
1227 struct rtw89_core_tx_request *tx_req,
1228 struct ieee80211_tx_info *info)
1229 {
1230 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen];
1231 enum mac80211_rate_control_flags flags = info->control.rates[0].flags;
1232 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1233 const struct rtw89_chan *chan;
1234 u8 idx = info->control.rates[0].idx;
1235 u8 nss, mcs;
1236
1237 desc_info->use_rate = true;
1238 desc_info->dis_data_fb = true;
1239
1240 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
1241 desc_info->data_bw = 3;
1242 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
1243 desc_info->data_bw = 2;
1244 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1245 desc_info->data_bw = 1;
1246
1247 if (flags & IEEE80211_TX_RC_SHORT_GI)
1248 desc_info->gi_ltf = 1;
1249
1250 if (flags & IEEE80211_TX_RC_VHT_MCS) {
1251 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1);
1252 mcs = idx & 0xf;
1253 desc_info->data_rate = hw_rate->vht[nss] + mcs;
1254 } else if (flags & IEEE80211_TX_RC_MCS) {
1255 desc_info->data_rate = hw_rate->ht + idx;
1256 } else {
1257 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx);
1258
1259 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ?
1260 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6);
1261 }
1262 }
1263
1264 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1265 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
1266 struct rtw89_core_tx_request *tx_req)
1267 {
1268 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1269 struct sk_buff *skb = tx_req->skb;
1270 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1271 struct ieee80211_hdr *hdr = (void *)skb->data;
1272 struct rtw89_addr_cam_entry *addr_cam;
1273 enum btc_pkt_type pkt_type;
1274 bool upd_wlan_hdr = false;
1275 bool is_bmc;
1276 u16 seq;
1277
1278 desc_info->pkt_size = skb->len;
1279
1280 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) {
1281 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1282 return;
1283 }
1284
1285 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1286
1287 if (tx_req->sta)
1288 desc_info->mlo = tx_req->sta->mlo;
1289 else if (tx_req->vif)
1290 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
1291
1292 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
1293 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1294 tx_req->rtwsta_link);
1295 if (addr_cam->valid && desc_info->mlo)
1296 upd_wlan_hdr = true;
1297
1298 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait)
1299 rtw89_tx_rpt_init(rtwdev, tx_req);
1300
1301 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
1302 is_multicast_ether_addr(hdr->addr1));
1303
1304 desc_info->seq = seq;
1305 desc_info->is_bmc = is_bmc;
1306 desc_info->wd_page = true;
1307 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
1308 desc_info->upd_wlan_hdr = upd_wlan_hdr;
1309
1310 switch (tx_req->tx_type) {
1311 case RTW89_CORE_TX_TYPE_MGMT:
1312 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
1313 break;
1314 case RTW89_CORE_TX_TYPE_DATA:
1315 rtw89_core_tx_update_data_info(rtwdev, tx_req);
1316 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
1317 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
1318 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1319 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1320 break;
1321 default:
1322 break;
1323 }
1324
1325 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED))
1326 rtw89_core_tx_update_injection(rtwdev, tx_req, info);
1327 }
1328
rtw89_tx_wait_work(struct wiphy * wiphy,struct wiphy_work * work)1329 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work)
1330 {
1331 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1332 tx_wait_work.work);
1333
1334 rtw89_tx_wait_list_clear(rtwdev);
1335 }
1336
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)1337 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
1338 {
1339 u8 ch_dma;
1340
1341 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1342
1343 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
1344 }
1345
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_tx_wait_info * wait,int qsel,unsigned int timeout)1346 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1347 struct rtw89_tx_wait_info *wait, int qsel,
1348 unsigned int timeout)
1349 {
1350 unsigned long time_left;
1351 int ret = 0;
1352
1353 lockdep_assert_wiphy(rtwdev->hw->wiphy);
1354
1355 rtw89_core_tx_kick_off(rtwdev, qsel);
1356 time_left = wait_for_completion_timeout(&wait->completion,
1357 msecs_to_jiffies(timeout));
1358
1359 if (time_left == 0) {
1360 ret = -ETIMEDOUT;
1361 list_add_tail(&wait->list, &rtwdev->tx_waits);
1362 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work,
1363 RTW89_TX_WAIT_WORK_TIMEOUT);
1364 } else {
1365 if (!wait->tx_done)
1366 ret = -EAGAIN;
1367 rtw89_tx_wait_release(wait);
1368 }
1369
1370 return ret;
1371 }
1372
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1373 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1374 struct sk_buff *skb, bool fwdl)
1375 {
1376 struct rtw89_core_tx_request tx_req = {0};
1377 u32 cnt;
1378 int ret;
1379
1380 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1381 rtw89_debug(rtwdev, RTW89_DBG_FW,
1382 "ignore h2c due to power is off with firmware state=%d\n",
1383 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1384 dev_kfree_skb(skb);
1385 return 0;
1386 }
1387
1388 tx_req.skb = skb;
1389 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1390 if (fwdl)
1391 tx_req.desc_info.fw_dl = true;
1392
1393 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1394
1395 if (!fwdl)
1396 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1397
1398 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1399 if (cnt == 0) {
1400 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1401 return -ENOSPC;
1402 }
1403
1404 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1405 if (ret) {
1406 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1407 return ret;
1408 }
1409 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1410
1411 return 0;
1412 }
1413
rtw89_core_tx_write_link(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct sk_buff * skb,int * qsel,struct rtw89_tx_wait_info * wait)1414 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev,
1415 struct rtw89_vif_link *rtwvif_link,
1416 struct rtw89_sta_link *rtwsta_link,
1417 struct sk_buff *skb, int *qsel,
1418 struct rtw89_tx_wait_info *wait)
1419 {
1420 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
1421 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1422 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1423 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1424 struct rtw89_core_tx_request tx_req = {};
1425 int ret;
1426
1427 tx_req.skb = skb;
1428 tx_req.vif = vif;
1429 tx_req.sta = sta;
1430 tx_req.rtwvif_link = rtwvif_link;
1431 tx_req.rtwsta_link = rtwsta_link;
1432 tx_req.with_wait = !!wait;
1433
1434 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true);
1435 rtw89_wow_parse_akm(rtwdev, skb);
1436 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1437 rtw89_core_tx_wake(rtwdev, &tx_req);
1438
1439 rcu_assign_pointer(skb_data->wait, wait);
1440
1441 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1442 if (ret) {
1443 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1444 return ret;
1445 }
1446
1447 if (qsel)
1448 *qsel = tx_req.desc_info.qsel;
1449
1450 return 0;
1451 }
1452
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1453 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1454 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1455 {
1456 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1457 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1458 struct rtw89_sta_link *rtwsta_link = NULL;
1459 struct rtw89_vif_link *rtwvif_link;
1460
1461 if (rtwsta) {
1462 rtwsta_link = rtw89_get_designated_link(rtwsta);
1463 if (unlikely(!rtwsta_link)) {
1464 rtw89_err(rtwdev, "tx: find no sta designated link\n");
1465 return -ENOLINK;
1466 }
1467
1468 rtwvif_link = rtwsta_link->rtwvif_link;
1469 } else {
1470 rtwvif_link = rtw89_get_designated_link(rtwvif);
1471 if (unlikely(!rtwvif_link)) {
1472 rtw89_err(rtwdev, "tx: find no vif designated link\n");
1473 return -ENOLINK;
1474 }
1475 }
1476
1477 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL);
1478 }
1479
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1480 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1481 {
1482 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1483 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1484 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1485 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1486 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1487 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1488 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1489 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1490
1491 return cpu_to_le32(dword);
1492 }
1493
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1494 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1495 {
1496 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1497 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1498 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1499 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1500 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1501 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1502
1503 return cpu_to_le32(dword);
1504 }
1505
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1506 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1507 {
1508 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1509 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1510 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1511
1512 return cpu_to_le32(dword);
1513 }
1514
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1515 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1516 {
1517 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1518 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1519 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1520 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1521
1522 return cpu_to_le32(dword);
1523 }
1524
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1525 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1526 {
1527 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1528 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1529 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1530
1531 return cpu_to_le32(dword);
1532 }
1533
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1534 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1535 {
1536 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1537 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1538
1539 return cpu_to_le32(dword);
1540 }
1541
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1542 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1543 {
1544 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1545 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1546 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1547 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1548
1549 return cpu_to_le32(dword);
1550 }
1551
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1552 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1553 {
1554 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1555 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) |
1556 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) |
1557 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1558
1559 return cpu_to_le32(dword);
1560 }
1561
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1562 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1563 {
1564 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1565 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) |
1566 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) |
1567 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1568 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1569 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1570 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1571 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1572
1573 return cpu_to_le32(dword);
1574 }
1575
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1576 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1577 {
1578 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1579 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1580 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1581 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1582 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1583 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1584
1585 return cpu_to_le32(dword);
1586 }
1587
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1588 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1589 {
1590 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1591 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1592 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1593 desc_info->data_retry_lowest_rate) |
1594 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL,
1595 desc_info->tx_cnt_lmt_en) |
1596 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1597
1598 return cpu_to_le32(dword);
1599 }
1600
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1601 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1602 {
1603 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1604 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1605 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1606 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1607
1608 return cpu_to_le32(dword);
1609 }
1610
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1611 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1612 {
1613 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1614 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1615 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1616
1617 return cpu_to_le32(dword);
1618 }
1619
rtw89_build_txwd_info3(struct rtw89_tx_desc_info * desc_info)1620 static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info)
1621 {
1622 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report);
1623
1624 return cpu_to_le32(dword);
1625 }
1626
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1627 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1628 {
1629 bool rts_en = !desc_info->is_bmc;
1630 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1631 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) |
1632 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn);
1633
1634 return cpu_to_le32(dword);
1635 }
1636
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1637 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1638 struct rtw89_tx_desc_info *desc_info,
1639 void *txdesc)
1640 {
1641 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1642 struct rtw89_txwd_info *txwd_info;
1643
1644 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1645 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1646 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1647
1648 if (!desc_info->en_wd_info)
1649 return;
1650
1651 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1652 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1653 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1654 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1655 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1656 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1657
1658 }
1659 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1660
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1661 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1662 struct rtw89_tx_desc_info *desc_info,
1663 void *txdesc)
1664 {
1665 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1666 struct rtw89_txwd_info *txwd_info;
1667
1668 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1669 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1670 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1671 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1672 if (desc_info->sec_en) {
1673 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1674 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1675 }
1676 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1677
1678 if (!desc_info->en_wd_info)
1679 return;
1680
1681 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1682 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1683 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1684 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1685 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1686 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1687 }
1688 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1689
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1690 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1691 {
1692 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1693 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1694 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1695 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1696 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1697
1698 return cpu_to_le32(dword);
1699 }
1700
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1701 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1702 {
1703 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1704 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1705 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1706
1707 return cpu_to_le32(dword);
1708 }
1709
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1710 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1711 {
1712 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1713 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1714 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1715 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1716 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1717 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1718
1719 return cpu_to_le32(dword);
1720 }
1721
rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info * desc_info)1722 static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info)
1723 {
1724 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) |
1725 FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) |
1726 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1727 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1728 FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id);
1729
1730 return cpu_to_le32(dword);
1731 }
1732
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1733 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1734 {
1735 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1736 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1737 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld);
1738
1739 return cpu_to_le32(dword);
1740 }
1741
rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info * desc_info)1742 static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info)
1743 {
1744 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1745 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1746 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) |
1747 FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk);
1748
1749 return cpu_to_le32(dword);
1750 }
1751
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1752 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1753 {
1754 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1755 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1756
1757 return cpu_to_le32(dword);
1758 }
1759
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1760 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1761 {
1762 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1763 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1764 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1765 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1766
1767 return cpu_to_le32(dword);
1768 }
1769
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1770 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1771 {
1772 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1773
1774 return cpu_to_le32(dword);
1775 }
1776
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1777 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1778 {
1779 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1780 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) |
1781 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) |
1782 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1783 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1784 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1785
1786 return cpu_to_le32(dword);
1787 }
1788
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1789 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1790 {
1791 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1792 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1793 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1794 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) |
1795 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL,
1796 desc_info->tx_cnt_lmt_en) |
1797 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1798
1799 return cpu_to_le32(dword);
1800 }
1801
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1802 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1803 {
1804 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1805 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1806 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1807 desc_info->data_retry_lowest_rate) |
1808 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn);
1809
1810 return cpu_to_le32(dword);
1811 }
1812
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1813 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1814 {
1815 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1816 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1817 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) |
1818 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report);
1819
1820 return cpu_to_le32(dword);
1821 }
1822
rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info * desc_info)1823 static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info)
1824 {
1825 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1826 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) |
1827 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx);
1828
1829 return cpu_to_le32(dword);
1830 }
1831
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1832 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1833 {
1834 bool rts_en = !desc_info->is_bmc;
1835 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1836 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1837
1838 return cpu_to_le32(dword);
1839 }
1840
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1841 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1842 struct rtw89_tx_desc_info *desc_info,
1843 void *txdesc)
1844 {
1845 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1846 struct rtw89_txwd_info_v2 *txwd_info;
1847
1848 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1849 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1850 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1851 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1852 if (desc_info->sec_en) {
1853 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1854 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1855 }
1856 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1857 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1858
1859 if (!desc_info->en_wd_info)
1860 return;
1861
1862 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1863 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1864 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1865 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1866 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1867 }
1868 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1869
rtw89_core_fill_txdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1870 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
1871 struct rtw89_tx_desc_info *desc_info,
1872 void *txdesc)
1873 {
1874 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1875 struct rtw89_txwd_info_v2 *txwd_info;
1876
1877 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1878 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1879 txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info);
1880 txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info);
1881 if (desc_info->sec_en) {
1882 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1883 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1884 }
1885 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1886 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1887
1888 if (!desc_info->en_wd_info)
1889 return;
1890
1891 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1892 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1893 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1894 txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info);
1895 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1896 }
1897 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3);
1898
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1899 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1900 {
1901 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1902 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1903 RTW89_CORE_RX_TYPE_FWDL :
1904 RTW89_CORE_RX_TYPE_H2C);
1905
1906 return cpu_to_le32(dword);
1907 }
1908
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1909 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1910 struct rtw89_tx_desc_info *desc_info,
1911 void *txdesc)
1912 {
1913 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1914
1915 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1916 }
1917 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1918
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1919 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1920 {
1921 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1922 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1923 RTW89_CORE_RX_TYPE_FWDL :
1924 RTW89_CORE_RX_TYPE_H2C);
1925
1926 return cpu_to_le32(dword);
1927 }
1928
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1929 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1930 struct rtw89_tx_desc_info *desc_info,
1931 void *txdesc)
1932 {
1933 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1934
1935 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1936 }
1937 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1938
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1939 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1940 struct sk_buff *skb,
1941 struct rtw89_rx_phy_ppdu *phy_ppdu)
1942 {
1943 const struct rtw89_chip_info *chip = rtwdev->chip;
1944 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1945 const struct rtw89_rxinfo_user *user;
1946 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1947 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1948 bool rx_cnt_valid = false;
1949 bool invalid = false;
1950 u8 plcp_size = 0;
1951 u8 *phy_sts;
1952 u8 usr_num;
1953 int i;
1954
1955 if (chip_gen == RTW89_CHIP_BE) {
1956 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1957 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1958 }
1959
1960 if (invalid)
1961 return -EINVAL;
1962
1963 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1964 if (chip_gen == RTW89_CHIP_BE) {
1965 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1966 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1967 } else {
1968 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1969 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1970 }
1971 if (usr_num > chip->ppdu_max_usr) {
1972 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1973 usr_num);
1974 return -EINVAL;
1975 }
1976
1977 for (i = 0; i < usr_num; i++) {
1978 user = &rxinfo->user[i];
1979 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1980 continue;
1981 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1982 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1983 */
1984 if (chip->chip_id == RTL8922A)
1985 phy_ppdu->mac_id =
1986 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1987 else if (chip->chip_id == RTL8922D)
1988 phy_ppdu->mac_id =
1989 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1);
1990
1991 phy_ppdu->has_data =
1992 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1993 phy_ppdu->has_bcn =
1994 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1995 break;
1996 }
1997
1998 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1999 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
2000 /* 8-byte alignment */
2001 if (usr_num & BIT(0))
2002 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
2003 if (rx_cnt_valid)
2004 phy_sts += rx_cnt_size;
2005 phy_sts += plcp_size;
2006
2007 if (phy_sts > skb->data + skb->len)
2008 return -EINVAL;
2009
2010 phy_ppdu->buf = phy_sts;
2011 phy_ppdu->len = skb->data + skb->len - phy_sts;
2012
2013 return 0;
2014 }
2015
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)2016 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
2017 {
2018 u8 data_rate_mode;
2019
2020 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2021 switch (data_rate_mode) {
2022 case DATA_RATE_MODE_NON_HT:
2023 return 1;
2024 case DATA_RATE_MODE_HT:
2025 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
2026 case DATA_RATE_MODE_VHT:
2027 case DATA_RATE_MODE_HE:
2028 case DATA_RATE_MODE_EHT:
2029 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
2030 default:
2031 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2032 return 0;
2033 }
2034 }
2035
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)2036 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
2037 struct ieee80211_sta *sta)
2038 {
2039 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
2040 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2041 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
2042 struct rtw89_hal *hal = &rtwdev->hal;
2043 struct rtw89_sta_link *rtwsta_link;
2044 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
2045 u8 ant_pos = U8_MAX;
2046 u8 evm_pos = 0;
2047 int i;
2048
2049 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx);
2050 if (unlikely(!rtwsta_link))
2051 return;
2052
2053 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
2054 return;
2055
2056 if (hal->ant_diversity && hal->antenna_rx) {
2057 ant_pos = __ffs(hal->antenna_rx);
2058 evm_pos = ant_pos;
2059 }
2060
2061 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
2062
2063 if (ant_pos < ant_num) {
2064 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
2065 } else {
2066 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2067 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
2068 }
2069
2070 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
2071 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
2072 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
2073 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
2074 } else {
2075 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
2076 phy_ppdu->ofdm.evm_min);
2077 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
2078 phy_ppdu->ofdm.evm_max);
2079 }
2080 }
2081 }
2082
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)2083 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
2084 const struct rtw89_phy_sts_iehdr *iehdr)
2085 {
2086 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
2087 const u8 *physts_ie_len_tab = phy->physt_ie_len;
2088 u16 ie_len;
2089 u8 ie;
2090
2091 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2092 if (physts_ie_len_tab[ie] != VAR_LEN)
2093 ie_len = physts_ie_len_tab[ie];
2094 else
2095 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
2096
2097 return ie_len;
2098 }
2099
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2100 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
2101 const struct rtw89_phy_sts_iehdr *iehdr,
2102 struct rtw89_rx_phy_ppdu *phy_ppdu)
2103 {
2104 const struct rtw89_phy_sts_ie01_v2 *ie;
2105 u8 *rpl_fd = phy_ppdu->rpl_fd;
2106
2107 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
2108 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
2109 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
2110 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
2111 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
2112
2113 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
2114 }
2115
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2116 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
2117 const struct rtw89_phy_sts_iehdr *iehdr,
2118 struct rtw89_rx_phy_ppdu *phy_ppdu)
2119 {
2120 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
2121 s16 cfo;
2122 u32 t;
2123
2124 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
2125 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
2126 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
2127 phy_ppdu->bf = le32_get_bits(ie->w3, RTW89_PHY_STS_IE01_W3_BF);
2128
2129 if (!phy_ppdu->hdr_2_en)
2130 phy_ppdu->rx_path_en =
2131 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
2132
2133 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
2134 return;
2135
2136 if (!phy_ppdu->to_self)
2137 return;
2138
2139 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
2140 phy_ppdu->su = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_SU);
2141 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
2142 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
2143 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
2144 phy_ppdu->ofdm.has = true;
2145
2146 /* sign conversion for S(12,2) */
2147 if (rtwdev->chip->cfo_src_fd) {
2148 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
2149 cfo = sign_extend32(t, 11);
2150 } else {
2151 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
2152 cfo = sign_extend32(t, 11);
2153 }
2154
2155 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
2156
2157 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2158 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
2159 }
2160
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2161 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
2162 const struct rtw89_phy_sts_iehdr *iehdr,
2163 struct rtw89_rx_phy_ppdu *phy_ppdu)
2164 {
2165 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
2166 u16 tmp_rpl;
2167
2168 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
2169 phy_ppdu->rpl_avg = tmp_rpl >> 1;
2170
2171 if (!phy_ppdu->hdr_2_en)
2172 phy_ppdu->rx_path_en =
2173 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN);
2174 }
2175
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2176 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
2177 const struct rtw89_phy_sts_iehdr *iehdr,
2178 struct rtw89_rx_phy_ppdu *phy_ppdu)
2179 {
2180 const struct rtw89_phy_sts_ie00_v2 *ie;
2181 u8 *rpl_path = phy_ppdu->rpl_path;
2182 u16 tmp_rpl[RF_PATH_MAX];
2183 u8 i;
2184
2185 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
2186 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
2187 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
2188 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
2189 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
2190
2191 for (i = 0; i < RF_PATH_MAX; i++)
2192 rpl_path[i] = tmp_rpl[i] >> 1;
2193 }
2194
rtw89_core_parse_phy_status_ie09(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2195 static void rtw89_core_parse_phy_status_ie09(struct rtw89_dev *rtwdev,
2196 const struct rtw89_phy_sts_iehdr *iehdr,
2197 struct rtw89_rx_phy_ppdu *phy_ppdu)
2198 {
2199 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
2200 const union rtw89_phy_sts_ie09 *ie09;
2201 u16 ie_len;
2202
2203 ie09 = (const void *)iehdr;
2204
2205 if (phy->physt_gen >= 2) {
2206 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, (const void *)iehdr);
2207 if (ie_len < sizeof(ie09->gen2))
2208 return;
2209 }
2210
2211 phy_ppdu->ie09 = ie09;
2212 }
2213
rtw89_core_parse_phy_status_ie10(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2214 static void rtw89_core_parse_phy_status_ie10(struct rtw89_dev *rtwdev,
2215 const struct rtw89_phy_sts_iehdr *iehdr,
2216 struct rtw89_rx_phy_ppdu *phy_ppdu)
2217 {
2218 phy_ppdu->ie10 = (const void *)iehdr;
2219 }
2220
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2221 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
2222 const struct rtw89_phy_sts_iehdr *iehdr,
2223 struct rtw89_rx_phy_ppdu *phy_ppdu)
2224 {
2225 bool accept;
2226 u8 ie;
2227
2228 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2229
2230 /*
2231 * For normal mode, only parse ppdu_sts that are A1-matched, except for
2232 * scanning that needs to get chan_idx in IE01.
2233 */
2234 accept = phy_ppdu->to_self || ie == RTW89_PHYSTS_IE01_CMN_OFDM ||
2235 rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR;
2236 if (!accept)
2237 return 0;
2238
2239 switch (ie) {
2240 case RTW89_PHYSTS_IE00_CMN_CCK:
2241 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
2242 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2243 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
2244 break;
2245 case RTW89_PHYSTS_IE01_CMN_OFDM:
2246 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
2247 break;
2248 case RTW89_PHYSTS_IE09_FTR_0:
2249 rtw89_core_parse_phy_status_ie09(rtwdev, iehdr, phy_ppdu);
2250 break;
2251 case RTW89_PHYSTS_IE10_FTR_PLCP_EXT:
2252 rtw89_core_parse_phy_status_ie10(rtwdev, iehdr, phy_ppdu);
2253 break;
2254 default:
2255 break;
2256 }
2257
2258 return 0;
2259 }
2260
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)2261 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
2262 {
2263 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
2264
2265 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
2266 }
2267
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)2268 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
2269 {
2270 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2271 u8 *rssi = phy_ppdu->rssi;
2272
2273 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
2274 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
2275 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
2276 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
2277 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
2278 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
2279
2280 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
2281 if (phy_ppdu->hdr_2_en)
2282 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
2283 }
2284
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2285 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
2286 struct rtw89_rx_phy_ppdu *phy_ppdu)
2287 {
2288 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2289 u32 len_from_header;
2290 bool physts_valid;
2291
2292 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
2293 if (!physts_valid)
2294 return -EINVAL;
2295
2296 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
2297
2298 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2299 len_from_header += PHY_STS_HDR_LEN;
2300
2301 if (len_from_header != phy_ppdu->len) {
2302 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
2303 return -EINVAL;
2304 }
2305 rtw89_core_update_phy_ppdu(phy_ppdu);
2306
2307 return 0;
2308 }
2309
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2310 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
2311 struct rtw89_rx_phy_ppdu *phy_ppdu)
2312 {
2313 void *pos, *end;
2314 bool accept;
2315 u16 ie_len;
2316
2317 /* for normal mode, mark invalid reports and bypass them */
2318 accept = phy_ppdu->ie >= RTW89_CCK_PKT ||
2319 rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR;
2320 if (!accept)
2321 return -EINVAL;
2322
2323 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
2324 if (phy_ppdu->hdr_2_en)
2325 pos += PHY_STS_HDR_LEN;
2326 end = phy_ppdu->buf + phy_ppdu->len;
2327 while (pos < end) {
2328 const struct rtw89_phy_sts_iehdr *iehdr = pos;
2329
2330 /*
2331 * RTL8922D might reports 8 bytes zeros at end if IE09 presents.
2332 * Check and ignore the zeros.
2333 */
2334 if (unlikely(phy_ppdu->ie09 && end - pos == 8 && iehdr->w0 == 0))
2335 break;
2336
2337 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
2338 pos += ie_len;
2339 if (pos > end || ie_len == 0) {
2340 /* clear pointers to prevent accessing out of IE */
2341 phy_ppdu->ie09 = NULL;
2342 phy_ppdu->ie10 = NULL;
2343
2344 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2345 "phy status parse failed\n");
2346
2347 return -EINVAL;
2348 }
2349
2350 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
2351 }
2352
2353 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
2354 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
2355
2356 return 0;
2357 }
2358
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2359 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
2360 struct rtw89_rx_phy_ppdu *phy_ppdu)
2361 {
2362 int ret;
2363
2364 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
2365 if (ret)
2366 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
2367 else
2368 phy_ppdu->valid = true;
2369
2370 ieee80211_iterate_stations_atomic(rtwdev->hw,
2371 rtw89_core_rx_process_phy_ppdu_iter,
2372 phy_ppdu);
2373 }
2374
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2375 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
2376 u8 desc_info_gi,
2377 bool rx_status)
2378 {
2379 switch (desc_info_gi) {
2380 case RTW89_GILTF_SGI_4XHE08:
2381 case RTW89_GILTF_2XHE08:
2382 case RTW89_GILTF_1XHE08:
2383 return NL80211_RATE_INFO_HE_GI_0_8;
2384 case RTW89_GILTF_2XHE16:
2385 case RTW89_GILTF_1XHE16:
2386 return NL80211_RATE_INFO_HE_GI_1_6;
2387 case RTW89_GILTF_LGI_4XHE32:
2388 return NL80211_RATE_INFO_HE_GI_3_2;
2389 default:
2390 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2391 if (rx_status)
2392 return NL80211_RATE_INFO_HE_GI_3_2;
2393 return U8_MAX;
2394 }
2395 }
2396
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2397 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
2398 u8 desc_info_gi,
2399 bool rx_status)
2400 {
2401 switch (desc_info_gi) {
2402 case RTW89_GILTF_SGI_4XHE08:
2403 case RTW89_GILTF_2XHE08:
2404 case RTW89_GILTF_1XHE08:
2405 return NL80211_RATE_INFO_EHT_GI_0_8;
2406 case RTW89_GILTF_2XHE16:
2407 case RTW89_GILTF_1XHE16:
2408 return NL80211_RATE_INFO_EHT_GI_1_6;
2409 case RTW89_GILTF_LGI_4XHE32:
2410 return NL80211_RATE_INFO_EHT_GI_3_2;
2411 default:
2412 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2413 if (rx_status)
2414 return NL80211_RATE_INFO_EHT_GI_3_2;
2415 return U8_MAX;
2416 }
2417 }
2418
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)2419 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
2420 u8 desc_info_gi,
2421 bool rx_status, bool eht)
2422 {
2423 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
2424 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
2425 }
2426
2427 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)2428 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
2429 bool eht)
2430 {
2431 if (eht)
2432 return status->eht.gi == gi_ltf;
2433
2434 return status->he_gi == gi_ltf;
2435 }
2436
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)2437 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
2438 struct rtw89_rx_desc_info *desc_info,
2439 struct ieee80211_rx_status *status)
2440 {
2441 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2442 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
2443 bool eht = false;
2444 u16 data_rate;
2445 bool ret;
2446
2447 data_rate = desc_info->data_rate;
2448 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2449 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2450 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2451 /* rate_idx is still hardware value here */
2452 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2453 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2454 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
2455 data_rate_mode == DATA_RATE_MODE_HE ||
2456 data_rate_mode == DATA_RATE_MODE_EHT) {
2457 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2458 } else {
2459 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2460 }
2461
2462 eht = data_rate_mode == DATA_RATE_MODE_EHT;
2463 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2464 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
2465 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
2466 status->rate_idx == rate_idx &&
2467 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
2468 status->bw == bw;
2469
2470 return ret;
2471 }
2472
2473 struct rtw89_vif_rx_stats_iter_data {
2474 struct rtw89_dev *rtwdev;
2475 struct rtw89_rx_phy_ppdu *phy_ppdu;
2476 struct rtw89_rx_desc_info *desc_info;
2477 struct sk_buff *skb;
2478 const u8 *bssid;
2479 };
2480
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)2481 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
2482 struct rtw89_vif_link *rtwvif_link,
2483 struct ieee80211_bss_conf *bss_conf,
2484 struct sk_buff *skb)
2485 {
2486 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
2487 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
2488 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2489 u8 *pos, *end, type, tf_bw;
2490 u16 aid, tf_rua;
2491
2492 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
2493 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
2494 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
2495 return;
2496
2497 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
2498 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
2499 return;
2500
2501 end = (u8 *)tf + skb->len;
2502 pos = tf->variable;
2503
2504 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
2505 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
2506 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
2507 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
2508 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2509 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2510 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
2511 tf_rua, tf_bw);
2512
2513 if (aid == RTW89_TF_PAD)
2514 break;
2515
2516 if (aid == vif->cfg.aid) {
2517 enum nl80211_he_ru_alloc rua;
2518
2519 rtwvif->stats.rx_tf_acc++;
2520 rtwdev->stats.rx_tf_acc++;
2521
2522 /* The following only required for HE trigger frame, but we
2523 * cannot use UL HE-SIG-A2 reserved subfield to identify it
2524 * since some 11ax APs will fill it with all 0s, which will
2525 * be misunderstood as EHT trigger frame.
2526 */
2527 if (bss_conf->eht_support)
2528 break;
2529
2530 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2531
2532 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2533 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2534 rtwvif_link->pwr_diff_en = true;
2535 break;
2536 }
2537
2538 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2539 }
2540 }
2541
rtw89_cancel_6ghz_probe_work(struct wiphy * wiphy,struct wiphy_work * work)2542 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work)
2543 {
2544 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2545 cancel_6ghz_probe_work);
2546 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2547 struct rtw89_pktofld_info *info;
2548
2549 lockdep_assert_wiphy(wiphy);
2550
2551 if (!rtwdev->scanning)
2552 return;
2553
2554 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2555 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2556 continue;
2557
2558 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2559
2560 /* Don't delete/free info from pkt_list at this moment. Let it
2561 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2562 * since if during scanning, pkt_list is accessed in bottom half.
2563 */
2564 }
2565 }
2566
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2567 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2568 struct sk_buff *skb)
2569 {
2570 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2571 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2572 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2573 struct rtw89_pktofld_info *info;
2574 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2575 bool queue_work = false;
2576
2577 if (rx_status->band != NL80211_BAND_6GHZ)
2578 return;
2579
2580 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) {
2581 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n");
2582 return;
2583 }
2584
2585 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2586
2587 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2588 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2589 info->cancel = true;
2590 queue_work = true;
2591 continue;
2592 }
2593
2594 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2595 continue;
2596
2597 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2598 info->cancel = true;
2599 queue_work = true;
2600 }
2601 }
2602
2603 if (queue_work)
2604 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work);
2605 }
2606
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2607 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2608 struct ieee80211_hdr *hdr, size_t len)
2609 {
2610 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2611
2612 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2613 return;
2614
2615 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2616 }
2617
rtw89_bcn_calc_min_tbtt(struct rtw89_dev * rtwdev,u32 tbtt1,u32 tbtt2)2618 static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2)
2619 {
2620 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2621 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th;
2622 u32 tbtt_diff_th = bcn_track->tbtt_diff_th;
2623
2624 if (tbtt2 > tbtt1)
2625 swap(tbtt1, tbtt2);
2626
2627 if (tbtt1 - tbtt2 > tbtt_diff_th)
2628 return tbtt1;
2629 else if (tbtt2 > close_bcn_intvl_th)
2630 return tbtt2;
2631 else if (tbtt1 > close_bcn_intvl_th)
2632 return tbtt1;
2633 else
2634 return tbtt2;
2635 }
2636
rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2637 static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev,
2638 struct rtw89_vif_link *rtwvif_link)
2639 {
2640 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2641 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2642 u32 offset = bcn_track->tbtt_offset;
2643
2644 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2645 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2646 const struct rtw89_port_reg *p = mac->port_base;
2647 u32 bcnspc, val;
2648
2649 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link,
2650 p->bcn_space, B_AX_BCN_SPACE_MASK);
2651 val = bcnspc - (offset / 1024);
2652 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) |
2653 B_AX_TBTT_SHIFT_OFST_SIGN;
2654
2655 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift,
2656 B_AX_TBTT_SHIFT_OFST_MASK, val);
2657
2658 return;
2659 }
2660
2661 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset);
2662 }
2663
rtw89_bcn_update_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2664 static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev,
2665 struct rtw89_vif_link *rtwvif_link)
2666 {
2667 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2668 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2669 u32 *tbtt_us = bcn_stat->tbtt_us;
2670 u32 offset = tbtt_us[0];
2671 u8 i;
2672
2673 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++)
2674 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset);
2675
2676 if (bcn_track->tbtt_offset == offset)
2677 return;
2678
2679 bcn_track->tbtt_offset = offset;
2680 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link);
2681 }
2682
cmp_u16(const void * a,const void * b)2683 static int cmp_u16(const void *a, const void *b)
2684 {
2685 return *(const u16 *)a - *(const u16 *)b;
2686 }
2687
_rtw89_bcn_calc_drift(u16 tbtt,u16 offset,u16 beacon_int)2688 static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int)
2689 {
2690 if (tbtt < offset)
2691 return beacon_int - offset + tbtt;
2692
2693 return tbtt - offset;
2694 }
2695
rtw89_bcn_calc_drift(struct rtw89_dev * rtwdev)2696 static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev)
2697 {
2698 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2699 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2700 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2701 u16 *tbtt_tu = bcn_stat->tbtt_tu;
2702 u16 *drift = bcn_stat->drift;
2703 u8 i;
2704
2705 bcn_stat->tbtt_tu_min = U16_MAX;
2706 bcn_stat->tbtt_tu_max = 0;
2707 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2708 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu,
2709 bcn_track->beacon_int);
2710
2711 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]);
2712 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]);
2713 }
2714
2715 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL);
2716 }
2717
rtw89_bcn_calc_distribution(struct rtw89_dev * rtwdev)2718 static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev)
2719 {
2720 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2721 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2722 u16 lower_bound, upper_bound, outlier_count = 0;
2723 u16 *drift = bcn_stat->drift;
2724 u16 *bins = bcn_dist->bins;
2725 u16 q1, q3, iqr, tmp;
2726 u8 i;
2727
2728 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0);
2729
2730 memset(bcn_dist, 0, sizeof(*bcn_dist));
2731
2732 bcn_dist->min = drift[0];
2733 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1];
2734
2735 tmp = RTW89_BCN_TRACK_STAT_NR / 4;
2736 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2737
2738 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4;
2739 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2740
2741 iqr = q3 - q1;
2742 tmp = (3 * iqr) / 2;
2743
2744 if (bcn_dist->min <= 5)
2745 lower_bound = bcn_dist->min;
2746 else if (q1 > tmp)
2747 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2748 else
2749 lower_bound = 0;
2750
2751 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2752
2753 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2754 u16 tbtt = bcn_stat->tbtt_tu[i];
2755 u16 min = bcn_stat->tbtt_tu_min;
2756 u8 bin_idx;
2757
2758 /* histogram */
2759 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH,
2760 RTW89_BCN_TRACK_MAX_BIN_NUM - 1);
2761 bins[bin_idx]++;
2762
2763 /* boxplot outlier */
2764 if (drift[i] < lower_bound || drift[i] > upper_bound)
2765 outlier_count++;
2766 }
2767
2768 bcn_dist->outlier_count = outlier_count;
2769 bcn_dist->lower_bound = lower_bound;
2770 bcn_dist->upper_bound = upper_bound;
2771 }
2772
rtw89_bcn_get_coverage(struct rtw89_dev * rtwdev,u16 threshold)2773 static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold)
2774 {
2775 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2776 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m;
2777 u16 *drift = bcn_stat->drift;
2778 int index = -1;
2779 u8 count = 0;
2780
2781 while (l <= r) {
2782 m = l + (r - l) / 2;
2783
2784 if (drift[m] <= threshold) {
2785 index = m;
2786 l = m + 1;
2787 } else {
2788 r = m - 1;
2789 }
2790 }
2791
2792 count = (index == -1) ? 0 : (index + 1);
2793
2794 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR;
2795 }
2796
rtw89_bcn_get_histogram_bound(struct rtw89_dev * rtwdev,u8 target)2797 static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target)
2798 {
2799 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2800 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2801 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max;
2802 u16 upper, lower = bcn_stat->tbtt_tu_min;
2803 u8 i, count = 0;
2804
2805 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) {
2806 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1;
2807 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1)
2808 upper = max(upper, tbtt_tu_max);
2809
2810 count += bcn_dist->bins[i];
2811 if (count > target)
2812 break;
2813
2814 lower = upper + 1;
2815 }
2816
2817 return upper;
2818 }
2819
rtw89_bcn_get_rx_time(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2820 static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev,
2821 struct rtw89_vif_link *rtwvif_link)
2822 {
2823 #define RTW89_SYMBOL_TIME_2GHZ 192
2824 #define RTW89_SYMBOL_TIME_5GHZ 20
2825 #define RTW89_SYMBOL_TIME_6GHZ 20
2826 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
2827 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
2828 struct rtw89_pkt_stat *pkt_stat = &bb->cur_pkt_stat;
2829 u16 bitrate, val;
2830
2831 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate))
2832 return 0;
2833
2834 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate;
2835
2836 switch (chan->band_type) {
2837 default:
2838 case RTW89_BAND_2G:
2839 val += RTW89_SYMBOL_TIME_2GHZ;
2840 break;
2841 case RTW89_BAND_5G:
2842 val += RTW89_SYMBOL_TIME_5GHZ;
2843 break;
2844 case RTW89_BAND_6G:
2845 val += RTW89_SYMBOL_TIME_6GHZ;
2846 break;
2847 }
2848
2849 /* convert to millisecond */
2850 return DIV_ROUND_UP(val, 1000);
2851 }
2852
rtw89_bcn_calc_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2853 static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev,
2854 struct rtw89_vif_link *rtwvif_link)
2855 {
2856 #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5
2857 #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */
2858 #define RTW89_BCN_TRACK_STRONG_RSSI 80
2859 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
2860 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2861 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2862 struct rtw89_pkt_stat *pkt_stat = &bb->cur_pkt_stat;
2863 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2864 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th;
2865 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th;
2866 u16 target_bcn_th = bcn_track->target_bcn_th;
2867 u8 rssi = ewma_rssi_read(&bb->bcn_rssi);
2868 u16 low_bcn_th = bcn_track->low_bcn_th;
2869 u16 med_bcn_th = bcn_track->med_bcn_th;
2870 u16 beacon_int = bcn_track->beacon_int;
2871 u16 bcn_timeout;
2872
2873 if (pkt_stat->beacon_nr < low_bcn_th) {
2874 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT;
2875 goto out;
2876 }
2877
2878 if (bcn_dist->outlier_count >= outlier_high_bcn_th) {
2879 bcn_timeout = bcn_dist->max;
2880 goto out;
2881 }
2882
2883 if (pkt_stat->beacon_nr < med_bcn_th) {
2884 if (bcn_dist->outlier_count > outlier_low_bcn_th)
2885 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2;
2886 else
2887 bcn_timeout = bcn_dist->upper_bound +
2888 RTW89_BCN_TRACK_EXTEND_TIMEOUT;
2889
2890 goto out;
2891 }
2892
2893 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) {
2894 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) {
2895 /* ideal case */
2896 bcn_timeout = 0;
2897 } else {
2898 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2899 u16 upper_bound;
2900
2901 upper_bound =
2902 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th);
2903 bcn_timeout =
2904 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int);
2905 }
2906
2907 goto out;
2908 }
2909
2910 bcn_timeout = bcn_stat->drift[target_bcn_th];
2911
2912 out:
2913 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, rtwvif_link);
2914 }
2915
rtw89_bcn_update_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2916 static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev,
2917 struct rtw89_vif_link *rtwvif_link)
2918 {
2919 rtw89_bcn_calc_drift(rtwdev);
2920 rtw89_bcn_calc_distribution(rtwdev);
2921 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link);
2922 }
2923
rtw89_core_bcn_track(struct rtw89_dev * rtwdev)2924 static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev)
2925 {
2926 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2927 struct rtw89_vif_link *rtwvif_link;
2928 struct rtw89_vif *rtwvif;
2929 unsigned int link_id;
2930
2931 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2932 return;
2933
2934 if (!rtwdev->lps_enabled)
2935 return;
2936
2937 if (!bcn_track->is_data_ready)
2938 return;
2939
2940 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
2941 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) {
2942 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION ||
2943 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT))
2944 continue;
2945
2946 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link);
2947 rtw89_bcn_update_timeout(rtwdev, rtwvif_link);
2948 }
2949 }
2950 }
2951
rtw89_core_bcn_track_can_lps(struct rtw89_dev * rtwdev)2952 static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev)
2953 {
2954 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2955
2956 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2957 return true;
2958
2959 return bcn_track->is_data_ready;
2960 }
2961
rtw89_core_bcn_track_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2962 static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev,
2963 struct rtw89_vif_link *rtwvif_link)
2964 {
2965 #define RTW89_BCN_TRACK_MED_BCN 70
2966 #define RTW89_BCN_TRACK_LOW_BCN 30
2967 #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30
2968 #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20
2969 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2970 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD);
2971 struct ieee80211_bss_conf *bss_conf;
2972 u32 beacons_in_period;
2973 u32 bcn_intvl_us;
2974 u16 beacon_int;
2975 u8 dtim;
2976
2977 rcu_read_lock();
2978 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
2979 beacon_int = bss_conf->beacon_int ?: 100;
2980 dtim = bss_conf->dtim_period;
2981 rcu_read_unlock();
2982
2983 beacons_in_period = period / beacon_int / dtim;
2984 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int);
2985
2986 bcn_track->low_bcn_th =
2987 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT;
2988 bcn_track->med_bcn_th =
2989 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT;
2990 bcn_track->outlier_low_bcn_th =
2991 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT;
2992 bcn_track->outlier_high_bcn_th =
2993 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT;
2994 bcn_track->target_bcn_th =
2995 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT;
2996
2997 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3);
2998 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT;
2999 bcn_track->beacon_int = beacon_int;
3000 bcn_track->dtim = dtim;
3001 }
3002
rtw89_core_bcn_track_reset(struct rtw89_dev * rtwdev)3003 static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev)
3004 {
3005 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat));
3006 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track));
3007 }
3008
rtw89_core_proto_stats_can_lps(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,enum rtw89_tfc_interval interval)3009 static bool rtw89_core_proto_stats_can_lps(struct rtw89_dev *rtwdev,
3010 struct rtw89_vif *rtwvif,
3011 enum rtw89_tfc_interval interval)
3012 {
3013 if (rtwdev->chip->chip_id != RTL8852A)
3014 return true;
3015
3016 if (rtwvif->burst_active)
3017 return false;
3018
3019 if (interval == RTW89_TFC_INTERVAL_100MS &&
3020 hweight8(rtwvif->stats_ps.active_histogram) < 3)
3021 return false;
3022
3023 return true;
3024 }
3025
rtw89_vif_rx_bcn_stat(struct rtw89_dev * rtwdev,struct sk_buff * skb)3026 static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb)
3027 {
3028 #define RTW89_APPEND_TSF_2GHZ 384
3029 #define RTW89_APPEND_TSF_5GHZ 52
3030 #define RTW89_APPEND_TSF_6GHZ 52
3031 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
3032 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
3033 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
3034 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
3035 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int);
3036 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp);
3037 u8 wp, num = bcn_stat->num;
3038 u16 append;
3039
3040 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
3041 return;
3042
3043 /* Skip if not yet associated */
3044 if (!bcn_intvl_us)
3045 return;
3046
3047 switch (rx_status->band) {
3048 default:
3049 case NL80211_BAND_2GHZ:
3050 append = RTW89_APPEND_TSF_2GHZ;
3051 break;
3052 case NL80211_BAND_5GHZ:
3053 append = RTW89_APPEND_TSF_5GHZ;
3054 break;
3055 case NL80211_BAND_6GHZ:
3056 append = RTW89_APPEND_TSF_6GHZ;
3057 break;
3058 }
3059
3060 wp = bcn_stat->wp;
3061 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]);
3062 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024;
3063 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR;
3064 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR);
3065 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR;
3066 }
3067
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)3068 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
3069 struct ieee80211_vif *vif)
3070 {
3071 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
3072 struct rtw89_dev *rtwdev = iter_data->rtwdev;
3073 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
3074 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
3075 struct sk_buff *skb = iter_data->skb;
3076 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
3077 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3078 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
3079 bool is_mld = ieee80211_vif_is_mld(vif);
3080 struct ieee80211_bss_conf *bss_conf;
3081 struct rtw89_vif_link *rtwvif_link;
3082 const u8 *bssid = iter_data->bssid;
3083 struct rtw89_pkt_stat *pkt_stat;
3084 struct rtw89_bb_ctx *bb;
3085 const u8 *target_bssid;
3086
3087 if (rtwdev->scanning &&
3088 (ieee80211_is_beacon(hdr->frame_control) ||
3089 ieee80211_is_probe_resp(hdr->frame_control)))
3090 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
3091
3092 rcu_read_lock();
3093
3094 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel);
3095 if (unlikely(!rtwvif_link))
3096 goto out;
3097
3098 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3099 if (!bss_conf->bssid)
3100 goto out;
3101
3102 if (ieee80211_is_trigger(hdr->frame_control)) {
3103 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
3104 goto out;
3105 }
3106
3107 target_bssid = ieee80211_is_beacon(hdr->frame_control) &&
3108 bss_conf->nontransmitted ?
3109 bss_conf->transmitter_bssid : bss_conf->bssid;
3110 if (!ether_addr_equal(target_bssid, bssid))
3111 goto out;
3112
3113 if (is_mld) {
3114 rx_status->link_valid = true;
3115 rx_status->link_id = rtwvif_link->link_id;
3116 }
3117
3118 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
3119 pkt_stat = &bb->cur_pkt_stat;
3120
3121 if (ieee80211_is_beacon(hdr->frame_control)) {
3122 if (vif->type == NL80211_IFTYPE_STATION &&
3123 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
3124 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
3125 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
3126 }
3127
3128 if (phy_ppdu) {
3129 ewma_rssi_add(&bb->bcn_rssi, phy_ppdu->rssi_avg);
3130 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
3131 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx;
3132 }
3133
3134 pkt_stat->beacon_nr++;
3135 pkt_stat->beacon_rate = desc_info->data_rate;
3136 pkt_stat->beacon_len = skb->len;
3137
3138 rtw89_vif_rx_bcn_stat(rtwdev, skb);
3139 }
3140
3141 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
3142 goto out;
3143
3144 if (desc_info->data_rate < RTW89_HW_RATE_NR)
3145 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
3146
3147 if (phy_ppdu && phy_ppdu->ofdm.has) {
3148 if (phy_ppdu->ldpc)
3149 pkt_stat->rx.ldpc++;
3150 else
3151 pkt_stat->rx.bcc++;
3152
3153 if (phy_ppdu->stbc)
3154 pkt_stat->rx.stbc++;
3155
3156 if (!phy_ppdu->su)
3157 pkt_stat->rx.mu++;
3158 else if (phy_ppdu->bf)
3159 pkt_stat->rx.su_bf++;
3160 else
3161 pkt_stat->rx.su_non_bf++;
3162 }
3163
3164 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false);
3165
3166 out:
3167 rcu_read_unlock();
3168 }
3169
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3170 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
3171 struct rtw89_rx_phy_ppdu *phy_ppdu,
3172 struct rtw89_rx_desc_info *desc_info,
3173 struct sk_buff *skb)
3174 {
3175 struct rtw89_vif_rx_stats_iter_data iter_data;
3176
3177 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false);
3178
3179 iter_data.rtwdev = rtwdev;
3180 iter_data.phy_ppdu = phy_ppdu;
3181 iter_data.desc_info = desc_info;
3182 iter_data.skb = skb;
3183 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
3184 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
3185 }
3186
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)3187 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
3188 struct ieee80211_rx_status *status)
3189 {
3190 const struct rtw89_chan_rcd *rcd =
3191 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
3192 u16 chan = rcd->prev_primary_channel;
3193 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
3194
3195 if (status->band != NL80211_BAND_2GHZ &&
3196 status->encoding == RX_ENC_LEGACY &&
3197 status->rate_idx < RTW89_HW_RATE_OFDM6) {
3198 status->freq = ieee80211_channel_to_frequency(chan, band);
3199 status->band = band;
3200 }
3201 }
3202
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)3203 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
3204 {
3205 if (rx_status->band == NL80211_BAND_2GHZ ||
3206 rx_status->encoding != RX_ENC_LEGACY)
3207 return;
3208
3209 /* Some control frames' freq(ACKs in this case) are reported wrong due
3210 * to FW notify timing, set to lowest rate to prevent overflow.
3211 */
3212 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
3213 rx_status->rate_idx = 0;
3214 return;
3215 }
3216
3217 /* No 4 CCK rates for non-2G */
3218 rx_status->rate_idx -= 4;
3219 }
3220
3221 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3222 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
3223 struct ieee80211_rx_status *rx_status,
3224 struct rtw89_rx_phy_ppdu *phy_ppdu)
3225 {
3226 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3227 return;
3228
3229 if (!phy_ppdu)
3230 return;
3231
3232 if (phy_ppdu->bf)
3233 rx_status->enc_flags |= RX_ENC_FLAG_BF;
3234 if (phy_ppdu->ldpc)
3235 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
3236 if (phy_ppdu->stbc)
3237 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
3238 }
3239
rtw89_core_update_radiotap_vht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3240 static void rtw89_core_update_radiotap_vht(struct rtw89_dev *rtwdev,
3241 struct sk_buff *skb,
3242 struct ieee80211_rx_status *rx_status,
3243 struct rtw89_rx_phy_ppdu *phy_ppdu)
3244 {
3245 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3246 const union rtw89_phy_sts_ie09 *ie09;
3247 struct ieee80211_radiotap_vht *vht;
3248 u8 group_id;
3249 u32 sig_a1;
3250 u16 paid;
3251 u8 nss;
3252
3253 if (!phy_ppdu)
3254 return;
3255
3256 ie09 = phy_ppdu->ie09;
3257 if (!ie09)
3258 return;
3259
3260 vht = skb_push(skb, sizeof(*vht));
3261 memset(vht, 0, sizeof(*vht));
3262 rx_status->flag |= RX_FLAG_RADIOTAP_VHT;
3263
3264 if (phy->physt_gen >= 2)
3265 sig_a1 = le64_get_bits(ie09->gen2.qw0, RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK_GEN2);
3266 else
3267 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK);
3268
3269 group_id = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_GRP_ID);
3270 vht->group_id = group_id;
3271
3272 if (group_id == 0 || group_id == 63) {
3273 paid = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_SU_PAID);
3274 vht->partial_aid = cpu_to_le16(paid);
3275 } else {
3276 /* let mac80211 fill vht->mcs_nss[0] */
3277 #define WITH_MCS_IS_NOT_KNOWN(nss) ((nss) ? (15 << 4) | (nss) : 0)
3278 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS1);
3279 vht->mcs_nss[1] = WITH_MCS_IS_NOT_KNOWN(nss);
3280 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS2);
3281 vht->mcs_nss[2] = WITH_MCS_IS_NOT_KNOWN(nss);
3282 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS3);
3283 vht->mcs_nss[3] = WITH_MCS_IS_NOT_KNOWN(nss);
3284 #undef WITH_MCS_IS_NOT_KNOWN
3285 }
3286 }
3287
rtw89_core_update_radiotap_he_su(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct ieee80211_radiotap_he * he,const union rtw89_phy_sts_ie09 * ie09)3288 static void rtw89_core_update_radiotap_he_su(struct rtw89_dev *rtwdev,
3289 struct sk_buff *skb,
3290 struct ieee80211_rx_status *rx_status,
3291 struct ieee80211_radiotap_he *he,
3292 const union rtw89_phy_sts_ie09 *ie09)
3293 {
3294 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3295 u32 sig_a1, sig_a2;
3296 u16 t;
3297
3298 if (!ie09)
3299 return;
3300
3301 if (phy->physt_gen >= 2) {
3302 sig_a1 = le64_get_bits(ie09->gen2.qw0,
3303 RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK_GEN2);
3304 sig_a2 = le64_get_bits(ie09->gen2.qw0,
3305 RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_L0);
3306 sig_a2 |= le64_get_bits(ie09->gen2.qw1,
3307 RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_H6) << 6;
3308 } else {
3309 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK);
3310 sig_a2 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK);
3311 }
3312
3313 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN |
3314 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
3315 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
3316 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN |
3317 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN |
3318 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN |
3319 0);
3320
3321 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
3322 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN |
3323 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
3324 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN |
3325 0);
3326
3327 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BEAM_CHANGE);
3328 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE);
3329
3330 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_ULDL);
3331 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_UL_DL);
3332
3333 rx_status->he_dcm = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_DCM);
3334
3335 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BSS_COLOR);
3336 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR);
3337
3338 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_SR);
3339 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE);
3340
3341 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_TXOP);
3342 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP);
3343
3344 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_LDPC_XSYMSEG);
3345 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG);
3346
3347 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_BEAMFORMED);
3348 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_TXBF);
3349
3350 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PREFEC);
3351 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD);
3352
3353 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PE);
3354 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG);
3355
3356 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_DOPPLER);
3357 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_DOPPLER);
3358 }
3359
rtw89_core_update_radiotap_he_tb(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct ieee80211_radiotap_he * he,const union rtw89_phy_sts_ie09 * sig)3360 static void rtw89_core_update_radiotap_he_tb(struct rtw89_dev *rtwdev,
3361 struct sk_buff *skb,
3362 struct ieee80211_rx_status *rx_status,
3363 struct ieee80211_radiotap_he *he,
3364 const union rtw89_phy_sts_ie09 *sig)
3365 {
3366 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3367 u32 sig_a1, sig_a2;
3368 u16 t;
3369
3370 if (!sig)
3371 return;
3372
3373 if (phy->physt_gen >= 2) {
3374 sig_a1 = le64_get_bits(sig->gen2.qw0,
3375 RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK_GEN2);
3376 sig_a2 = le64_get_bits(sig->gen2.qw0,
3377 RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_L0);
3378 sig_a2 |= le64_get_bits(sig->gen2.qw1,
3379 RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_H6);
3380 } else {
3381 sig_a1 = le64_get_bits(sig->gen0.qw0, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK);
3382 sig_a2 = le64_get_bits(sig->gen0.qw0, RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK);
3383 }
3384
3385 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
3386 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN |
3387 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN |
3388 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN |
3389 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN);
3390
3391 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN);
3392
3393 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_BSS_COLOR);
3394 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR);
3395
3396 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB1);
3397 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1);
3398 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB2);
3399 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2);
3400 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB3);
3401 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3);
3402 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB4);
3403 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4);
3404
3405 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_TB_SIG_A2_TXOP);
3406 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP);
3407 }
3408
rtw89_core_he_mu_get_n_user_fields_by_ru_alloc(struct rtw89_dev * rtwdev,u8 ru_alloc)3409 static u8 rtw89_core_he_mu_get_n_user_fields_by_ru_alloc(struct rtw89_dev *rtwdev,
3410 u8 ru_alloc)
3411 {
3412 u8 mu_users;
3413
3414 if (ru_alloc <= 15) {
3415 static const u8 entries_0_15[16] = {
3416 9, 8, 8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6, 6, 5,
3417 };
3418
3419 return entries_0_15[ru_alloc];
3420 }
3421
3422 if (ru_alloc >= 16 && ru_alloc <= 95) {
3423 mu_users = ru_alloc & 0x07;
3424
3425 switch (ru_alloc & 0xF8) {
3426 case 16: case 24: return mu_users + 3;
3427 case 32: case 64: return mu_users + 6;
3428 case 40: case 48: case 72: case 80: return mu_users + 5;
3429 case 56: case 88: return mu_users + 4;
3430 }
3431 }
3432
3433 if (ru_alloc >= 96 && ru_alloc <= 111) {
3434 mu_users = ru_alloc & 0x03;
3435 mu_users += ru_alloc >> 2 & 0x03;
3436
3437 return mu_users + 2;
3438 }
3439
3440 if (ru_alloc == 112)
3441 return 4;
3442
3443 if (ru_alloc >= 113 && ru_alloc <= 115)
3444 return 0;
3445
3446 if (ru_alloc >= 128 && ru_alloc <= 191) {
3447 mu_users = ru_alloc & 0x07;
3448 mu_users += ru_alloc >> 3 & 0x07;
3449
3450 return mu_users + 3;
3451 }
3452
3453 if (ru_alloc >= 192 && ru_alloc <= 215)
3454 return (ru_alloc & 0x07) + 1;
3455
3456 return 0;
3457 }
3458
rtw89_core_he_mu_get_n_ru_alloc(struct rtw89_dev * rtwdev,u8 bw)3459 static int rtw89_core_he_mu_get_n_ru_alloc(struct rtw89_dev *rtwdev, u8 bw)
3460 {
3461 switch (bw) {
3462 case 0:
3463 case 1:
3464 return 1;
3465 case 2:
3466 case 4:
3467 case 5:
3468 return 2;
3469 case 3:
3470 case 6:
3471 case 7:
3472 return 3;
3473 }
3474
3475 return 0;
3476 }
3477
rtw89_core_he_mu_get_cc_ptr(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_ie10 * ie10,u8 bw,int n_ru,int n_center_26tone,const u8 ** c1,const u8 ** c2)3478 static void rtw89_core_he_mu_get_cc_ptr(struct rtw89_dev *rtwdev,
3479 const struct rtw89_phy_sts_ie10 *ie10,
3480 u8 bw, int n_ru, int n_center_26tone,
3481 const u8 **c1, const u8 **c2)
3482 {
3483 const u8 *sigb, *end_sigb;
3484 int total_bits, c2_offset;
3485 int n_user_fields = 0;
3486 const u8 *ptr;
3487 int i;
3488
3489 sigb = &ie10->sigb[0];
3490 end_sigb = (const void *)ie10 +
3491 rtw89_core_get_phy_status_ie_len(rtwdev, (const void *)ie10);
3492
3493 ptr = sigb;
3494 if (ptr + n_ru + n_center_26tone >= end_sigb)
3495 return;
3496 *c1 = ptr;
3497
3498 if (bw == 0) /* 20MHz doesn't have content channel 2 */
3499 return;
3500
3501 for (i = 0; i < n_ru; i++)
3502 n_user_fields +=
3503 rtw89_core_he_mu_get_n_user_fields_by_ru_alloc(rtwdev, (*c1)[i]);
3504
3505 /* hardware report max 15 recordes, align 8 */
3506 n_user_fields = min(n_user_fields, 15);
3507
3508 total_bits = n_ru * 8 + n_center_26tone + 10 +
3509 n_user_fields * 21 + DIV_ROUND_UP(n_user_fields, 2) * 10;
3510 c2_offset = ALIGN(DIV_ROUND_UP(total_bits, 8), 8);
3511
3512 ptr = &sigb[c2_offset];
3513 if (ptr + n_ru + n_center_26tone >= end_sigb)
3514 return;
3515
3516 *c2 = ptr;
3517 }
3518
rtw89_core_update_radiotap_he_mu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct ieee80211_radiotap_he * he,struct ieee80211_radiotap_he_mu * he_mu,const union rtw89_phy_sts_ie09 * ie09,const struct rtw89_phy_sts_ie10 * ie10)3519 static void rtw89_core_update_radiotap_he_mu(struct rtw89_dev *rtwdev,
3520 struct sk_buff *skb,
3521 struct ieee80211_rx_status *rx_status,
3522 struct ieee80211_radiotap_he *he,
3523 struct ieee80211_radiotap_he_mu *he_mu,
3524 const union rtw89_phy_sts_ie09 *ie09,
3525 const struct rtw89_phy_sts_ie10 *ie10)
3526 {
3527 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
3528 const u8 *c1 = NULL, *c2 = NULL;
3529 int n_center_26tone, n_ru, i;
3530 bool doppler, comp;
3531 u32 sig_a1, sig_a2;
3532 u16 t;
3533 u8 bw;
3534
3535 if (!ie09)
3536 return;
3537
3538 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN |
3539 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN |
3540 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN |
3541 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN |
3542 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN);
3543 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN |
3544 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN |
3545 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN |
3546 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN);
3547
3548 if (phy->physt_gen >= 2) {
3549 sig_a1 = le64_get_bits(ie09->gen2.qw0,
3550 RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK_GEN2);
3551 sig_a2 = le64_get_bits(ie09->gen2.qw0,
3552 RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_L0);
3553 sig_a2 |= le64_get_bits(ie09->gen2.qw1,
3554 RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_H6) << 6;
3555 } else {
3556 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK);
3557 sig_a2 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK);
3558 }
3559
3560 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_ULDL);
3561 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_UL_DL);
3562
3563 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BSS_COLOR);
3564 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR);
3565
3566 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SR);
3567 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE);
3568
3569 doppler = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_DOPPLER);
3570 he->data6 |= le16_encode_bits(doppler, IEEE80211_RADIOTAP_HE_DATA6_DOPPLER);
3571
3572 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_TXOP);
3573 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP);
3574
3575 if (doppler) {
3576 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MID);
3577 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY);
3578 }
3579
3580 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_LPDC_XSYMSEG);
3581 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG);
3582
3583 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_FEC);
3584 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD);
3585
3586 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_PE);
3587 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG);
3588
3589 he_mu->flags1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN |
3590 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN |
3591 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN |
3592 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN);
3593 he_mu->flags2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN);
3594
3595 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_MCS);
3596 he_mu->flags1 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS);
3597
3598 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_DCM);
3599 he_mu->flags1 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM);
3600
3601 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_SYM_USR);
3602 he_mu->flags2 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS);
3603
3604 comp = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_COM);
3605 he_mu->flags2 |= le16_encode_bits(comp, IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP);
3606
3607 bw = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BW);
3608 he_mu->flags2 |= le16_encode_bits(bw, IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW);
3609
3610 if (comp == 0 && bw <= 5) {
3611 u8 punc = clamp_t(int, bw - 3, 0, 2);
3612
3613 he_mu->flags2 |=
3614 cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN);
3615 he_mu->flags2 |=
3616 le16_encode_bits(punc, IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW);
3617 }
3618
3619 /* the Common field in the HE-SIG-B field is not present */
3620 if (comp || !ie10)
3621 return;
3622
3623 n_ru = rtw89_core_he_mu_get_n_ru_alloc(rtwdev, bw);
3624 n_center_26tone = bw >= 1;
3625
3626 rtw89_core_he_mu_get_cc_ptr(rtwdev, ie10, bw, n_ru, n_center_26tone, &c1, &c2);
3627 if (!c1)
3628 return;
3629
3630 he_mu->flags1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN |
3631 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN |
3632 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN |
3633 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN);
3634
3635 for (i = 0; i < n_ru; i++) {
3636 he_mu->ru_ch1[i] = c1[i];
3637 if (c2)
3638 he_mu->ru_ch2[i] = c2[i];
3639 }
3640
3641 if (n_center_26tone) {
3642 u8 ru;
3643
3644 ru = c1[n_ru] & BIT(0);
3645 he_mu->flags1 |=
3646 le16_encode_bits(ru, IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU);
3647
3648 ru = c2 ? c2[n_ru] & BIT(0) : 0;
3649 he_mu->flags1 |=
3650 le16_encode_bits(ru, IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU);
3651 }
3652 }
3653
rtw89_core_get_radiotap_he_format(struct rtw89_rx_desc_info * desc_info)3654 static u16 rtw89_core_get_radiotap_he_format(struct rtw89_rx_desc_info *desc_info)
3655 {
3656 switch (desc_info->ppdu_type) {
3657 case RTW89_RX_PPDU_T_HE_MU:
3658 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU;
3659 case RTW89_RX_PPDU_T_HE_ERSU:
3660 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU;
3661 case RTW89_RX_PPDU_T_HE_TB:
3662 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG;
3663 default:
3664 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU;
3665 }
3666 }
3667
rtw89_core_update_radiotap_he(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3668 static void rtw89_core_update_radiotap_he(struct rtw89_dev *rtwdev,
3669 struct rtw89_rx_desc_info *desc_info,
3670 struct sk_buff *skb,
3671 struct ieee80211_rx_status *rx_status,
3672 struct rtw89_rx_phy_ppdu *phy_ppdu)
3673 {
3674 static const struct ieee80211_radiotap_he known_he = {
3675 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
3676 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
3677 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
3678 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
3679 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
3680 };
3681 struct ieee80211_radiotap_he_mu *he_mu = NULL;
3682 const union rtw89_phy_sts_ie09 *ie09;
3683 const struct rtw89_phy_sts_ie10 *ie10;
3684 struct ieee80211_radiotap_he *he;
3685 u16 he_format;
3686
3687 he_format = rtw89_core_get_radiotap_he_format(desc_info);
3688
3689 /* Radiotap of HE-MU must be placed after HE (skb_push ahead) */
3690 if (he_format == IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU) {
3691 rx_status->flag |= RX_FLAG_RADIOTAP_HE_MU;
3692 he_mu = skb_push(skb, sizeof(*he_mu));
3693 memset(he_mu, 0, sizeof(*he_mu));
3694 }
3695
3696 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
3697 he = skb_push(skb, sizeof(*he));
3698 *he = known_he;
3699
3700 he->data1 |= le16_encode_bits(he_format, IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK);
3701
3702 if (!phy_ppdu)
3703 return;
3704
3705 ie09 = phy_ppdu->ie09;
3706 ie10 = phy_ppdu->ie10;
3707
3708 switch (he_format) {
3709 case IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU:
3710 rtw89_core_update_radiotap_he_mu(rtwdev, skb, rx_status, he, he_mu,
3711 ie09, ie10);
3712 break;
3713 case IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG:
3714 rtw89_core_update_radiotap_he_tb(rtwdev, skb, rx_status, he, ie09);
3715 break;
3716 default:
3717 rtw89_core_update_radiotap_he_su(rtwdev, skb, rx_status, he, ie09);
3718 break;
3719 }
3720 }
3721
3722 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
3723 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
3724 [RATE_INFO_BW_5] = U8_MAX,
3725 [RATE_INFO_BW_10] = U8_MAX,
3726 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
3727 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
3728 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
3729 [RATE_INFO_BW_HE_RU] = U8_MAX,
3730 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
3731 [RATE_INFO_BW_EHT_RU] = U8_MAX,
3732 };
3733
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3734 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
3735 struct sk_buff *skb,
3736 struct ieee80211_rx_status *rx_status)
3737 {
3738 struct ieee80211_radiotap_eht_usig *usig;
3739 struct ieee80211_radiotap_eht *eht;
3740 struct ieee80211_radiotap_tlv *tlv;
3741 int eht_len = struct_size(eht, user_info, 1);
3742 int usig_len = sizeof(*usig);
3743 int len;
3744 u8 bw;
3745
3746 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
3747 sizeof(*tlv) + ALIGN(usig_len, 4);
3748
3749 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
3750 skb_reset_mac_header(skb);
3751
3752 /* EHT */
3753 tlv = skb_push(skb, len);
3754 memset(tlv, 0, len);
3755 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
3756 tlv->len = cpu_to_le16(eht_len);
3757
3758 eht = (struct ieee80211_radiotap_eht *)tlv->data;
3759 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
3760 eht->data[0] =
3761 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
3762
3763 eht->user_info[0] =
3764 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
3765 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
3766 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
3767 eht->user_info[0] |=
3768 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
3769 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
3770 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
3771 eht->user_info[0] |=
3772 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
3773
3774 /* U-SIG */
3775 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
3776 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
3777 tlv->len = cpu_to_le16(usig_len);
3778
3779 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
3780 return;
3781
3782 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
3783 if (bw == U8_MAX)
3784 return;
3785
3786 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
3787 usig->common =
3788 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
3789 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
3790 }
3791
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3792 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
3793 struct rtw89_rx_desc_info *desc_info,
3794 struct sk_buff *skb,
3795 struct ieee80211_rx_status *rx_status,
3796 struct rtw89_rx_phy_ppdu *phy_ppdu)
3797 {
3798 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3799 return;
3800
3801 /*
3802 * At transient adding a monitor vif from a station vif, the headroom
3803 * might not include radiotap.
3804 */
3805 if (unlikely(skb_headroom(skb) < RTW89_RADIOTAP_ROOM + NET_SKB_PAD))
3806 return;
3807
3808 if (rx_status->encoding == RX_ENC_VHT)
3809 rtw89_core_update_radiotap_vht(rtwdev, skb, rx_status, phy_ppdu);
3810 else if (rx_status->encoding == RX_ENC_HE)
3811 rtw89_core_update_radiotap_he(rtwdev, desc_info, skb, rx_status, phy_ppdu);
3812 else if (rx_status->encoding == RX_ENC_EHT)
3813 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
3814 }
3815
rtw89_core_validate_rx_signal(struct ieee80211_rx_status * rx_status)3816 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status)
3817 {
3818 if (!rx_status->signal)
3819 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
3820 }
3821
rtw89_core_update_rx_freq_from_ie(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3822 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev,
3823 struct sk_buff *skb,
3824 struct ieee80211_rx_status *rx_status)
3825 {
3826 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
3827 size_t hdr_len, ielen;
3828 u8 *variable;
3829 int chan;
3830
3831 if (!rtwdev->chip->rx_freq_from_ie)
3832 return;
3833
3834 if (!rtwdev->scanning)
3835 return;
3836
3837 if (ieee80211_is_beacon(mgmt->frame_control)) {
3838 variable = mgmt->u.beacon.variable;
3839 hdr_len = offsetof(struct ieee80211_mgmt,
3840 u.beacon.variable);
3841 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) {
3842 variable = mgmt->u.probe_resp.variable;
3843 hdr_len = offsetof(struct ieee80211_mgmt,
3844 u.probe_resp.variable);
3845 } else {
3846 return;
3847 }
3848
3849 if (skb->len > hdr_len)
3850 ielen = skb->len - hdr_len;
3851 else
3852 return;
3853
3854 /* The parsing code for both 2GHz and 5GHz bands is the same in this
3855 * function.
3856 */
3857 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ);
3858 if (chan == -1)
3859 return;
3860
3861 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
3862 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band);
3863 }
3864
rtw89_core_correct_mcc_chan(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3865 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev,
3866 struct rtw89_rx_desc_info *desc_info,
3867 struct ieee80211_rx_status *rx_status,
3868 struct rtw89_rx_phy_ppdu *phy_ppdu)
3869 {
3870 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
3871 struct rtw89_vif_link *rtwvif_link;
3872 struct rtw89_sta_link *rtwsta_link;
3873 const struct rtw89_chan *chan;
3874 u8 mac_id = desc_info->mac_id;
3875 enum rtw89_entity_mode mode;
3876 enum nl80211_band band;
3877
3878 mode = rtw89_get_entity_mode(rtwdev);
3879 if (likely(mode != RTW89_ENTITY_MODE_MCC))
3880 return;
3881
3882 if (chip_gen == RTW89_CHIP_BE && phy_ppdu)
3883 mac_id = phy_ppdu->mac_id;
3884
3885 rcu_read_lock();
3886
3887 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id);
3888 if (!rtwsta_link)
3889 goto out;
3890
3891 rtwvif_link = rtwsta_link->rtwvif_link;
3892 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3893 band = rtw89_hw_to_nl80211_band(chan->band_type);
3894 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band);
3895
3896 out:
3897 rcu_read_unlock();
3898 }
3899
__rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats * tid_stats)3900 static void __rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats *tid_stats)
3901 {
3902 tid_stats->last_pn = -1LL;
3903 tid_stats->last_sn = IEEE80211_SN_MASK;
3904 }
3905
rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,struct ieee80211_ampdu_params * params,bool enable)3906 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3907 struct ieee80211_ampdu_params *params, bool enable)
3908 {
3909 struct rtw89_tid_stats *tid_stats;
3910 u16 tid = params->tid;
3911
3912 tid_stats = &rtwsta->tid_rx_stats[tid];
3913
3914 if (enable) {
3915 __rtw89_core_tid_rx_stats_reset(tid_stats);
3916 tid_stats->started = true;
3917 } else {
3918 tid_stats->started = false;
3919 }
3920 }
3921
rtw89_core_tid_rx_stats_reset(struct rtw89_dev * rtwdev)3922 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev)
3923 {
3924 struct rtw89_tid_stats *tid_stats;
3925 struct ieee80211_sta *sta;
3926 struct rtw89_sta *rtwsta;
3927 u16 tid;
3928
3929 for_each_station(sta, rtwdev->hw) {
3930 rtwsta = sta_to_rtwsta(sta);
3931
3932 for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) {
3933 tid_stats = &rtwsta->tid_rx_stats[tid];
3934
3935 if (!tid_stats->started)
3936 continue;
3937
3938 __rtw89_core_tid_rx_stats_reset(tid_stats);
3939 }
3940 }
3941 }
3942
rtw89_core_skb_pn_valid(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3943 static bool rtw89_core_skb_pn_valid(struct rtw89_dev *rtwdev,
3944 struct rtw89_rx_desc_info *desc_info,
3945 struct sk_buff *skb)
3946 {
3947 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3948 const struct rtw89_chip_info *chip = rtwdev->chip;
3949 struct rtw89_sta_link *rtwsta_link;
3950 struct rtw89_tid_stats *tid_stats;
3951 struct rtw89_sta *rtwsta;
3952 u8 tid, *ccmp_hdr_ptr;
3953 s64 pn, last_pn;
3954 u16 mpdu_sn;
3955 int hdrlen;
3956
3957 if (chip->chip_gen != RTW89_CHIP_AX)
3958 return true;
3959
3960 if (!ieee80211_is_data_qos(hdr->frame_control))
3961 return true;
3962
3963 if (!desc_info->hw_dec || !desc_info->addr1_match)
3964 return true;
3965
3966 guard(rcu)();
3967
3968 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, desc_info->mac_id);
3969 if (!rtwsta_link)
3970 return true;
3971
3972 rtwsta = rtwsta_link->rtwsta;
3973 tid = ieee80211_get_tid(hdr);
3974 tid_stats = &rtwsta->tid_rx_stats[tid];
3975
3976 if (!tid_stats->started)
3977 return true;
3978
3979 switch (desc_info->sec_type) {
3980 case RTW89_SEC_KEY_TYPE_CCMP128:
3981 case RTW89_SEC_KEY_TYPE_CCMP256:
3982 case RTW89_SEC_KEY_TYPE_GCMP128:
3983 case RTW89_SEC_KEY_TYPE_GCMP256:
3984 mpdu_sn = ieee80211_get_sn(hdr);
3985 hdrlen = ieee80211_hdrlen(hdr->frame_control);
3986 ccmp_hdr_ptr = skb->data + hdrlen;
3987 ccmp_hdr2pn(&pn, ccmp_hdr_ptr);
3988 last_pn = tid_stats->last_pn;
3989
3990 if (pn > last_pn) {
3991 if (last_pn != -1LL &&
3992 ieee80211_sn_less(mpdu_sn, tid_stats->last_sn)) {
3993 dev_kfree_skb_any(skb);
3994
3995 return false;
3996 }
3997
3998 tid_stats->last_sn = mpdu_sn;
3999 tid_stats->last_pn = pn;
4000 }
4001 break;
4002 default:
4003 break;
4004 }
4005
4006 return true;
4007 }
4008
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)4009 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
4010 struct rtw89_rx_phy_ppdu *phy_ppdu,
4011 struct rtw89_rx_desc_info *desc_info,
4012 struct sk_buff *skb_ppdu,
4013 struct ieee80211_rx_status *rx_status)
4014 {
4015 struct napi_struct *napi = &rtwdev->napi;
4016
4017 /* In low power mode, napi isn't scheduled. Receive it to netif. */
4018 if (unlikely(!napi_is_scheduled(napi)))
4019 napi = NULL;
4020
4021 rtw89_core_hw_to_sband_rate(rx_status);
4022 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
4023 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
4024 rtw89_core_update_radiotap(rtwdev, desc_info, skb_ppdu, rx_status, phy_ppdu);
4025 rtw89_core_validate_rx_signal(rx_status);
4026 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status);
4027 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu);
4028
4029 /* In low power mode, it does RX in thread context. */
4030 local_bh_disable();
4031 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
4032 local_bh_enable();
4033 rtwdev->napi_budget_countdown--;
4034 }
4035
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)4036 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
4037 struct rtw89_rx_phy_ppdu *phy_ppdu,
4038 struct rtw89_rx_desc_info *desc_info,
4039 struct sk_buff *skb)
4040 {
4041 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
4042 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
4043 struct sk_buff *skb_ppdu = NULL, *tmp;
4044 struct ieee80211_rx_status *rx_status;
4045
4046 if (curr > RTW89_MAX_PPDU_CNT)
4047 return;
4048
4049 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
4050 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
4051 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
4052 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
4053 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
4054 rtw89_correct_cck_chan(rtwdev, rx_status);
4055 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
4056 }
4057 }
4058
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)4059 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
4060 struct rtw89_rx_desc_info *desc_info,
4061 struct sk_buff *skb)
4062 {
4063 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
4064 .len = skb->len,
4065 .to_self = desc_info->addr1_match,
4066 .rate = desc_info->data_rate,
4067 .mac_id = desc_info->mac_id,
4068 .phy_idx = desc_info->bb_sel};
4069 int ret;
4070
4071 if (desc_info->mac_info_valid) {
4072 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
4073 if (ret)
4074 goto out;
4075 }
4076
4077 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
4078 if (ret)
4079 goto out;
4080
4081 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
4082
4083 out:
4084 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
4085 dev_kfree_skb_any(skb);
4086 }
4087
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)4088 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
4089 struct rtw89_rx_desc_info *desc_info,
4090 struct sk_buff *skb)
4091 {
4092 switch (desc_info->pkt_type) {
4093 case RTW89_CORE_RX_TYPE_C2H:
4094 rtw89_fw_c2h_irqsafe(rtwdev, skb);
4095 break;
4096 case RTW89_CORE_RX_TYPE_PPDU_STAT:
4097 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
4098 break;
4099 default:
4100 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
4101 desc_info->pkt_type);
4102 dev_kfree_skb_any(skb);
4103 break;
4104 }
4105 }
4106
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)4107 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
4108 struct rtw89_rx_desc_info *desc_info,
4109 u8 *data, u32 data_offset)
4110 {
4111 const struct rtw89_chip_info *chip = rtwdev->chip;
4112 struct rtw89_rxdesc_short *rxd_s;
4113 struct rtw89_rxdesc_long *rxd_l;
4114 u8 shift_len, drv_info_len;
4115
4116 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
4117 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
4118 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
4119 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
4120 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
4121 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
4122 if (chip->chip_id == RTL8852C)
4123 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
4124 else
4125 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
4126 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
4127 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
4128 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
4129 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
4130 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
4131 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
4132 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
4133 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
4134 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
4135 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
4136 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
4137 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
4138 desc_info->ampdu = le32_get_bits(rxd_s->dword3, AX_RXD_AMPDU);
4139
4140 shift_len = desc_info->shift << 1; /* 2-byte unit */
4141 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
4142 desc_info->offset = data_offset + shift_len + drv_info_len;
4143 if (desc_info->long_rxdesc)
4144 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
4145 else
4146 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
4147 desc_info->ready = true;
4148
4149 if (!desc_info->long_rxdesc)
4150 return;
4151
4152 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
4153 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
4154 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
4155 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
4156 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
4157 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
4158 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
4159 desc_info->sec_type = le32_get_bits(rxd_l->dword7, AX_RXD_SEC_TYPE_MASK);
4160 }
4161 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
4162
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)4163 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
4164 struct rtw89_rx_desc_info *desc_info,
4165 u8 *data, u32 data_offset)
4166 {
4167 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
4168 struct rtw89_rxdesc_short_v2 *rxd_s;
4169 struct rtw89_rxdesc_long_v2 *rxd_l;
4170 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
4171
4172 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
4173
4174 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
4175 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
4176 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
4177 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
4178 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
4179 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
4180 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
4181 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
4182 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
4183 desc_info->mac_info_valid = true;
4184
4185 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
4186 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
4187 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
4188
4189 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
4190 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
4191 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
4192 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
4193 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
4194 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
4195 desc_info->ampdu = le32_get_bits(rxd_s->dword3, BE_RXD_AMPDU);
4196
4197 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
4198 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
4199 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
4200 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
4201 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
4202
4203 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
4204
4205 shift_len = desc_info->shift << 1; /* 2-byte unit */
4206 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
4207 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
4208 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
4209 desc_info->offset = data_offset + shift_len + drv_info_len +
4210 phy_rtp_len + hdr_cnv_len;
4211
4212 if (desc_info->long_rxdesc)
4213 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
4214 else
4215 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
4216 desc_info->ready = true;
4217
4218 if (phy_rtp_len == sizeof(*rxd_rpt)) {
4219 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
4220 desc_info->rxd_len);
4221 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
4222 }
4223
4224 if (!desc_info->long_rxdesc)
4225 return;
4226
4227 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
4228
4229 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
4230 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
4231 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
4232 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
4233
4234 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
4235 }
4236 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
4237
rtw89_core_query_rxdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)4238 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
4239 struct rtw89_rx_desc_info *desc_info,
4240 u8 *data, u32 data_offset)
4241 {
4242 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
4243 struct rtw89_rxdesc_short_v3 *rxd_s;
4244 struct rtw89_rxdesc_long_v3 *rxd_l;
4245 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
4246
4247 rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset);
4248
4249 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
4250 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
4251 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
4252 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
4253 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
4254 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
4255 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
4256 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
4257 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
4258 desc_info->mac_info_valid = true;
4259
4260 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
4261 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
4262 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
4263
4264 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK);
4265 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
4266 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
4267 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
4268 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
4269 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
4270 desc_info->ampdu = le32_get_bits(rxd_s->dword3, BE_RXD_AMPDU);
4271
4272 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
4273 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
4274 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
4275 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
4276 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
4277
4278 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
4279
4280 shift_len = desc_info->shift << 1; /* 2-byte unit */
4281 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
4282 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
4283 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
4284 desc_info->offset = data_offset + shift_len + drv_info_len +
4285 phy_rtp_len + hdr_cnv_len;
4286
4287 if (desc_info->long_rxdesc)
4288 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3);
4289 else
4290 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3);
4291 desc_info->ready = true;
4292
4293 if (phy_rtp_len == sizeof(*rxd_rpt)) {
4294 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
4295 desc_info->rxd_len);
4296 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
4297 }
4298
4299 if (!desc_info->long_rxdesc)
4300 return;
4301
4302 rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset);
4303
4304 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
4305 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
4306 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1);
4307 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1);
4308
4309 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
4310 }
4311 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3);
4312
4313 struct rtw89_core_iter_rx_status {
4314 struct rtw89_dev *rtwdev;
4315 struct ieee80211_rx_status *rx_status;
4316 struct rtw89_rx_desc_info *desc_info;
4317 u8 mac_id;
4318 };
4319
4320 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)4321 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
4322 {
4323 struct rtw89_core_iter_rx_status *iter_data =
4324 (struct rtw89_core_iter_rx_status *)data;
4325 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
4326 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
4327 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4328 struct rtw89_sta_link *rtwsta_link;
4329 u8 mac_id = iter_data->mac_id;
4330
4331 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel);
4332 if (unlikely(!rtwsta_link))
4333 return;
4334
4335 if (mac_id != rtwsta_link->mac_id)
4336 return;
4337
4338 rtwsta_link->rx_status = *rx_status;
4339 rtwsta_link->rx_hw_rate = desc_info->data_rate;
4340 }
4341
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)4342 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
4343 struct rtw89_rx_desc_info *desc_info,
4344 struct ieee80211_rx_status *rx_status)
4345 {
4346 struct rtw89_core_iter_rx_status iter_data;
4347
4348 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
4349 return;
4350
4351 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
4352 return;
4353
4354 iter_data.rtwdev = rtwdev;
4355 iter_data.rx_status = rx_status;
4356 iter_data.desc_info = desc_info;
4357 iter_data.mac_id = desc_info->mac_id;
4358 ieee80211_iterate_stations_atomic(rtwdev->hw,
4359 rtw89_core_stats_sta_rx_status_iter,
4360 &iter_data);
4361 }
4362
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)4363 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
4364 struct sk_buff *skb,
4365 struct rtw89_rx_desc_info *desc_info,
4366 struct ieee80211_rx_status *rx_status)
4367 {
4368 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4369 const struct cfg80211_chan_def *chandef =
4370 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
4371 u16 data_rate;
4372 u8 data_rate_mode;
4373 bool eht = false;
4374 u8 gi;
4375
4376 /* currently using single PHY */
4377 rx_status->freq = chandef->chan->center_freq;
4378 rx_status->band = chandef->chan->band;
4379
4380 if (ieee80211_is_beacon(hdr->frame_control) ||
4381 ieee80211_is_probe_resp(hdr->frame_control))
4382 rx_status->boottime_ns = ktime_get_boottime_ns();
4383
4384 if (rtwdev->scanning &&
4385 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
4386 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
4387 u8 chan = cur->primary_channel;
4388 u8 band = cur->band_type;
4389 enum nl80211_band nl_band;
4390
4391 nl_band = rtw89_hw_to_nl80211_band(band);
4392 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
4393 rx_status->band = nl_band;
4394 }
4395
4396 if (desc_info->icv_err || desc_info->crc32_err)
4397 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
4398
4399 if (desc_info->hw_dec &&
4400 !(desc_info->sw_dec || desc_info->icv_err))
4401 rx_status->flag |= RX_FLAG_DECRYPTED;
4402
4403 if (desc_info->ampdu) {
4404 rx_status->flag |= RX_FLAG_AMPDU_DETAILS;
4405 rx_status->ampdu_reference = desc_info->ppdu_cnt;
4406 }
4407
4408 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
4409
4410 data_rate = desc_info->data_rate;
4411 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
4412 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
4413 rx_status->encoding = RX_ENC_LEGACY;
4414 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
4415 /* convert rate_idx after we get the correct band */
4416 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
4417 rx_status->encoding = RX_ENC_HT;
4418 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
4419 if (desc_info->gi_ltf)
4420 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
4421 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
4422 rx_status->encoding = RX_ENC_VHT;
4423 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
4424 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
4425 if (desc_info->gi_ltf)
4426 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
4427 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
4428 rx_status->encoding = RX_ENC_HE;
4429 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
4430 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
4431 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
4432 rx_status->encoding = RX_ENC_EHT;
4433 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
4434 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
4435 eht = true;
4436 } else {
4437 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
4438 }
4439
4440 /* he_gi is used to match ppdu, so we always fill it. */
4441 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
4442 if (eht)
4443 rx_status->eht.gi = gi;
4444 else
4445 rx_status->he_gi = gi;
4446 rx_status->flag |= RX_FLAG_MACTIME_START;
4447 rx_status->mactime = desc_info->free_run_cnt;
4448
4449 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
4450 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
4451 }
4452
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)4453 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
4454 {
4455 const struct rtw89_chip_info *chip = rtwdev->chip;
4456
4457 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
4458 return RTW89_PS_MODE_NONE;
4459
4460 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
4461 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
4462 return RTW89_PS_MODE_NONE;
4463
4464 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
4465 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
4466 return RTW89_PS_MODE_PWR_GATED;
4467
4468 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
4469 return RTW89_PS_MODE_CLK_GATED;
4470
4471 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
4472 return RTW89_PS_MODE_RFOFF;
4473
4474 return RTW89_PS_MODE_NONE;
4475 }
4476
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)4477 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
4478 struct rtw89_rx_desc_info *desc_info)
4479 {
4480 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
4481 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
4482 struct ieee80211_rx_status *rx_status;
4483 struct sk_buff *skb_ppdu, *tmp;
4484
4485 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
4486 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
4487 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
4488 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
4489 }
4490 }
4491
4492 static
rtw89_core_rx_pkt_hdl(struct rtw89_dev * rtwdev,const struct sk_buff * skb,const struct rtw89_rx_desc_info * desc)4493 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb,
4494 const struct rtw89_rx_desc_info *desc)
4495 {
4496 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4497 struct rtw89_sta_link *rtwsta_link;
4498 struct ieee80211_sta *sta;
4499 struct rtw89_sta *rtwsta;
4500 u8 macid = desc->mac_id;
4501
4502 if (!refcount_read(&rtwdev->refcount_ap_info))
4503 return;
4504
4505 rcu_read_lock();
4506
4507 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
4508 if (!rtwsta_link)
4509 goto out;
4510
4511 rtwsta = rtwsta_link->rtwsta;
4512 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags))
4513 goto out;
4514
4515 sta = rtwsta_to_sta(rtwsta);
4516 if (ieee80211_is_pspoll(hdr->frame_control))
4517 ieee80211_sta_pspoll(sta);
4518 else if (ieee80211_has_pm(hdr->frame_control) &&
4519 (ieee80211_is_data_qos(hdr->frame_control) ||
4520 ieee80211_is_qos_nullfunc(hdr->frame_control)))
4521 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr));
4522
4523 out:
4524 rcu_read_unlock();
4525 }
4526
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)4527 void rtw89_core_rx(struct rtw89_dev *rtwdev,
4528 struct rtw89_rx_desc_info *desc_info,
4529 struct sk_buff *skb)
4530 {
4531 struct ieee80211_rx_status *rx_status;
4532 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
4533 u8 ppdu_cnt = desc_info->ppdu_cnt;
4534 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
4535
4536 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
4537 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
4538 return;
4539 }
4540
4541 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
4542 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
4543 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
4544 }
4545
4546 rx_status = IEEE80211_SKB_RXCB(skb);
4547 memset(rx_status, 0, sizeof(*rx_status));
4548 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status);
4549 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
4550
4551 if (!rtw89_core_skb_pn_valid(rtwdev, desc_info, skb))
4552 return;
4553
4554 if (desc_info->long_rxdesc &&
4555 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
4556 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
4557 else
4558 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
4559 }
4560 EXPORT_SYMBOL(rtw89_core_rx);
4561
rtw89_core_napi_start(struct rtw89_dev * rtwdev)4562 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
4563 {
4564 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
4565 return;
4566
4567 napi_enable(&rtwdev->napi);
4568 }
4569 EXPORT_SYMBOL(rtw89_core_napi_start);
4570
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)4571 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
4572 {
4573 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
4574 return;
4575
4576 napi_synchronize(&rtwdev->napi);
4577 napi_disable(&rtwdev->napi);
4578 }
4579 EXPORT_SYMBOL(rtw89_core_napi_stop);
4580
rtw89_core_napi_init(struct rtw89_dev * rtwdev)4581 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
4582 {
4583 rtwdev->netdev = alloc_netdev_dummy(0);
4584 if (!rtwdev->netdev)
4585 return -ENOMEM;
4586
4587 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
4588 rtwdev->hci.ops->napi_poll);
4589 return 0;
4590 }
4591 EXPORT_SYMBOL(rtw89_core_napi_init);
4592
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)4593 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
4594 {
4595 rtw89_core_napi_stop(rtwdev);
4596 netif_napi_del(&rtwdev->napi);
4597 free_netdev(rtwdev->netdev);
4598 }
4599 EXPORT_SYMBOL(rtw89_core_napi_deinit);
4600
rtw89_core_ba_work(struct work_struct * work)4601 static void rtw89_core_ba_work(struct work_struct *work)
4602 {
4603 struct rtw89_dev *rtwdev =
4604 container_of(work, struct rtw89_dev, ba_work);
4605 struct rtw89_txq *rtwtxq, *tmp;
4606 int ret;
4607
4608 spin_lock_bh(&rtwdev->ba_lock);
4609 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
4610 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4611 struct ieee80211_sta *sta = txq->sta;
4612 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
4613 u8 tid = txq->tid;
4614
4615 if (!sta) {
4616 rtw89_warn(rtwdev, "cannot start BA without sta\n");
4617 goto skip_ba_work;
4618 }
4619
4620 if (rtwsta->disassoc) {
4621 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4622 "cannot start BA with disassoc sta\n");
4623 goto skip_ba_work;
4624 }
4625
4626 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
4627 if (ret) {
4628 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4629 "failed to setup BA session for %pM:%2d: %d\n",
4630 sta->addr, tid, ret);
4631 if (ret == -EINVAL)
4632 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
4633 }
4634 skip_ba_work:
4635 list_del_init(&rtwtxq->list);
4636 }
4637 spin_unlock_bh(&rtwdev->ba_lock);
4638 }
4639
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)4640 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
4641 struct ieee80211_sta *sta)
4642 {
4643 struct rtw89_txq *rtwtxq, *tmp;
4644
4645 spin_lock_bh(&rtwdev->ba_lock);
4646 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
4647 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4648
4649 if (sta == txq->sta)
4650 list_del_init(&rtwtxq->list);
4651 }
4652 spin_unlock_bh(&rtwdev->ba_lock);
4653 }
4654
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)4655 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
4656 struct ieee80211_sta *sta)
4657 {
4658 struct rtw89_txq *rtwtxq, *tmp;
4659
4660 spin_lock_bh(&rtwdev->ba_lock);
4661 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
4662 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4663
4664 if (sta == txq->sta) {
4665 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4666 list_del_init(&rtwtxq->list);
4667 }
4668 }
4669 spin_unlock_bh(&rtwdev->ba_lock);
4670 }
4671
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)4672 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
4673 struct ieee80211_sta *sta)
4674 {
4675 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4676 struct sk_buff *skb;
4677
4678 while ((skb = skb_dequeue(&rtwsta->roc_queue)))
4679 dev_kfree_skb_any(skb);
4680 }
4681
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)4682 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
4683 struct rtw89_txq *rtwtxq)
4684 {
4685 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4686 struct ieee80211_sta *sta = txq->sta;
4687 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
4688
4689 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
4690 return;
4691
4692 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
4693 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4694 return;
4695
4696 spin_lock_bh(&rtwdev->ba_lock);
4697 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4698 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
4699 spin_unlock_bh(&rtwdev->ba_lock);
4700
4701 ieee80211_stop_tx_ba_session(sta, txq->tid);
4702 cancel_delayed_work(&rtwdev->forbid_ba_work);
4703 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
4704 RTW89_FORBID_BA_TIMER);
4705 }
4706
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)4707 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
4708 struct rtw89_txq *rtwtxq,
4709 struct sk_buff *skb)
4710 {
4711 struct ieee80211_hw *hw = rtwdev->hw;
4712 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4713 struct ieee80211_sta *sta = txq->sta;
4714 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
4715
4716 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4717 return;
4718
4719 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
4720 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
4721 return;
4722 }
4723
4724 if (unlikely(!sta))
4725 return;
4726
4727 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
4728 return;
4729
4730 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
4731 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
4732 return;
4733 }
4734
4735 spin_lock_bh(&rtwdev->ba_lock);
4736 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
4737 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
4738 ieee80211_queue_work(hw, &rtwdev->ba_work);
4739 }
4740 spin_unlock_bh(&rtwdev->ba_lock);
4741 }
4742
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)4743 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
4744 struct rtw89_txq *rtwtxq,
4745 unsigned long frame_cnt,
4746 unsigned long byte_cnt)
4747 {
4748 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4749 struct ieee80211_vif *vif = txq->vif;
4750 struct ieee80211_sta *sta = txq->sta;
4751 struct sk_buff *skb;
4752 unsigned long i;
4753 int ret;
4754
4755 rcu_read_lock();
4756 for (i = 0; i < frame_cnt; i++) {
4757 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
4758 if (!skb) {
4759 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
4760 goto out;
4761 }
4762 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
4763 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
4764 if (ret) {
4765 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
4766 ieee80211_free_txskb(rtwdev->hw, skb);
4767 break;
4768 }
4769 }
4770 out:
4771 rcu_read_unlock();
4772 }
4773
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)4774 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
4775 {
4776 u8 qsel, ch_dma;
4777
4778 qsel = rtw89_core_get_qsel(rtwdev, tid);
4779 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
4780
4781 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
4782 }
4783
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)4784 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
4785 struct ieee80211_txq *txq,
4786 unsigned long *frame_cnt,
4787 bool *sched_txq, bool *reinvoke)
4788 {
4789 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4790 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
4791 struct rtw89_sta_link *rtwsta_link;
4792
4793 if (!rtwsta)
4794 return false;
4795
4796 rtwsta_link = rtw89_get_designated_link(rtwsta);
4797 if (unlikely(!rtwsta_link)) {
4798 rtw89_err(rtwdev, "agg wait: find no designated link\n");
4799 return false;
4800 }
4801
4802 if (rtwsta_link->max_agg_wait <= 0)
4803 return false;
4804
4805 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
4806 return false;
4807
4808 if (*frame_cnt > 1) {
4809 *frame_cnt -= 1;
4810 *sched_txq = true;
4811 *reinvoke = true;
4812 rtwtxq->wait_cnt = 1;
4813 return false;
4814 }
4815
4816 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
4817 *reinvoke = true;
4818 rtwtxq->wait_cnt++;
4819 return true;
4820 }
4821
4822 rtwtxq->wait_cnt = 0;
4823 return false;
4824 }
4825
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)4826 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
4827 {
4828 struct ieee80211_hw *hw = rtwdev->hw;
4829 struct ieee80211_txq *txq;
4830 struct rtw89_vif *rtwvif;
4831 struct rtw89_txq *rtwtxq;
4832 unsigned long frame_cnt;
4833 unsigned long byte_cnt;
4834 u32 tx_resource;
4835 bool sched_txq;
4836
4837 ieee80211_txq_schedule_start(hw, ac);
4838 while ((txq = ieee80211_next_txq(hw, ac))) {
4839 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4840 rtwvif = vif_to_rtwvif(txq->vif);
4841
4842 if (rtwvif->offchan) {
4843 ieee80211_return_txq(hw, txq, true);
4844 continue;
4845 }
4846 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
4847 sched_txq = false;
4848
4849 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
4850 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
4851 ieee80211_return_txq(hw, txq, true);
4852 continue;
4853 }
4854 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
4855 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
4856 ieee80211_return_txq(hw, txq, sched_txq);
4857 if (frame_cnt != 0)
4858 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
4859
4860 /* bound of tx_resource could get stuck due to burst traffic */
4861 if (frame_cnt == tx_resource)
4862 *reinvoke = true;
4863 }
4864 ieee80211_txq_schedule_end(hw, ac);
4865 }
4866
rtw89_ips_work(struct wiphy * wiphy,struct wiphy_work * work)4867 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work)
4868 {
4869 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4870 ips_work);
4871
4872 lockdep_assert_wiphy(wiphy);
4873
4874 rtw89_enter_ips_by_hwflags(rtwdev);
4875 }
4876
rtw89_core_txq_work(struct work_struct * w)4877 static void rtw89_core_txq_work(struct work_struct *w)
4878 {
4879 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
4880 bool reinvoke = false;
4881 u8 ac;
4882
4883 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
4884 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
4885
4886 if (reinvoke) {
4887 /* reinvoke to process the last frame */
4888 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
4889 }
4890 }
4891
rtw89_core_txq_reinvoke_work(struct work_struct * w)4892 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
4893 {
4894 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4895 txq_reinvoke_work.work);
4896
4897 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
4898 }
4899
rtw89_forbid_ba_work(struct work_struct * w)4900 static void rtw89_forbid_ba_work(struct work_struct *w)
4901 {
4902 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4903 forbid_ba_work.work);
4904 struct rtw89_txq *rtwtxq, *tmp;
4905
4906 spin_lock_bh(&rtwdev->ba_lock);
4907 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
4908 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4909 list_del_init(&rtwtxq->list);
4910 }
4911 spin_unlock_bh(&rtwdev->ba_lock);
4912 }
4913
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)4914 static void rtw89_core_sta_pending_tx_iter(void *data,
4915 struct ieee80211_sta *sta)
4916 {
4917 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4918 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
4919 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4920 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4921 struct rtw89_vif_link *target = data;
4922 struct rtw89_vif_link *rtwvif_link;
4923 unsigned int link_id;
4924 struct sk_buff *skb;
4925 int qsel, ret;
4926
4927 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4928 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
4929 goto bottom;
4930
4931 return;
4932
4933 bottom:
4934 if (skb_queue_len(&rtwsta->roc_queue) == 0)
4935 return;
4936
4937 while ((skb = skb_dequeue(&rtwsta->roc_queue))) {
4938 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
4939 if (ret) {
4940 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
4941 dev_kfree_skb_any(skb);
4942 } else {
4943 rtw89_core_tx_kick_off(rtwdev, qsel);
4944 }
4945 }
4946 }
4947
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4948 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
4949 struct rtw89_vif_link *rtwvif_link)
4950 {
4951 ieee80211_iterate_stations_atomic(rtwdev->hw,
4952 rtw89_core_sta_pending_tx_iter,
4953 rtwvif_link);
4954 }
4955
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps,int timeout)4956 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4957 bool qos, bool ps, int timeout)
4958 {
4959 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4960 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
4961 struct rtw89_sta_link *rtwsta_link;
4962 struct rtw89_tx_wait_info *wait;
4963 struct ieee80211_sta *sta;
4964 struct ieee80211_hdr *hdr;
4965 struct rtw89_sta *rtwsta;
4966 struct sk_buff *skb;
4967 int ret, qsel;
4968
4969 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
4970 return 0;
4971
4972 wait = kzalloc_obj(*wait);
4973 if (!wait)
4974 return -ENOMEM;
4975
4976 init_completion(&wait->completion);
4977
4978 rcu_read_lock();
4979 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
4980 if (!sta) {
4981 ret = -EINVAL;
4982 goto out;
4983 }
4984 rtwsta = sta_to_rtwsta(sta);
4985
4986 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos);
4987 if (!skb) {
4988 ret = -ENOMEM;
4989 goto out;
4990 }
4991
4992 wait->skb = skb;
4993
4994 hdr = (struct ieee80211_hdr *)skb->data;
4995 if (ps)
4996 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
4997
4998 rtwsta_link = rtwsta->links[rtwvif_link->link_id];
4999 if (unlikely(!rtwsta_link)) {
5000 ret = -ENOLINK;
5001 dev_kfree_skb_any(skb);
5002 goto out;
5003 }
5004
5005 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait);
5006 if (ret) {
5007 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
5008 dev_kfree_skb_any(skb);
5009 goto out;
5010 }
5011
5012 rcu_read_unlock();
5013
5014 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel,
5015 timeout);
5016 out:
5017 rcu_read_unlock();
5018 kfree(wait);
5019
5020 return ret;
5021 }
5022
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)5023 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
5024 {
5025 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5026 struct rtw89_chanctx_pause_parm pause_parm = {
5027 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC,
5028 };
5029 struct ieee80211_hw *hw = rtwdev->hw;
5030 struct rtw89_roc *roc = &rtwvif->roc;
5031 struct rtw89_vif_link *rtwvif_link;
5032 struct cfg80211_chan_def roc_chan;
5033 struct rtw89_vif *tmp_vif;
5034 u32 reg;
5035 int ret;
5036
5037 lockdep_assert_wiphy(hw->wiphy);
5038
5039 rtw89_leave_ips_by_hwflags(rtwdev);
5040 rtw89_leave_lps(rtwdev);
5041
5042 rtwvif_link = rtw89_get_designated_link(rtwvif);
5043 if (unlikely(!rtwvif_link)) {
5044 rtw89_err(rtwdev, "roc start: find no designated link\n");
5045 return;
5046 }
5047
5048 roc->link_id = rtwvif_link->link_id;
5049
5050 pause_parm.trigger = rtwvif_link;
5051 rtw89_chanctx_pause(rtwdev, &pause_parm);
5052
5053 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true,
5054 RTW89_ROC_TX_TIMEOUT);
5055 if (ret)
5056 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
5057 "roc send null-1 failed: %d\n", ret);
5058
5059 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
5060 struct rtw89_vif_link *tmp_link;
5061 unsigned int link_id;
5062
5063 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
5064 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
5065 tmp_vif->offchan = true;
5066 break;
5067 }
5068 }
5069 }
5070
5071 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
5072 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan);
5073 rtw89_set_channel(rtwdev);
5074
5075 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
5076 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
5077
5078 rtw89_phy_dig_suspend(rtwdev);
5079 ieee80211_ready_on_channel(hw);
5080 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work);
5081 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work,
5082 msecs_to_jiffies(rtwvif->roc.duration));
5083 }
5084
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)5085 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
5086 {
5087 struct ieee80211_hw *hw = rtwdev->hw;
5088 struct rtw89_roc *roc = &rtwvif->roc;
5089 struct rtw89_vif_link *rtwvif_link;
5090 struct rtw89_vif *tmp_vif;
5091 int ret;
5092
5093 lockdep_assert_wiphy(hw->wiphy);
5094
5095 ieee80211_remain_on_channel_expired(hw);
5096
5097 rtw89_leave_ips_by_hwflags(rtwdev);
5098 rtw89_leave_lps(rtwdev);
5099
5100 rtwvif_link = rtwvif->links[roc->link_id];
5101 if (unlikely(!rtwvif_link)) {
5102 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n",
5103 roc->link_id);
5104 return;
5105 }
5106
5107 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
5108
5109 roc->state = RTW89_ROC_IDLE;
5110 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL);
5111 rtw89_chanctx_proceed(rtwdev, NULL);
5112 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false,
5113 RTW89_ROC_TX_TIMEOUT);
5114 if (ret)
5115 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
5116 "roc send null-0 failed: %d\n", ret);
5117
5118 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
5119 tmp_vif->offchan = false;
5120
5121 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
5122 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
5123 rtw89_phy_dig_resume(rtwdev, true);
5124
5125 if (hw->conf.flags & IEEE80211_CONF_IDLE)
5126 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work,
5127 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
5128 }
5129
rtw89_roc_work(struct wiphy * wiphy,struct wiphy_work * work)5130 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work)
5131 {
5132 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
5133 roc.roc_work.work);
5134 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
5135 struct rtw89_roc *roc = &rtwvif->roc;
5136
5137 lockdep_assert_wiphy(wiphy);
5138
5139 switch (roc->state) {
5140 case RTW89_ROC_IDLE:
5141 rtw89_enter_ips_by_hwflags(rtwdev);
5142 break;
5143 case RTW89_ROC_MGMT:
5144 case RTW89_ROC_NORMAL:
5145 rtw89_roc_end(rtwdev, rtwvif);
5146 break;
5147 default:
5148 break;
5149 }
5150 }
5151
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt,enum rtw89_tfc_interval interval)5152 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
5153 u32 throughput, u64 cnt,
5154 enum rtw89_tfc_interval interval)
5155 {
5156 u64 cnt_level;
5157
5158 switch (interval) {
5159 default:
5160 case RTW89_TFC_INTERVAL_100MS:
5161 cnt_level = 5;
5162 break;
5163 case RTW89_TFC_INTERVAL_2SEC:
5164 cnt_level = 100;
5165 break;
5166 }
5167
5168 if (cnt < cnt_level)
5169 return RTW89_TFC_IDLE;
5170 if (throughput > 50)
5171 return RTW89_TFC_HIGH;
5172 if (throughput > 10)
5173 return RTW89_TFC_MID;
5174 if (throughput > 2)
5175 return RTW89_TFC_LOW;
5176 return RTW89_TFC_ULTRA_LOW;
5177 }
5178
rtw89_calc_vif_active_histogram(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,enum rtw89_tfc_interval interval)5179 static void rtw89_calc_vif_active_histogram(struct rtw89_dev *rtwdev,
5180 struct rtw89_traffic_stats *stats,
5181 enum rtw89_tfc_interval interval)
5182 {
5183 struct rtw89_vif *rtwvif;
5184
5185 stats->udp_ratio = stats->tx_cnt ?
5186 DIV_ROUND_DOWN_ULL(stats->udp * 100, stats->tx_cnt) : 0;
5187 stats->active_histogram <<= 1;
5188
5189 switch (interval) {
5190 case RTW89_TFC_INTERVAL_2SEC:
5191 rtwvif = container_of(stats, struct rtw89_vif, stats);
5192
5193 if (stats->tcp >= RTW89_TCP_TH && stats->tx_cnt >= stats->rx_cnt)
5194 stats->active_histogram |= BIT(0);
5195
5196 if (stats->active_histogram & RTW89_RECENT_ACTIVE_HIST)
5197 rtwvif->burst_active = true;
5198 else
5199 rtwvif->burst_active = false;
5200
5201 break;
5202 case RTW89_TFC_INTERVAL_100MS:
5203 if (stats->udp_ratio >= RTW89_UDP_RATIO_TH)
5204 stats->active_histogram |= BIT(0);
5205 break;
5206 }
5207
5208 stats->tcp = 0;
5209 stats->udp = 0;
5210 }
5211
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,enum rtw89_tfc_interval interval,bool by_vif)5212 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
5213 struct rtw89_traffic_stats *stats,
5214 enum rtw89_tfc_interval interval, bool by_vif)
5215 {
5216 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
5217 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
5218
5219 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval);
5220 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval);
5221
5222 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
5223 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
5224
5225 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
5226 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
5227 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
5228 stats->tx_cnt, interval);
5229 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
5230 stats->rx_cnt, interval);
5231 stats->tx_avg_len = stats->tx_cnt ?
5232 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
5233 stats->rx_avg_len = stats->rx_cnt ?
5234 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
5235
5236 if (by_vif)
5237 rtw89_calc_vif_active_histogram(rtwdev, stats, interval);
5238
5239 stats->tx_unicast = 0;
5240 stats->rx_unicast = 0;
5241 stats->tx_cnt = 0;
5242 stats->rx_cnt = 0;
5243 stats->rx_tf_periodic = stats->rx_tf_acc;
5244 stats->rx_tf_acc = 0;
5245
5246 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
5247 return true;
5248
5249 return false;
5250 }
5251
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)5252 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
5253 {
5254 struct rtw89_vif_link *rtwvif_link;
5255 struct rtw89_vif *rtwvif;
5256 unsigned int link_id;
5257 bool tfc_changed;
5258
5259 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats,
5260 RTW89_TFC_INTERVAL_2SEC, false);
5261
5262 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
5263 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats,
5264 RTW89_TFC_INTERVAL_2SEC, true);
5265
5266 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
5267 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
5268 }
5269
5270 return tfc_changed;
5271 }
5272
rtw89_enter_lps_track(struct rtw89_dev * rtwdev,enum rtw89_tfc_interval interval)5273 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev,
5274 enum rtw89_tfc_interval interval)
5275 {
5276 struct rtw89_hal *hal = &rtwdev->hal;
5277 struct ieee80211_vif *vif;
5278 struct rtw89_vif *rtwvif;
5279
5280 /*
5281 * If vcore level is set, temperature is high and voltage is low. As
5282 * entering power save must reset voltage to default, avoid power save
5283 * until vcore decreases to zero resulting from temperature becomes low.
5284 */
5285 if (hal->thermal_prot_vlv)
5286 return;
5287
5288 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
5289 if (rtwvif->tdls_peer)
5290 continue;
5291 if (rtwvif->offchan)
5292 continue;
5293
5294 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID ||
5295 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID)
5296 continue;
5297
5298 vif = rtwvif_to_vif(rtwvif);
5299
5300 if (!(vif->type == NL80211_IFTYPE_STATION ||
5301 vif->type == NL80211_IFTYPE_P2P_CLIENT))
5302 continue;
5303
5304 if (!rtw89_core_bcn_track_can_lps(rtwdev))
5305 continue;
5306
5307 if (!rtw89_core_proto_stats_can_lps(rtwdev, rtwvif, interval))
5308 continue;
5309
5310 rtw89_enter_lps(rtwdev, rtwvif, true);
5311 }
5312 }
5313
rtw89_core_rfk_tssi_record(struct rtw89_dev * rtwdev)5314 static void rtw89_core_rfk_tssi_record(struct rtw89_dev *rtwdev)
5315 {
5316 const struct rtw89_chip_info *chip = rtwdev->chip;
5317 u8 path_num = min(chip->rf_path_num, RTW89_RFK_RECORD_PATH_NR);
5318 struct rtw89_rfk_wait_info *info = &rtwdev->rfk_wait;
5319 int i = info->record_tssi_idx;
5320 u32 base;
5321 u32 mask;
5322 int path;
5323
5324 if (chip->chip_gen == RTW89_CHIP_AX)
5325 return;
5326
5327 info->record_tssi_idx = (info->record_tssi_idx + 1) %
5328 RTW89_RFK_RECORD_HISTORY_NR;
5329
5330 if (chip->chip_id == RTL8922A) {
5331 base = 0x2ee10;
5332 mask = 0x7fc00;
5333 } else {
5334 base = 0x2f918;
5335 mask = 0x000001ff;
5336 }
5337
5338 for (path = 0; path < path_num; path++) {
5339 u32 addr = base + 0x100 * path;
5340
5341 info->tssi_code[i][path] = rtw89_read32_mask(rtwdev, addr, mask);
5342 }
5343 }
5344
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)5345 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
5346 {
5347 enum rtw89_entity_mode mode;
5348
5349 mode = rtw89_get_entity_mode(rtwdev);
5350 if (mode == RTW89_ENTITY_MODE_MCC)
5351 return;
5352
5353 rtw89_chip_rfk_track(rtwdev);
5354
5355 rtw89_core_rfk_tssi_record(rtwdev);
5356 }
5357
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)5358 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
5359 struct rtw89_vif_link *rtwvif_link,
5360 struct ieee80211_bss_conf *bss_conf)
5361 {
5362 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
5363
5364 if (mode == RTW89_ENTITY_MODE_MCC)
5365 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
5366 else
5367 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
5368 }
5369
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)5370 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
5371 struct rtw89_traffic_stats *stats)
5372 {
5373 stats->tx_unicast = 0;
5374 stats->rx_unicast = 0;
5375 stats->tx_cnt = 0;
5376 stats->rx_cnt = 0;
5377 ewma_tp_init(&stats->tx_ewma_tp);
5378 ewma_tp_init(&stats->rx_ewma_tp);
5379 }
5380
5381 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53
5382 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38
rtw89_core_mlsr_link_decision(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)5383 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev,
5384 struct rtw89_vif *rtwvif)
5385 {
5386 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS;
5387 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
5388 u8 decided_bands = BIT(RTW89_BAND_NUM) - 1;
5389 struct rtw89_vif_link *rtwvif_link;
5390 const struct rtw89_chan *chan;
5391 unsigned long usable_links;
5392 struct rtw89_bb_ctx *bb;
5393 unsigned int link_id;
5394 u8 rssi;
5395
5396 usable_links = ieee80211_vif_usable_links(vif);
5397
5398 rtwvif_link = rtw89_get_designated_link(rtwvif);
5399 if (unlikely(!rtwvif_link))
5400 goto select;
5401
5402 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5403 rssi = ewma_rssi_read(&bb->bcn_rssi);
5404 if (unlikely(!rssi))
5405 return;
5406
5407 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD)
5408 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G);
5409 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD)
5410 decided_bands = BIT(RTW89_BAND_2G);
5411 else
5412 return;
5413
5414 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
5415 if (decided_bands & BIT(chan->band_type))
5416 return;
5417
5418 usable_links &= ~BIT(rtwvif_link->link_id);
5419
5420 select:
5421 rcu_read_lock();
5422
5423 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) {
5424 struct ieee80211_bss_conf *link_conf;
5425 struct ieee80211_channel *channel;
5426 enum rtw89_band band;
5427
5428 link_conf = rcu_dereference(vif->link_conf[link_id]);
5429 if (unlikely(!link_conf))
5430 continue;
5431
5432 channel = link_conf->chanreq.oper.chan;
5433 if (unlikely(!channel))
5434 continue;
5435
5436 band = rtw89_nl80211_to_hw_band(channel->band);
5437 if (decided_bands & BIT(band)) {
5438 sel_link_id = link_id;
5439 break;
5440 }
5441 }
5442
5443 rcu_read_unlock();
5444
5445 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS)
5446 return;
5447
5448 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id);
5449 }
5450
rtw89_core_mlo_track(struct rtw89_dev * rtwdev)5451 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev)
5452 {
5453 struct rtw89_hal *hal = &rtwdev->hal;
5454 struct ieee80211_vif *vif;
5455 struct rtw89_vif *rtwvif;
5456
5457 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO))
5458 return;
5459
5460 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
5461 vif = rtwvif_to_vif(rtwvif);
5462 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif))
5463 continue;
5464
5465 switch (rtwvif->mlo_mode) {
5466 case RTW89_MLO_MODE_MLSR:
5467 rtw89_core_mlsr_link_decision(rtwdev, rtwvif);
5468 break;
5469 default:
5470 break;
5471 }
5472 }
5473 }
5474
rtw89_track_ps_work(struct wiphy * wiphy,struct wiphy_work * work)5475 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work)
5476 {
5477 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
5478 track_ps_work.work);
5479 struct rtw89_vif *rtwvif;
5480
5481 lockdep_assert_wiphy(wiphy);
5482
5483 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
5484 return;
5485
5486 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
5487 return;
5488
5489 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work,
5490 RTW89_TRACK_PS_WORK_PERIOD);
5491
5492 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5493 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps,
5494 RTW89_TFC_INTERVAL_100MS, true);
5495
5496 if (rtwdev->scanning)
5497 return;
5498
5499 if (rtwdev->lps_enabled && !rtwdev->btc.btc_ctrl_lps)
5500 rtw89_enter_lps_track(rtwdev, RTW89_TFC_INTERVAL_100MS);
5501 }
5502
rtw89_track_work(struct wiphy * wiphy,struct wiphy_work * work)5503 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work)
5504 {
5505 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
5506 track_work.work);
5507 bool tfc_changed;
5508
5509 lockdep_assert_wiphy(wiphy);
5510
5511 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
5512 return;
5513
5514 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
5515 return;
5516
5517 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work,
5518 RTW89_TRACK_WORK_PERIOD);
5519
5520 tfc_changed = rtw89_traffic_stats_track(rtwdev);
5521 if (rtwdev->scanning)
5522 return;
5523
5524 rtw89_leave_lps(rtwdev);
5525
5526 if (tfc_changed) {
5527 rtw89_hci_recalc_int_mit(rtwdev);
5528 rtw89_btc_ntfy_wl_sta(rtwdev);
5529 }
5530 rtw89_mac_bf_monitor_track(rtwdev);
5531 rtw89_core_bcn_track(rtwdev);
5532 rtw89_phy_stat_track(rtwdev);
5533 rtw89_phy_env_monitor_track(rtwdev);
5534 rtw89_phy_dig(rtwdev);
5535 rtw89_core_rfk_track(rtwdev);
5536 rtw89_phy_ra_update(rtwdev);
5537 rtw89_phy_cfo_track(rtwdev);
5538 rtw89_phy_tx_path_div_track(rtwdev);
5539 rtw89_phy_antdiv_track(rtwdev);
5540 rtw89_phy_ul_tb_ctrl_track(rtwdev);
5541 rtw89_phy_edcca_track(rtwdev);
5542 rtw89_sar_track(rtwdev);
5543 rtw89_chanctx_track(rtwdev);
5544 rtw89_core_rfkill_poll(rtwdev, false);
5545 rtw89_core_mlo_track(rtwdev);
5546
5547 if (rtwdev->lps_enabled && !rtwdev->btc.btc_ctrl_lps)
5548 rtw89_enter_lps_track(rtwdev, RTW89_TFC_INTERVAL_2SEC);
5549 }
5550
rtw89_core_dm_disable_cfg(struct rtw89_dev * rtwdev,u32 new)5551 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new)
5552 {
5553 struct rtw89_hal *hal = &rtwdev->hal;
5554 u32 old = hal->disabled_dm_bitmap;
5555
5556 if (new == old)
5557 return;
5558
5559 hal->disabled_dm_bitmap = new;
5560
5561 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new);
5562 }
5563
rtw89_core_dm_disable_set(struct rtw89_dev * rtwdev,enum rtw89_dm_type type)5564 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
5565 {
5566 struct rtw89_hal *hal = &rtwdev->hal;
5567 u32 cur = hal->disabled_dm_bitmap;
5568
5569 rtw89_core_dm_disable_cfg(rtwdev, cur | BIT(type));
5570 }
5571
rtw89_core_dm_disable_clr(struct rtw89_dev * rtwdev,enum rtw89_dm_type type)5572 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type)
5573 {
5574 struct rtw89_hal *hal = &rtwdev->hal;
5575 u32 cur = hal->disabled_dm_bitmap;
5576
5577 rtw89_core_dm_disable_cfg(rtwdev, cur & ~BIT(type));
5578 }
5579
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)5580 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
5581 {
5582 unsigned long bit;
5583
5584 bit = find_first_zero_bit(addr, size);
5585 if (bit < size)
5586 set_bit(bit, addr);
5587
5588 return bit;
5589 }
5590
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)5591 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
5592 {
5593 clear_bit(bit, addr);
5594 }
5595
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)5596 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
5597 {
5598 bitmap_zero(addr, nbits);
5599 }
5600
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)5601 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
5602 struct rtw89_sta_link *rtwsta_link, u8 tid,
5603 u8 *cam_idx)
5604 {
5605 const struct rtw89_chip_info *chip = rtwdev->chip;
5606 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
5607 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
5608 u8 idx;
5609 int i;
5610
5611 lockdep_assert_wiphy(rtwdev->hw->wiphy);
5612
5613 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
5614 if (idx == chip->bacam_num) {
5615 /* allocate a static BA CAM to tid=0/5, so replace the existing
5616 * one if BA CAM is full. Hardware will process the original tid
5617 * automatically.
5618 */
5619 if (tid != 0 && tid != 5)
5620 return -ENOSPC;
5621
5622 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
5623 tmp = &cam_info->ba_cam_entry[i];
5624 if (tmp->tid == 0 || tmp->tid == 5)
5625 continue;
5626
5627 idx = i;
5628 entry = tmp;
5629 list_del(&entry->list);
5630 break;
5631 }
5632
5633 if (!entry)
5634 return -ENOSPC;
5635 } else {
5636 entry = &cam_info->ba_cam_entry[idx];
5637 }
5638
5639 entry->tid = tid;
5640 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
5641
5642 *cam_idx = idx;
5643
5644 return 0;
5645 }
5646
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)5647 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
5648 struct rtw89_sta_link *rtwsta_link, u8 tid,
5649 u8 *cam_idx)
5650 {
5651 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
5652 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
5653 u8 idx;
5654
5655 lockdep_assert_wiphy(rtwdev->hw->wiphy);
5656
5657 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
5658 if (entry->tid != tid)
5659 continue;
5660
5661 idx = entry - cam_info->ba_cam_entry;
5662 list_del(&entry->list);
5663
5664 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
5665 *cam_idx = idx;
5666 return 0;
5667 }
5668
5669 return -ENOENT;
5670 }
5671
5672 #define RTW89_TYPE_MAPPING(_type) \
5673 case NL80211_IFTYPE_ ## _type: \
5674 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
5675 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)5676 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
5677 {
5678 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5679 const struct ieee80211_bss_conf *bss_conf;
5680
5681 switch (vif->type) {
5682 case NL80211_IFTYPE_STATION:
5683 if (vif->p2p)
5684 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
5685 else
5686 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
5687 break;
5688 case NL80211_IFTYPE_AP:
5689 if (vif->p2p)
5690 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
5691 else
5692 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
5693 break;
5694 RTW89_TYPE_MAPPING(ADHOC);
5695 RTW89_TYPE_MAPPING(MONITOR);
5696 RTW89_TYPE_MAPPING(MESH_POINT);
5697 default:
5698 WARN_ON(1);
5699 break;
5700 }
5701
5702 switch (vif->type) {
5703 case NL80211_IFTYPE_AP:
5704 case NL80211_IFTYPE_MESH_POINT:
5705 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
5706 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
5707 break;
5708 case NL80211_IFTYPE_ADHOC:
5709 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
5710 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
5711 break;
5712 case NL80211_IFTYPE_STATION:
5713 if (assoc) {
5714 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
5715
5716 rcu_read_lock();
5717 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
5718 rtwvif_link->trigger = bss_conf->he_support;
5719 rcu_read_unlock();
5720 } else {
5721 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
5722 rtwvif_link->trigger = false;
5723 }
5724 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
5725 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
5726 break;
5727 case NL80211_IFTYPE_MONITOR:
5728 break;
5729 default:
5730 WARN_ON(1);
5731 break;
5732 }
5733 }
5734
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5735 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
5736 struct rtw89_vif_link *rtwvif_link,
5737 struct rtw89_sta_link *rtwsta_link)
5738 {
5739 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5740 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5741 struct rtw89_hal *hal = &rtwdev->hal;
5742 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
5743 int i;
5744 int ret;
5745
5746 rtwsta_link->prev_rssi = 0;
5747 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
5748 ewma_rssi_init(&rtwsta_link->avg_rssi);
5749 ewma_snr_init(&rtwsta_link->avg_snr);
5750 ewma_evm_init(&rtwsta_link->evm_1ss);
5751 for (i = 0; i < ant_num; i++) {
5752 ewma_rssi_init(&rtwsta_link->rssi[i]);
5753 ewma_evm_init(&rtwsta_link->evm_min[i]);
5754 ewma_evm_init(&rtwsta_link->evm_max[i]);
5755 }
5756
5757 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5758 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
5759 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
5760 if (ret)
5761 return ret;
5762
5763 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5764 BTC_ROLE_MSTS_STA_CONN_START);
5765 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
5766
5767 if (vif->p2p) {
5768 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link,
5769 &rtwsta_link->tx_retry);
5770 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60);
5771 }
5772 rtw89_phy_dig_suspend(rtwdev);
5773 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5774 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
5775 if (ret) {
5776 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
5777 return ret;
5778 }
5779
5780 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
5781 RTW89_ROLE_CREATE);
5782 if (ret) {
5783 rtw89_warn(rtwdev, "failed to send h2c role info\n");
5784 return ret;
5785 }
5786
5787 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5788 if (ret)
5789 return ret;
5790
5791 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5792 if (ret)
5793 return ret;
5794 }
5795
5796 return 0;
5797 }
5798
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5799 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
5800 struct rtw89_vif_link *rtwvif_link,
5801 struct rtw89_sta_link *rtwsta_link)
5802 {
5803 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5804
5805 rtw89_assoc_link_clr(rtwsta_link);
5806
5807 if (vif->type == NL80211_IFTYPE_STATION) {
5808 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
5809 rtw89_core_bcn_track_reset(rtwdev);
5810 }
5811
5812 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
5813 rtw89_p2p_noa_once_deinit(rtwvif_link);
5814
5815 return 0;
5816 }
5817
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5818 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
5819 struct rtw89_vif_link *rtwvif_link,
5820 struct rtw89_sta_link *rtwsta_link)
5821 {
5822 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5823 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5824 int ret;
5825
5826 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
5827 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
5828
5829 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
5830 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
5831 if (sta->tdls)
5832 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
5833
5834 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5835 rtw89_vif_type_mapping(rtwvif_link, false);
5836 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
5837 }
5838
5839 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5840 if (ret) {
5841 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
5842 return ret;
5843 }
5844
5845 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
5846 if (ret) {
5847 rtw89_warn(rtwdev, "failed to send h2c join info\n");
5848 return ret;
5849 }
5850
5851 /* update cam aid mac_id net_type */
5852 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
5853 RTW89_ROLE_CON_DISCONN);
5854 if (ret) {
5855 rtw89_warn(rtwdev, "failed to send h2c cam\n");
5856 return ret;
5857 }
5858
5859 return ret;
5860 }
5861
rtw89_sta_link_can_er(struct rtw89_dev * rtwdev,struct ieee80211_bss_conf * bss_conf,struct ieee80211_link_sta * link_sta)5862 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev,
5863 struct ieee80211_bss_conf *bss_conf,
5864 struct ieee80211_link_sta *link_sta)
5865 {
5866 if (!bss_conf->he_support ||
5867 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)
5868 return false;
5869
5870 if (rtwdev->chip->chip_id == RTL8852C &&
5871 rtw89_sta_link_has_su_mu_4xhe08(link_sta) &&
5872 !rtw89_sta_link_has_er_su_4xhe08(link_sta))
5873 return false;
5874
5875 return true;
5876 }
5877
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5878 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
5879 struct rtw89_vif_link *rtwvif_link,
5880 struct rtw89_sta_link *rtwsta_link)
5881 {
5882 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5883 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5884 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
5885 rtwsta_link);
5886 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
5887 rtwvif_link->chanctx_idx);
5888 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5889 struct ieee80211_link_sta *link_sta;
5890 int ret;
5891
5892 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5893 if (sta->tdls) {
5894 rcu_read_lock();
5895
5896 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5897 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
5898 link_sta->addr);
5899 if (ret) {
5900 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
5901 rcu_read_unlock();
5902 return ret;
5903 }
5904
5905 rcu_read_unlock();
5906 }
5907
5908 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
5909 if (ret) {
5910 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
5911 return ret;
5912 }
5913 }
5914
5915 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5916 if (ret) {
5917 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
5918 return ret;
5919 }
5920
5921 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
5922 if (ret) {
5923 rtw89_warn(rtwdev, "failed to send h2c join info\n");
5924 return ret;
5925 }
5926
5927 /* update cam aid mac_id net_type */
5928 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
5929 RTW89_ROLE_CON_DISCONN);
5930 if (ret) {
5931 rtw89_warn(rtwdev, "failed to send h2c cam\n");
5932 return ret;
5933 }
5934
5935 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
5936 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
5937 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
5938
5939 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5940 struct ieee80211_bss_conf *bss_conf;
5941 u8 link_mode = 0;
5942
5943 rcu_read_lock();
5944
5945 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5946 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5947 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta);
5948
5949 if (link_sta->he_cap.has_he || link_sta->eht_cap.has_eht)
5950 link_mode = 2;
5951 else if (link_sta->vht_cap.vht_supported)
5952 link_mode = 1;
5953 bb->path_diff.link_mode = link_mode;
5954
5955 rcu_read_unlock();
5956
5957 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5958 BTC_ROLE_MSTS_STA_CONN_END);
5959 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
5960 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
5961 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link);
5962
5963 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
5964 if (ret) {
5965 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
5966 return ret;
5967 }
5968
5969 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5970
5971 if (vif->p2p)
5972 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5973 rtwsta_link->tx_retry);
5974 rtw89_phy_dig_resume(rtwdev, false);
5975 }
5976
5977 rtw89_assoc_link_set(rtwsta_link);
5978 return ret;
5979 }
5980
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5981 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
5982 struct rtw89_vif_link *rtwvif_link,
5983 struct rtw89_sta_link *rtwsta_link)
5984 {
5985 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5986 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5987 int ret;
5988
5989 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5990 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
5991 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5992 BTC_ROLE_MSTS_STA_DIS_CONN);
5993
5994 if (vif->p2p)
5995 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5996 rtwsta_link->tx_retry);
5997 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5998 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
5999 RTW89_ROLE_REMOVE);
6000 if (ret) {
6001 rtw89_warn(rtwdev, "failed to send h2c role info\n");
6002 return ret;
6003 }
6004 }
6005
6006 return 0;
6007 }
6008
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)6009 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6010 struct ieee80211_sta *sta,
6011 struct cfg80211_tid_cfg *tid_conf)
6012 {
6013 struct ieee80211_txq *txq;
6014 struct rtw89_txq *rtwtxq;
6015 u32 mask = tid_conf->mask;
6016 u8 tids = tid_conf->tids;
6017 int tids_nbit = BITS_PER_BYTE;
6018 int i;
6019
6020 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
6021 if (!tids)
6022 break;
6023
6024 if (!(tids & BIT(0)))
6025 continue;
6026
6027 txq = sta->txq[i];
6028 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6029
6030 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
6031 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
6032 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
6033 } else {
6034 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
6035 ieee80211_stop_tx_ba_session(sta, txq->tid);
6036 spin_lock_bh(&rtwdev->ba_lock);
6037 list_del_init(&rtwtxq->list);
6038 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
6039 spin_unlock_bh(&rtwdev->ba_lock);
6040 }
6041 }
6042
6043 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
6044 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
6045 sta->max_amsdu_subframes = 0;
6046 else
6047 sta->max_amsdu_subframes = 1;
6048 }
6049 }
6050 }
6051
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)6052 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6053 struct ieee80211_sta *sta,
6054 struct cfg80211_tid_config *tid_config)
6055 {
6056 int i;
6057
6058 for (i = 0; i < tid_config->n_tid_conf; i++)
6059 _rtw89_core_set_tid_config(rtwdev, sta,
6060 &tid_config->tid_conf[i]);
6061 }
6062
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)6063 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
6064 struct ieee80211_sta_ht_cap *ht_cap)
6065 {
6066 static const __le16 highest[RF_PATH_MAX] = {
6067 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
6068 };
6069 struct rtw89_hal *hal = &rtwdev->hal;
6070 u8 nss = hal->rx_nss;
6071 int i;
6072
6073 ht_cap->ht_supported = true;
6074 ht_cap->cap = 0;
6075 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
6076 IEEE80211_HT_CAP_MAX_AMSDU |
6077 IEEE80211_HT_CAP_TX_STBC |
6078 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
6079 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
6080 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
6081 IEEE80211_HT_CAP_DSSSCCK40 |
6082 IEEE80211_HT_CAP_SGI_40;
6083 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6084 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
6085 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6086 for (i = 0; i < nss; i++)
6087 ht_cap->mcs.rx_mask[i] = 0xFF;
6088 ht_cap->mcs.rx_mask[4] = 0x01;
6089 ht_cap->mcs.rx_highest = highest[nss - 1];
6090 }
6091
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)6092 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
6093 struct ieee80211_sta_vht_cap *vht_cap)
6094 {
6095 static const __le16 highest_bw80[RF_PATH_MAX] = {
6096 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
6097 };
6098 static const __le16 highest_bw160[RF_PATH_MAX] = {
6099 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
6100 };
6101 const struct rtw89_chip_info *chip = rtwdev->chip;
6102 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
6103 highest_bw160 : highest_bw80;
6104 struct rtw89_hal *hal = &rtwdev->hal;
6105 u16 tx_mcs_map = 0, rx_mcs_map = 0;
6106 u8 sts_cap = 3;
6107 int i;
6108
6109 for (i = 0; i < 8; i++) {
6110 if (i < hal->tx_nss)
6111 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
6112 else
6113 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
6114 if (i < hal->rx_nss)
6115 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
6116 else
6117 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
6118 }
6119
6120 vht_cap->vht_supported = true;
6121 vht_cap->cap = chip->max_vht_mpdu_cap |
6122 IEEE80211_VHT_CAP_SHORT_GI_80 |
6123 IEEE80211_VHT_CAP_RXSTBC_1 |
6124 IEEE80211_VHT_CAP_HTC_VHT |
6125 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
6126 0;
6127 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
6128 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
6129 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
6130 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
6131 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
6132 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6133 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
6134 IEEE80211_VHT_CAP_SHORT_GI_160;
6135 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
6136 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
6137 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
6138 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
6139
6140 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
6141 vht_cap->vht_mcs.tx_highest |=
6142 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
6143 }
6144
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)6145 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
6146 enum nl80211_band band,
6147 enum nl80211_iftype iftype,
6148 struct ieee80211_sband_iftype_data *iftype_data)
6149 {
6150 const struct rtw89_chip_info *chip = rtwdev->chip;
6151 struct rtw89_hal *hal = &rtwdev->hal;
6152 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
6153 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
6154 struct ieee80211_sta_he_cap *he_cap;
6155 int nss = hal->rx_nss;
6156 u8 *mac_cap_info;
6157 u8 *phy_cap_info;
6158 u16 mcs_map = 0;
6159 int i;
6160
6161 for (i = 0; i < 8; i++) {
6162 if (i < nss)
6163 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
6164 else
6165 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
6166 }
6167
6168 he_cap = &iftype_data->he_cap;
6169 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
6170 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
6171
6172 he_cap->has_he = true;
6173 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
6174 if (iftype == NL80211_IFTYPE_STATION)
6175 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
6176 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
6177 IEEE80211_HE_MAC_CAP2_BSR;
6178 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
6179 if (iftype == NL80211_IFTYPE_AP)
6180 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
6181 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
6182 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
6183 if (iftype == NL80211_IFTYPE_STATION)
6184 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
6185 if (band == NL80211_BAND_2GHZ) {
6186 phy_cap_info[0] =
6187 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
6188 } else {
6189 phy_cap_info[0] =
6190 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
6191 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6192 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
6193 }
6194 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
6195 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
6196 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
6197 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
6198 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
6199 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
6200 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
6201 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
6202 if (iftype == NL80211_IFTYPE_STATION)
6203 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
6204 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
6205 if (iftype == NL80211_IFTYPE_AP)
6206 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
6207 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
6208 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
6209 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6210 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
6211 phy_cap_info[5] = no_ng16 ? 0 :
6212 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
6213 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
6214 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
6215 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
6216 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
6217 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
6218 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
6219 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
6220 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
6221 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
6222 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
6223 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
6224 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6225 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
6226 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
6227 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
6228 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
6229 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
6230 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
6231 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
6232 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
6233 if (iftype == NL80211_IFTYPE_STATION)
6234 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
6235 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
6236 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
6237 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
6238 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
6239 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
6240 }
6241
6242 if (band == NL80211_BAND_6GHZ) {
6243 __le16 capa;
6244
6245 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
6246 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
6247 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
6248 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
6249 le16_encode_bits(chip->max_vht_mpdu_cap,
6250 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
6251 iftype_data->he_6ghz_capa.capa = capa;
6252 }
6253 }
6254
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)6255 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
6256 enum nl80211_band band,
6257 enum nl80211_iftype iftype,
6258 struct ieee80211_sband_iftype_data *iftype_data)
6259 {
6260 const struct rtw89_chip_info *chip = rtwdev->chip;
6261 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
6262 struct ieee80211_eht_mcs_nss_supp *eht_nss;
6263 struct ieee80211_sta_eht_cap *eht_cap;
6264 struct rtw89_hal *hal = &rtwdev->hal;
6265 bool support_mcs_12_13 = true;
6266 bool support_320mhz = false;
6267 u8 val, val_mcs13;
6268 int sts = 8;
6269
6270 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht)
6271 return;
6272
6273 if (hal->no_mcs_12_13)
6274 support_mcs_12_13 = false;
6275
6276 if (band == NL80211_BAND_6GHZ &&
6277 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
6278 support_320mhz = true;
6279
6280 eht_cap = &iftype_data->eht_cap;
6281 eht_cap_elem = &eht_cap->eht_cap_elem;
6282 eht_nss = &eht_cap->eht_mcs_nss_supp;
6283
6284 eht_cap->has_eht = true;
6285
6286 eht_cap_elem->mac_cap_info[0] =
6287 u8_encode_bits(chip->max_eht_mpdu_cap,
6288 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
6289 eht_cap_elem->mac_cap_info[1] = 0;
6290
6291 eht_cap_elem->phy_cap_info[0] =
6292 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
6293 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
6294 if (support_320mhz)
6295 eht_cap_elem->phy_cap_info[0] |=
6296 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
6297
6298 eht_cap_elem->phy_cap_info[0] |=
6299 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
6300 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
6301 eht_cap_elem->phy_cap_info[1] =
6302 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
6303 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
6304 u8_encode_bits(sts - 1,
6305 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
6306 if (support_320mhz)
6307 eht_cap_elem->phy_cap_info[1] |=
6308 u8_encode_bits(sts - 1,
6309 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
6310
6311 eht_cap_elem->phy_cap_info[2] = 0;
6312
6313 eht_cap_elem->phy_cap_info[3] =
6314 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
6315 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
6316 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
6317 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
6318
6319 eht_cap_elem->phy_cap_info[4] =
6320 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
6321 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
6322
6323 eht_cap_elem->phy_cap_info[5] =
6324 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
6325 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
6326
6327 eht_cap_elem->phy_cap_info[6] = 0;
6328 eht_cap_elem->phy_cap_info[7] = 0;
6329 eht_cap_elem->phy_cap_info[8] = 0;
6330
6331 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
6332 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
6333 val_mcs13 = support_mcs_12_13 ? val : 0;
6334
6335 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
6336 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
6337 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13;
6338 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
6339 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
6340 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13;
6341 if (support_320mhz) {
6342 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
6343 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
6344 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13;
6345 }
6346 }
6347
6348 #define RTW89_SBAND_IFTYPES_NR 2
6349
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)6350 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
6351 enum nl80211_band band,
6352 struct ieee80211_supported_band *sband)
6353 {
6354 struct ieee80211_sband_iftype_data *iftype_data;
6355 enum nl80211_iftype iftype;
6356 int idx = 0;
6357
6358 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR,
6359 sizeof(*iftype_data), GFP_KERNEL);
6360 if (!iftype_data)
6361 return -ENOMEM;
6362
6363 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
6364 switch (iftype) {
6365 case NL80211_IFTYPE_STATION:
6366 case NL80211_IFTYPE_AP:
6367 break;
6368 default:
6369 continue;
6370 }
6371
6372 if (idx >= RTW89_SBAND_IFTYPES_NR) {
6373 rtw89_warn(rtwdev, "run out of iftype_data\n");
6374 break;
6375 }
6376
6377 iftype_data[idx].types_mask = BIT(iftype);
6378
6379 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
6380 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
6381
6382 idx++;
6383 }
6384
6385 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
6386 return 0;
6387 }
6388
6389 static struct ieee80211_supported_band *
rtw89_core_sband_dup(struct rtw89_dev * rtwdev,const struct ieee80211_supported_band * sband)6390 rtw89_core_sband_dup(struct rtw89_dev *rtwdev,
6391 const struct ieee80211_supported_band *sband)
6392 {
6393 struct ieee80211_supported_band *dup;
6394
6395 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
6396 if (!dup)
6397 return NULL;
6398
6399 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels,
6400 sizeof(*sband->channels) * sband->n_channels,
6401 GFP_KERNEL);
6402 if (!dup->channels)
6403 return NULL;
6404
6405 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates,
6406 sizeof(*sband->bitrates) * sband->n_bitrates,
6407 GFP_KERNEL);
6408 if (!dup->bitrates)
6409 return NULL;
6410
6411 return dup;
6412 }
6413
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)6414 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
6415 {
6416 struct ieee80211_hw *hw = rtwdev->hw;
6417 struct ieee80211_supported_band *sband;
6418 u8 support_bands = rtwdev->chip->support_bands;
6419 int ret;
6420
6421 if (test_bit(RTW89_QUIRK_DISABLE_2GHZ, rtwdev->quirks))
6422 support_bands &= ~BIT(NL80211_BAND_2GHZ);
6423
6424 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
6425 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz);
6426 if (!sband)
6427 return -ENOMEM;
6428 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
6429 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband);
6430 if (ret)
6431 return ret;
6432 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6433 }
6434
6435 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
6436 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz);
6437 if (!sband)
6438 return -ENOMEM;
6439 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
6440 rtw89_init_vht_cap(rtwdev, &sband->vht_cap);
6441 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband);
6442 if (ret)
6443 return ret;
6444 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
6445 }
6446
6447 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
6448 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz);
6449 if (!sband)
6450 return -ENOMEM;
6451 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband);
6452 if (ret)
6453 return ret;
6454 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband;
6455 }
6456
6457 return 0;
6458 }
6459
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)6460 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
6461 {
6462 int i;
6463
6464 for (i = 0; i < RTW89_PHY_NUM; i++)
6465 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
6466 for (i = 0; i < RTW89_PHY_NUM; i++)
6467 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
6468 }
6469
rtw89_core_update_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)6470 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
6471 {
6472 struct rtw89_dev *rtwdev;
6473 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
6474 update_beacon_work);
6475
6476 lockdep_assert_wiphy(wiphy);
6477
6478 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
6479 return;
6480
6481 rtwdev = rtwvif_link->rtwvif->rtwdev;
6482
6483 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
6484 }
6485
rtw89_core_csa_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)6486 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
6487 {
6488 struct rtw89_vif_link *rtwvif_link =
6489 container_of(work, struct rtw89_vif_link, csa_beacon_work.work);
6490 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6491 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6492 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
6493 struct ieee80211_bss_conf *bss_conf;
6494 unsigned int delay;
6495
6496 lockdep_assert_wiphy(wiphy);
6497
6498 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
6499 return;
6500
6501 rcu_read_lock();
6502
6503 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6504 if (!bss_conf->csa_active) {
6505 rcu_read_unlock();
6506 return;
6507 }
6508
6509 delay = ieee80211_tu_to_usec(bss_conf->beacon_int);
6510
6511 rcu_read_unlock();
6512
6513 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) {
6514 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
6515
6516 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work,
6517 usecs_to_jiffies(delay));
6518 } else {
6519 ieee80211_csa_finish(vif, rtwvif_link->link_id);
6520 }
6521 }
6522
6523 struct rtw89_wait_response *
rtw89_wait_for_cond_prep(struct rtw89_wait_info * wait,unsigned int cond)6524 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
6525 {
6526 struct rtw89_wait_response *prep;
6527 unsigned int cur;
6528
6529 /* use -EPERM _iff_ telling eval side not to make any changes */
6530
6531 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
6532 if (cur != RTW89_WAIT_COND_IDLE)
6533 return ERR_PTR(-EPERM);
6534
6535 prep = kzalloc_obj(*prep);
6536 if (!prep)
6537 return ERR_PTR(-ENOMEM);
6538
6539 init_completion(&prep->completion);
6540
6541 rcu_assign_pointer(wait->resp, prep);
6542
6543 return prep;
6544 }
6545
rtw89_wait_for_cond_eval(struct rtw89_wait_info * wait,struct rtw89_wait_response * prep,int err)6546 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
6547 struct rtw89_wait_response *prep, int err)
6548 {
6549 unsigned long time_left;
6550
6551 if (IS_ERR(prep)) {
6552 err = err ?: PTR_ERR(prep);
6553
6554 /* special error case: no permission to reset anything */
6555 if (PTR_ERR(prep) == -EPERM)
6556 return err;
6557
6558 goto reset;
6559 }
6560
6561 if (err)
6562 goto cleanup;
6563
6564 time_left = wait_for_completion_timeout(&prep->completion,
6565 RTW89_WAIT_FOR_COND_TIMEOUT);
6566 if (time_left == 0) {
6567 err = -ETIMEDOUT;
6568 goto cleanup;
6569 }
6570
6571 wait->data = prep->data;
6572
6573 cleanup:
6574 rcu_assign_pointer(wait->resp, NULL);
6575 kfree_rcu(prep, rcu_head);
6576
6577 reset:
6578 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
6579
6580 if (err)
6581 return err;
6582
6583 if (wait->data.err)
6584 return -EFAULT;
6585
6586 return 0;
6587 }
6588
rtw89_complete_cond_resp(struct rtw89_wait_response * resp,const struct rtw89_completion_data * data)6589 static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp,
6590 const struct rtw89_completion_data *data)
6591 {
6592 resp->data = *data;
6593 complete(&resp->completion);
6594 }
6595
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)6596 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6597 const struct rtw89_completion_data *data)
6598 {
6599 struct rtw89_wait_response *resp;
6600 unsigned int cur;
6601
6602 guard(rcu)();
6603
6604 resp = rcu_dereference(wait->resp);
6605 if (!resp)
6606 return;
6607
6608 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
6609 if (cur != cond)
6610 return;
6611
6612 rtw89_complete_cond_resp(resp, data);
6613 }
6614
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event,enum rtw89_phy_idx phy_idx)6615 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev,
6616 enum rtw89_btc_hmsg event,
6617 enum rtw89_phy_idx phy_idx)
6618 {
6619 u16 bt_slot_req[RTW89_PHY_NUM];
6620
6621 switch (event) {
6622 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
6623 bt_slot_req[phy_idx] = rtw89_coex_query_bt_req_len(rtwdev, phy_idx);
6624 rtw89_debug(rtwdev, RTW89_DBG_BTC,
6625 "coex updates PHY-%d BT req len to %d TU\n",
6626 phy_idx, bt_slot_req[phy_idx]);
6627 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
6628 break;
6629 default:
6630 if (event < NUM_OF_RTW89_BTC_HMSG)
6631 rtw89_debug(rtwdev, RTW89_DBG_BTC,
6632 "unhandled BTC HMSG event: %d\n", event);
6633 else
6634 rtw89_warn(rtwdev,
6635 "unrecognized BTC HMSG event: %d\n", event);
6636 break;
6637 }
6638 }
6639
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)6640 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
6641 {
6642 const struct dmi_system_id *match;
6643 enum rtw89_quirks quirk;
6644
6645 if (!quirks)
6646 return;
6647
6648 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
6649 quirk = (uintptr_t)match->driver_data;
6650 if (quirk >= NUM_OF_RTW89_QUIRKS)
6651 continue;
6652
6653 set_bit(quirk, rtwdev->quirks);
6654 }
6655 }
6656 EXPORT_SYMBOL(rtw89_check_quirks);
6657
rtw89_core_start(struct rtw89_dev * rtwdev)6658 int rtw89_core_start(struct rtw89_dev *rtwdev)
6659 {
6660 bool no_bbmcu = !rtwdev->chip->bbmcu_nr;
6661 int ret;
6662
6663 ret = rtw89_mac_preinit(rtwdev);
6664 if (ret) {
6665 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret);
6666 return ret;
6667 }
6668
6669 if (no_bbmcu)
6670 rtw89_chip_bb_preinit(rtwdev);
6671
6672 rtw89_phy_init_bb_afe(rtwdev);
6673
6674 /* above do preinit before downloading firmware */
6675
6676 ret = rtw89_mac_init(rtwdev);
6677 if (ret) {
6678 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
6679 return ret;
6680 }
6681
6682 rtw89_btc_ntfy_poweron(rtwdev);
6683
6684 /* efuse process */
6685
6686 /* pre-config BB/RF, BB reset/RFC reset */
6687 ret = rtw89_chip_reset_bb_rf(rtwdev);
6688 if (ret)
6689 return ret;
6690
6691 rtw89_phy_init_bb_reg(rtwdev);
6692 rtw89_chip_bb_postinit(rtwdev);
6693 rtw89_phy_init_rf_reg(rtwdev, false);
6694
6695 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
6696
6697 rtw89_phy_dm_init(rtwdev);
6698
6699 rtw89_mac_set_edcca_mode_bands(rtwdev, true);
6700 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
6701 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
6702 rtw89_mac_update_rts_threshold(rtwdev);
6703
6704 ret = rtw89_hci_start(rtwdev);
6705 if (ret) {
6706 rtw89_err(rtwdev, "failed to start hci\n");
6707 return ret;
6708 }
6709
6710 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work,
6711 RTW89_TRACK_WORK_PERIOD);
6712 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work,
6713 RTW89_TRACK_PS_WORK_PERIOD);
6714
6715 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
6716
6717 rtw89_chip_rfk_init_late(rtwdev);
6718 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
6719 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
6720 rtw89_fw_h2c_init_ba_cam(rtwdev);
6721 rtw89_tas_fw_timer_enable(rtwdev, true);
6722 rtwdev->ps_hang_cnt = 0;
6723
6724 return 0;
6725 }
6726
rtw89_core_stop(struct rtw89_dev * rtwdev)6727 void rtw89_core_stop(struct rtw89_dev *rtwdev)
6728 {
6729 struct wiphy *wiphy = rtwdev->hw->wiphy;
6730 struct rtw89_btc *btc = &rtwdev->btc;
6731
6732 lockdep_assert_wiphy(wiphy);
6733
6734 /* Prvent to stop twice; enter_ips and ops_stop */
6735 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
6736 return;
6737
6738 rtw89_tas_fw_timer_enable(rtwdev, false);
6739 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
6740
6741 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
6742
6743 wiphy_work_cancel(wiphy, &rtwdev->c2h_work);
6744 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work);
6745 wiphy_work_cancel(wiphy, &btc->eapol_notify_work);
6746 wiphy_work_cancel(wiphy, &btc->arp_notify_work);
6747 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work);
6748 wiphy_work_cancel(wiphy, &btc->icmp_notify_work);
6749 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
6750 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work);
6751 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work);
6752 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work);
6753 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work);
6754 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work);
6755 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work);
6756 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work);
6757 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work);
6758 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work);
6759 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
6760 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work);
6761
6762 rtw89_btc_ntfy_poweroff(rtwdev);
6763 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
6764 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
6765 rtw89_hci_stop(rtwdev);
6766 rtw89_hci_deinit(rtwdev);
6767 rtw89_mac_pwr_off(rtwdev);
6768 rtw89_hci_reset(rtwdev);
6769 }
6770
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)6771 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
6772 {
6773 const struct rtw89_chip_info *chip = rtwdev->chip;
6774 u8 mac_id_num;
6775 u8 mac_id;
6776
6777 if (rtwdev->support_mlo)
6778 mac_id_num = chip->support_macid_num / chip->support_link_num;
6779 else
6780 mac_id_num = chip->support_macid_num;
6781
6782 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
6783 if (mac_id == mac_id_num)
6784 return RTW89_MAX_MAC_ID_NUM;
6785
6786 set_bit(mac_id, rtwdev->mac_id_map);
6787 return mac_id;
6788 }
6789
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)6790 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
6791 {
6792 clear_bit(mac_id, rtwdev->mac_id_map);
6793 }
6794
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)6795 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6796 u8 mac_id, u8 port)
6797 {
6798 const struct rtw89_chip_info *chip = rtwdev->chip;
6799 u8 support_link_num = chip->support_link_num;
6800 u8 support_mld_num = 0;
6801 unsigned int link_id;
6802 u8 index;
6803
6804 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6805 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
6806 rtwvif->links[link_id] = NULL;
6807
6808 rtwvif->rtwdev = rtwdev;
6809
6810 if (rtwdev->support_mlo) {
6811 rtwvif->links_inst_valid_num = support_link_num;
6812 support_mld_num = chip->support_macid_num / support_link_num;
6813 } else {
6814 rtwvif->links_inst_valid_num = 1;
6815 }
6816
6817 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
6818 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
6819
6820 inst->rtwvif = rtwvif;
6821 inst->mac_id = mac_id + index * support_mld_num;
6822 inst->mac_idx = RTW89_MAC_0 + index;
6823 inst->phy_idx = RTW89_PHY_0 + index;
6824
6825 /* multi-link use the same port id on different HW bands */
6826 inst->port = port;
6827 }
6828 }
6829
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)6830 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6831 struct rtw89_sta *rtwsta, u8 mac_id)
6832 {
6833 const struct rtw89_chip_info *chip = rtwdev->chip;
6834 u8 support_link_num = chip->support_link_num;
6835 u8 support_mld_num = 0;
6836 unsigned int link_id;
6837 u8 index;
6838
6839 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6840 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
6841 rtwsta->links[link_id] = NULL;
6842
6843 rtwsta->rtwdev = rtwdev;
6844 rtwsta->rtwvif = rtwvif;
6845
6846 if (rtwdev->support_mlo) {
6847 rtwsta->links_inst_valid_num = support_link_num;
6848 support_mld_num = chip->support_macid_num / support_link_num;
6849 } else {
6850 rtwsta->links_inst_valid_num = 1;
6851 }
6852
6853 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
6854 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
6855
6856 inst->rtwvif_link = &rtwvif->links_inst[index];
6857
6858 inst->rtwsta = rtwsta;
6859 inst->mac_id = mac_id + index * support_mld_num;
6860 }
6861 }
6862
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)6863 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
6864 unsigned int link_id)
6865 {
6866 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
6867 u8 index;
6868 int ret;
6869
6870 if (rtwvif_link)
6871 return rtwvif_link;
6872
6873 index = find_first_zero_bit(rtwvif->links_inst_map,
6874 rtwvif->links_inst_valid_num);
6875 if (index == rtwvif->links_inst_valid_num) {
6876 ret = -EBUSY;
6877 goto err;
6878 }
6879
6880 rtwvif_link = &rtwvif->links_inst[index];
6881 rtwvif_link->link_id = link_id;
6882
6883 set_bit(index, rtwvif->links_inst_map);
6884 rtwvif->links[link_id] = rtwvif_link;
6885 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool);
6886 return rtwvif_link;
6887
6888 err:
6889 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
6890 link_id, ret);
6891 return NULL;
6892 }
6893
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)6894 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
6895 {
6896 struct rtw89_vif_link **container = &rtwvif->links[link_id];
6897 struct rtw89_vif_link *link = *container;
6898 u8 index;
6899
6900 if (!link)
6901 return;
6902
6903 index = rtw89_vif_link_inst_get_index(link);
6904 clear_bit(index, rtwvif->links_inst_map);
6905 *container = NULL;
6906 list_del(&link->dlink_schd);
6907 }
6908
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)6909 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
6910 unsigned int link_id)
6911 {
6912 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6913 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
6914 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
6915 u8 index;
6916 int ret;
6917
6918 if (rtwsta_link)
6919 return rtwsta_link;
6920
6921 if (!rtwvif_link) {
6922 ret = -ENOLINK;
6923 goto err;
6924 }
6925
6926 index = rtw89_vif_link_inst_get_index(rtwvif_link);
6927 if (test_bit(index, rtwsta->links_inst_map)) {
6928 ret = -EBUSY;
6929 goto err;
6930 }
6931
6932 rtwsta_link = &rtwsta->links_inst[index];
6933 rtwsta_link->link_id = link_id;
6934
6935 set_bit(index, rtwsta->links_inst_map);
6936 rtwsta->links[link_id] = rtwsta_link;
6937 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool);
6938 return rtwsta_link;
6939
6940 err:
6941 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
6942 link_id, ret);
6943 return NULL;
6944 }
6945
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)6946 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
6947 {
6948 struct rtw89_sta_link **container = &rtwsta->links[link_id];
6949 struct rtw89_sta_link *link = *container;
6950 u8 index;
6951
6952 if (!link)
6953 return;
6954
6955 index = rtw89_sta_link_inst_get_index(link);
6956 clear_bit(index, rtwsta->links_inst_map);
6957 *container = NULL;
6958 list_del(&link->dlink_schd);
6959 }
6960
rtw89_core_init(struct rtw89_dev * rtwdev)6961 int rtw89_core_init(struct rtw89_dev *rtwdev)
6962 {
6963 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6964 struct rtw89_btc *btc = &rtwdev->btc;
6965 u8 band;
6966
6967 rtwdev->io = rtw89_fw_cmd_ofld_alloc_and_get_io_ops(rtwdev);
6968
6969 bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks,
6970 NUM_OF_RTW89_QUIRKS);
6971
6972 INIT_LIST_HEAD(&rtwdev->ba_list);
6973 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
6974 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
6975 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
6976 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
6977 if (!(rtwdev->chip->support_bands & BIT(band)))
6978 continue;
6979 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
6980 }
6981 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list);
6982 INIT_LIST_HEAD(&rtwdev->tx_waits);
6983 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
6984 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
6985 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
6986 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work);
6987 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work);
6988 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work);
6989 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
6990 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
6991 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
6992 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
6993 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work);
6994 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work);
6995 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
6996 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
6997 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
6998 if (!rtwdev->txq_wq)
6999 return -ENOMEM;
7000 spin_lock_init(&rtwdev->ba_lock);
7001 spin_lock_init(&rtwdev->rpwm_lock);
7002 rtwdev->total_sta_assoc = 0;
7003
7004 rtw89_init_wait(&rtwdev->mcc.wait);
7005 rtw89_init_wait(&rtwdev->mlo.wait);
7006 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
7007 rtw89_init_wait(&rtwdev->wow.wait);
7008 rtw89_init_wait(&rtwdev->mac.ps_wait);
7009
7010 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work);
7011 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work);
7012 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
7013 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
7014
7015 spin_lock_init(&rtwdev->tx_rpt.skb_lock);
7016 skb_queue_head_init(&rtwdev->c2h_queue);
7017 rtw89_core_ppdu_sts_init(rtwdev);
7018 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
7019
7020 rtwdev->hal.rx_fltr = mac->default_rx_fltr;
7021 rtwdev->dbcc_en = false;
7022 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
7023 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
7024
7025 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
7026 rtwdev->dbcc_en = true;
7027 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
7028 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF;
7029 }
7030
7031 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0;
7032 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1;
7033
7034 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
7035 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
7036 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
7037 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
7038
7039 init_completion(&rtwdev->fw.req.completion);
7040 init_completion(&rtwdev->rfk_wait.completion);
7041
7042 schedule_work(&rtwdev->load_firmware_work);
7043
7044 rtw89_ser_init(rtwdev);
7045 rtw89_entity_init(rtwdev);
7046 rtw89_sar_init(rtwdev);
7047 rtw89_phy_ant_gain_init(rtwdev);
7048
7049 return 0;
7050 }
7051 EXPORT_SYMBOL(rtw89_core_init);
7052
rtw89_core_deinit(struct rtw89_dev * rtwdev)7053 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
7054 {
7055 rtw89_ser_deinit(rtwdev);
7056 rtw89_unload_firmware(rtwdev);
7057 __rtw89_fw_free_all_early_h2c(rtwdev);
7058
7059 destroy_workqueue(rtwdev->txq_wq);
7060 }
7061 EXPORT_SYMBOL(rtw89_core_deinit);
7062
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)7063 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7064 const u8 *mac_addr, bool hw_scan)
7065 {
7066 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
7067 rtwvif_link->chanctx_idx);
7068 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
7069
7070 rtwdev->scanning = true;
7071
7072 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
7073 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
7074 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
7075 rtw89_hci_recalc_int_mit(rtwdev);
7076 rtw89_phy_config_edcca(rtwdev, bb, true);
7077 rtw89_tas_scan(rtwdev, true);
7078
7079 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr,
7080 RTW89_ROLE_INFO_CHANGE);
7081 }
7082
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)7083 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
7084 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
7085 {
7086 struct ieee80211_bss_conf *bss_conf;
7087 struct rtw89_bb_ctx *bb;
7088 int ret;
7089
7090 if (!rtwvif_link)
7091 return;
7092
7093 rcu_read_lock();
7094
7095 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
7096 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
7097
7098 rcu_read_unlock();
7099
7100 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL,
7101 RTW89_ROLE_INFO_CHANGE);
7102
7103 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
7104 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
7105 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
7106 rtw89_phy_config_edcca(rtwdev, bb, false);
7107 rtw89_tas_scan(rtwdev, false);
7108
7109 if (hw_scan) {
7110 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false,
7111 RTW89_SCAN_NULL_TIMEOUT);
7112 if (ret)
7113 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
7114 "scan send null-0 failed: %d\n", ret);
7115 }
7116
7117 rtwdev->scanning = false;
7118 rtw89_for_each_active_bb(rtwdev, bb)
7119 bb->dig.bypass_dig = true;
7120 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
7121 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work);
7122 }
7123
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)7124 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
7125 {
7126 const struct rtw89_chip_info *chip = rtwdev->chip;
7127 struct rtw89_hal *hal = &rtwdev->hal;
7128 int ret;
7129 u8 val2;
7130 u8 val;
7131 u8 cv;
7132
7133 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
7134 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
7135 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
7136 cv = CHIP_CAV;
7137 else
7138 cv = CHIP_CBV;
7139 }
7140
7141 hal->cv = cv;
7142
7143 if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) {
7144 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
7145 if (ret)
7146 return;
7147
7148 hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
7149 }
7150
7151 if (chip->chip_gen >= RTW89_CHIP_BE) {
7152 hal->cid =
7153 rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK);
7154
7155 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val);
7156 if (ret)
7157 return;
7158 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2);
7159 if (ret)
7160 return;
7161
7162 hal->aid = val | val2 << 8;
7163 }
7164 }
7165
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)7166 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
7167 {
7168 const struct rtw89_chip_info *chip = rtwdev->chip;
7169
7170 rtwdev->hal.support_cckpd =
7171 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
7172 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
7173 rtwdev->hal.support_igi =
7174 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
7175
7176 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
7177 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
7178 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
7179 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
7180 else
7181 rtwdev->hal.thermal_prot_th = 0;
7182 }
7183
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)7184 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
7185 {
7186 const struct rtw89_chip_info *chip = rtwdev->chip;
7187 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
7188 struct rtw89_efuse *efuse = &rtwdev->efuse;
7189 const struct rtw89_rfe_parms *sel;
7190 u8 rfe_type = efuse->rfe_type;
7191
7192 if (!conf) {
7193 sel = chip->dflt_parms;
7194 goto out;
7195 }
7196
7197 while (conf->rfe_parms) {
7198 if (rfe_type == conf->rfe_type) {
7199 sel = conf->rfe_parms;
7200 goto out;
7201 }
7202 conf++;
7203 }
7204
7205 sel = chip->dflt_parms;
7206
7207 out:
7208 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
7209 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
7210 }
7211
rtw89_core_mlsr_switch(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,unsigned int link_id)7212 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7213 unsigned int link_id)
7214 {
7215 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
7216 u16 usable_links = ieee80211_vif_usable_links(vif);
7217 u16 active_links = vif->active_links;
7218 struct rtw89_vif_link *target;
7219 int ret;
7220
7221 lockdep_assert_wiphy(rtwdev->hw->wiphy);
7222
7223 if (unlikely(!ieee80211_vif_is_mld(vif)))
7224 return -EOPNOTSUPP;
7225
7226 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS ||
7227 !(usable_links & BIT(link_id)))) {
7228 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__,
7229 link_id);
7230 return -ENOLINK;
7231 }
7232
7233 if (active_links == BIT(link_id))
7234 return 0;
7235
7236 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n",
7237 __func__, link_id);
7238
7239 rtw89_leave_lps(rtwdev);
7240
7241 ieee80211_stop_queues(rtwdev->hw);
7242 flush_work(&rtwdev->txq_work);
7243
7244 ret = ieee80211_set_active_links(vif, BIT(link_id));
7245 if (ret) {
7246 rtw89_err(rtwdev, "%s: failed to work on link id %u\n",
7247 __func__, link_id);
7248 goto wake_queue;
7249 }
7250
7251 target = rtwvif->links[link_id];
7252 if (unlikely(!target)) {
7253 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n",
7254 __func__, link_id);
7255
7256 ieee80211_set_active_links(vif, active_links);
7257 ret = -EFAULT;
7258 goto wake_queue;
7259 }
7260
7261 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
7262 rtw89_chip_rfk_channel(rtwdev, target);
7263
7264 rtw89_fw_h2c_tx_history(rtwdev, target->mac_id);
7265
7266 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
7267
7268 wake_queue:
7269 ieee80211_wake_queues(rtwdev->hw);
7270
7271 return ret;
7272 }
7273
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)7274 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
7275 {
7276 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
7277 const struct rtw89_chip_info *chip = rtwdev->chip;
7278 bool bb_preinit = false;
7279 int ret;
7280
7281 /*
7282 * Normally in probe stage, we don't need to do BB pre-initialization.
7283 * However, RTL8922D firmware can access BB registers at firmware
7284 * initial state, so initialize it to avoid BB IO stuck in firmware.
7285 */
7286 if (chip->chip_id == RTL8922D)
7287 bb_preinit = true;
7288
7289 ret = rtw89_mac_partial_init(rtwdev, false, bb_preinit);
7290 if (ret)
7291 return ret;
7292
7293 ret = mac->parse_efuse_map(rtwdev);
7294 if (ret)
7295 return ret;
7296
7297 ret = mac->parse_phycap_map(rtwdev);
7298 if (ret)
7299 return ret;
7300
7301 ret = rtw89_mac_setup_phycap(rtwdev);
7302 if (ret)
7303 return ret;
7304
7305 rtw89_core_setup_phycap(rtwdev);
7306
7307 rtw89_hci_mac_pre_deinit(rtwdev);
7308
7309 return 0;
7310 }
7311
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)7312 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
7313 {
7314 rtw89_chip_fem_setup(rtwdev);
7315
7316 return 0;
7317 }
7318
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)7319 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
7320 {
7321 return !!rtwdev->chip->rfkill_init;
7322 }
7323
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)7324 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
7325 {
7326 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
7327
7328 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
7329 regs->pinmux.mask, regs->pinmux.data);
7330 rtw89_write16_mask(rtwdev, regs->mode.addr,
7331 regs->mode.mask, regs->mode.data);
7332 }
7333
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)7334 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
7335 {
7336 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
7337
7338 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
7339 }
7340
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)7341 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
7342 {
7343 if (!rtw89_chip_has_rfkill(rtwdev))
7344 return;
7345
7346 rtw89_core_rfkill_init(rtwdev);
7347 rtw89_core_rfkill_poll(rtwdev, true);
7348 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
7349 }
7350
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)7351 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
7352 {
7353 if (!rtw89_chip_has_rfkill(rtwdev))
7354 return;
7355
7356 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
7357 }
7358
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)7359 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
7360 {
7361 bool prev, blocked;
7362
7363 if (!rtw89_chip_has_rfkill(rtwdev))
7364 return;
7365
7366 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
7367 blocked = rtw89_core_rfkill_get(rtwdev);
7368
7369 if (!force && prev == blocked)
7370 return;
7371
7372 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
7373 str_enable_disable(!blocked));
7374
7375 if (blocked)
7376 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
7377 else
7378 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
7379
7380 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
7381 }
7382
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)7383 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
7384 {
7385 struct rtw89_efuse *efuse = &rtwdev->efuse;
7386 struct rtw89_hal *hal = &rtwdev->hal;
7387 int ret;
7388
7389 rtw89_read_chip_ver(rtwdev);
7390
7391 ret = rtw89_mac_pwr_on(rtwdev);
7392 if (ret) {
7393 rtw89_err(rtwdev, "failed to power on\n");
7394 return ret;
7395 }
7396
7397 ret = rtw89_wait_firmware_completion(rtwdev);
7398 if (ret) {
7399 rtw89_err(rtwdev, "failed to wait firmware completion\n");
7400 goto out;
7401 }
7402
7403 ret = rtw89_fw_recognize(rtwdev);
7404 if (ret) {
7405 rtw89_err(rtwdev, "failed to recognize firmware\n");
7406 goto out;
7407 }
7408
7409 ret = rtw89_chip_efuse_info_setup(rtwdev);
7410 if (ret)
7411 goto out;
7412
7413 ret = rtw89_fw_recognize_elements(rtwdev);
7414 if (ret) {
7415 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
7416 goto out;
7417 }
7418
7419 ret = rtw89_chip_board_info_setup(rtwdev);
7420 if (ret)
7421 goto out;
7422
7423 ret = rtw89_chip_data_setup(rtwdev);
7424 if (ret)
7425 goto out;
7426
7427 rtw89_core_setup_rfe_parms(rtwdev);
7428 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
7429
7430 rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n",
7431 hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type);
7432
7433 out:
7434 rtw89_mac_pwr_off(rtwdev);
7435
7436 return ret;
7437 }
7438 EXPORT_SYMBOL(rtw89_chip_info_setup);
7439
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)7440 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
7441 struct rtw89_vif_link *rtwvif_link)
7442 {
7443 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
7444 const struct rtw89_chip_info *chip = rtwdev->chip;
7445 struct ieee80211_bss_conf *bss_conf;
7446
7447 rcu_read_lock();
7448
7449 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
7450 if (!bss_conf->he_support || !vif->cfg.assoc) {
7451 rcu_read_unlock();
7452 return;
7453 }
7454
7455 rcu_read_unlock();
7456
7457 if (chip->ops->set_txpwr_ul_tb_offset)
7458 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
7459 }
7460
rtw89_core_register_hw(struct rtw89_dev * rtwdev)7461 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
7462 {
7463 const struct rtw89_chip_info *chip = rtwdev->chip;
7464 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
7465 struct ieee80211_hw *hw = rtwdev->hw;
7466 struct rtw89_efuse *efuse = &rtwdev->efuse;
7467 struct rtw89_hal *hal = &rtwdev->hal;
7468 int ret;
7469 int tx_headroom = IEEE80211_HT_CTL_LEN;
7470
7471 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
7472 tx_headroom += chip->txwd_body_size + chip->txwd_info_size;
7473
7474 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
7475 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
7476 hw->txq_data_size = sizeof(struct rtw89_txq);
7477 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
7478
7479 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
7480
7481 hw->extra_tx_headroom = tx_headroom;
7482 hw->queues = IEEE80211_NUM_ACS;
7483 hw->max_rx_aggregation_subframes = chip->max_rx_agg_num;
7484 hw->max_tx_aggregation_subframes = chip->max_tx_agg_num;
7485 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
7486
7487 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
7488 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
7489 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC |
7490 IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED;
7491
7492 ieee80211_hw_set(hw, SIGNAL_DBM);
7493 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7494 ieee80211_hw_set(hw, MFP_CAPABLE);
7495 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
7496 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7497 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
7498 ieee80211_hw_set(hw, TX_AMSDU);
7499 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
7500 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
7501 ieee80211_hw_set(hw, SUPPORTS_PS);
7502 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
7503 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
7504 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
7505 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
7506 ieee80211_hw_set(hw, CHANCTX_STA_CSA);
7507
7508 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
7509 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
7510
7511 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
7512 ieee80211_hw_set(hw, CONNECTION_MONITOR);
7513
7514 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw))
7515 ieee80211_hw_set(hw, AP_LINK_PS);
7516
7517 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
7518 BIT(NL80211_IFTYPE_AP) |
7519 BIT(NL80211_IFTYPE_P2P_CLIENT) |
7520 BIT(NL80211_IFTYPE_P2P_GO);
7521
7522 if (hal->ant_diversity) {
7523 hw->wiphy->available_antennas_tx = 0x3;
7524 hw->wiphy->available_antennas_rx = 0x3;
7525 } else {
7526 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
7527 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
7528 }
7529
7530 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
7531 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
7532 WIPHY_FLAG_AP_UAPSD |
7533 WIPHY_FLAG_HAS_CHANNEL_SWITCH |
7534 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
7535
7536 if (!chip->support_rnr)
7537 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
7538
7539 if (rtwdev->support_mlo) {
7540 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
7541 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa;
7542 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa);
7543 }
7544
7545 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
7546
7547 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
7548 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
7549
7550 #ifdef CONFIG_PM
7551 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
7552 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
7553 #endif
7554
7555 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
7556 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
7557 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
7558 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
7559 hw->wiphy->max_remain_on_channel_duration = 1000;
7560
7561 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
7562 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
7563 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
7564
7565 ret = rtw89_core_set_supported_band(rtwdev);
7566 if (ret) {
7567 rtw89_err(rtwdev, "failed to set supported band\n");
7568 return ret;
7569 }
7570
7571 ret = rtw89_regd_setup(rtwdev);
7572 if (ret) {
7573 rtw89_err(rtwdev, "failed to set up regd\n");
7574 return ret;
7575 }
7576
7577 hw->wiphy->sar_capa = &rtw89_sar_capa;
7578
7579 ret = ieee80211_register_hw(hw);
7580 if (ret) {
7581 rtw89_err(rtwdev, "failed to register hw\n");
7582 return ret;
7583 }
7584
7585 ret = rtw89_regd_init_hint(rtwdev);
7586 if (ret) {
7587 rtw89_err(rtwdev, "failed to init regd\n");
7588 goto err_unregister_hw;
7589 }
7590
7591 rtw89_rfkill_polling_init(rtwdev);
7592 rtw89_btc_init(rtwdev);
7593 rtw89_led_init(rtwdev);
7594
7595 return 0;
7596
7597 err_unregister_hw:
7598 ieee80211_unregister_hw(hw);
7599
7600 return ret;
7601 }
7602
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)7603 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
7604 {
7605 struct ieee80211_hw *hw = rtwdev->hw;
7606
7607 rtw89_led_deinit(rtwdev);
7608 rtw89_rfkill_polling_deinit(rtwdev);
7609 ieee80211_unregister_hw(hw);
7610 }
7611
rtw89_core_register(struct rtw89_dev * rtwdev)7612 int rtw89_core_register(struct rtw89_dev *rtwdev)
7613 {
7614 int ret;
7615
7616 ret = rtw89_core_register_hw(rtwdev);
7617 if (ret) {
7618 rtw89_err(rtwdev, "failed to register core hw\n");
7619 return ret;
7620 }
7621
7622 rtw89_phy_dm_init_data(rtwdev);
7623 rtw89_debugfs_init(rtwdev);
7624
7625 return 0;
7626 }
7627 EXPORT_SYMBOL(rtw89_core_register);
7628
rtw89_core_unregister(struct rtw89_dev * rtwdev)7629 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
7630 {
7631 rtw89_core_unregister_hw(rtwdev);
7632
7633 rtw89_debugfs_deinit(rtwdev);
7634 }
7635 EXPORT_SYMBOL(rtw89_core_unregister);
7636
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_driver_info * info)7637 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
7638 u32 bus_data_size,
7639 const struct rtw89_driver_info *info)
7640 {
7641 const unsigned long *dev_id_quirks = &info->dev_id_quirks;
7642 const struct rtw89_chip_variant *variant = info->variant;
7643 const struct rtw89_chip_info *chip = info->chip;
7644 struct rtw89_fw_info early_fw = {};
7645 const struct firmware *firmware;
7646 struct ieee80211_hw *hw;
7647 struct rtw89_dev *rtwdev;
7648 struct ieee80211_ops *ops;
7649 u32 driver_data_size;
7650 int fw_format = -1;
7651 bool support_mlo;
7652 bool no_chanctx;
7653
7654 firmware = rtw89_early_fw_feature_recognize(device, chip, variant,
7655 &early_fw, &fw_format);
7656
7657 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
7658 if (!ops)
7659 goto err;
7660
7661 no_chanctx = chip->support_chanctx_num == 0 ||
7662 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
7663 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
7664
7665 if (no_chanctx) {
7666 ops->add_chanctx = ieee80211_emulate_add_chanctx;
7667 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
7668 ops->change_chanctx = ieee80211_emulate_change_chanctx;
7669 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
7670 ops->assign_vif_chanctx = NULL;
7671 ops->unassign_vif_chanctx = NULL;
7672 ops->remain_on_channel = NULL;
7673 ops->cancel_remain_on_channel = NULL;
7674 }
7675
7676 if (!chip->support_noise)
7677 ops->get_survey = NULL;
7678
7679 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
7680 hw = ieee80211_alloc_hw(driver_data_size, ops);
7681 if (!hw)
7682 goto err;
7683
7684 /* Currently, our AP_LINK_PS handling only works for non-MLD softap
7685 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges,
7686 * please tweak entire AP_LINKS_PS handling before supporting MLO.
7687 */
7688 support_mlo = !no_chanctx && chip->support_link_num &&
7689 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) &&
7690 RTW89_MLD_NON_STA_LINK_NUM == 1;
7691
7692 hw->wiphy->iface_combinations = rtw89_iface_combs;
7693
7694 if (no_chanctx || chip->support_chanctx_num == 1)
7695 hw->wiphy->n_iface_combinations = 1;
7696 else
7697 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
7698
7699 rtwdev = hw->priv;
7700 rtwdev->hw = hw;
7701 rtwdev->dev = device;
7702 rtwdev->ops = ops;
7703 rtwdev->chip = chip;
7704 rtwdev->variant = variant;
7705 rtwdev->board = info->board;
7706 rtwdev->fw.req.firmware = firmware;
7707 rtwdev->fw.fw_format = fw_format;
7708 rtwdev->support_mlo = support_mlo;
7709
7710 bitmap_or(rtwdev->quirks, rtwdev->quirks, dev_id_quirks,
7711 NUM_OF_RTW89_QUIRKS);
7712
7713 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
7714 no_chanctx ? "without" : "with");
7715 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
7716 support_mlo ? "with" : "without");
7717
7718 return rtwdev;
7719
7720 err:
7721 kfree(ops);
7722 release_firmware(firmware);
7723 return NULL;
7724 }
7725 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
7726
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)7727 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
7728 {
7729 kfree(rtwdev->ops);
7730 kfree(rtwdev->rfe_data);
7731 release_firmware(rtwdev->fw.req.firmware);
7732 ieee80211_free_hw(rtwdev->hw);
7733 }
7734 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
7735
7736 MODULE_AUTHOR("Realtek Corporation");
7737 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
7738 MODULE_LICENSE("Dual BSD/GPL");
7739