1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8 #ifndef _ASUS_ARMOURY_H_ 9 #define _ASUS_ARMOURY_H_ 10 11 #include <linux/dmi.h> 12 #include <linux/platform_device.h> 13 #include <linux/sysfs.h> 14 #include <linux/types.h> 15 16 #define DRIVER_NAME "asus-armoury" 17 18 /** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41 ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45 /** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57 ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60 #define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66 #define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72 #define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75 #define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84 #define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91 /* Create functions and attributes for use in other macros or on their own */ 92 93 /* Shows a formatted static variable */ 94 #define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103 #define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122 #define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143 /* Boolean style enumeration, base macro. Requires adding show/store */ 144 #define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160 #define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164 #define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167 #define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170 /* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173 #define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178 /* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182 #define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201 #define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217 /* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222 #define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236 #define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254 #define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286 #define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309 /* Default is always the maximum value unless *_def is specified */ 310 struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336 }; 337 338 struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342 }; 343 344 /* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348 static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401EA"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 95, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 100, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 115, 361 }, 362 .dc_data = &(struct power_limits) { 363 .ppt_pl1_spl_min = 15, 364 .ppt_pl1_spl_max = 71, 365 .ppt_pl2_sppt_min = 35, 366 .ppt_pl2_sppt_max = 71, 367 .ppt_pl3_fppt_min = 35, 368 .ppt_pl3_fppt_max = 71, 369 }, 370 }, 371 }, 372 { 373 .matches = { 374 DMI_MATCH(DMI_BOARD_NAME, "FA401KM"), 375 }, 376 .driver_data = &(struct power_data) { 377 .ac_data = &(struct power_limits) { 378 .nv_dynamic_boost_max = 15, 379 .nv_dynamic_boost_min = 5, 380 .nv_temp_target_max = 87, 381 .nv_temp_target_min = 75, 382 .nv_tgp_max = 95, 383 .nv_tgp_min = 55, 384 .ppt_pl1_spl_max = 80, 385 .ppt_pl1_spl_min = 15, 386 .ppt_pl2_sppt_max = 80, 387 .ppt_pl2_sppt_min = 35, 388 .ppt_pl3_fppt_max = 80, 389 .ppt_pl3_fppt_min = 35, 390 }, 391 .dc_data = &(struct power_limits) { 392 .nv_temp_target_max = 87, 393 .nv_temp_target_min = 75, 394 .ppt_pl1_spl_max = 35, 395 .ppt_pl1_spl_min = 25, 396 .ppt_pl2_sppt_max = 44, 397 .ppt_pl2_sppt_min = 31, 398 .ppt_pl3_fppt_max = 65, 399 .ppt_pl3_fppt_min = 45, 400 }, 401 .requires_fan_curve = true, 402 }, 403 }, 404 { 405 .matches = { 406 DMI_MATCH(DMI_BOARD_NAME, "FA401UM"), 407 }, 408 .driver_data = &(struct power_data) { 409 .ac_data = &(struct power_limits) { 410 .ppt_pl1_spl_min = 15, 411 .ppt_pl1_spl_max = 80, 412 .ppt_pl2_sppt_min = 35, 413 .ppt_pl2_sppt_max = 80, 414 .ppt_pl3_fppt_min = 35, 415 .ppt_pl3_fppt_max = 80, 416 .nv_dynamic_boost_min = 5, 417 .nv_dynamic_boost_max = 15, 418 .nv_temp_target_min = 75, 419 .nv_temp_target_max = 87, 420 }, 421 .dc_data = &(struct power_limits) { 422 .ppt_pl1_spl_min = 25, 423 .ppt_pl1_spl_max = 35, 424 .ppt_pl2_sppt_min = 31, 425 .ppt_pl2_sppt_max = 44, 426 .ppt_pl3_fppt_min = 45, 427 .ppt_pl3_fppt_max = 65, 428 .nv_temp_target_min = 75, 429 .nv_temp_target_max = 87, 430 }, 431 }, 432 }, 433 { 434 .matches = { 435 DMI_MATCH(DMI_BOARD_NAME, "FA401UV"), 436 }, 437 .driver_data = &(struct power_data) { 438 .ac_data = &(struct power_limits) { 439 .ppt_pl1_spl_min = 15, 440 .ppt_pl1_spl_max = 80, 441 .ppt_pl2_sppt_min = 35, 442 .ppt_pl2_sppt_max = 80, 443 .ppt_pl3_fppt_min = 35, 444 .ppt_pl3_fppt_max = 80, 445 .nv_dynamic_boost_min = 5, 446 .nv_dynamic_boost_max = 25, 447 .nv_temp_target_min = 75, 448 .nv_temp_target_max = 87, 449 .nv_tgp_min = 55, 450 .nv_tgp_max = 75, 451 }, 452 .dc_data = &(struct power_limits) { 453 .ppt_pl1_spl_min = 25, 454 .ppt_pl1_spl_max = 35, 455 .ppt_pl2_sppt_min = 31, 456 .ppt_pl2_sppt_max = 44, 457 .ppt_pl3_fppt_min = 45, 458 .ppt_pl3_fppt_max = 65, 459 .nv_temp_target_min = 75, 460 .nv_temp_target_max = 87, 461 }, 462 }, 463 }, 464 { 465 .matches = { 466 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 467 }, 468 .driver_data = &(struct power_data) { 469 .ac_data = &(struct power_limits) { 470 .ppt_pl1_spl_min = 15, 471 .ppt_pl1_spl_max = 80, 472 .ppt_pl2_sppt_min = 35, 473 .ppt_pl2_sppt_max = 80, 474 .ppt_pl3_fppt_min = 35, 475 .ppt_pl3_fppt_max = 80, 476 .nv_dynamic_boost_min = 5, 477 .nv_dynamic_boost_max = 25, 478 .nv_temp_target_min = 75, 479 .nv_temp_target_max = 87, 480 .nv_tgp_min = 55, 481 .nv_tgp_max = 75, 482 }, 483 .dc_data = &(struct power_limits) { 484 .ppt_pl1_spl_min = 25, 485 .ppt_pl1_spl_max = 30, 486 .ppt_pl2_sppt_min = 31, 487 .ppt_pl2_sppt_max = 44, 488 .ppt_pl3_fppt_min = 45, 489 .ppt_pl3_fppt_max = 65, 490 .nv_temp_target_min = 75, 491 .nv_temp_target_max = 87, 492 }, 493 }, 494 }, 495 { 496 .matches = { 497 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 498 }, 499 .driver_data = &(struct power_data) { 500 .ac_data = &(struct power_limits) { 501 .ppt_pl1_spl_min = 15, 502 .ppt_pl1_spl_max = 80, 503 .ppt_pl2_sppt_min = 35, 504 .ppt_pl2_sppt_max = 80, 505 .ppt_pl3_fppt_min = 35, 506 .ppt_pl3_fppt_max = 80, 507 .nv_dynamic_boost_min = 5, 508 .nv_dynamic_boost_max = 25, 509 .nv_temp_target_min = 75, 510 .nv_temp_target_max = 87, 511 }, 512 .dc_data = &(struct power_limits) { 513 .ppt_pl1_spl_min = 15, 514 .ppt_pl1_spl_def = 45, 515 .ppt_pl1_spl_max = 65, 516 .ppt_pl2_sppt_min = 35, 517 .ppt_pl2_sppt_def = 54, 518 .ppt_pl2_sppt_max = 65, 519 .ppt_pl3_fppt_min = 35, 520 .ppt_pl3_fppt_max = 65, 521 .nv_temp_target_min = 75, 522 .nv_temp_target_max = 87, 523 }, 524 }, 525 }, 526 { 527 .matches = { 528 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 529 }, 530 .driver_data = &(struct power_data) { 531 .ac_data = &(struct power_limits) { 532 .ppt_pl1_spl_min = 15, 533 .ppt_pl1_spl_max = 80, 534 .ppt_pl2_sppt_min = 35, 535 .ppt_pl2_sppt_max = 80, 536 .ppt_pl3_fppt_min = 35, 537 .ppt_pl3_fppt_max = 80, 538 .nv_dynamic_boost_min = 5, 539 .nv_dynamic_boost_max = 25, 540 .nv_temp_target_min = 75, 541 .nv_temp_target_max = 87, 542 .nv_tgp_min = 55, 543 .nv_tgp_max = 115, 544 }, 545 .dc_data = &(struct power_limits) { 546 .ppt_pl1_spl_min = 15, 547 .ppt_pl1_spl_def = 45, 548 .ppt_pl1_spl_max = 65, 549 .ppt_pl2_sppt_min = 35, 550 .ppt_pl2_sppt_def = 54, 551 .ppt_pl2_sppt_max = 65, 552 .ppt_pl3_fppt_min = 35, 553 .ppt_pl3_fppt_max = 65, 554 .nv_temp_target_min = 75, 555 .nv_temp_target_max = 87, 556 }, 557 }, 558 }, 559 { 560 .matches = { 561 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 562 }, 563 .driver_data = &(struct power_data) { 564 .ac_data = &(struct power_limits) { 565 .ppt_pl1_spl_min = 15, 566 .ppt_pl1_spl_max = 80, 567 .ppt_pl2_sppt_min = 35, 568 .ppt_pl2_sppt_max = 80, 569 .ppt_pl3_fppt_min = 35, 570 .ppt_pl3_fppt_max = 80, 571 .nv_dynamic_boost_min = 5, 572 .nv_dynamic_boost_max = 25, 573 .nv_temp_target_min = 75, 574 .nv_temp_target_max = 87, 575 }, 576 .dc_data = &(struct power_limits) { 577 .ppt_pl1_spl_min = 15, 578 .ppt_pl1_spl_def = 45, 579 .ppt_pl1_spl_max = 65, 580 .ppt_pl2_sppt_min = 35, 581 .ppt_pl2_sppt_def = 54, 582 .ppt_pl2_sppt_max = 65, 583 .ppt_pl3_fppt_min = 35, 584 .ppt_pl3_fppt_max = 65, 585 .nv_temp_target_min = 75, 586 .nv_temp_target_max = 87, 587 }, 588 }, 589 }, 590 { 591 .matches = { 592 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 593 }, 594 .driver_data = &(struct power_data) { 595 .ac_data = &(struct power_limits) { 596 .ppt_pl1_spl_min = 15, 597 .ppt_pl1_spl_max = 80, 598 .ppt_pl2_sppt_min = 35, 599 .ppt_pl2_sppt_max = 80, 600 .ppt_pl3_fppt_min = 35, 601 .ppt_pl3_fppt_max = 80, 602 .nv_dynamic_boost_min = 5, 603 .nv_dynamic_boost_max = 20, 604 .nv_temp_target_min = 75, 605 .nv_temp_target_max = 87, 606 .nv_tgp_min = 55, 607 .nv_tgp_max = 85, 608 }, 609 .dc_data = &(struct power_limits) { 610 .ppt_pl1_spl_min = 15, 611 .ppt_pl1_spl_def = 45, 612 .ppt_pl1_spl_max = 65, 613 .ppt_pl2_sppt_min = 35, 614 .ppt_pl2_sppt_def = 54, 615 .ppt_pl2_sppt_max = 65, 616 .ppt_pl3_fppt_min = 35, 617 .ppt_pl3_fppt_max = 65, 618 .nv_temp_target_min = 75, 619 .nv_temp_target_max = 87, 620 }, 621 }, 622 }, 623 { 624 .matches = { 625 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 626 }, 627 .driver_data = &(struct power_data) { 628 .ac_data = &(struct power_limits) { 629 .ppt_pl1_spl_min = 28, 630 .ppt_pl1_spl_max = 65, 631 .ppt_pl2_sppt_min = 28, 632 .ppt_pl2_sppt_max = 105, 633 .nv_dynamic_boost_min = 5, 634 .nv_dynamic_boost_max = 15, 635 .nv_temp_target_min = 75, 636 .nv_temp_target_max = 87, 637 .nv_tgp_min = 55, 638 .nv_tgp_max = 85, 639 }, 640 .dc_data = &(struct power_limits) { 641 .ppt_pl1_spl_min = 25, 642 .ppt_pl1_spl_max = 45, 643 .ppt_pl2_sppt_min = 35, 644 .ppt_pl2_sppt_max = 60, 645 .nv_temp_target_min = 75, 646 .nv_temp_target_max = 87, 647 }, 648 }, 649 }, 650 { 651 .matches = { 652 DMI_MATCH(DMI_BOARD_NAME, "FA607NU"), 653 }, 654 .driver_data = &(struct power_data) { 655 .ac_data = &(struct power_limits) { 656 .ppt_pl1_spl_min = 15, 657 .ppt_pl1_spl_max = 80, 658 .ppt_pl2_sppt_min = 35, 659 .ppt_pl2_sppt_max = 80, 660 .ppt_pl3_fppt_min = 35, 661 .ppt_pl3_fppt_max = 80, 662 .nv_dynamic_boost_min = 5, 663 .nv_dynamic_boost_max = 25, 664 .nv_temp_target_min = 75, 665 .nv_temp_target_max = 87, 666 }, 667 .dc_data = &(struct power_limits) { 668 .ppt_pl1_spl_min = 25, 669 .ppt_pl1_spl_def = 45, 670 .ppt_pl1_spl_max = 65, 671 .ppt_pl2_sppt_min = 25, 672 .ppt_pl2_sppt_def = 54, 673 .ppt_pl2_sppt_max = 65, 674 .ppt_pl3_fppt_min = 25, 675 .ppt_pl3_fppt_max = 65, 676 .nv_temp_target_min = 75, 677 .nv_temp_target_max = 87, 678 }, 679 }, 680 }, 681 { 682 .matches = { 683 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 684 }, 685 .driver_data = &(struct power_data) { 686 .ac_data = &(struct power_limits) { 687 .ppt_pl1_spl_min = 30, 688 .ppt_pl1_spl_def = 100, 689 .ppt_pl1_spl_max = 135, 690 .ppt_pl2_sppt_min = 30, 691 .ppt_pl2_sppt_def = 115, 692 .ppt_pl2_sppt_max = 135, 693 .ppt_pl3_fppt_min = 30, 694 .ppt_pl3_fppt_max = 135, 695 .nv_dynamic_boost_min = 5, 696 .nv_dynamic_boost_max = 25, 697 .nv_temp_target_min = 75, 698 .nv_temp_target_max = 87, 699 .nv_tgp_min = 55, 700 .nv_tgp_max = 115, 701 }, 702 .dc_data = &(struct power_limits) { 703 .ppt_pl1_spl_min = 25, 704 .ppt_pl1_spl_def = 45, 705 .ppt_pl1_spl_max = 80, 706 .ppt_pl2_sppt_min = 25, 707 .ppt_pl2_sppt_def = 60, 708 .ppt_pl2_sppt_max = 80, 709 .ppt_pl3_fppt_min = 25, 710 .ppt_pl3_fppt_max = 80, 711 .nv_temp_target_min = 75, 712 .nv_temp_target_max = 87, 713 }, 714 }, 715 }, 716 { 717 .matches = { 718 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 719 }, 720 .driver_data = &(struct power_data) { 721 .ac_data = &(struct power_limits) { 722 .ppt_pl1_spl_min = 15, 723 .ppt_pl1_spl_def = 45, 724 .ppt_pl1_spl_max = 90, 725 .ppt_pl2_sppt_min = 35, 726 .ppt_pl2_sppt_def = 54, 727 .ppt_pl2_sppt_max = 90, 728 .ppt_pl3_fppt_min = 35, 729 .ppt_pl3_fppt_def = 65, 730 .ppt_pl3_fppt_max = 90, 731 .nv_dynamic_boost_min = 10, 732 .nv_dynamic_boost_max = 15, 733 .nv_temp_target_min = 75, 734 .nv_temp_target_max = 87, 735 .nv_tgp_min = 55, 736 .nv_tgp_max = 100, 737 }, 738 .dc_data = &(struct power_limits) { 739 .ppt_pl1_spl_min = 15, 740 .ppt_pl1_spl_def = 45, 741 .ppt_pl1_spl_max = 65, 742 .ppt_pl2_sppt_min = 35, 743 .ppt_pl2_sppt_def = 54, 744 .ppt_pl2_sppt_max = 65, 745 .ppt_pl3_fppt_min = 35, 746 .ppt_pl3_fppt_max = 65, 747 .nv_temp_target_min = 75, 748 .nv_temp_target_max = 87, 749 }, 750 }, 751 }, 752 { 753 .matches = { 754 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 755 }, 756 .driver_data = &(struct power_data) { 757 .ac_data = &(struct power_limits) { 758 .ppt_pl1_spl_min = 15, 759 .ppt_pl1_spl_def = 90, 760 .ppt_pl1_spl_max = 90, 761 .ppt_pl2_sppt_min = 35, 762 .ppt_pl2_sppt_def = 90, 763 .ppt_pl2_sppt_max = 90, 764 .ppt_pl3_fppt_min = 35, 765 .ppt_pl3_fppt_def = 90, 766 .ppt_pl3_fppt_max = 90, 767 .nv_dynamic_boost_min = 5, 768 .nv_dynamic_boost_max = 25, 769 .nv_temp_target_min = 75, 770 .nv_temp_target_max = 87, 771 .nv_tgp_min = 55, 772 .nv_tgp_max = 115, 773 }, 774 .dc_data = &(struct power_limits) { 775 .ppt_pl1_spl_min = 15, 776 .ppt_pl1_spl_def = 45, 777 .ppt_pl1_spl_max = 65, 778 .ppt_pl2_sppt_min = 35, 779 .ppt_pl2_sppt_def = 54, 780 .ppt_pl2_sppt_max = 65, 781 .ppt_pl3_fppt_min = 35, 782 .ppt_pl3_fppt_def = 65, 783 .ppt_pl3_fppt_max = 65, 784 .nv_temp_target_min = 75, 785 .nv_temp_target_max = 87, 786 }, 787 }, 788 }, 789 { 790 .matches = { 791 DMI_MATCH(DMI_BOARD_NAME, "FA608WV"), 792 }, 793 .driver_data = &(struct power_data) { 794 .ac_data = &(struct power_limits) { 795 .nv_dynamic_boost_max = 25, 796 .nv_dynamic_boost_min = 5, 797 .nv_temp_target_max = 87, 798 .nv_temp_target_min = 75, 799 .nv_tgp_max = 115, 800 .nv_tgp_min = 55, 801 .ppt_pl1_spl_max = 90, 802 .ppt_pl1_spl_min = 15, 803 .ppt_pl2_sppt_max = 90, 804 .ppt_pl2_sppt_min = 35, 805 .ppt_pl3_fppt_max = 90, 806 .ppt_pl3_fppt_min = 35, 807 }, 808 .dc_data = &(struct power_limits) { 809 .nv_temp_target_max = 87, 810 .nv_temp_target_min = 75, 811 .ppt_pl1_spl_def = 45, 812 .ppt_pl1_spl_max = 65, 813 .ppt_pl1_spl_min = 15, 814 .ppt_pl2_sppt_def = 54, 815 .ppt_pl2_sppt_max = 65, 816 .ppt_pl2_sppt_min = 35, 817 .ppt_pl3_fppt_max = 65, 818 .ppt_pl3_fppt_min = 35, 819 }, 820 .requires_fan_curve = true, 821 }, 822 }, 823 { 824 .matches = { 825 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 826 }, 827 .driver_data = &(struct power_data) { 828 .ac_data = &(struct power_limits) { 829 .ppt_apu_sppt_min = 15, 830 .ppt_apu_sppt_max = 80, 831 .ppt_platform_sppt_min = 30, 832 .ppt_platform_sppt_max = 120, 833 }, 834 .dc_data = &(struct power_limits) { 835 .ppt_apu_sppt_min = 25, 836 .ppt_apu_sppt_max = 35, 837 .ppt_platform_sppt_min = 45, 838 .ppt_platform_sppt_max = 100, 839 }, 840 }, 841 }, 842 { 843 .matches = { 844 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 845 }, 846 .driver_data = &(struct power_data) { 847 .ac_data = &(struct power_limits) { 848 .ppt_apu_sppt_min = 15, 849 .ppt_apu_sppt_max = 80, 850 .ppt_platform_sppt_min = 30, 851 .ppt_platform_sppt_max = 115, 852 }, 853 .dc_data = &(struct power_limits) { 854 .ppt_apu_sppt_min = 15, 855 .ppt_apu_sppt_max = 45, 856 .ppt_platform_sppt_min = 30, 857 .ppt_platform_sppt_max = 50, 858 }, 859 }, 860 }, 861 { 862 .matches = { 863 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 864 }, 865 .driver_data = &(struct power_data) { 866 .ac_data = &(struct power_limits) { 867 .ppt_apu_sppt_min = 15, 868 .ppt_apu_sppt_max = 80, 869 .ppt_platform_sppt_min = 30, 870 .ppt_platform_sppt_max = 120, 871 .nv_temp_target_min = 75, 872 .nv_temp_target_max = 87, 873 }, 874 .dc_data = &(struct power_limits) { 875 .ppt_apu_sppt_min = 25, 876 .ppt_apu_sppt_max = 35, 877 .ppt_platform_sppt_min = 45, 878 .ppt_platform_sppt_max = 100, 879 .nv_temp_target_min = 75, 880 .nv_temp_target_max = 87, 881 }, 882 }, 883 }, 884 { 885 .matches = { 886 DMI_MATCH(DMI_BOARD_NAME, "FA617XT"), 887 }, 888 .driver_data = &(struct power_data) { 889 .ac_data = &(struct power_limits) { 890 .ppt_apu_sppt_min = 15, 891 .ppt_apu_sppt_max = 80, 892 .ppt_platform_sppt_min = 30, 893 .ppt_platform_sppt_max = 145, 894 }, 895 .dc_data = &(struct power_limits) { 896 .ppt_apu_sppt_min = 25, 897 .ppt_apu_sppt_max = 35, 898 .ppt_platform_sppt_min = 45, 899 .ppt_platform_sppt_max = 100, 900 }, 901 }, 902 }, 903 { 904 .matches = { 905 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 906 }, 907 .driver_data = &(struct power_data) { 908 .ac_data = &(struct power_limits) { 909 .ppt_pl1_spl_min = 28, 910 .ppt_pl1_spl_max = 135, 911 .ppt_pl2_sppt_min = 28, 912 .ppt_pl2_sppt_max = 135, 913 .nv_dynamic_boost_min = 5, 914 .nv_dynamic_boost_max = 25, 915 .nv_temp_target_min = 75, 916 .nv_temp_target_max = 87, 917 }, 918 .dc_data = &(struct power_limits) { 919 .ppt_pl1_spl_min = 25, 920 .ppt_pl1_spl_max = 45, 921 .ppt_pl2_sppt_min = 35, 922 .ppt_pl2_sppt_max = 60, 923 .nv_temp_target_min = 75, 924 .nv_temp_target_max = 87, 925 }, 926 .requires_fan_curve = true, 927 }, 928 }, 929 { 930 .matches = { 931 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 932 }, 933 .driver_data = &(struct power_data) { 934 .ac_data = &(struct power_limits) { 935 .ppt_pl1_spl_min = 28, 936 .ppt_pl1_spl_def = 115, 937 .ppt_pl1_spl_max = 135, 938 .ppt_pl2_sppt_min = 28, 939 .ppt_pl2_sppt_max = 135, 940 .nv_dynamic_boost_min = 5, 941 .nv_dynamic_boost_max = 25, 942 .nv_temp_target_min = 75, 943 .nv_temp_target_max = 87, 944 }, 945 .dc_data = &(struct power_limits) { 946 .ppt_pl1_spl_min = 25, 947 .ppt_pl1_spl_max = 45, 948 .ppt_pl2_sppt_min = 35, 949 .ppt_pl2_sppt_max = 60, 950 .nv_temp_target_min = 75, 951 .nv_temp_target_max = 87, 952 }, 953 .requires_fan_curve = true, 954 }, 955 }, 956 { 957 .matches = { 958 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 959 }, 960 .driver_data = &(struct power_data) { 961 .ac_data = &(struct power_limits) { 962 .ppt_pl1_spl_min = 28, 963 .ppt_pl1_spl_max = 90, 964 .ppt_pl2_sppt_min = 28, 965 .ppt_pl2_sppt_max = 135, 966 .nv_dynamic_boost_min = 5, 967 .nv_dynamic_boost_max = 15, 968 }, 969 .dc_data = &(struct power_limits) { 970 .ppt_pl1_spl_min = 25, 971 .ppt_pl1_spl_max = 45, 972 .ppt_pl2_sppt_min = 35, 973 .ppt_pl2_sppt_max = 60, 974 }, 975 .requires_fan_curve = true, 976 }, 977 }, 978 { 979 .matches = { 980 DMI_MATCH(DMI_BOARD_NAME, "FX517ZR"), 981 }, 982 .driver_data = &(struct power_data) { 983 .ac_data = &(struct power_limits) { 984 .ppt_pl1_spl_min = 28, 985 .ppt_pl1_spl_max = 85, 986 .ppt_pl2_sppt_min = 28, 987 .ppt_pl2_sppt_max = 135, 988 .nv_dynamic_boost_min = 5, 989 .nv_dynamic_boost_max = 25, 990 .nv_temp_target_min = 75, 991 .nv_temp_target_max = 87, 992 }, 993 .dc_data = &(struct power_limits) { 994 .ppt_pl1_spl_min = 25, 995 .ppt_pl1_spl_max = 45, 996 .ppt_pl2_sppt_min = 35, 997 .ppt_pl2_sppt_max = 60, 998 .nv_temp_target_min = 75, 999 .nv_temp_target_max = 87, 1000 }, 1001 .requires_fan_curve = true, 1002 }, 1003 }, 1004 { 1005 .matches = { 1006 DMI_MATCH(DMI_BOARD_NAME, "FX607VU"), 1007 }, 1008 .driver_data = &(struct power_data) { 1009 .ac_data = &(struct power_limits) { 1010 .ppt_pl1_spl_min = 28, 1011 .ppt_pl1_spl_def = 115, 1012 .ppt_pl1_spl_max = 135, 1013 .ppt_pl2_sppt_min = 28, 1014 .ppt_pl2_sppt_max = 135, 1015 .nv_dynamic_boost_min = 5, 1016 .nv_dynamic_boost_max = 25, 1017 .nv_temp_target_min = 75, 1018 .nv_temp_target_max = 87, 1019 }, 1020 .dc_data = &(struct power_limits) { 1021 .ppt_pl1_spl_min = 25, 1022 .ppt_pl1_spl_max = 45, 1023 .ppt_pl2_sppt_min = 35, 1024 .ppt_pl2_sppt_max = 60, 1025 .nv_temp_target_min = 75, 1026 .nv_temp_target_max = 87, 1027 }, 1028 .requires_fan_curve = true, 1029 }, 1030 }, 1031 { 1032 .matches = { 1033 DMI_MATCH(DMI_BOARD_NAME, "FX608JPR"), 1034 }, 1035 .driver_data = &(struct power_data) { 1036 .ac_data = &(struct power_limits) { 1037 .ppt_pl1_spl_min = 28, 1038 .ppt_pl1_spl_max = 100, 1039 .ppt_pl2_sppt_min = 28, 1040 .ppt_pl2_sppt_max = 135, 1041 .nv_dynamic_boost_min = 10, 1042 .nv_dynamic_boost_max = 15, 1043 .nv_temp_target_min = 75, 1044 .nv_temp_target_max = 87, 1045 .nv_tgp_min = 55, 1046 .nv_tgp_max = 100, 1047 }, 1048 .dc_data = &(struct power_limits) { 1049 .ppt_pl1_spl_min = 25, 1050 .ppt_pl1_spl_max = 53, 1051 .ppt_pl2_sppt_min = 25, 1052 .ppt_pl2_sppt_max = 65, 1053 .nv_temp_target_min = 75, 1054 .nv_temp_target_max = 87, 1055 }, 1056 .requires_fan_curve = true, 1057 }, 1058 }, 1059 { 1060 .matches = { 1061 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 1062 }, 1063 .driver_data = &(struct power_data) { 1064 .ac_data = &(struct power_limits) { 1065 .ppt_pl1_spl_min = 15, 1066 .ppt_pl1_spl_max = 80, 1067 .ppt_pl2_sppt_min = 15, 1068 .ppt_pl2_sppt_max = 80, 1069 }, 1070 .dc_data = NULL, 1071 }, 1072 }, 1073 { 1074 .matches = { 1075 DMI_MATCH(DMI_BOARD_NAME, "GA402NJ"), 1076 }, 1077 .driver_data = &(struct power_data) { 1078 .ac_data = &(struct power_limits) { 1079 .ppt_pl1_spl_min = 15, 1080 .ppt_pl1_spl_def = 35, 1081 .ppt_pl1_spl_max = 80, 1082 .ppt_pl2_sppt_min = 25, 1083 .ppt_pl2_sppt_def = 65, 1084 .ppt_pl2_sppt_max = 80, 1085 .ppt_pl3_fppt_min = 35, 1086 .ppt_pl3_fppt_max = 80, 1087 .nv_temp_target_min = 75, 1088 .nv_temp_target_max = 87, 1089 .nv_dynamic_boost_min = 5, 1090 .nv_dynamic_boost_def = 10, 1091 .nv_dynamic_boost_max = 15, 1092 }, 1093 .dc_data = &(struct power_limits) { 1094 .ppt_pl1_spl_min = 15, 1095 .ppt_pl1_spl_max = 35, 1096 .ppt_pl2_sppt_min = 25, 1097 .ppt_pl2_sppt_max = 35, 1098 .ppt_pl3_fppt_min = 35, 1099 .ppt_pl3_fppt_max = 65, 1100 .nv_temp_target_min = 75, 1101 .nv_temp_target_max = 87, 1102 }, 1103 }, 1104 }, 1105 { 1106 .matches = { 1107 // This model is full AMD. No Nvidia dGPU. 1108 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 1109 }, 1110 .driver_data = &(struct power_data) { 1111 .ac_data = &(struct power_limits) { 1112 .ppt_apu_sppt_min = 15, 1113 .ppt_apu_sppt_max = 80, 1114 .ppt_platform_sppt_min = 30, 1115 .ppt_platform_sppt_max = 115, 1116 }, 1117 .dc_data = &(struct power_limits) { 1118 .ppt_apu_sppt_min = 25, 1119 .ppt_apu_sppt_def = 30, 1120 .ppt_apu_sppt_max = 45, 1121 .ppt_platform_sppt_min = 40, 1122 .ppt_platform_sppt_max = 60, 1123 }, 1124 }, 1125 }, 1126 { 1127 .matches = { 1128 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 1129 }, 1130 .driver_data = &(struct power_data) { 1131 .ac_data = &(struct power_limits) { 1132 .ppt_pl1_spl_min = 15, 1133 .ppt_pl1_spl_def = 35, 1134 .ppt_pl1_spl_max = 80, 1135 .ppt_pl2_sppt_min = 25, 1136 .ppt_pl2_sppt_def = 65, 1137 .ppt_pl2_sppt_max = 80, 1138 .ppt_pl3_fppt_min = 35, 1139 .ppt_pl3_fppt_max = 80, 1140 .nv_temp_target_min = 75, 1141 .nv_temp_target_max = 87, 1142 }, 1143 .dc_data = &(struct power_limits) { 1144 .ppt_pl1_spl_min = 15, 1145 .ppt_pl1_spl_max = 35, 1146 .ppt_pl2_sppt_min = 25, 1147 .ppt_pl2_sppt_max = 35, 1148 .ppt_pl3_fppt_min = 35, 1149 .ppt_pl3_fppt_max = 65, 1150 .nv_temp_target_min = 75, 1151 .nv_temp_target_max = 87, 1152 }, 1153 .requires_fan_curve = true, 1154 }, 1155 }, 1156 { 1157 .matches = { 1158 DMI_MATCH(DMI_BOARD_NAME, "GA403UI"), 1159 }, 1160 .driver_data = &(struct power_data) { 1161 .ac_data = &(struct power_limits) { 1162 .ppt_pl1_spl_min = 15, 1163 .ppt_pl1_spl_max = 80, 1164 .ppt_pl2_sppt_min = 25, 1165 .ppt_pl2_sppt_max = 80, 1166 .ppt_pl3_fppt_min = 35, 1167 .ppt_pl3_fppt_max = 80, 1168 .nv_dynamic_boost_min = 5, 1169 .nv_dynamic_boost_max = 25, 1170 .nv_temp_target_min = 75, 1171 .nv_temp_target_max = 87, 1172 .nv_tgp_min = 55, 1173 .nv_tgp_max = 65, 1174 }, 1175 .dc_data = &(struct power_limits) { 1176 .ppt_pl1_spl_min = 15, 1177 .ppt_pl1_spl_max = 35, 1178 .ppt_pl2_sppt_min = 25, 1179 .ppt_pl2_sppt_max = 35, 1180 .ppt_pl3_fppt_min = 35, 1181 .ppt_pl3_fppt_max = 65, 1182 .nv_temp_target_min = 75, 1183 .nv_temp_target_max = 87, 1184 }, 1185 .requires_fan_curve = true, 1186 }, 1187 }, 1188 { 1189 .matches = { 1190 DMI_MATCH(DMI_BOARD_NAME, "GA403UM"), 1191 }, 1192 .driver_data = &(struct power_data) { 1193 .ac_data = &(struct power_limits) { 1194 .ppt_pl1_spl_min = 15, 1195 .ppt_pl1_spl_max = 80, 1196 .ppt_pl2_sppt_min = 25, 1197 .ppt_pl2_sppt_max = 80, 1198 .ppt_pl3_fppt_min = 35, 1199 .ppt_pl3_fppt_max = 80, 1200 .nv_dynamic_boost_min = 0, 1201 .nv_dynamic_boost_max = 15, 1202 .nv_temp_target_min = 75, 1203 .nv_temp_target_max = 87, 1204 .nv_tgp_min = 55, 1205 .nv_tgp_max = 85, 1206 }, 1207 .dc_data = &(struct power_limits) { 1208 .ppt_pl1_spl_min = 15, 1209 .ppt_pl1_spl_max = 35, 1210 .ppt_pl2_sppt_min = 25, 1211 .ppt_pl2_sppt_max = 35, 1212 .ppt_pl3_fppt_min = 35, 1213 .ppt_pl3_fppt_max = 65, 1214 .nv_temp_target_min = 75, 1215 .nv_temp_target_max = 87, 1216 }, 1217 .requires_fan_curve = true, 1218 }, 1219 }, 1220 { 1221 .matches = { 1222 DMI_MATCH(DMI_BOARD_NAME, "GA403UV"), 1223 }, 1224 .driver_data = &(struct power_data) { 1225 .ac_data = &(struct power_limits) { 1226 .ppt_pl1_spl_min = 15, 1227 .ppt_pl1_spl_max = 80, 1228 .ppt_pl2_sppt_min = 25, 1229 .ppt_pl2_sppt_max = 80, 1230 .ppt_pl3_fppt_min = 35, 1231 .ppt_pl3_fppt_max = 80, 1232 .nv_dynamic_boost_min = 5, 1233 .nv_dynamic_boost_max = 25, 1234 .nv_temp_target_min = 75, 1235 .nv_temp_target_max = 87, 1236 .nv_tgp_min = 55, 1237 .nv_tgp_max = 65, 1238 }, 1239 .dc_data = &(struct power_limits) { 1240 .ppt_pl1_spl_min = 15, 1241 .ppt_pl1_spl_max = 35, 1242 .ppt_pl2_sppt_min = 25, 1243 .ppt_pl2_sppt_max = 35, 1244 .ppt_pl3_fppt_min = 35, 1245 .ppt_pl3_fppt_max = 65, 1246 .nv_temp_target_min = 75, 1247 .nv_temp_target_max = 87, 1248 }, 1249 .requires_fan_curve = true, 1250 }, 1251 }, 1252 { 1253 .matches = { 1254 DMI_MATCH(DMI_BOARD_NAME, "GA403WM"), 1255 }, 1256 .driver_data = &(struct power_data) { 1257 .ac_data = &(struct power_limits) { 1258 .ppt_pl1_spl_min = 15, 1259 .ppt_pl1_spl_max = 80, 1260 .ppt_pl2_sppt_min = 25, 1261 .ppt_pl2_sppt_max = 80, 1262 .ppt_pl3_fppt_min = 35, 1263 .ppt_pl3_fppt_max = 80, 1264 .nv_dynamic_boost_min = 0, 1265 .nv_dynamic_boost_max = 15, 1266 .nv_temp_target_min = 75, 1267 .nv_temp_target_max = 87, 1268 .nv_tgp_min = 55, 1269 .nv_tgp_max = 85, 1270 }, 1271 .dc_data = &(struct power_limits) { 1272 .ppt_pl1_spl_min = 15, 1273 .ppt_pl1_spl_max = 35, 1274 .ppt_pl2_sppt_min = 25, 1275 .ppt_pl2_sppt_max = 35, 1276 .ppt_pl3_fppt_min = 35, 1277 .ppt_pl3_fppt_max = 65, 1278 .nv_temp_target_min = 75, 1279 .nv_temp_target_max = 87, 1280 }, 1281 .requires_fan_curve = true, 1282 }, 1283 }, 1284 { 1285 .matches = { 1286 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 1287 }, 1288 .driver_data = &(struct power_data) { 1289 .ac_data = &(struct power_limits) { 1290 .ppt_pl1_spl_min = 15, 1291 .ppt_pl1_spl_max = 80, 1292 .ppt_pl2_sppt_min = 25, 1293 .ppt_pl2_sppt_max = 80, 1294 .ppt_pl3_fppt_min = 35, 1295 .ppt_pl3_fppt_max = 80, 1296 .nv_dynamic_boost_min = 0, 1297 .nv_dynamic_boost_max = 25, 1298 .nv_temp_target_min = 75, 1299 .nv_temp_target_max = 87, 1300 .nv_tgp_min = 80, 1301 .nv_tgp_max = 95, 1302 }, 1303 .dc_data = &(struct power_limits) { 1304 .ppt_pl1_spl_min = 15, 1305 .ppt_pl1_spl_max = 35, 1306 .ppt_pl2_sppt_min = 25, 1307 .ppt_pl2_sppt_max = 35, 1308 .ppt_pl3_fppt_min = 35, 1309 .ppt_pl3_fppt_max = 65, 1310 .nv_temp_target_min = 75, 1311 .nv_temp_target_max = 87, 1312 }, 1313 .requires_fan_curve = true, 1314 }, 1315 }, 1316 { 1317 .matches = { 1318 DMI_MATCH(DMI_BOARD_NAME, "GA403WW"), 1319 }, 1320 .driver_data = &(struct power_data) { 1321 .ac_data = &(struct power_limits) { 1322 .ppt_pl1_spl_min = 15, 1323 .ppt_pl1_spl_max = 80, 1324 .ppt_pl2_sppt_min = 25, 1325 .ppt_pl2_sppt_max = 80, 1326 .ppt_pl3_fppt_min = 35, 1327 .ppt_pl3_fppt_max = 80, 1328 .nv_dynamic_boost_min = 0, 1329 .nv_dynamic_boost_max = 25, 1330 .nv_temp_target_min = 75, 1331 .nv_temp_target_max = 87, 1332 .nv_tgp_min = 80, 1333 .nv_tgp_max = 95, 1334 }, 1335 .dc_data = &(struct power_limits) { 1336 .ppt_pl1_spl_min = 15, 1337 .ppt_pl1_spl_max = 35, 1338 .ppt_pl2_sppt_min = 25, 1339 .ppt_pl2_sppt_max = 35, 1340 .ppt_pl3_fppt_min = 35, 1341 .ppt_pl3_fppt_max = 65, 1342 .nv_temp_target_min = 75, 1343 .nv_temp_target_max = 87, 1344 }, 1345 .requires_fan_curve = true, 1346 }, 1347 }, 1348 { 1349 .matches = { 1350 DMI_MATCH(DMI_BOARD_NAME, "GA503QM"), 1351 }, 1352 .driver_data = &(struct power_data) { 1353 .ac_data = &(struct power_limits) { 1354 .ppt_pl1_spl_min = 15, 1355 .ppt_pl1_spl_def = 35, 1356 .ppt_pl1_spl_max = 80, 1357 .ppt_pl2_sppt_min = 65, 1358 .ppt_pl2_sppt_max = 80, 1359 }, 1360 }, 1361 }, 1362 { 1363 .matches = { 1364 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 1365 }, 1366 .driver_data = &(struct power_data) { 1367 .ac_data = &(struct power_limits) { 1368 .ppt_pl1_spl_min = 15, 1369 .ppt_pl1_spl_def = 35, 1370 .ppt_pl1_spl_max = 80, 1371 .ppt_pl2_sppt_min = 65, 1372 .ppt_pl2_sppt_max = 80, 1373 }, 1374 }, 1375 }, 1376 { 1377 .matches = { 1378 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 1379 }, 1380 .driver_data = &(struct power_data) { 1381 .ac_data = &(struct power_limits) { 1382 .ppt_pl1_spl_min = 15, 1383 .ppt_pl1_spl_def = 35, 1384 .ppt_pl1_spl_max = 80, 1385 .ppt_pl2_sppt_min = 35, 1386 .ppt_pl2_sppt_def = 65, 1387 .ppt_pl2_sppt_max = 80, 1388 .ppt_pl3_fppt_min = 35, 1389 .ppt_pl3_fppt_max = 80, 1390 .nv_dynamic_boost_min = 5, 1391 .nv_dynamic_boost_max = 20, 1392 .nv_temp_target_min = 75, 1393 .nv_temp_target_max = 87, 1394 }, 1395 .dc_data = &(struct power_limits) { 1396 .ppt_pl1_spl_min = 15, 1397 .ppt_pl1_spl_def = 25, 1398 .ppt_pl1_spl_max = 65, 1399 .ppt_pl2_sppt_min = 35, 1400 .ppt_pl2_sppt_def = 54, 1401 .ppt_pl2_sppt_max = 60, 1402 .ppt_pl3_fppt_min = 35, 1403 .ppt_pl3_fppt_max = 65, 1404 }, 1405 }, 1406 }, 1407 { 1408 .matches = { 1409 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 1410 }, 1411 .driver_data = &(struct power_data) { 1412 .ac_data = &(struct power_limits) { 1413 .ppt_pl1_spl_min = 15, 1414 .ppt_pl1_spl_max = 80, 1415 .ppt_pl2_sppt_min = 35, 1416 .ppt_pl2_sppt_max = 80, 1417 .ppt_pl3_fppt_min = 35, 1418 .ppt_pl3_fppt_max = 80, 1419 .nv_dynamic_boost_min = 5, 1420 .nv_dynamic_boost_max = 20, 1421 .nv_temp_target_min = 75, 1422 .nv_temp_target_max = 87, 1423 .nv_tgp_min = 55, 1424 .nv_tgp_max = 85, 1425 }, 1426 .dc_data = &(struct power_limits) { 1427 .ppt_pl1_spl_min = 25, 1428 .ppt_pl1_spl_max = 35, 1429 .ppt_pl2_sppt_min = 31, 1430 .ppt_pl2_sppt_max = 44, 1431 .ppt_pl3_fppt_min = 45, 1432 .ppt_pl3_fppt_max = 65, 1433 .nv_temp_target_min = 75, 1434 .nv_temp_target_max = 87, 1435 }, 1436 .requires_fan_curve = true, 1437 }, 1438 }, 1439 { 1440 .matches = { 1441 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 1442 }, 1443 .driver_data = &(struct power_data) { 1444 .ac_data = &(struct power_limits) { 1445 .ppt_pl1_spl_min = 25, 1446 .ppt_pl1_spl_max = 60, 1447 .ppt_pl2_sppt_min = 25, 1448 .ppt_pl2_sppt_max = 135, 1449 .nv_dynamic_boost_min = 5, 1450 .nv_dynamic_boost_max = 20, 1451 .nv_temp_target_min = 75, 1452 .nv_temp_target_max = 87, 1453 }, 1454 .dc_data = &(struct power_limits) { 1455 .ppt_pl1_spl_min = 25, 1456 .ppt_pl1_spl_max = 40, 1457 .ppt_pl2_sppt_min = 25, 1458 .ppt_pl2_sppt_max = 40, 1459 .nv_temp_target_min = 75, 1460 .nv_temp_target_max = 87, 1461 } 1462 }, 1463 }, 1464 { 1465 .matches = { 1466 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1467 }, 1468 .driver_data = &(struct power_data) { 1469 .ac_data = &(struct power_limits) { 1470 .ppt_pl1_spl_min = 65, 1471 .ppt_pl1_spl_max = 120, 1472 .ppt_pl2_sppt_min = 65, 1473 .ppt_pl2_sppt_max = 150, 1474 .nv_dynamic_boost_min = 5, 1475 .nv_dynamic_boost_max = 25, 1476 .nv_temp_target_min = 75, 1477 .nv_temp_target_max = 87, 1478 }, 1479 .dc_data = &(struct power_limits) { 1480 .ppt_pl1_spl_min = 25, 1481 .ppt_pl1_spl_max = 40, 1482 .ppt_pl2_sppt_min = 35, 1483 .ppt_pl2_sppt_def = 40, 1484 .ppt_pl2_sppt_max = 60, 1485 .nv_temp_target_min = 75, 1486 .nv_temp_target_max = 87, 1487 }, 1488 }, 1489 }, 1490 { 1491 .matches = { 1492 DMI_MATCH(DMI_BOARD_NAME, "GU605CP"), 1493 }, 1494 .driver_data = &(struct power_data) { 1495 .ac_data = &(struct power_limits) { 1496 .ppt_pl1_spl_min = 45, 1497 .ppt_pl1_spl_max = 75, 1498 .ppt_pl2_sppt_min = 56, 1499 .ppt_pl2_sppt_max = 95, 1500 .nv_dynamic_boost_min = 5, 1501 .nv_dynamic_boost_max = 15, 1502 .nv_temp_target_min = 75, 1503 .nv_temp_target_max = 87, 1504 .nv_tgp_min = 55, 1505 .nv_tgp_def = 75, 1506 .nv_tgp_max = 95, 1507 }, 1508 .dc_data = &(struct power_limits) { 1509 .ppt_pl1_spl_min = 25, 1510 .ppt_pl1_spl_max = 75, 1511 .ppt_pl2_sppt_min = 32, 1512 .ppt_pl2_sppt_max = 95, 1513 .nv_temp_target_min = 75, 1514 .nv_temp_target_max = 87, 1515 }, 1516 .requires_fan_curve = true, 1517 }, 1518 }, 1519 { 1520 .matches = { 1521 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1522 }, 1523 .driver_data = &(struct power_data) { 1524 .ac_data = &(struct power_limits) { 1525 .ppt_pl1_spl_min = 30, 1526 .ppt_pl1_spl_max = 85, 1527 .ppt_pl2_sppt_min = 38, 1528 .ppt_pl2_sppt_max = 110, 1529 .nv_dynamic_boost_min = 5, 1530 .nv_dynamic_boost_max = 20, 1531 .nv_temp_target_min = 75, 1532 .nv_temp_target_max = 87, 1533 .nv_tgp_min = 80, 1534 .nv_tgp_def = 90, 1535 .nv_tgp_max = 105, 1536 }, 1537 .dc_data = &(struct power_limits) { 1538 .ppt_pl1_spl_min = 30, 1539 .ppt_pl1_spl_max = 85, 1540 .ppt_pl2_sppt_min = 38, 1541 .ppt_pl2_sppt_max = 110, 1542 .nv_temp_target_min = 75, 1543 .nv_temp_target_max = 87, 1544 }, 1545 .requires_fan_curve = true, 1546 }, 1547 }, 1548 { 1549 .matches = { 1550 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1551 }, 1552 .driver_data = &(struct power_data) { 1553 .ac_data = &(struct power_limits) { 1554 .ppt_pl1_spl_min = 45, 1555 .ppt_pl1_spl_max = 85, 1556 .ppt_pl2_sppt_min = 56, 1557 .ppt_pl2_sppt_max = 110, 1558 .nv_dynamic_boost_min = 5, 1559 .nv_dynamic_boost_max = 20, 1560 .nv_temp_target_min = 75, 1561 .nv_temp_target_max = 87, 1562 .nv_tgp_min = 80, 1563 .nv_tgp_def = 90, 1564 .nv_tgp_max = 110, 1565 }, 1566 .dc_data = &(struct power_limits) { 1567 .ppt_pl1_spl_min = 25, 1568 .ppt_pl1_spl_max = 85, 1569 .ppt_pl2_sppt_min = 32, 1570 .ppt_pl2_sppt_max = 110, 1571 .nv_temp_target_min = 75, 1572 .nv_temp_target_max = 87, 1573 }, 1574 .requires_fan_curve = true, 1575 }, 1576 }, 1577 { 1578 .matches = { 1579 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1580 }, 1581 .driver_data = &(struct power_data) { 1582 .ac_data = &(struct power_limits) { 1583 .ppt_pl1_spl_min = 45, 1584 .ppt_pl1_spl_max = 85, 1585 .ppt_pl2_sppt_min = 56, 1586 .ppt_pl2_sppt_max = 110, 1587 .nv_dynamic_boost_min = 5, 1588 .nv_dynamic_boost_max = 20, 1589 .nv_temp_target_min = 7, 1590 .nv_temp_target_max = 87, 1591 .nv_tgp_min = 95, 1592 .nv_tgp_def = 100, 1593 .nv_tgp_max = 110, 1594 }, 1595 .dc_data = &(struct power_limits) { 1596 .ppt_pl1_spl_min = 25, 1597 .ppt_pl1_spl_max = 85, 1598 .ppt_pl2_sppt_min = 32, 1599 .ppt_pl2_sppt_max = 110, 1600 .nv_temp_target_min = 75, 1601 .nv_temp_target_max = 87, 1602 }, 1603 .requires_fan_curve = true, 1604 }, 1605 }, 1606 { 1607 .matches = { 1608 DMI_MATCH(DMI_BOARD_NAME, "GU605MU"), 1609 }, 1610 .driver_data = &(struct power_data) { 1611 .ac_data = &(struct power_limits) { 1612 .ppt_pl1_spl_min = 28, 1613 .ppt_pl1_spl_max = 90, 1614 .ppt_pl2_sppt_min = 28, 1615 .ppt_pl2_sppt_max = 135, 1616 .nv_dynamic_boost_min = 5, 1617 .nv_dynamic_boost_max = 20, 1618 .nv_temp_target_min = 75, 1619 .nv_temp_target_max = 87, 1620 .nv_tgp_min = 55, 1621 .nv_tgp_max = 85, 1622 }, 1623 .dc_data = &(struct power_limits) { 1624 .ppt_pl1_spl_min = 25, 1625 .ppt_pl1_spl_max = 35, 1626 .ppt_pl2_sppt_min = 38, 1627 .ppt_pl2_sppt_max = 53, 1628 .nv_temp_target_min = 75, 1629 .nv_temp_target_max = 87, 1630 }, 1631 .requires_fan_curve = true, 1632 }, 1633 }, 1634 { 1635 .matches = { 1636 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1637 }, 1638 .driver_data = &(struct power_data) { 1639 .ac_data = &(struct power_limits) { 1640 .ppt_pl1_spl_min = 28, 1641 .ppt_pl1_spl_max = 90, 1642 .ppt_pl2_sppt_min = 28, 1643 .ppt_pl2_sppt_max = 135, 1644 .nv_dynamic_boost_min = 5, 1645 .nv_dynamic_boost_max = 20, 1646 .nv_temp_target_min = 75, 1647 .nv_temp_target_max = 87, 1648 }, 1649 .dc_data = &(struct power_limits) { 1650 .ppt_pl1_spl_min = 25, 1651 .ppt_pl1_spl_max = 35, 1652 .ppt_pl2_sppt_min = 38, 1653 .ppt_pl2_sppt_max = 53, 1654 .nv_temp_target_min = 75, 1655 .nv_temp_target_max = 87, 1656 }, 1657 .requires_fan_curve = true, 1658 }, 1659 }, 1660 { 1661 .matches = { 1662 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1663 }, 1664 .driver_data = &(struct power_data) { 1665 .ac_data = &(struct power_limits) { 1666 .ppt_pl1_spl_min = 15, 1667 .ppt_pl1_spl_max = 45, 1668 .ppt_pl2_sppt_min = 65, 1669 .ppt_pl2_sppt_max = 80, 1670 }, 1671 .dc_data = NULL, 1672 }, 1673 }, 1674 { 1675 .matches = { 1676 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1677 }, 1678 .driver_data = &(struct power_data) { 1679 .ac_data = &(struct power_limits) { 1680 .ppt_pl1_spl_min = 15, 1681 .ppt_pl1_spl_max = 45, 1682 .ppt_pl2_sppt_min = 25, 1683 .ppt_pl2_sppt_max = 54, 1684 .ppt_pl3_fppt_min = 35, 1685 .ppt_pl3_fppt_max = 65, 1686 .nv_temp_target_min = 75, 1687 .nv_temp_target_max = 87, 1688 }, 1689 .dc_data = &(struct power_limits) { 1690 .ppt_pl1_spl_min = 15, 1691 .ppt_pl1_spl_max = 35, 1692 .ppt_pl2_sppt_min = 25, 1693 .ppt_pl2_sppt_max = 35, 1694 .ppt_pl3_fppt_min = 35, 1695 .ppt_pl3_fppt_max = 65, 1696 .nv_temp_target_min = 75, 1697 .nv_temp_target_max = 87, 1698 }, 1699 }, 1700 }, 1701 { 1702 .matches = { 1703 DMI_MATCH(DMI_BOARD_NAME, "GV302XU"), 1704 }, 1705 .driver_data = &(struct power_data) { 1706 .ac_data = &(struct power_limits) { 1707 .ppt_pl1_spl_min = 15, 1708 .ppt_pl1_spl_max = 55, 1709 .ppt_pl2_sppt_min = 25, 1710 .ppt_pl2_sppt_max = 60, 1711 .ppt_pl3_fppt_min = 35, 1712 .ppt_pl3_fppt_max = 65, 1713 .nv_temp_target_min = 75, 1714 .nv_temp_target_max = 87, 1715 }, 1716 .dc_data = &(struct power_limits) { 1717 .ppt_pl1_spl_min = 15, 1718 .ppt_pl1_spl_max = 35, 1719 .ppt_pl2_sppt_min = 25, 1720 .ppt_pl2_sppt_max = 35, 1721 .ppt_pl3_fppt_min = 35, 1722 .ppt_pl3_fppt_max = 65, 1723 .nv_temp_target_min = 75, 1724 .nv_temp_target_max = 87, 1725 }, 1726 }, 1727 }, 1728 { 1729 .matches = { 1730 DMI_MATCH(DMI_BOARD_NAME, "GV302XV"), 1731 }, 1732 .driver_data = &(struct power_data) { 1733 .ac_data = &(struct power_limits) { 1734 .ppt_pl1_spl_min = 15, 1735 .ppt_pl1_spl_max = 55, 1736 .ppt_pl2_sppt_min = 25, 1737 .ppt_pl2_sppt_max = 60, 1738 .ppt_pl3_fppt_min = 35, 1739 .ppt_pl3_fppt_max = 65, 1740 .nv_temp_target_min = 75, 1741 .nv_temp_target_max = 87, 1742 }, 1743 .dc_data = &(struct power_limits) { 1744 .ppt_pl1_spl_min = 15, 1745 .ppt_pl1_spl_max = 35, 1746 .ppt_pl2_sppt_min = 25, 1747 .ppt_pl2_sppt_max = 35, 1748 .ppt_pl3_fppt_min = 35, 1749 .ppt_pl3_fppt_max = 65, 1750 .nv_temp_target_min = 75, 1751 .nv_temp_target_max = 87, 1752 }, 1753 }, 1754 }, 1755 { 1756 .matches = { 1757 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1758 }, 1759 .driver_data = &(struct power_data) { 1760 .ac_data = &(struct power_limits) { 1761 .ppt_pl1_spl_min = 15, 1762 .ppt_pl1_spl_def = 35, 1763 .ppt_pl1_spl_max = 90, 1764 .ppt_pl2_sppt_min = 35, 1765 .ppt_pl2_sppt_def = 54, 1766 .ppt_pl2_sppt_max = 100, 1767 .ppt_pl3_fppt_min = 35, 1768 .ppt_pl3_fppt_def = 80, 1769 .ppt_pl3_fppt_max = 125, 1770 .nv_dynamic_boost_min = 5, 1771 .nv_dynamic_boost_max = 25, 1772 .nv_temp_target_min = 75, 1773 .nv_temp_target_max = 87, 1774 }, 1775 .dc_data = &(struct power_limits) { 1776 .ppt_pl1_spl_min = 15, 1777 .ppt_pl1_spl_def = 28, 1778 .ppt_pl1_spl_max = 65, 1779 .ppt_pl2_sppt_min = 35, 1780 .ppt_pl2_sppt_def = 54, 1781 .ppt_pl2_sppt_max = 60, 1782 .ppt_pl3_fppt_min = 35, 1783 .ppt_pl3_fppt_def = 80, 1784 .ppt_pl3_fppt_max = 65, 1785 .nv_temp_target_min = 75, 1786 .nv_temp_target_max = 87, 1787 }, 1788 }, 1789 }, 1790 { 1791 .matches = { 1792 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1793 }, 1794 .driver_data = &(struct power_data) { 1795 .ac_data = &(struct power_limits) { 1796 .ppt_pl1_spl_min = 28, 1797 .ppt_pl1_spl_def = 100, 1798 .ppt_pl1_spl_max = 110, 1799 .ppt_pl2_sppt_min = 28, 1800 .ppt_pl2_sppt_max = 135, 1801 .nv_dynamic_boost_min = 5, 1802 .nv_dynamic_boost_max = 20, 1803 .nv_temp_target_min = 75, 1804 .nv_temp_target_max = 87, 1805 }, 1806 .dc_data = &(struct power_limits) { 1807 .ppt_pl1_spl_min = 25, 1808 .ppt_pl1_spl_max = 40, 1809 .ppt_pl2_sppt_min = 35, 1810 .ppt_pl2_sppt_def = 40, 1811 .ppt_pl2_sppt_max = 60, 1812 .nv_temp_target_min = 75, 1813 .nv_temp_target_max = 87, 1814 }, 1815 }, 1816 }, 1817 { 1818 .matches = { 1819 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1820 }, 1821 .driver_data = &(struct power_data) { 1822 .ac_data = &(struct power_limits) { 1823 .ppt_pl1_spl_min = 15, 1824 .ppt_pl1_spl_def = 110, 1825 .ppt_pl1_spl_max = 130, 1826 .ppt_pl2_sppt_min = 35, 1827 .ppt_pl2_sppt_def = 125, 1828 .ppt_pl2_sppt_max = 130, 1829 .ppt_pl3_fppt_min = 35, 1830 .ppt_pl3_fppt_def = 125, 1831 .ppt_pl3_fppt_max = 135, 1832 .nv_dynamic_boost_min = 5, 1833 .nv_dynamic_boost_max = 25, 1834 .nv_temp_target_min = 75, 1835 .nv_temp_target_max = 87, 1836 }, 1837 .dc_data = &(struct power_limits) { 1838 .ppt_pl1_spl_min = 15, 1839 .ppt_pl1_spl_def = 25, 1840 .ppt_pl1_spl_max = 65, 1841 .ppt_pl2_sppt_min = 35, 1842 .ppt_pl2_sppt_def = 35, 1843 .ppt_pl2_sppt_max = 65, 1844 .ppt_pl3_fppt_min = 35, 1845 .ppt_pl3_fppt_def = 42, 1846 .ppt_pl3_fppt_max = 65, 1847 .nv_temp_target_min = 75, 1848 .nv_temp_target_max = 87, 1849 }, 1850 }, 1851 }, 1852 { 1853 .matches = { 1854 DMI_MATCH(DMI_BOARD_NAME, "GX650RX"), 1855 }, 1856 .driver_data = &(struct power_data) { 1857 .ac_data = &(struct power_limits) { 1858 .ppt_pl1_spl_min = 28, 1859 .ppt_pl1_spl_def = 70, 1860 .ppt_pl1_spl_max = 90, 1861 .ppt_pl2_sppt_min = 28, 1862 .ppt_pl2_sppt_def = 70, 1863 .ppt_pl2_sppt_max = 100, 1864 .ppt_pl3_fppt_min = 28, 1865 .ppt_pl3_fppt_def = 110, 1866 .ppt_pl3_fppt_max = 125, 1867 .nv_dynamic_boost_min = 5, 1868 .nv_dynamic_boost_max = 25, 1869 .nv_temp_target_min = 76, 1870 .nv_temp_target_max = 87, 1871 }, 1872 .dc_data = &(struct power_limits) { 1873 .ppt_pl1_spl_min = 28, 1874 .ppt_pl1_spl_max = 50, 1875 .ppt_pl2_sppt_min = 28, 1876 .ppt_pl2_sppt_max = 50, 1877 .ppt_pl3_fppt_min = 28, 1878 .ppt_pl3_fppt_max = 65, 1879 .nv_temp_target_min = 76, 1880 .nv_temp_target_max = 87, 1881 }, 1882 }, 1883 }, 1884 { 1885 .matches = { 1886 DMI_MATCH(DMI_BOARD_NAME, "GZ302EA"), 1887 }, 1888 .driver_data = &(struct power_data) { 1889 .ac_data = &(struct power_limits) { 1890 .ppt_pl1_spl_min = 28, 1891 .ppt_pl1_spl_def = 60, 1892 .ppt_pl1_spl_max = 80, 1893 .ppt_pl2_sppt_min = 32, 1894 .ppt_pl2_sppt_def = 75, 1895 .ppt_pl2_sppt_max = 92, 1896 .ppt_pl3_fppt_min = 45, 1897 .ppt_pl3_fppt_def = 86, 1898 .ppt_pl3_fppt_max = 93, 1899 }, 1900 .dc_data = &(struct power_limits) { 1901 .ppt_pl1_spl_min = 28, 1902 .ppt_pl1_spl_def = 45, 1903 .ppt_pl1_spl_max = 80, 1904 .ppt_pl2_sppt_min = 32, 1905 .ppt_pl2_sppt_def = 52, 1906 .ppt_pl2_sppt_max = 92, 1907 .ppt_pl3_fppt_min = 45, 1908 .ppt_pl3_fppt_def = 71, 1909 .ppt_pl3_fppt_max = 93, 1910 }, 1911 }, 1912 }, 1913 { 1914 .matches = { 1915 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1916 }, 1917 .driver_data = &(struct power_data) { 1918 .ac_data = &(struct power_limits) { 1919 /* Yes this laptop is very limited */ 1920 .ppt_pl1_spl_min = 15, 1921 .ppt_pl1_spl_max = 80, 1922 .ppt_pl2_sppt_min = 15, 1923 .ppt_pl2_sppt_max = 80, 1924 }, 1925 .dc_data = NULL, 1926 .requires_fan_curve = true, 1927 }, 1928 }, 1929 { 1930 .matches = { 1931 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1932 }, 1933 .driver_data = &(struct power_data) { 1934 .ac_data = &(struct power_limits) { 1935 /* Yes this laptop is very limited */ 1936 .ppt_pl1_spl_min = 15, 1937 .ppt_pl1_spl_max = 100, 1938 .ppt_pl2_sppt_min = 15, 1939 .ppt_pl2_sppt_max = 190, 1940 }, 1941 .dc_data = NULL, 1942 .requires_fan_curve = true, 1943 }, 1944 }, 1945 { 1946 .matches = { 1947 DMI_MATCH(DMI_BOARD_NAME, "G513QY"), 1948 }, 1949 .driver_data = &(struct power_data) { 1950 .ac_data = &(struct power_limits) { 1951 /* Advantage Edition Laptop, no PL1 or PL2 limits */ 1952 .ppt_apu_sppt_min = 15, 1953 .ppt_apu_sppt_max = 100, 1954 .ppt_platform_sppt_min = 70, 1955 .ppt_platform_sppt_max = 190, 1956 }, 1957 .dc_data = NULL, 1958 .requires_fan_curve = true, 1959 }, 1960 }, 1961 { 1962 .matches = { 1963 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1964 }, 1965 .driver_data = &(struct power_data) { 1966 .ac_data = &(struct power_limits) { 1967 .ppt_pl1_spl_min = 35, 1968 .ppt_pl1_spl_max = 90, 1969 .ppt_pl2_sppt_min = 54, 1970 .ppt_pl2_sppt_max = 100, 1971 .ppt_pl3_fppt_min = 54, 1972 .ppt_pl3_fppt_max = 125, 1973 .nv_dynamic_boost_min = 5, 1974 .nv_dynamic_boost_max = 25, 1975 .nv_temp_target_min = 75, 1976 .nv_temp_target_max = 87, 1977 }, 1978 .dc_data = &(struct power_limits) { 1979 .ppt_pl1_spl_min = 28, 1980 .ppt_pl1_spl_max = 50, 1981 .ppt_pl2_sppt_min = 28, 1982 .ppt_pl2_sppt_max = 50, 1983 .ppt_pl3_fppt_min = 28, 1984 .ppt_pl3_fppt_max = 65, 1985 .nv_temp_target_min = 75, 1986 .nv_temp_target_max = 87, 1987 }, 1988 .requires_fan_curve = true, 1989 }, 1990 }, 1991 { 1992 .matches = { 1993 DMI_MATCH(DMI_BOARD_NAME, "G614FP"), 1994 }, 1995 .driver_data = &(struct power_data) { 1996 .ac_data = &(struct power_limits) { 1997 .ppt_pl1_spl_min = 30, 1998 .ppt_pl1_spl_max = 120, 1999 .ppt_pl2_sppt_min = 65, 2000 .ppt_pl2_sppt_def = 140, 2001 .ppt_pl2_sppt_max = 165, 2002 .ppt_pl3_fppt_min = 65, 2003 .ppt_pl3_fppt_def = 140, 2004 .ppt_pl3_fppt_max = 165, 2005 .nv_temp_target_min = 75, 2006 .nv_temp_target_max = 87, 2007 .nv_dynamic_boost_min = 5, 2008 .nv_dynamic_boost_max = 15, 2009 .nv_tgp_min = 50, 2010 .nv_tgp_max = 100, 2011 }, 2012 .dc_data = &(struct power_limits) { 2013 .ppt_pl1_spl_min = 25, 2014 .ppt_pl1_spl_max = 65, 2015 .ppt_pl2_sppt_min = 25, 2016 .ppt_pl2_sppt_max = 65, 2017 .ppt_pl3_fppt_min = 35, 2018 .ppt_pl3_fppt_max = 75, 2019 .nv_temp_target_min = 75, 2020 .nv_temp_target_max = 87, 2021 }, 2022 .requires_fan_curve = true, 2023 }, 2024 }, 2025 { 2026 .matches = { 2027 DMI_MATCH(DMI_BOARD_NAME, "G614FR"), 2028 }, 2029 .driver_data = &(struct power_data) { 2030 .ac_data = &(struct power_limits) { 2031 .ppt_pl1_spl_min = 30, 2032 .ppt_pl1_spl_max = 120, 2033 .ppt_pl2_sppt_min = 65, 2034 .ppt_pl2_sppt_def = 140, 2035 .ppt_pl2_sppt_max = 162, 2036 .ppt_pl3_fppt_min = 65, 2037 .ppt_pl3_fppt_def = 140, 2038 .ppt_pl3_fppt_max = 162, 2039 .nv_temp_target_min = 75, 2040 .nv_temp_target_max = 87, 2041 .nv_dynamic_boost_min = 5, 2042 .nv_dynamic_boost_max = 25, 2043 .nv_tgp_min = 65, 2044 .nv_tgp_max = 115, 2045 }, 2046 .dc_data = &(struct power_limits) { 2047 .ppt_pl1_spl_min = 25, 2048 .ppt_pl1_spl_max = 65, 2049 .ppt_pl2_sppt_min = 25, 2050 .ppt_pl2_sppt_max = 65, 2051 .ppt_pl3_fppt_min = 35, 2052 .ppt_pl3_fppt_max = 75, 2053 .nv_temp_target_min = 75, 2054 .nv_temp_target_max = 87, 2055 }, 2056 .requires_fan_curve = true, 2057 }, 2058 }, 2059 { 2060 .matches = { 2061 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 2062 }, 2063 .driver_data = &(struct power_data) { 2064 .ac_data = &(struct power_limits) { 2065 .ppt_pl1_spl_min = 28, 2066 .ppt_pl1_spl_max = 140, 2067 .ppt_pl2_sppt_min = 28, 2068 .ppt_pl2_sppt_max = 175, 2069 .nv_temp_target_min = 75, 2070 .nv_temp_target_max = 87, 2071 .nv_dynamic_boost_min = 5, 2072 .nv_dynamic_boost_max = 25, 2073 }, 2074 .dc_data = &(struct power_limits) { 2075 .ppt_pl1_spl_min = 25, 2076 .ppt_pl1_spl_max = 55, 2077 .ppt_pl2_sppt_min = 25, 2078 .ppt_pl2_sppt_max = 70, 2079 .nv_temp_target_min = 75, 2080 .nv_temp_target_max = 87, 2081 }, 2082 .requires_fan_curve = true, 2083 }, 2084 }, 2085 { 2086 .matches = { 2087 DMI_MATCH(DMI_BOARD_NAME, "G614PR"), 2088 }, 2089 .driver_data = &(struct power_data) { 2090 .ac_data = &(struct power_limits) { 2091 .ppt_pl1_spl_min = 30, 2092 .ppt_pl1_spl_max = 120, 2093 .ppt_pl2_sppt_min = 65, 2094 .ppt_pl2_sppt_def = 140, 2095 .ppt_pl2_sppt_max = 145, 2096 .ppt_pl3_fppt_min = 65, 2097 .ppt_pl3_fppt_def = 140, 2098 .ppt_pl3_fppt_max = 145, 2099 .nv_temp_target_min = 75, 2100 .nv_temp_target_max = 87, 2101 .nv_dynamic_boost_min = 5, 2102 .nv_dynamic_boost_max = 25, 2103 .nv_tgp_min = 65, 2104 .nv_tgp_max = 115, 2105 }, 2106 .dc_data = &(struct power_limits) { 2107 .ppt_pl1_spl_min = 25, 2108 .ppt_pl1_spl_max = 65, 2109 .ppt_pl2_sppt_min = 25, 2110 .ppt_pl2_sppt_max = 65, 2111 .ppt_pl3_fppt_min = 35, 2112 .ppt_pl3_fppt_max = 75, 2113 .nv_temp_target_min = 75, 2114 .nv_temp_target_max = 87, 2115 }, 2116 .requires_fan_curve = true, 2117 }, 2118 }, 2119 { 2120 .matches = { 2121 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 2122 }, 2123 .driver_data = &(struct power_data) { 2124 .ac_data = &(struct power_limits) { 2125 .ppt_pl1_spl_min = 28, 2126 .ppt_pl1_spl_def = 140, 2127 .ppt_pl1_spl_max = 175, 2128 .ppt_pl2_sppt_min = 28, 2129 .ppt_pl2_sppt_max = 175, 2130 .nv_temp_target_min = 75, 2131 .nv_temp_target_max = 87, 2132 .nv_dynamic_boost_min = 5, 2133 .nv_dynamic_boost_max = 25, 2134 .nv_tgp_min = 65, 2135 .nv_tgp_max = 115, 2136 }, 2137 .dc_data = &(struct power_limits) { 2138 .ppt_pl1_spl_min = 25, 2139 .ppt_pl1_spl_max = 55, 2140 .ppt_pl2_sppt_min = 25, 2141 .ppt_pl2_sppt_max = 70, 2142 .nv_temp_target_min = 75, 2143 .nv_temp_target_max = 87, 2144 }, 2145 .requires_fan_curve = true, 2146 }, 2147 }, 2148 { 2149 .matches = { 2150 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 2151 }, 2152 .driver_data = &(struct power_data) { 2153 .ac_data = &(struct power_limits) { 2154 .ppt_pl1_spl_min = 28, 2155 .ppt_pl1_spl_max = 140, 2156 .ppt_pl2_sppt_min = 28, 2157 .ppt_pl2_sppt_max = 175, 2158 .nv_temp_target_min = 75, 2159 .nv_temp_target_max = 87, 2160 .nv_dynamic_boost_min = 5, 2161 .nv_dynamic_boost_max = 25, 2162 }, 2163 .dc_data = &(struct power_limits) { 2164 .ppt_pl1_spl_min = 25, 2165 .ppt_pl1_spl_max = 55, 2166 .ppt_pl2_sppt_min = 25, 2167 .ppt_pl2_sppt_max = 70, 2168 .nv_temp_target_min = 75, 2169 .nv_temp_target_max = 87, 2170 }, 2171 .requires_fan_curve = true, 2172 }, 2173 }, 2174 { 2175 .matches = { 2176 DMI_MATCH(DMI_BOARD_NAME, "G635LX"), 2177 }, 2178 .driver_data = &(struct power_data) { 2179 .ac_data = &(struct power_limits) { 2180 .ppt_pl1_spl_min = 28, 2181 .ppt_pl1_spl_def = 140, 2182 .ppt_pl1_spl_max = 175, 2183 .ppt_pl2_sppt_min = 28, 2184 .ppt_pl2_sppt_max = 175, 2185 .nv_dynamic_boost_min = 5, 2186 .nv_dynamic_boost_max = 25, 2187 .nv_temp_target_min = 75, 2188 .nv_temp_target_max = 87, 2189 .nv_tgp_min = 80, 2190 .nv_tgp_max = 150, 2191 }, 2192 .dc_data = &(struct power_limits) { 2193 .ppt_pl1_spl_min = 25, 2194 .ppt_pl1_spl_max = 55, 2195 .ppt_pl2_sppt_min = 25, 2196 .ppt_pl2_sppt_max = 70, 2197 .nv_temp_target_min = 75, 2198 .nv_temp_target_max = 87, 2199 }, 2200 .requires_fan_curve = true, 2201 }, 2202 }, 2203 { 2204 .matches = { 2205 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 2206 }, 2207 .driver_data = &(struct power_data) { 2208 .ac_data = &(struct power_limits) { 2209 .ppt_pl1_spl_min = 30, 2210 .ppt_pl1_spl_def = 120, 2211 .ppt_pl1_spl_max = 130, 2212 .ppt_pl2_sppt_min = 65, 2213 .ppt_pl2_sppt_def = 125, 2214 .ppt_pl2_sppt_max = 130, 2215 .ppt_pl3_fppt_min = 65, 2216 .ppt_pl3_fppt_def = 125, 2217 .ppt_pl3_fppt_max = 130, 2218 .nv_temp_target_min = 75, 2219 .nv_temp_target_max = 87, 2220 .nv_dynamic_boost_min = 5, 2221 .nv_dynamic_boost_max = 25, 2222 }, 2223 .dc_data = &(struct power_limits) { 2224 .ppt_pl1_spl_min = 25, 2225 .ppt_pl1_spl_max = 65, 2226 .ppt_pl2_sppt_min = 25, 2227 .ppt_pl2_sppt_max = 65, 2228 .ppt_pl3_fppt_min = 35, 2229 .ppt_pl3_fppt_max = 75, 2230 .nv_temp_target_min = 75, 2231 .nv_temp_target_max = 87, 2232 }, 2233 .requires_fan_curve = true, 2234 }, 2235 }, 2236 { 2237 .matches = { 2238 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 2239 }, 2240 .driver_data = &(struct power_data) { 2241 .ac_data = &(struct power_limits) { 2242 .ppt_pl1_spl_min = 28, 2243 .ppt_pl1_spl_max = 170, 2244 .ppt_pl2_sppt_min = 28, 2245 .ppt_pl2_sppt_max = 175, 2246 .nv_temp_target_min = 75, 2247 .nv_temp_target_max = 87, 2248 .nv_dynamic_boost_min = 5, 2249 .nv_dynamic_boost_max = 25, 2250 }, 2251 .dc_data = &(struct power_limits) { 2252 .ppt_pl1_spl_min = 28, 2253 .ppt_pl1_spl_max = 35, 2254 .ppt_pl2_sppt_min = 28, 2255 .ppt_pl2_sppt_max = 35, 2256 .nv_temp_target_min = 75, 2257 .nv_temp_target_max = 87, 2258 }, 2259 .requires_fan_curve = true, 2260 }, 2261 }, 2262 { 2263 .matches = { 2264 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 2265 }, 2266 .driver_data = &(struct power_data) { 2267 .ac_data = &(struct power_limits) { 2268 .ppt_pl1_spl_min = 30, 2269 .ppt_pl1_spl_def = 100, 2270 .ppt_pl1_spl_max = 130, 2271 .ppt_pl2_sppt_min = 65, 2272 .ppt_pl2_sppt_def = 125, 2273 .ppt_pl2_sppt_max = 130, 2274 .ppt_pl3_fppt_min = 65, 2275 .ppt_pl3_fppt_def = 125, 2276 .ppt_pl3_fppt_max = 130, 2277 .nv_temp_target_min = 75, 2278 .nv_temp_target_max = 87, 2279 .nv_dynamic_boost_min = 5, 2280 .nv_dynamic_boost_max = 25, 2281 }, 2282 .dc_data = &(struct power_limits) { 2283 .ppt_pl1_spl_min = 25, 2284 .ppt_pl1_spl_max = 65, 2285 .ppt_pl2_sppt_min = 25, 2286 .ppt_pl2_sppt_max = 65, 2287 .ppt_pl3_fppt_min = 35, 2288 .ppt_pl3_fppt_max = 75, 2289 .nv_temp_target_min = 75, 2290 .nv_temp_target_max = 87, 2291 }, 2292 .requires_fan_curve = true, 2293 }, 2294 }, 2295 { 2296 .matches = { 2297 DMI_MATCH(DMI_BOARD_NAME, "G733QS"), 2298 }, 2299 .driver_data = &(struct power_data) { 2300 .ac_data = &(struct power_limits) { 2301 .ppt_pl1_spl_min = 15, 2302 .ppt_pl1_spl_max = 80, 2303 .ppt_pl2_sppt_min = 15, 2304 .ppt_pl2_sppt_max = 80, 2305 }, 2306 .requires_fan_curve = false, 2307 }, 2308 }, 2309 { 2310 .matches = { 2311 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 2312 }, 2313 .driver_data = &(struct power_data) { 2314 .ac_data = &(struct power_limits) { 2315 .ppt_pl1_spl_min = 28, 2316 .ppt_pl1_spl_max = 140, 2317 .ppt_pl2_sppt_min = 28, 2318 .ppt_pl2_sppt_max = 140, 2319 .nv_dynamic_boost_min = 5, 2320 .nv_dynamic_boost_max = 25, 2321 }, 2322 .dc_data = &(struct power_limits) { 2323 .ppt_pl1_spl_min = 25, 2324 .ppt_pl1_spl_max = 55, 2325 .ppt_pl2_sppt_min = 25, 2326 .ppt_pl2_sppt_max = 70, 2327 }, 2328 .requires_fan_curve = true, 2329 }, 2330 }, 2331 { 2332 .matches = { 2333 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 2334 }, 2335 .driver_data = &(struct power_data) { 2336 .ac_data = &(struct power_limits) { 2337 .ppt_pl1_spl_min = 28, 2338 .ppt_pl1_spl_max = 140, 2339 .ppt_pl2_sppt_min = 28, 2340 .ppt_pl2_sppt_max = 175, 2341 .nv_dynamic_boost_min = 5, 2342 .nv_dynamic_boost_max = 25, 2343 .nv_temp_target_min = 75, 2344 .nv_temp_target_max = 87, 2345 }, 2346 .dc_data = &(struct power_limits) { 2347 .ppt_pl1_spl_min = 25, 2348 .ppt_pl1_spl_max = 55, 2349 .ppt_pl2_sppt_min = 25, 2350 .ppt_pl2_sppt_max = 70, 2351 .nv_temp_target_min = 75, 2352 .nv_temp_target_max = 87, 2353 }, 2354 .requires_fan_curve = true, 2355 }, 2356 }, 2357 { 2358 .matches = { 2359 DMI_MATCH(DMI_BOARD_NAME, "G835LR"), 2360 }, 2361 .driver_data = &(struct power_data) { 2362 .ac_data = &(struct power_limits) { 2363 .ppt_pl1_spl_min = 28, 2364 .ppt_pl1_spl_def = 140, 2365 .ppt_pl1_spl_max = 175, 2366 .ppt_pl2_sppt_min = 28, 2367 .ppt_pl2_sppt_max = 175, 2368 .nv_dynamic_boost_min = 5, 2369 .nv_dynamic_boost_max = 25, 2370 .nv_temp_target_min = 75, 2371 .nv_temp_target_max = 87, 2372 .nv_tgp_min = 65, 2373 .nv_tgp_max = 115, 2374 }, 2375 .dc_data = &(struct power_limits) { 2376 .ppt_pl1_spl_min = 25, 2377 .ppt_pl1_spl_max = 55, 2378 .ppt_pl2_sppt_min = 25, 2379 .ppt_pl2_sppt_max = 70, 2380 .nv_temp_target_min = 75, 2381 .nv_temp_target_max = 87, 2382 }, 2383 .requires_fan_curve = true, 2384 }, 2385 }, 2386 { 2387 .matches = { 2388 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 2389 }, 2390 .driver_data = &(struct power_data) { 2391 .ac_data = &(struct power_limits) { 2392 .ppt_pl1_spl_min = 28, 2393 .ppt_pl1_spl_def = 140, 2394 .ppt_pl1_spl_max = 175, 2395 .ppt_pl2_sppt_min = 28, 2396 .ppt_pl2_sppt_max = 175, 2397 .nv_dynamic_boost_min = 5, 2398 .nv_dynamic_boost_max = 25, 2399 .nv_temp_target_min = 75, 2400 .nv_temp_target_max = 87, 2401 .nv_tgp_min = 80, 2402 .nv_tgp_max = 150, 2403 }, 2404 .dc_data = &(struct power_limits) { 2405 .ppt_pl1_spl_min = 25, 2406 .ppt_pl1_spl_max = 55, 2407 .ppt_pl2_sppt_min = 25, 2408 .ppt_pl2_sppt_max = 70, 2409 .nv_temp_target_min = 75, 2410 .nv_temp_target_max = 87, 2411 }, 2412 .requires_fan_curve = true, 2413 }, 2414 }, 2415 { 2416 .matches = { 2417 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 2418 }, 2419 .driver_data = &(struct power_data) { 2420 .ac_data = &(struct power_limits) { 2421 .ppt_pl1_spl_min = 15, 2422 .ppt_pl1_spl_max = 80, 2423 .ppt_pl2_sppt_min = 35, 2424 .ppt_pl2_sppt_max = 80, 2425 .ppt_pl3_fppt_min = 35, 2426 .ppt_pl3_fppt_max = 80, 2427 .nv_dynamic_boost_min = 5, 2428 .nv_dynamic_boost_max = 20, 2429 .nv_temp_target_min = 75, 2430 .nv_temp_target_max = 87, 2431 .nv_tgp_min = 55, 2432 .nv_tgp_max = 85, 2433 }, 2434 .dc_data = &(struct power_limits) { 2435 .ppt_pl1_spl_min = 25, 2436 .ppt_pl1_spl_max = 35, 2437 .ppt_pl2_sppt_min = 31, 2438 .ppt_pl2_sppt_max = 44, 2439 .ppt_pl3_fppt_min = 45, 2440 .ppt_pl3_fppt_max = 65, 2441 .nv_temp_target_min = 75, 2442 .nv_temp_target_max = 87, 2443 }, 2444 }, 2445 }, 2446 { 2447 .matches = { 2448 DMI_MATCH(DMI_BOARD_NAME, "HN7306EA"), 2449 }, 2450 .driver_data = &(struct power_data) { 2451 .ac_data = &(struct power_limits) { 2452 .ppt_pl1_spl_min = 35, 2453 .ppt_pl1_spl_def = 60, 2454 .ppt_pl1_spl_max = 85, 2455 .ppt_pl2_sppt_min = 40, 2456 .ppt_pl2_sppt_def = 70, 2457 .ppt_pl2_sppt_max = 95, 2458 .ppt_pl3_fppt_min = 50, 2459 .ppt_pl3_fppt_def = 85, 2460 .ppt_pl3_fppt_max = 115, 2461 }, 2462 .dc_data = &(struct power_limits) { 2463 .ppt_pl1_spl_min = 35, 2464 .ppt_pl1_spl_def = 45, 2465 .ppt_pl1_spl_max = 60, 2466 .ppt_pl2_sppt_min = 40, 2467 .ppt_pl2_sppt_def = 55, 2468 .ppt_pl2_sppt_max = 70, 2469 .ppt_pl3_fppt_min = 50, 2470 .ppt_pl3_fppt_def = 65, 2471 .ppt_pl3_fppt_max = 85, 2472 }, 2473 }, 2474 }, 2475 { 2476 .matches = { 2477 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 2478 }, 2479 .driver_data = &(struct power_data) { 2480 .ac_data = &(struct power_limits) { 2481 .ppt_pl1_spl_min = 7, 2482 .ppt_pl1_spl_max = 30, 2483 .ppt_pl2_sppt_min = 15, 2484 .ppt_pl2_sppt_max = 43, 2485 .ppt_pl3_fppt_min = 15, 2486 .ppt_pl3_fppt_max = 53, 2487 }, 2488 .dc_data = &(struct power_limits) { 2489 .ppt_pl1_spl_min = 7, 2490 .ppt_pl1_spl_def = 15, 2491 .ppt_pl1_spl_max = 25, 2492 .ppt_pl2_sppt_min = 15, 2493 .ppt_pl2_sppt_def = 20, 2494 .ppt_pl2_sppt_max = 30, 2495 .ppt_pl3_fppt_min = 15, 2496 .ppt_pl3_fppt_def = 25, 2497 .ppt_pl3_fppt_max = 35, 2498 }, 2499 }, 2500 }, 2501 { 2502 .matches = { 2503 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 2504 }, 2505 .driver_data = &(struct power_data) { 2506 .ac_data = &(struct power_limits) { 2507 .ppt_pl1_spl_min = 7, 2508 .ppt_pl1_spl_max = 30, 2509 .ppt_pl2_sppt_min = 15, 2510 .ppt_pl2_sppt_max = 43, 2511 .ppt_pl3_fppt_min = 15, 2512 .ppt_pl3_fppt_max = 53, 2513 }, 2514 .dc_data = &(struct power_limits) { 2515 .ppt_pl1_spl_min = 7, 2516 .ppt_pl1_spl_def = 17, 2517 .ppt_pl1_spl_max = 25, 2518 .ppt_pl2_sppt_min = 15, 2519 .ppt_pl2_sppt_def = 24, 2520 .ppt_pl2_sppt_max = 30, 2521 .ppt_pl3_fppt_min = 15, 2522 .ppt_pl3_fppt_def = 30, 2523 .ppt_pl3_fppt_max = 35, 2524 }, 2525 }, 2526 }, 2527 { 2528 .matches = { 2529 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 2530 }, 2531 .driver_data = &(struct power_data) { 2532 .ac_data = &(struct power_limits) { 2533 .ppt_pl1_spl_min = 7, 2534 .ppt_pl1_spl_max = 35, 2535 .ppt_pl2_sppt_min = 14, 2536 .ppt_pl2_sppt_max = 45, 2537 .ppt_pl3_fppt_min = 19, 2538 .ppt_pl3_fppt_max = 55, 2539 }, 2540 .dc_data = &(struct power_limits) { 2541 .ppt_pl1_spl_min = 7, 2542 .ppt_pl1_spl_def = 17, 2543 .ppt_pl1_spl_max = 35, 2544 .ppt_pl2_sppt_min = 13, 2545 .ppt_pl2_sppt_def = 21, 2546 .ppt_pl2_sppt_max = 45, 2547 .ppt_pl3_fppt_min = 19, 2548 .ppt_pl3_fppt_def = 26, 2549 .ppt_pl3_fppt_max = 55, 2550 }, 2551 }, 2552 }, 2553 {} 2554 }; 2555 2556 #endif /* _ASUS_ARMOURY_H_ */ 2557