1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8 #ifndef _ASUS_ARMOURY_H_ 9 #define _ASUS_ARMOURY_H_ 10 11 #include <linux/dmi.h> 12 #include <linux/platform_device.h> 13 #include <linux/sysfs.h> 14 #include <linux/types.h> 15 16 #define DRIVER_NAME "asus-armoury" 17 18 /** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41 ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45 /** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57 ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60 #define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66 #define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72 #define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75 #define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84 #define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91 /* Create functions and attributes for use in other macros or on their own */ 92 93 /* Shows a formatted static variable */ 94 #define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103 #define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122 #define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143 /* Boolean style enumeration, base macro. Requires adding show/store */ 144 #define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160 #define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164 #define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167 #define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170 /* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173 #define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178 /* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182 #define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201 #define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217 /* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222 #define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236 #define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254 #define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286 #define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309 /* Default is always the maximum value unless *_def is specified */ 310 struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336 }; 337 338 struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342 }; 343 344 /* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348 static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401UM"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 80, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 80, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 80, 361 .nv_dynamic_boost_min = 5, 362 .nv_dynamic_boost_max = 15, 363 .nv_temp_target_min = 75, 364 .nv_temp_target_max = 87, 365 }, 366 .dc_data = &(struct power_limits) { 367 .ppt_pl1_spl_min = 25, 368 .ppt_pl1_spl_max = 35, 369 .ppt_pl2_sppt_min = 31, 370 .ppt_pl2_sppt_max = 44, 371 .ppt_pl3_fppt_min = 45, 372 .ppt_pl3_fppt_max = 65, 373 .nv_temp_target_min = 75, 374 .nv_temp_target_max = 87, 375 }, 376 }, 377 }, 378 { 379 .matches = { 380 DMI_MATCH(DMI_BOARD_NAME, "FA401UV"), 381 }, 382 .driver_data = &(struct power_data) { 383 .ac_data = &(struct power_limits) { 384 .ppt_pl1_spl_min = 15, 385 .ppt_pl1_spl_max = 80, 386 .ppt_pl2_sppt_min = 35, 387 .ppt_pl2_sppt_max = 80, 388 .ppt_pl3_fppt_min = 35, 389 .ppt_pl3_fppt_max = 80, 390 .nv_dynamic_boost_min = 5, 391 .nv_dynamic_boost_max = 25, 392 .nv_temp_target_min = 75, 393 .nv_temp_target_max = 87, 394 .nv_tgp_min = 55, 395 .nv_tgp_max = 75, 396 }, 397 .dc_data = &(struct power_limits) { 398 .ppt_pl1_spl_min = 25, 399 .ppt_pl1_spl_max = 35, 400 .ppt_pl2_sppt_min = 31, 401 .ppt_pl2_sppt_max = 44, 402 .ppt_pl3_fppt_min = 45, 403 .ppt_pl3_fppt_max = 65, 404 .nv_temp_target_min = 75, 405 .nv_temp_target_max = 87, 406 }, 407 }, 408 }, 409 { 410 .matches = { 411 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 412 }, 413 .driver_data = &(struct power_data) { 414 .ac_data = &(struct power_limits) { 415 .ppt_pl1_spl_min = 15, 416 .ppt_pl1_spl_max = 80, 417 .ppt_pl2_sppt_min = 35, 418 .ppt_pl2_sppt_max = 80, 419 .ppt_pl3_fppt_min = 35, 420 .ppt_pl3_fppt_max = 80, 421 .nv_dynamic_boost_min = 5, 422 .nv_dynamic_boost_max = 25, 423 .nv_temp_target_min = 75, 424 .nv_temp_target_max = 87, 425 .nv_tgp_min = 55, 426 .nv_tgp_max = 75, 427 }, 428 .dc_data = &(struct power_limits) { 429 .ppt_pl1_spl_min = 25, 430 .ppt_pl1_spl_max = 30, 431 .ppt_pl2_sppt_min = 31, 432 .ppt_pl2_sppt_max = 44, 433 .ppt_pl3_fppt_min = 45, 434 .ppt_pl3_fppt_max = 65, 435 .nv_temp_target_min = 75, 436 .nv_temp_target_max = 87, 437 }, 438 }, 439 }, 440 { 441 .matches = { 442 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 443 }, 444 .driver_data = &(struct power_data) { 445 .ac_data = &(struct power_limits) { 446 .ppt_pl1_spl_min = 15, 447 .ppt_pl1_spl_max = 80, 448 .ppt_pl2_sppt_min = 35, 449 .ppt_pl2_sppt_max = 80, 450 .ppt_pl3_fppt_min = 35, 451 .ppt_pl3_fppt_max = 80, 452 .nv_dynamic_boost_min = 5, 453 .nv_dynamic_boost_max = 25, 454 .nv_temp_target_min = 75, 455 .nv_temp_target_max = 87, 456 }, 457 .dc_data = &(struct power_limits) { 458 .ppt_pl1_spl_min = 15, 459 .ppt_pl1_spl_def = 45, 460 .ppt_pl1_spl_max = 65, 461 .ppt_pl2_sppt_min = 35, 462 .ppt_pl2_sppt_def = 54, 463 .ppt_pl2_sppt_max = 65, 464 .ppt_pl3_fppt_min = 35, 465 .ppt_pl3_fppt_max = 65, 466 .nv_temp_target_min = 75, 467 .nv_temp_target_max = 87, 468 }, 469 }, 470 }, 471 { 472 .matches = { 473 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 474 }, 475 .driver_data = &(struct power_data) { 476 .ac_data = &(struct power_limits) { 477 .ppt_pl1_spl_min = 15, 478 .ppt_pl1_spl_max = 80, 479 .ppt_pl2_sppt_min = 35, 480 .ppt_pl2_sppt_max = 80, 481 .ppt_pl3_fppt_min = 35, 482 .ppt_pl3_fppt_max = 80, 483 .nv_dynamic_boost_min = 5, 484 .nv_dynamic_boost_max = 25, 485 .nv_temp_target_min = 75, 486 .nv_temp_target_max = 87, 487 .nv_tgp_min = 55, 488 .nv_tgp_max = 115, 489 }, 490 .dc_data = &(struct power_limits) { 491 .ppt_pl1_spl_min = 15, 492 .ppt_pl1_spl_def = 45, 493 .ppt_pl1_spl_max = 65, 494 .ppt_pl2_sppt_min = 35, 495 .ppt_pl2_sppt_def = 54, 496 .ppt_pl2_sppt_max = 65, 497 .ppt_pl3_fppt_min = 35, 498 .ppt_pl3_fppt_max = 65, 499 .nv_temp_target_min = 75, 500 .nv_temp_target_max = 87, 501 }, 502 }, 503 }, 504 { 505 .matches = { 506 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 507 }, 508 .driver_data = &(struct power_data) { 509 .ac_data = &(struct power_limits) { 510 .ppt_pl1_spl_min = 15, 511 .ppt_pl1_spl_max = 80, 512 .ppt_pl2_sppt_min = 35, 513 .ppt_pl2_sppt_max = 80, 514 .ppt_pl3_fppt_min = 35, 515 .ppt_pl3_fppt_max = 80, 516 .nv_dynamic_boost_min = 5, 517 .nv_dynamic_boost_max = 25, 518 .nv_temp_target_min = 75, 519 .nv_temp_target_max = 87, 520 }, 521 .dc_data = &(struct power_limits) { 522 .ppt_pl1_spl_min = 15, 523 .ppt_pl1_spl_def = 45, 524 .ppt_pl1_spl_max = 65, 525 .ppt_pl2_sppt_min = 35, 526 .ppt_pl2_sppt_def = 54, 527 .ppt_pl2_sppt_max = 65, 528 .ppt_pl3_fppt_min = 35, 529 .ppt_pl3_fppt_max = 65, 530 .nv_temp_target_min = 75, 531 .nv_temp_target_max = 87, 532 }, 533 }, 534 }, 535 { 536 .matches = { 537 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 538 }, 539 .driver_data = &(struct power_data) { 540 .ac_data = &(struct power_limits) { 541 .ppt_pl1_spl_min = 15, 542 .ppt_pl1_spl_max = 80, 543 .ppt_pl2_sppt_min = 35, 544 .ppt_pl2_sppt_max = 80, 545 .ppt_pl3_fppt_min = 35, 546 .ppt_pl3_fppt_max = 80, 547 .nv_dynamic_boost_min = 5, 548 .nv_dynamic_boost_max = 20, 549 .nv_temp_target_min = 75, 550 .nv_temp_target_max = 87, 551 .nv_tgp_min = 55, 552 .nv_tgp_max = 85, 553 }, 554 .dc_data = &(struct power_limits) { 555 .ppt_pl1_spl_min = 15, 556 .ppt_pl1_spl_def = 45, 557 .ppt_pl1_spl_max = 65, 558 .ppt_pl2_sppt_min = 35, 559 .ppt_pl2_sppt_def = 54, 560 .ppt_pl2_sppt_max = 65, 561 .ppt_pl3_fppt_min = 35, 562 .ppt_pl3_fppt_max = 65, 563 .nv_temp_target_min = 75, 564 .nv_temp_target_max = 87, 565 }, 566 }, 567 }, 568 { 569 .matches = { 570 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 571 }, 572 .driver_data = &(struct power_data) { 573 .ac_data = &(struct power_limits) { 574 .ppt_pl1_spl_min = 28, 575 .ppt_pl1_spl_max = 65, 576 .ppt_pl2_sppt_min = 28, 577 .ppt_pl2_sppt_max = 105, 578 .nv_dynamic_boost_min = 5, 579 .nv_dynamic_boost_max = 15, 580 .nv_temp_target_min = 75, 581 .nv_temp_target_max = 87, 582 .nv_tgp_min = 55, 583 .nv_tgp_max = 85, 584 }, 585 .dc_data = &(struct power_limits) { 586 .ppt_pl1_spl_min = 25, 587 .ppt_pl1_spl_max = 45, 588 .ppt_pl2_sppt_min = 35, 589 .ppt_pl2_sppt_max = 60, 590 .nv_temp_target_min = 75, 591 .nv_temp_target_max = 87, 592 }, 593 }, 594 }, 595 { 596 .matches = { 597 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 598 }, 599 .driver_data = &(struct power_data) { 600 .ac_data = &(struct power_limits) { 601 .ppt_pl1_spl_min = 30, 602 .ppt_pl1_spl_def = 100, 603 .ppt_pl1_spl_max = 135, 604 .ppt_pl2_sppt_min = 30, 605 .ppt_pl2_sppt_def = 115, 606 .ppt_pl2_sppt_max = 135, 607 .ppt_pl3_fppt_min = 30, 608 .ppt_pl3_fppt_max = 135, 609 .nv_dynamic_boost_min = 5, 610 .nv_dynamic_boost_max = 25, 611 .nv_temp_target_min = 75, 612 .nv_temp_target_max = 87, 613 .nv_tgp_min = 55, 614 .nv_tgp_max = 115, 615 }, 616 .dc_data = &(struct power_limits) { 617 .ppt_pl1_spl_min = 25, 618 .ppt_pl1_spl_def = 45, 619 .ppt_pl1_spl_max = 80, 620 .ppt_pl2_sppt_min = 25, 621 .ppt_pl2_sppt_def = 60, 622 .ppt_pl2_sppt_max = 80, 623 .ppt_pl3_fppt_min = 25, 624 .ppt_pl3_fppt_max = 80, 625 .nv_temp_target_min = 75, 626 .nv_temp_target_max = 87, 627 }, 628 }, 629 }, 630 { 631 .matches = { 632 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 633 }, 634 .driver_data = &(struct power_data) { 635 .ac_data = &(struct power_limits) { 636 .ppt_pl1_spl_min = 15, 637 .ppt_pl1_spl_def = 45, 638 .ppt_pl1_spl_max = 90, 639 .ppt_pl2_sppt_min = 35, 640 .ppt_pl2_sppt_def = 54, 641 .ppt_pl2_sppt_max = 90, 642 .ppt_pl3_fppt_min = 35, 643 .ppt_pl3_fppt_def = 65, 644 .ppt_pl3_fppt_max = 90, 645 .nv_dynamic_boost_min = 10, 646 .nv_dynamic_boost_max = 15, 647 .nv_temp_target_min = 75, 648 .nv_temp_target_max = 87, 649 .nv_tgp_min = 55, 650 .nv_tgp_max = 100, 651 }, 652 .dc_data = &(struct power_limits) { 653 .ppt_pl1_spl_min = 15, 654 .ppt_pl1_spl_def = 45, 655 .ppt_pl1_spl_max = 65, 656 .ppt_pl2_sppt_min = 35, 657 .ppt_pl2_sppt_def = 54, 658 .ppt_pl2_sppt_max = 65, 659 .ppt_pl3_fppt_min = 35, 660 .ppt_pl3_fppt_max = 65, 661 .nv_temp_target_min = 75, 662 .nv_temp_target_max = 87, 663 }, 664 }, 665 }, 666 { 667 .matches = { 668 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 669 }, 670 .driver_data = &(struct power_data) { 671 .ac_data = &(struct power_limits) { 672 .ppt_pl1_spl_min = 15, 673 .ppt_pl1_spl_def = 90, 674 .ppt_pl1_spl_max = 90, 675 .ppt_pl2_sppt_min = 35, 676 .ppt_pl2_sppt_def = 90, 677 .ppt_pl2_sppt_max = 90, 678 .ppt_pl3_fppt_min = 35, 679 .ppt_pl3_fppt_def = 90, 680 .ppt_pl3_fppt_max = 90, 681 .nv_dynamic_boost_min = 5, 682 .nv_dynamic_boost_max = 25, 683 .nv_temp_target_min = 75, 684 .nv_temp_target_max = 87, 685 .nv_tgp_min = 55, 686 .nv_tgp_max = 115, 687 }, 688 .dc_data = &(struct power_limits) { 689 .ppt_pl1_spl_min = 15, 690 .ppt_pl1_spl_def = 45, 691 .ppt_pl1_spl_max = 65, 692 .ppt_pl2_sppt_min = 35, 693 .ppt_pl2_sppt_def = 54, 694 .ppt_pl2_sppt_max = 65, 695 .ppt_pl3_fppt_min = 35, 696 .ppt_pl3_fppt_def = 65, 697 .ppt_pl3_fppt_max = 65, 698 .nv_temp_target_min = 75, 699 .nv_temp_target_max = 87, 700 }, 701 }, 702 }, 703 { 704 .matches = { 705 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 706 }, 707 .driver_data = &(struct power_data) { 708 .ac_data = &(struct power_limits) { 709 .ppt_apu_sppt_min = 15, 710 .ppt_apu_sppt_max = 80, 711 .ppt_platform_sppt_min = 30, 712 .ppt_platform_sppt_max = 120, 713 }, 714 .dc_data = &(struct power_limits) { 715 .ppt_apu_sppt_min = 25, 716 .ppt_apu_sppt_max = 35, 717 .ppt_platform_sppt_min = 45, 718 .ppt_platform_sppt_max = 100, 719 }, 720 }, 721 }, 722 { 723 .matches = { 724 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 725 }, 726 .driver_data = &(struct power_data) { 727 .ac_data = &(struct power_limits) { 728 .ppt_apu_sppt_min = 15, 729 .ppt_apu_sppt_max = 80, 730 .ppt_platform_sppt_min = 30, 731 .ppt_platform_sppt_max = 115, 732 }, 733 .dc_data = &(struct power_limits) { 734 .ppt_apu_sppt_min = 15, 735 .ppt_apu_sppt_max = 45, 736 .ppt_platform_sppt_min = 30, 737 .ppt_platform_sppt_max = 50, 738 }, 739 }, 740 }, 741 { 742 .matches = { 743 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 744 }, 745 .driver_data = &(struct power_data) { 746 .ac_data = &(struct power_limits) { 747 .ppt_apu_sppt_min = 15, 748 .ppt_apu_sppt_max = 80, 749 .ppt_platform_sppt_min = 30, 750 .ppt_platform_sppt_max = 120, 751 .nv_temp_target_min = 75, 752 .nv_temp_target_max = 87, 753 }, 754 .dc_data = &(struct power_limits) { 755 .ppt_apu_sppt_min = 25, 756 .ppt_apu_sppt_max = 35, 757 .ppt_platform_sppt_min = 45, 758 .ppt_platform_sppt_max = 100, 759 .nv_temp_target_min = 75, 760 .nv_temp_target_max = 87, 761 }, 762 }, 763 }, 764 { 765 .matches = { 766 DMI_MATCH(DMI_BOARD_NAME, "FA617XT"), 767 }, 768 .driver_data = &(struct power_data) { 769 .ac_data = &(struct power_limits) { 770 .ppt_apu_sppt_min = 15, 771 .ppt_apu_sppt_max = 80, 772 .ppt_platform_sppt_min = 30, 773 .ppt_platform_sppt_max = 145, 774 }, 775 .dc_data = &(struct power_limits) { 776 .ppt_apu_sppt_min = 25, 777 .ppt_apu_sppt_max = 35, 778 .ppt_platform_sppt_min = 45, 779 .ppt_platform_sppt_max = 100, 780 }, 781 }, 782 }, 783 { 784 .matches = { 785 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 786 }, 787 .driver_data = &(struct power_data) { 788 .ac_data = &(struct power_limits) { 789 .ppt_pl1_spl_min = 28, 790 .ppt_pl1_spl_max = 135, 791 .ppt_pl2_sppt_min = 28, 792 .ppt_pl2_sppt_max = 135, 793 .nv_dynamic_boost_min = 5, 794 .nv_dynamic_boost_max = 25, 795 .nv_temp_target_min = 75, 796 .nv_temp_target_max = 87, 797 }, 798 .dc_data = &(struct power_limits) { 799 .ppt_pl1_spl_min = 25, 800 .ppt_pl1_spl_max = 45, 801 .ppt_pl2_sppt_min = 35, 802 .ppt_pl2_sppt_max = 60, 803 .nv_temp_target_min = 75, 804 .nv_temp_target_max = 87, 805 }, 806 .requires_fan_curve = true, 807 }, 808 }, 809 { 810 .matches = { 811 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 812 }, 813 .driver_data = &(struct power_data) { 814 .ac_data = &(struct power_limits) { 815 .ppt_pl1_spl_min = 28, 816 .ppt_pl1_spl_def = 115, 817 .ppt_pl1_spl_max = 135, 818 .ppt_pl2_sppt_min = 28, 819 .ppt_pl2_sppt_max = 135, 820 .nv_dynamic_boost_min = 5, 821 .nv_dynamic_boost_max = 25, 822 .nv_temp_target_min = 75, 823 .nv_temp_target_max = 87, 824 }, 825 .dc_data = &(struct power_limits) { 826 .ppt_pl1_spl_min = 25, 827 .ppt_pl1_spl_max = 45, 828 .ppt_pl2_sppt_min = 35, 829 .ppt_pl2_sppt_max = 60, 830 .nv_temp_target_min = 75, 831 .nv_temp_target_max = 87, 832 }, 833 .requires_fan_curve = true, 834 }, 835 }, 836 { 837 .matches = { 838 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 839 }, 840 .driver_data = &(struct power_data) { 841 .ac_data = &(struct power_limits) { 842 .ppt_pl1_spl_min = 28, 843 .ppt_pl1_spl_max = 90, 844 .ppt_pl2_sppt_min = 28, 845 .ppt_pl2_sppt_max = 135, 846 .nv_dynamic_boost_min = 5, 847 .nv_dynamic_boost_max = 15, 848 }, 849 .dc_data = &(struct power_limits) { 850 .ppt_pl1_spl_min = 25, 851 .ppt_pl1_spl_max = 45, 852 .ppt_pl2_sppt_min = 35, 853 .ppt_pl2_sppt_max = 60, 854 }, 855 .requires_fan_curve = true, 856 }, 857 }, 858 { 859 .matches = { 860 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 861 }, 862 .driver_data = &(struct power_data) { 863 .ac_data = &(struct power_limits) { 864 .ppt_pl1_spl_min = 15, 865 .ppt_pl1_spl_max = 80, 866 .ppt_pl2_sppt_min = 15, 867 .ppt_pl2_sppt_max = 80, 868 }, 869 .dc_data = NULL, 870 }, 871 }, 872 { 873 .matches = { 874 // This model is full AMD. No Nvidia dGPU. 875 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 876 }, 877 .driver_data = &(struct power_data) { 878 .ac_data = &(struct power_limits) { 879 .ppt_apu_sppt_min = 15, 880 .ppt_apu_sppt_max = 80, 881 .ppt_platform_sppt_min = 30, 882 .ppt_platform_sppt_max = 115, 883 }, 884 .dc_data = &(struct power_limits) { 885 .ppt_apu_sppt_min = 25, 886 .ppt_apu_sppt_def = 30, 887 .ppt_apu_sppt_max = 45, 888 .ppt_platform_sppt_min = 40, 889 .ppt_platform_sppt_max = 60, 890 }, 891 }, 892 }, 893 { 894 .matches = { 895 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 896 }, 897 .driver_data = &(struct power_data) { 898 .ac_data = &(struct power_limits) { 899 .ppt_pl1_spl_min = 15, 900 .ppt_pl1_spl_def = 35, 901 .ppt_pl1_spl_max = 80, 902 .ppt_pl2_sppt_min = 25, 903 .ppt_pl2_sppt_def = 65, 904 .ppt_pl2_sppt_max = 80, 905 .ppt_pl3_fppt_min = 35, 906 .ppt_pl3_fppt_max = 80, 907 .nv_temp_target_min = 75, 908 .nv_temp_target_max = 87, 909 }, 910 .dc_data = &(struct power_limits) { 911 .ppt_pl1_spl_min = 15, 912 .ppt_pl1_spl_max = 35, 913 .ppt_pl2_sppt_min = 25, 914 .ppt_pl2_sppt_max = 35, 915 .ppt_pl3_fppt_min = 35, 916 .ppt_pl3_fppt_max = 65, 917 .nv_temp_target_min = 75, 918 .nv_temp_target_max = 87, 919 }, 920 .requires_fan_curve = true, 921 }, 922 }, 923 { 924 .matches = { 925 DMI_MATCH(DMI_BOARD_NAME, "GA403UI"), 926 }, 927 .driver_data = &(struct power_data) { 928 .ac_data = &(struct power_limits) { 929 .ppt_pl1_spl_min = 15, 930 .ppt_pl1_spl_max = 80, 931 .ppt_pl2_sppt_min = 25, 932 .ppt_pl2_sppt_max = 80, 933 .ppt_pl3_fppt_min = 35, 934 .ppt_pl3_fppt_max = 80, 935 .nv_dynamic_boost_min = 5, 936 .nv_dynamic_boost_max = 25, 937 .nv_temp_target_min = 75, 938 .nv_temp_target_max = 87, 939 .nv_tgp_min = 55, 940 .nv_tgp_max = 65, 941 }, 942 .dc_data = &(struct power_limits) { 943 .ppt_pl1_spl_min = 15, 944 .ppt_pl1_spl_max = 35, 945 .ppt_pl2_sppt_min = 25, 946 .ppt_pl2_sppt_max = 35, 947 .ppt_pl3_fppt_min = 35, 948 .ppt_pl3_fppt_max = 65, 949 .nv_temp_target_min = 75, 950 .nv_temp_target_max = 87, 951 }, 952 .requires_fan_curve = true, 953 }, 954 }, 955 { 956 .matches = { 957 DMI_MATCH(DMI_BOARD_NAME, "GA403UV"), 958 }, 959 .driver_data = &(struct power_data) { 960 .ac_data = &(struct power_limits) { 961 .ppt_pl1_spl_min = 15, 962 .ppt_pl1_spl_max = 80, 963 .ppt_pl2_sppt_min = 25, 964 .ppt_pl2_sppt_max = 80, 965 .ppt_pl3_fppt_min = 35, 966 .ppt_pl3_fppt_max = 80, 967 .nv_dynamic_boost_min = 5, 968 .nv_dynamic_boost_max = 25, 969 .nv_temp_target_min = 75, 970 .nv_temp_target_max = 87, 971 .nv_tgp_min = 55, 972 .nv_tgp_max = 65, 973 }, 974 .dc_data = &(struct power_limits) { 975 .ppt_pl1_spl_min = 15, 976 .ppt_pl1_spl_max = 35, 977 .ppt_pl2_sppt_min = 25, 978 .ppt_pl2_sppt_max = 35, 979 .ppt_pl3_fppt_min = 35, 980 .ppt_pl3_fppt_max = 65, 981 .nv_temp_target_min = 75, 982 .nv_temp_target_max = 87, 983 }, 984 .requires_fan_curve = true, 985 }, 986 }, 987 { 988 .matches = { 989 DMI_MATCH(DMI_BOARD_NAME, "GA403WM"), 990 }, 991 .driver_data = &(struct power_data) { 992 .ac_data = &(struct power_limits) { 993 .ppt_pl1_spl_min = 15, 994 .ppt_pl1_spl_max = 80, 995 .ppt_pl2_sppt_min = 25, 996 .ppt_pl2_sppt_max = 80, 997 .ppt_pl3_fppt_min = 35, 998 .ppt_pl3_fppt_max = 80, 999 .nv_dynamic_boost_min = 0, 1000 .nv_dynamic_boost_max = 15, 1001 .nv_temp_target_min = 75, 1002 .nv_temp_target_max = 87, 1003 .nv_tgp_min = 55, 1004 .nv_tgp_max = 85, 1005 }, 1006 .dc_data = &(struct power_limits) { 1007 .ppt_pl1_spl_min = 15, 1008 .ppt_pl1_spl_max = 35, 1009 .ppt_pl2_sppt_min = 25, 1010 .ppt_pl2_sppt_max = 35, 1011 .ppt_pl3_fppt_min = 35, 1012 .ppt_pl3_fppt_max = 65, 1013 .nv_temp_target_min = 75, 1014 .nv_temp_target_max = 87, 1015 }, 1016 .requires_fan_curve = true, 1017 }, 1018 }, 1019 { 1020 .matches = { 1021 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 1022 }, 1023 .driver_data = &(struct power_data) { 1024 .ac_data = &(struct power_limits) { 1025 .ppt_pl1_spl_min = 15, 1026 .ppt_pl1_spl_max = 80, 1027 .ppt_pl2_sppt_min = 25, 1028 .ppt_pl2_sppt_max = 80, 1029 .ppt_pl3_fppt_min = 35, 1030 .ppt_pl3_fppt_max = 80, 1031 .nv_dynamic_boost_min = 0, 1032 .nv_dynamic_boost_max = 25, 1033 .nv_temp_target_min = 75, 1034 .nv_temp_target_max = 87, 1035 .nv_tgp_min = 80, 1036 .nv_tgp_max = 95, 1037 }, 1038 .dc_data = &(struct power_limits) { 1039 .ppt_pl1_spl_min = 15, 1040 .ppt_pl1_spl_max = 35, 1041 .ppt_pl2_sppt_min = 25, 1042 .ppt_pl2_sppt_max = 35, 1043 .ppt_pl3_fppt_min = 35, 1044 .ppt_pl3_fppt_max = 65, 1045 .nv_temp_target_min = 75, 1046 .nv_temp_target_max = 87, 1047 }, 1048 .requires_fan_curve = true, 1049 }, 1050 }, 1051 { 1052 .matches = { 1053 DMI_MATCH(DMI_BOARD_NAME, "GA403WW"), 1054 }, 1055 .driver_data = &(struct power_data) { 1056 .ac_data = &(struct power_limits) { 1057 .ppt_pl1_spl_min = 15, 1058 .ppt_pl1_spl_max = 80, 1059 .ppt_pl2_sppt_min = 25, 1060 .ppt_pl2_sppt_max = 80, 1061 .ppt_pl3_fppt_min = 35, 1062 .ppt_pl3_fppt_max = 80, 1063 .nv_dynamic_boost_min = 0, 1064 .nv_dynamic_boost_max = 25, 1065 .nv_temp_target_min = 75, 1066 .nv_temp_target_max = 87, 1067 .nv_tgp_min = 80, 1068 .nv_tgp_max = 95, 1069 }, 1070 .dc_data = &(struct power_limits) { 1071 .ppt_pl1_spl_min = 15, 1072 .ppt_pl1_spl_max = 35, 1073 .ppt_pl2_sppt_min = 25, 1074 .ppt_pl2_sppt_max = 35, 1075 .ppt_pl3_fppt_min = 35, 1076 .ppt_pl3_fppt_max = 65, 1077 .nv_temp_target_min = 75, 1078 .nv_temp_target_max = 87, 1079 }, 1080 .requires_fan_curve = true, 1081 }, 1082 }, 1083 { 1084 .matches = { 1085 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 1086 }, 1087 .driver_data = &(struct power_data) { 1088 .ac_data = &(struct power_limits) { 1089 .ppt_pl1_spl_min = 15, 1090 .ppt_pl1_spl_def = 35, 1091 .ppt_pl1_spl_max = 80, 1092 .ppt_pl2_sppt_min = 65, 1093 .ppt_pl2_sppt_max = 80, 1094 }, 1095 }, 1096 }, 1097 { 1098 .matches = { 1099 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 1100 }, 1101 .driver_data = &(struct power_data) { 1102 .ac_data = &(struct power_limits) { 1103 .ppt_pl1_spl_min = 15, 1104 .ppt_pl1_spl_def = 35, 1105 .ppt_pl1_spl_max = 80, 1106 .ppt_pl2_sppt_min = 35, 1107 .ppt_pl2_sppt_def = 65, 1108 .ppt_pl2_sppt_max = 80, 1109 .ppt_pl3_fppt_min = 35, 1110 .ppt_pl3_fppt_max = 80, 1111 .nv_dynamic_boost_min = 5, 1112 .nv_dynamic_boost_max = 20, 1113 .nv_temp_target_min = 75, 1114 .nv_temp_target_max = 87, 1115 }, 1116 .dc_data = &(struct power_limits) { 1117 .ppt_pl1_spl_min = 15, 1118 .ppt_pl1_spl_def = 25, 1119 .ppt_pl1_spl_max = 65, 1120 .ppt_pl2_sppt_min = 35, 1121 .ppt_pl2_sppt_def = 54, 1122 .ppt_pl2_sppt_max = 60, 1123 .ppt_pl3_fppt_min = 35, 1124 .ppt_pl3_fppt_max = 65, 1125 }, 1126 }, 1127 }, 1128 { 1129 .matches = { 1130 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 1131 }, 1132 .driver_data = &(struct power_data) { 1133 .ac_data = &(struct power_limits) { 1134 .ppt_pl1_spl_min = 15, 1135 .ppt_pl1_spl_max = 80, 1136 .ppt_pl2_sppt_min = 35, 1137 .ppt_pl2_sppt_max = 80, 1138 .ppt_pl3_fppt_min = 35, 1139 .ppt_pl3_fppt_max = 80, 1140 .nv_dynamic_boost_min = 5, 1141 .nv_dynamic_boost_max = 20, 1142 .nv_temp_target_min = 75, 1143 .nv_temp_target_max = 87, 1144 .nv_tgp_min = 55, 1145 .nv_tgp_max = 85, 1146 }, 1147 .dc_data = &(struct power_limits) { 1148 .ppt_pl1_spl_min = 25, 1149 .ppt_pl1_spl_max = 35, 1150 .ppt_pl2_sppt_min = 31, 1151 .ppt_pl2_sppt_max = 44, 1152 .ppt_pl3_fppt_min = 45, 1153 .ppt_pl3_fppt_max = 65, 1154 .nv_temp_target_min = 75, 1155 .nv_temp_target_max = 87, 1156 }, 1157 .requires_fan_curve = true, 1158 }, 1159 }, 1160 { 1161 .matches = { 1162 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 1163 }, 1164 .driver_data = &(struct power_data) { 1165 .ac_data = &(struct power_limits) { 1166 .ppt_pl1_spl_min = 25, 1167 .ppt_pl1_spl_max = 60, 1168 .ppt_pl2_sppt_min = 25, 1169 .ppt_pl2_sppt_max = 135, 1170 .nv_dynamic_boost_min = 5, 1171 .nv_dynamic_boost_max = 20, 1172 .nv_temp_target_min = 75, 1173 .nv_temp_target_max = 87, 1174 }, 1175 .dc_data = &(struct power_limits) { 1176 .ppt_pl1_spl_min = 25, 1177 .ppt_pl1_spl_max = 40, 1178 .ppt_pl2_sppt_min = 25, 1179 .ppt_pl2_sppt_max = 40, 1180 .nv_temp_target_min = 75, 1181 .nv_temp_target_max = 87, 1182 } 1183 }, 1184 }, 1185 { 1186 .matches = { 1187 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1188 }, 1189 .driver_data = &(struct power_data) { 1190 .ac_data = &(struct power_limits) { 1191 .ppt_pl1_spl_min = 65, 1192 .ppt_pl1_spl_max = 120, 1193 .ppt_pl2_sppt_min = 65, 1194 .ppt_pl2_sppt_max = 150, 1195 .nv_dynamic_boost_min = 5, 1196 .nv_dynamic_boost_max = 25, 1197 .nv_temp_target_min = 75, 1198 .nv_temp_target_max = 87, 1199 }, 1200 .dc_data = &(struct power_limits) { 1201 .ppt_pl1_spl_min = 25, 1202 .ppt_pl1_spl_max = 40, 1203 .ppt_pl2_sppt_min = 35, 1204 .ppt_pl2_sppt_def = 40, 1205 .ppt_pl2_sppt_max = 60, 1206 .nv_temp_target_min = 75, 1207 .nv_temp_target_max = 87, 1208 }, 1209 }, 1210 }, 1211 { 1212 .matches = { 1213 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1214 }, 1215 .driver_data = &(struct power_data) { 1216 .ac_data = &(struct power_limits) { 1217 .ppt_pl1_spl_min = 30, 1218 .ppt_pl1_spl_max = 85, 1219 .ppt_pl2_sppt_min = 38, 1220 .ppt_pl2_sppt_max = 110, 1221 .nv_dynamic_boost_min = 5, 1222 .nv_dynamic_boost_max = 20, 1223 .nv_temp_target_min = 75, 1224 .nv_temp_target_max = 87, 1225 .nv_tgp_min = 80, 1226 .nv_tgp_def = 90, 1227 .nv_tgp_max = 105, 1228 }, 1229 .dc_data = &(struct power_limits) { 1230 .ppt_pl1_spl_min = 30, 1231 .ppt_pl1_spl_max = 85, 1232 .ppt_pl2_sppt_min = 38, 1233 .ppt_pl2_sppt_max = 110, 1234 .nv_temp_target_min = 75, 1235 .nv_temp_target_max = 87, 1236 }, 1237 .requires_fan_curve = true, 1238 }, 1239 }, 1240 { 1241 .matches = { 1242 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1243 }, 1244 .driver_data = &(struct power_data) { 1245 .ac_data = &(struct power_limits) { 1246 .ppt_pl1_spl_min = 45, 1247 .ppt_pl1_spl_max = 85, 1248 .ppt_pl2_sppt_min = 56, 1249 .ppt_pl2_sppt_max = 110, 1250 .nv_dynamic_boost_min = 5, 1251 .nv_dynamic_boost_max = 20, 1252 .nv_temp_target_min = 75, 1253 .nv_temp_target_max = 87, 1254 .nv_tgp_min = 80, 1255 .nv_tgp_def = 90, 1256 .nv_tgp_max = 110, 1257 }, 1258 .dc_data = &(struct power_limits) { 1259 .ppt_pl1_spl_min = 25, 1260 .ppt_pl1_spl_max = 85, 1261 .ppt_pl2_sppt_min = 32, 1262 .ppt_pl2_sppt_max = 110, 1263 .nv_temp_target_min = 75, 1264 .nv_temp_target_max = 87, 1265 }, 1266 .requires_fan_curve = true, 1267 }, 1268 }, 1269 { 1270 .matches = { 1271 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1272 }, 1273 .driver_data = &(struct power_data) { 1274 .ac_data = &(struct power_limits) { 1275 .ppt_pl1_spl_min = 45, 1276 .ppt_pl1_spl_max = 85, 1277 .ppt_pl2_sppt_min = 56, 1278 .ppt_pl2_sppt_max = 110, 1279 .nv_dynamic_boost_min = 5, 1280 .nv_dynamic_boost_max = 20, 1281 .nv_temp_target_min = 7, 1282 .nv_temp_target_max = 87, 1283 .nv_tgp_min = 95, 1284 .nv_tgp_def = 100, 1285 .nv_tgp_max = 110, 1286 }, 1287 .dc_data = &(struct power_limits) { 1288 .ppt_pl1_spl_min = 25, 1289 .ppt_pl1_spl_max = 85, 1290 .ppt_pl2_sppt_min = 32, 1291 .ppt_pl2_sppt_max = 110, 1292 .nv_temp_target_min = 75, 1293 .nv_temp_target_max = 87, 1294 }, 1295 .requires_fan_curve = true, 1296 }, 1297 }, 1298 { 1299 .matches = { 1300 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1301 }, 1302 .driver_data = &(struct power_data) { 1303 .ac_data = &(struct power_limits) { 1304 .ppt_pl1_spl_min = 28, 1305 .ppt_pl1_spl_max = 90, 1306 .ppt_pl2_sppt_min = 28, 1307 .ppt_pl2_sppt_max = 135, 1308 .nv_dynamic_boost_min = 5, 1309 .nv_dynamic_boost_max = 20, 1310 .nv_temp_target_min = 75, 1311 .nv_temp_target_max = 87, 1312 }, 1313 .dc_data = &(struct power_limits) { 1314 .ppt_pl1_spl_min = 25, 1315 .ppt_pl1_spl_max = 35, 1316 .ppt_pl2_sppt_min = 38, 1317 .ppt_pl2_sppt_max = 53, 1318 .nv_temp_target_min = 75, 1319 .nv_temp_target_max = 87, 1320 }, 1321 .requires_fan_curve = true, 1322 }, 1323 }, 1324 { 1325 .matches = { 1326 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1327 }, 1328 .driver_data = &(struct power_data) { 1329 .ac_data = &(struct power_limits) { 1330 .ppt_pl1_spl_min = 15, 1331 .ppt_pl1_spl_max = 45, 1332 .ppt_pl2_sppt_min = 65, 1333 .ppt_pl2_sppt_max = 80, 1334 }, 1335 .dc_data = NULL, 1336 }, 1337 }, 1338 { 1339 .matches = { 1340 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1341 }, 1342 .driver_data = &(struct power_data) { 1343 .ac_data = &(struct power_limits) { 1344 .ppt_pl1_spl_min = 15, 1345 .ppt_pl1_spl_max = 45, 1346 .ppt_pl2_sppt_min = 25, 1347 .ppt_pl2_sppt_max = 54, 1348 .ppt_pl3_fppt_min = 35, 1349 .ppt_pl3_fppt_max = 65, 1350 .nv_temp_target_min = 75, 1351 .nv_temp_target_max = 87, 1352 }, 1353 .dc_data = &(struct power_limits) { 1354 .ppt_pl1_spl_min = 15, 1355 .ppt_pl1_spl_max = 35, 1356 .ppt_pl2_sppt_min = 25, 1357 .ppt_pl2_sppt_max = 35, 1358 .ppt_pl3_fppt_min = 35, 1359 .ppt_pl3_fppt_max = 65, 1360 .nv_temp_target_min = 75, 1361 .nv_temp_target_max = 87, 1362 }, 1363 }, 1364 }, 1365 { 1366 .matches = { 1367 DMI_MATCH(DMI_BOARD_NAME, "GV302XV"), 1368 }, 1369 .driver_data = &(struct power_data) { 1370 .ac_data = &(struct power_limits) { 1371 .ppt_pl1_spl_min = 15, 1372 .ppt_pl1_spl_max = 55, 1373 .ppt_pl2_sppt_min = 25, 1374 .ppt_pl2_sppt_max = 60, 1375 .ppt_pl3_fppt_min = 35, 1376 .ppt_pl3_fppt_max = 65, 1377 .nv_temp_target_min = 75, 1378 .nv_temp_target_max = 87, 1379 }, 1380 .dc_data = &(struct power_limits) { 1381 .ppt_pl1_spl_min = 15, 1382 .ppt_pl1_spl_max = 35, 1383 .ppt_pl2_sppt_min = 25, 1384 .ppt_pl2_sppt_max = 35, 1385 .ppt_pl3_fppt_min = 35, 1386 .ppt_pl3_fppt_max = 65, 1387 .nv_temp_target_min = 75, 1388 .nv_temp_target_max = 87, 1389 }, 1390 }, 1391 }, 1392 { 1393 .matches = { 1394 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1395 }, 1396 .driver_data = &(struct power_data) { 1397 .ac_data = &(struct power_limits) { 1398 .ppt_pl1_spl_min = 15, 1399 .ppt_pl1_spl_def = 35, 1400 .ppt_pl1_spl_max = 90, 1401 .ppt_pl2_sppt_min = 35, 1402 .ppt_pl2_sppt_def = 54, 1403 .ppt_pl2_sppt_max = 100, 1404 .ppt_pl3_fppt_min = 35, 1405 .ppt_pl3_fppt_def = 80, 1406 .ppt_pl3_fppt_max = 125, 1407 .nv_dynamic_boost_min = 5, 1408 .nv_dynamic_boost_max = 25, 1409 .nv_temp_target_min = 75, 1410 .nv_temp_target_max = 87, 1411 }, 1412 .dc_data = &(struct power_limits) { 1413 .ppt_pl1_spl_min = 15, 1414 .ppt_pl1_spl_def = 28, 1415 .ppt_pl1_spl_max = 65, 1416 .ppt_pl2_sppt_min = 35, 1417 .ppt_pl2_sppt_def = 54, 1418 .ppt_pl2_sppt_max = 60, 1419 .ppt_pl3_fppt_min = 35, 1420 .ppt_pl3_fppt_def = 80, 1421 .ppt_pl3_fppt_max = 65, 1422 .nv_temp_target_min = 75, 1423 .nv_temp_target_max = 87, 1424 }, 1425 }, 1426 }, 1427 { 1428 .matches = { 1429 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1430 }, 1431 .driver_data = &(struct power_data) { 1432 .ac_data = &(struct power_limits) { 1433 .ppt_pl1_spl_min = 28, 1434 .ppt_pl1_spl_def = 100, 1435 .ppt_pl1_spl_max = 110, 1436 .ppt_pl2_sppt_min = 28, 1437 .ppt_pl2_sppt_max = 135, 1438 .nv_dynamic_boost_min = 5, 1439 .nv_dynamic_boost_max = 20, 1440 .nv_temp_target_min = 75, 1441 .nv_temp_target_max = 87, 1442 }, 1443 .dc_data = &(struct power_limits) { 1444 .ppt_pl1_spl_min = 25, 1445 .ppt_pl1_spl_max = 40, 1446 .ppt_pl2_sppt_min = 35, 1447 .ppt_pl2_sppt_def = 40, 1448 .ppt_pl2_sppt_max = 60, 1449 .nv_temp_target_min = 75, 1450 .nv_temp_target_max = 87, 1451 }, 1452 }, 1453 }, 1454 { 1455 .matches = { 1456 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1457 }, 1458 .driver_data = &(struct power_data) { 1459 .ac_data = &(struct power_limits) { 1460 .ppt_pl1_spl_min = 15, 1461 .ppt_pl1_spl_def = 110, 1462 .ppt_pl1_spl_max = 130, 1463 .ppt_pl2_sppt_min = 35, 1464 .ppt_pl2_sppt_def = 125, 1465 .ppt_pl2_sppt_max = 130, 1466 .ppt_pl3_fppt_min = 35, 1467 .ppt_pl3_fppt_def = 125, 1468 .ppt_pl3_fppt_max = 135, 1469 .nv_dynamic_boost_min = 5, 1470 .nv_dynamic_boost_max = 25, 1471 .nv_temp_target_min = 75, 1472 .nv_temp_target_max = 87, 1473 }, 1474 .dc_data = &(struct power_limits) { 1475 .ppt_pl1_spl_min = 15, 1476 .ppt_pl1_spl_def = 25, 1477 .ppt_pl1_spl_max = 65, 1478 .ppt_pl2_sppt_min = 35, 1479 .ppt_pl2_sppt_def = 35, 1480 .ppt_pl2_sppt_max = 65, 1481 .ppt_pl3_fppt_min = 35, 1482 .ppt_pl3_fppt_def = 42, 1483 .ppt_pl3_fppt_max = 65, 1484 .nv_temp_target_min = 75, 1485 .nv_temp_target_max = 87, 1486 }, 1487 }, 1488 }, 1489 { 1490 .matches = { 1491 DMI_MATCH(DMI_BOARD_NAME, "GX650RX"), 1492 }, 1493 .driver_data = &(struct power_data) { 1494 .ac_data = &(struct power_limits) { 1495 .ppt_pl1_spl_min = 28, 1496 .ppt_pl1_spl_def = 70, 1497 .ppt_pl1_spl_max = 90, 1498 .ppt_pl2_sppt_min = 28, 1499 .ppt_pl2_sppt_def = 70, 1500 .ppt_pl2_sppt_max = 100, 1501 .ppt_pl3_fppt_min = 28, 1502 .ppt_pl3_fppt_def = 110, 1503 .ppt_pl3_fppt_max = 125, 1504 .nv_dynamic_boost_min = 5, 1505 .nv_dynamic_boost_max = 25, 1506 .nv_temp_target_min = 76, 1507 .nv_temp_target_max = 87, 1508 }, 1509 .dc_data = &(struct power_limits) { 1510 .ppt_pl1_spl_min = 28, 1511 .ppt_pl1_spl_max = 50, 1512 .ppt_pl2_sppt_min = 28, 1513 .ppt_pl2_sppt_max = 50, 1514 .ppt_pl3_fppt_min = 28, 1515 .ppt_pl3_fppt_max = 65, 1516 .nv_temp_target_min = 76, 1517 .nv_temp_target_max = 87, 1518 }, 1519 }, 1520 }, 1521 { 1522 .matches = { 1523 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1524 }, 1525 .driver_data = &(struct power_data) { 1526 .ac_data = &(struct power_limits) { 1527 /* Yes this laptop is very limited */ 1528 .ppt_pl1_spl_min = 15, 1529 .ppt_pl1_spl_max = 80, 1530 .ppt_pl2_sppt_min = 15, 1531 .ppt_pl2_sppt_max = 80, 1532 }, 1533 .dc_data = NULL, 1534 .requires_fan_curve = true, 1535 }, 1536 }, 1537 { 1538 .matches = { 1539 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1540 }, 1541 .driver_data = &(struct power_data) { 1542 .ac_data = &(struct power_limits) { 1543 /* Yes this laptop is very limited */ 1544 .ppt_pl1_spl_min = 15, 1545 .ppt_pl1_spl_max = 100, 1546 .ppt_pl2_sppt_min = 15, 1547 .ppt_pl2_sppt_max = 190, 1548 }, 1549 .dc_data = NULL, 1550 .requires_fan_curve = true, 1551 }, 1552 }, 1553 { 1554 .matches = { 1555 DMI_MATCH(DMI_BOARD_NAME, "G513QY"), 1556 }, 1557 .driver_data = &(struct power_data) { 1558 .ac_data = &(struct power_limits) { 1559 /* Advantage Edition Laptop, no PL1 or PL2 limits */ 1560 .ppt_apu_sppt_min = 15, 1561 .ppt_apu_sppt_max = 100, 1562 .ppt_platform_sppt_min = 70, 1563 .ppt_platform_sppt_max = 190, 1564 }, 1565 .dc_data = NULL, 1566 .requires_fan_curve = true, 1567 }, 1568 }, 1569 { 1570 .matches = { 1571 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1572 }, 1573 .driver_data = &(struct power_data) { 1574 .ac_data = &(struct power_limits) { 1575 .ppt_pl1_spl_min = 35, 1576 .ppt_pl1_spl_max = 90, 1577 .ppt_pl2_sppt_min = 54, 1578 .ppt_pl2_sppt_max = 100, 1579 .ppt_pl3_fppt_min = 54, 1580 .ppt_pl3_fppt_max = 125, 1581 .nv_dynamic_boost_min = 5, 1582 .nv_dynamic_boost_max = 25, 1583 .nv_temp_target_min = 75, 1584 .nv_temp_target_max = 87, 1585 }, 1586 .dc_data = &(struct power_limits) { 1587 .ppt_pl1_spl_min = 28, 1588 .ppt_pl1_spl_max = 50, 1589 .ppt_pl2_sppt_min = 28, 1590 .ppt_pl2_sppt_max = 50, 1591 .ppt_pl3_fppt_min = 28, 1592 .ppt_pl3_fppt_max = 65, 1593 .nv_temp_target_min = 75, 1594 .nv_temp_target_max = 87, 1595 }, 1596 .requires_fan_curve = true, 1597 }, 1598 }, 1599 { 1600 .matches = { 1601 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 1602 }, 1603 .driver_data = &(struct power_data) { 1604 .ac_data = &(struct power_limits) { 1605 .ppt_pl1_spl_min = 28, 1606 .ppt_pl1_spl_max = 140, 1607 .ppt_pl2_sppt_min = 28, 1608 .ppt_pl2_sppt_max = 175, 1609 .nv_temp_target_min = 75, 1610 .nv_temp_target_max = 87, 1611 .nv_dynamic_boost_min = 5, 1612 .nv_dynamic_boost_max = 25, 1613 }, 1614 .dc_data = &(struct power_limits) { 1615 .ppt_pl1_spl_min = 25, 1616 .ppt_pl1_spl_max = 55, 1617 .ppt_pl2_sppt_min = 25, 1618 .ppt_pl2_sppt_max = 70, 1619 .nv_temp_target_min = 75, 1620 .nv_temp_target_max = 87, 1621 }, 1622 .requires_fan_curve = true, 1623 }, 1624 }, 1625 { 1626 .matches = { 1627 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 1628 }, 1629 .driver_data = &(struct power_data) { 1630 .ac_data = &(struct power_limits) { 1631 .ppt_pl1_spl_min = 28, 1632 .ppt_pl1_spl_def = 140, 1633 .ppt_pl1_spl_max = 175, 1634 .ppt_pl2_sppt_min = 28, 1635 .ppt_pl2_sppt_max = 175, 1636 .nv_temp_target_min = 75, 1637 .nv_temp_target_max = 87, 1638 .nv_dynamic_boost_min = 5, 1639 .nv_dynamic_boost_max = 25, 1640 .nv_tgp_min = 65, 1641 .nv_tgp_max = 115, 1642 }, 1643 .dc_data = &(struct power_limits) { 1644 .ppt_pl1_spl_min = 25, 1645 .ppt_pl1_spl_max = 55, 1646 .ppt_pl2_sppt_min = 25, 1647 .ppt_pl2_sppt_max = 70, 1648 .nv_temp_target_min = 75, 1649 .nv_temp_target_max = 87, 1650 }, 1651 .requires_fan_curve = true, 1652 }, 1653 }, 1654 { 1655 .matches = { 1656 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 1657 }, 1658 .driver_data = &(struct power_data) { 1659 .ac_data = &(struct power_limits) { 1660 .ppt_pl1_spl_min = 28, 1661 .ppt_pl1_spl_max = 140, 1662 .ppt_pl2_sppt_min = 28, 1663 .ppt_pl2_sppt_max = 175, 1664 .nv_temp_target_min = 75, 1665 .nv_temp_target_max = 87, 1666 .nv_dynamic_boost_min = 5, 1667 .nv_dynamic_boost_max = 25, 1668 }, 1669 .dc_data = &(struct power_limits) { 1670 .ppt_pl1_spl_min = 25, 1671 .ppt_pl1_spl_max = 55, 1672 .ppt_pl2_sppt_min = 25, 1673 .ppt_pl2_sppt_max = 70, 1674 .nv_temp_target_min = 75, 1675 .nv_temp_target_max = 87, 1676 }, 1677 .requires_fan_curve = true, 1678 }, 1679 }, 1680 { 1681 .matches = { 1682 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 1683 }, 1684 .driver_data = &(struct power_data) { 1685 .ac_data = &(struct power_limits) { 1686 .ppt_pl1_spl_min = 30, 1687 .ppt_pl1_spl_def = 120, 1688 .ppt_pl1_spl_max = 130, 1689 .ppt_pl2_sppt_min = 65, 1690 .ppt_pl2_sppt_def = 125, 1691 .ppt_pl2_sppt_max = 130, 1692 .ppt_pl3_fppt_min = 65, 1693 .ppt_pl3_fppt_def = 125, 1694 .ppt_pl3_fppt_max = 130, 1695 .nv_temp_target_min = 75, 1696 .nv_temp_target_max = 87, 1697 .nv_dynamic_boost_min = 5, 1698 .nv_dynamic_boost_max = 25, 1699 }, 1700 .dc_data = &(struct power_limits) { 1701 .ppt_pl1_spl_min = 25, 1702 .ppt_pl1_spl_max = 65, 1703 .ppt_pl2_sppt_min = 25, 1704 .ppt_pl2_sppt_max = 65, 1705 .ppt_pl3_fppt_min = 35, 1706 .ppt_pl3_fppt_max = 75, 1707 .nv_temp_target_min = 75, 1708 .nv_temp_target_max = 87, 1709 }, 1710 .requires_fan_curve = true, 1711 }, 1712 }, 1713 { 1714 .matches = { 1715 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 1716 }, 1717 .driver_data = &(struct power_data) { 1718 .ac_data = &(struct power_limits) { 1719 .ppt_pl1_spl_min = 28, 1720 .ppt_pl1_spl_max = 170, 1721 .ppt_pl2_sppt_min = 28, 1722 .ppt_pl2_sppt_max = 175, 1723 .nv_temp_target_min = 75, 1724 .nv_temp_target_max = 87, 1725 .nv_dynamic_boost_min = 5, 1726 .nv_dynamic_boost_max = 25, 1727 }, 1728 .dc_data = &(struct power_limits) { 1729 .ppt_pl1_spl_min = 28, 1730 .ppt_pl1_spl_max = 35, 1731 .ppt_pl2_sppt_min = 28, 1732 .ppt_pl2_sppt_max = 35, 1733 .nv_temp_target_min = 75, 1734 .nv_temp_target_max = 87, 1735 }, 1736 .requires_fan_curve = true, 1737 }, 1738 }, 1739 { 1740 .matches = { 1741 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 1742 }, 1743 .driver_data = &(struct power_data) { 1744 .ac_data = &(struct power_limits) { 1745 .ppt_pl1_spl_min = 30, 1746 .ppt_pl1_spl_def = 100, 1747 .ppt_pl1_spl_max = 130, 1748 .ppt_pl2_sppt_min = 65, 1749 .ppt_pl2_sppt_def = 125, 1750 .ppt_pl2_sppt_max = 130, 1751 .ppt_pl3_fppt_min = 65, 1752 .ppt_pl3_fppt_def = 125, 1753 .ppt_pl3_fppt_max = 130, 1754 .nv_temp_target_min = 75, 1755 .nv_temp_target_max = 87, 1756 .nv_dynamic_boost_min = 5, 1757 .nv_dynamic_boost_max = 25, 1758 }, 1759 .dc_data = &(struct power_limits) { 1760 .ppt_pl1_spl_min = 25, 1761 .ppt_pl1_spl_max = 65, 1762 .ppt_pl2_sppt_min = 25, 1763 .ppt_pl2_sppt_max = 65, 1764 .ppt_pl3_fppt_min = 35, 1765 .ppt_pl3_fppt_max = 75, 1766 .nv_temp_target_min = 75, 1767 .nv_temp_target_max = 87, 1768 }, 1769 .requires_fan_curve = true, 1770 }, 1771 }, 1772 { 1773 .matches = { 1774 DMI_MATCH(DMI_BOARD_NAME, "G733QS"), 1775 }, 1776 .driver_data = &(struct power_data) { 1777 .ac_data = &(struct power_limits) { 1778 .ppt_pl1_spl_min = 15, 1779 .ppt_pl1_spl_max = 80, 1780 .ppt_pl2_sppt_min = 15, 1781 .ppt_pl2_sppt_max = 80, 1782 }, 1783 .requires_fan_curve = false, 1784 }, 1785 }, 1786 { 1787 .matches = { 1788 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 1789 }, 1790 .driver_data = &(struct power_data) { 1791 .ac_data = &(struct power_limits) { 1792 .ppt_pl1_spl_min = 28, 1793 .ppt_pl1_spl_max = 140, 1794 .ppt_pl2_sppt_min = 28, 1795 .ppt_pl2_sppt_max = 140, 1796 .nv_dynamic_boost_min = 5, 1797 .nv_dynamic_boost_max = 25, 1798 }, 1799 .dc_data = &(struct power_limits) { 1800 .ppt_pl1_spl_min = 25, 1801 .ppt_pl1_spl_max = 55, 1802 .ppt_pl2_sppt_min = 25, 1803 .ppt_pl2_sppt_max = 70, 1804 }, 1805 .requires_fan_curve = true, 1806 }, 1807 }, 1808 { 1809 .matches = { 1810 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 1811 }, 1812 .driver_data = &(struct power_data) { 1813 .ac_data = &(struct power_limits) { 1814 .ppt_pl1_spl_min = 28, 1815 .ppt_pl1_spl_max = 140, 1816 .ppt_pl2_sppt_min = 28, 1817 .ppt_pl2_sppt_max = 175, 1818 .nv_dynamic_boost_min = 5, 1819 .nv_dynamic_boost_max = 25, 1820 .nv_temp_target_min = 75, 1821 .nv_temp_target_max = 87, 1822 }, 1823 .dc_data = &(struct power_limits) { 1824 .ppt_pl1_spl_min = 25, 1825 .ppt_pl1_spl_max = 55, 1826 .ppt_pl2_sppt_min = 25, 1827 .ppt_pl2_sppt_max = 70, 1828 .nv_temp_target_min = 75, 1829 .nv_temp_target_max = 87, 1830 }, 1831 .requires_fan_curve = true, 1832 }, 1833 }, 1834 { 1835 .matches = { 1836 DMI_MATCH(DMI_BOARD_NAME, "G835LR"), 1837 }, 1838 .driver_data = &(struct power_data) { 1839 .ac_data = &(struct power_limits) { 1840 .ppt_pl1_spl_min = 28, 1841 .ppt_pl1_spl_def = 140, 1842 .ppt_pl1_spl_max = 175, 1843 .ppt_pl2_sppt_min = 28, 1844 .ppt_pl2_sppt_max = 175, 1845 .nv_dynamic_boost_min = 5, 1846 .nv_dynamic_boost_max = 25, 1847 .nv_temp_target_min = 75, 1848 .nv_temp_target_max = 87, 1849 .nv_tgp_min = 65, 1850 .nv_tgp_max = 115, 1851 }, 1852 .dc_data = &(struct power_limits) { 1853 .ppt_pl1_spl_min = 25, 1854 .ppt_pl1_spl_max = 55, 1855 .ppt_pl2_sppt_min = 25, 1856 .ppt_pl2_sppt_max = 70, 1857 .nv_temp_target_min = 75, 1858 .nv_temp_target_max = 87, 1859 }, 1860 .requires_fan_curve = true, 1861 }, 1862 }, 1863 { 1864 .matches = { 1865 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 1866 }, 1867 .driver_data = &(struct power_data) { 1868 .ac_data = &(struct power_limits) { 1869 .ppt_pl1_spl_min = 28, 1870 .ppt_pl1_spl_def = 140, 1871 .ppt_pl1_spl_max = 175, 1872 .ppt_pl2_sppt_min = 28, 1873 .ppt_pl2_sppt_max = 175, 1874 .nv_dynamic_boost_min = 5, 1875 .nv_dynamic_boost_max = 25, 1876 .nv_temp_target_min = 75, 1877 .nv_temp_target_max = 87, 1878 .nv_tgp_min = 80, 1879 .nv_tgp_max = 150, 1880 }, 1881 .dc_data = &(struct power_limits) { 1882 .ppt_pl1_spl_min = 25, 1883 .ppt_pl1_spl_max = 55, 1884 .ppt_pl2_sppt_min = 25, 1885 .ppt_pl2_sppt_max = 70, 1886 .nv_temp_target_min = 75, 1887 .nv_temp_target_max = 87, 1888 }, 1889 .requires_fan_curve = true, 1890 }, 1891 }, 1892 { 1893 .matches = { 1894 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 1895 }, 1896 .driver_data = &(struct power_data) { 1897 .ac_data = &(struct power_limits) { 1898 .ppt_pl1_spl_min = 15, 1899 .ppt_pl1_spl_max = 80, 1900 .ppt_pl2_sppt_min = 35, 1901 .ppt_pl2_sppt_max = 80, 1902 .ppt_pl3_fppt_min = 35, 1903 .ppt_pl3_fppt_max = 80, 1904 .nv_dynamic_boost_min = 5, 1905 .nv_dynamic_boost_max = 20, 1906 .nv_temp_target_min = 75, 1907 .nv_temp_target_max = 87, 1908 .nv_tgp_min = 55, 1909 .nv_tgp_max = 85, 1910 }, 1911 .dc_data = &(struct power_limits) { 1912 .ppt_pl1_spl_min = 25, 1913 .ppt_pl1_spl_max = 35, 1914 .ppt_pl2_sppt_min = 31, 1915 .ppt_pl2_sppt_max = 44, 1916 .ppt_pl3_fppt_min = 45, 1917 .ppt_pl3_fppt_max = 65, 1918 .nv_temp_target_min = 75, 1919 .nv_temp_target_max = 87, 1920 }, 1921 }, 1922 }, 1923 { 1924 .matches = { 1925 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 1926 }, 1927 .driver_data = &(struct power_data) { 1928 .ac_data = &(struct power_limits) { 1929 .ppt_pl1_spl_min = 7, 1930 .ppt_pl1_spl_max = 30, 1931 .ppt_pl2_sppt_min = 15, 1932 .ppt_pl2_sppt_max = 43, 1933 .ppt_pl3_fppt_min = 15, 1934 .ppt_pl3_fppt_max = 53, 1935 }, 1936 .dc_data = &(struct power_limits) { 1937 .ppt_pl1_spl_min = 7, 1938 .ppt_pl1_spl_def = 15, 1939 .ppt_pl1_spl_max = 25, 1940 .ppt_pl2_sppt_min = 15, 1941 .ppt_pl2_sppt_def = 20, 1942 .ppt_pl2_sppt_max = 30, 1943 .ppt_pl3_fppt_min = 15, 1944 .ppt_pl3_fppt_def = 25, 1945 .ppt_pl3_fppt_max = 35, 1946 }, 1947 }, 1948 }, 1949 { 1950 .matches = { 1951 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 1952 }, 1953 .driver_data = &(struct power_data) { 1954 .ac_data = &(struct power_limits) { 1955 .ppt_pl1_spl_min = 7, 1956 .ppt_pl1_spl_max = 30, 1957 .ppt_pl2_sppt_min = 15, 1958 .ppt_pl2_sppt_max = 43, 1959 .ppt_pl3_fppt_min = 15, 1960 .ppt_pl3_fppt_max = 53, 1961 }, 1962 .dc_data = &(struct power_limits) { 1963 .ppt_pl1_spl_min = 7, 1964 .ppt_pl1_spl_def = 17, 1965 .ppt_pl1_spl_max = 25, 1966 .ppt_pl2_sppt_min = 15, 1967 .ppt_pl2_sppt_def = 24, 1968 .ppt_pl2_sppt_max = 30, 1969 .ppt_pl3_fppt_min = 15, 1970 .ppt_pl3_fppt_def = 30, 1971 .ppt_pl3_fppt_max = 35, 1972 }, 1973 }, 1974 }, 1975 { 1976 .matches = { 1977 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 1978 }, 1979 .driver_data = &(struct power_data) { 1980 .ac_data = &(struct power_limits) { 1981 .ppt_pl1_spl_min = 7, 1982 .ppt_pl1_spl_max = 35, 1983 .ppt_pl2_sppt_min = 14, 1984 .ppt_pl2_sppt_max = 45, 1985 .ppt_pl3_fppt_min = 19, 1986 .ppt_pl3_fppt_max = 55, 1987 }, 1988 .dc_data = &(struct power_limits) { 1989 .ppt_pl1_spl_min = 7, 1990 .ppt_pl1_spl_def = 17, 1991 .ppt_pl1_spl_max = 35, 1992 .ppt_pl2_sppt_min = 13, 1993 .ppt_pl2_sppt_def = 21, 1994 .ppt_pl2_sppt_max = 45, 1995 .ppt_pl3_fppt_min = 19, 1996 .ppt_pl3_fppt_def = 26, 1997 .ppt_pl3_fppt_max = 55, 1998 }, 1999 }, 2000 }, 2001 {} 2002 }; 2003 2004 #endif /* _ASUS_ARMOURY_H_ */ 2005