1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8 #ifndef _ASUS_ARMOURY_H_ 9 #define _ASUS_ARMOURY_H_ 10 11 #include <linux/dmi.h> 12 #include <linux/platform_device.h> 13 #include <linux/sysfs.h> 14 #include <linux/types.h> 15 16 #define DRIVER_NAME "asus-armoury" 17 18 /** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41 ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45 /** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57 ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60 #define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66 #define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72 #define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75 #define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84 #define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91 /* Create functions and attributes for use in other macros or on their own */ 92 93 /* Shows a formatted static variable */ 94 #define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103 #define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122 #define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143 /* Boolean style enumeration, base macro. Requires adding show/store */ 144 #define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160 #define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164 #define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167 #define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170 /* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173 #define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178 /* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182 #define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201 #define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217 /* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222 #define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236 #define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254 #define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286 #define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309 /* Default is always the maximum value unless *_def is specified */ 310 struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336 }; 337 338 struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342 }; 343 344 /* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348 static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 80, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 80, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 80, 361 .nv_dynamic_boost_min = 5, 362 .nv_dynamic_boost_max = 25, 363 .nv_temp_target_min = 75, 364 .nv_temp_target_max = 87, 365 .nv_tgp_min = 55, 366 .nv_tgp_max = 75, 367 }, 368 .dc_data = &(struct power_limits) { 369 .ppt_pl1_spl_min = 25, 370 .ppt_pl1_spl_max = 30, 371 .ppt_pl2_sppt_min = 31, 372 .ppt_pl2_sppt_max = 44, 373 .ppt_pl3_fppt_min = 45, 374 .ppt_pl3_fppt_max = 65, 375 .nv_temp_target_min = 75, 376 .nv_temp_target_max = 87, 377 }, 378 }, 379 }, 380 { 381 .matches = { 382 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 383 }, 384 .driver_data = &(struct power_data) { 385 .ac_data = &(struct power_limits) { 386 .ppt_pl1_spl_min = 15, 387 .ppt_pl1_spl_max = 80, 388 .ppt_pl2_sppt_min = 35, 389 .ppt_pl2_sppt_max = 80, 390 .ppt_pl3_fppt_min = 35, 391 .ppt_pl3_fppt_max = 80, 392 .nv_dynamic_boost_min = 5, 393 .nv_dynamic_boost_max = 25, 394 .nv_temp_target_min = 75, 395 .nv_temp_target_max = 87, 396 }, 397 .dc_data = &(struct power_limits) { 398 .ppt_pl1_spl_min = 15, 399 .ppt_pl1_spl_def = 45, 400 .ppt_pl1_spl_max = 65, 401 .ppt_pl2_sppt_min = 35, 402 .ppt_pl2_sppt_def = 54, 403 .ppt_pl2_sppt_max = 65, 404 .ppt_pl3_fppt_min = 35, 405 .ppt_pl3_fppt_max = 65, 406 .nv_temp_target_min = 75, 407 .nv_temp_target_max = 87, 408 }, 409 }, 410 }, 411 { 412 .matches = { 413 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 414 }, 415 .driver_data = &(struct power_data) { 416 .ac_data = &(struct power_limits) { 417 .ppt_pl1_spl_min = 15, 418 .ppt_pl1_spl_max = 80, 419 .ppt_pl2_sppt_min = 35, 420 .ppt_pl2_sppt_max = 80, 421 .ppt_pl3_fppt_min = 35, 422 .ppt_pl3_fppt_max = 80, 423 .nv_dynamic_boost_min = 5, 424 .nv_dynamic_boost_max = 25, 425 .nv_temp_target_min = 75, 426 .nv_temp_target_max = 87, 427 .nv_tgp_min = 55, 428 .nv_tgp_max = 115, 429 }, 430 .dc_data = &(struct power_limits) { 431 .ppt_pl1_spl_min = 15, 432 .ppt_pl1_spl_def = 45, 433 .ppt_pl1_spl_max = 65, 434 .ppt_pl2_sppt_min = 35, 435 .ppt_pl2_sppt_def = 54, 436 .ppt_pl2_sppt_max = 65, 437 .ppt_pl3_fppt_min = 35, 438 .ppt_pl3_fppt_max = 65, 439 .nv_temp_target_min = 75, 440 .nv_temp_target_max = 87, 441 }, 442 }, 443 }, 444 { 445 .matches = { 446 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 447 }, 448 .driver_data = &(struct power_data) { 449 .ac_data = &(struct power_limits) { 450 .ppt_pl1_spl_min = 15, 451 .ppt_pl1_spl_max = 80, 452 .ppt_pl2_sppt_min = 35, 453 .ppt_pl2_sppt_max = 80, 454 .ppt_pl3_fppt_min = 35, 455 .ppt_pl3_fppt_max = 80, 456 .nv_dynamic_boost_min = 5, 457 .nv_dynamic_boost_max = 25, 458 .nv_temp_target_min = 75, 459 .nv_temp_target_max = 87, 460 }, 461 .dc_data = &(struct power_limits) { 462 .ppt_pl1_spl_min = 15, 463 .ppt_pl1_spl_def = 45, 464 .ppt_pl1_spl_max = 65, 465 .ppt_pl2_sppt_min = 35, 466 .ppt_pl2_sppt_def = 54, 467 .ppt_pl2_sppt_max = 65, 468 .ppt_pl3_fppt_min = 35, 469 .ppt_pl3_fppt_max = 65, 470 .nv_temp_target_min = 75, 471 .nv_temp_target_max = 87, 472 }, 473 }, 474 }, 475 { 476 .matches = { 477 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 478 }, 479 .driver_data = &(struct power_data) { 480 .ac_data = &(struct power_limits) { 481 .ppt_pl1_spl_min = 15, 482 .ppt_pl1_spl_max = 80, 483 .ppt_pl2_sppt_min = 35, 484 .ppt_pl2_sppt_max = 80, 485 .ppt_pl3_fppt_min = 35, 486 .ppt_pl3_fppt_max = 80, 487 .nv_dynamic_boost_min = 5, 488 .nv_dynamic_boost_max = 20, 489 .nv_temp_target_min = 75, 490 .nv_temp_target_max = 87, 491 .nv_tgp_min = 55, 492 .nv_tgp_max = 85, 493 }, 494 .dc_data = &(struct power_limits) { 495 .ppt_pl1_spl_min = 15, 496 .ppt_pl1_spl_def = 45, 497 .ppt_pl1_spl_max = 65, 498 .ppt_pl2_sppt_min = 35, 499 .ppt_pl2_sppt_def = 54, 500 .ppt_pl2_sppt_max = 65, 501 .ppt_pl3_fppt_min = 35, 502 .ppt_pl3_fppt_max = 65, 503 .nv_temp_target_min = 75, 504 .nv_temp_target_max = 87, 505 }, 506 }, 507 }, 508 { 509 .matches = { 510 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 511 }, 512 .driver_data = &(struct power_data) { 513 .ac_data = &(struct power_limits) { 514 .ppt_pl1_spl_min = 28, 515 .ppt_pl1_spl_max = 65, 516 .ppt_pl2_sppt_min = 28, 517 .ppt_pl2_sppt_max = 105, 518 .nv_dynamic_boost_min = 5, 519 .nv_dynamic_boost_max = 15, 520 .nv_temp_target_min = 75, 521 .nv_temp_target_max = 87, 522 .nv_tgp_min = 55, 523 .nv_tgp_max = 85, 524 }, 525 .dc_data = &(struct power_limits) { 526 .ppt_pl1_spl_min = 25, 527 .ppt_pl1_spl_max = 45, 528 .ppt_pl2_sppt_min = 35, 529 .ppt_pl2_sppt_max = 60, 530 .nv_temp_target_min = 75, 531 .nv_temp_target_max = 87, 532 }, 533 }, 534 }, 535 { 536 .matches = { 537 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 538 }, 539 .driver_data = &(struct power_data) { 540 .ac_data = &(struct power_limits) { 541 .ppt_pl1_spl_min = 30, 542 .ppt_pl1_spl_def = 100, 543 .ppt_pl1_spl_max = 135, 544 .ppt_pl2_sppt_min = 30, 545 .ppt_pl2_sppt_def = 115, 546 .ppt_pl2_sppt_max = 135, 547 .ppt_pl3_fppt_min = 30, 548 .ppt_pl3_fppt_max = 135, 549 .nv_dynamic_boost_min = 5, 550 .nv_dynamic_boost_max = 25, 551 .nv_temp_target_min = 75, 552 .nv_temp_target_max = 87, 553 .nv_tgp_min = 55, 554 .nv_tgp_max = 115, 555 }, 556 .dc_data = &(struct power_limits) { 557 .ppt_pl1_spl_min = 25, 558 .ppt_pl1_spl_def = 45, 559 .ppt_pl1_spl_max = 80, 560 .ppt_pl2_sppt_min = 25, 561 .ppt_pl2_sppt_def = 60, 562 .ppt_pl2_sppt_max = 80, 563 .ppt_pl3_fppt_min = 25, 564 .ppt_pl3_fppt_max = 80, 565 .nv_temp_target_min = 75, 566 .nv_temp_target_max = 87, 567 }, 568 }, 569 }, 570 { 571 .matches = { 572 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 573 }, 574 .driver_data = &(struct power_data) { 575 .ac_data = &(struct power_limits) { 576 .ppt_pl1_spl_min = 15, 577 .ppt_pl1_spl_def = 45, 578 .ppt_pl1_spl_max = 90, 579 .ppt_pl2_sppt_min = 35, 580 .ppt_pl2_sppt_def = 54, 581 .ppt_pl2_sppt_max = 90, 582 .ppt_pl3_fppt_min = 35, 583 .ppt_pl3_fppt_def = 90, 584 .ppt_pl3_fppt_max = 65, 585 .nv_dynamic_boost_min = 10, 586 .nv_dynamic_boost_max = 15, 587 .nv_temp_target_min = 75, 588 .nv_temp_target_max = 87, 589 .nv_tgp_min = 55, 590 .nv_tgp_max = 100, 591 }, 592 .dc_data = &(struct power_limits) { 593 .ppt_pl1_spl_min = 15, 594 .ppt_pl1_spl_def = 45, 595 .ppt_pl1_spl_max = 65, 596 .ppt_pl2_sppt_min = 35, 597 .ppt_pl2_sppt_def = 54, 598 .ppt_pl2_sppt_max = 65, 599 .ppt_pl3_fppt_min = 35, 600 .ppt_pl3_fppt_max = 65, 601 .nv_temp_target_min = 75, 602 .nv_temp_target_max = 87, 603 }, 604 }, 605 }, 606 { 607 .matches = { 608 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 609 }, 610 .driver_data = &(struct power_data) { 611 .ac_data = &(struct power_limits) { 612 .ppt_pl1_spl_min = 15, 613 .ppt_pl1_spl_def = 90, 614 .ppt_pl1_spl_max = 90, 615 .ppt_pl2_sppt_min = 35, 616 .ppt_pl2_sppt_def = 90, 617 .ppt_pl2_sppt_max = 90, 618 .ppt_pl3_fppt_min = 35, 619 .ppt_pl3_fppt_def = 90, 620 .ppt_pl3_fppt_max = 90, 621 .nv_dynamic_boost_min = 5, 622 .nv_dynamic_boost_max = 25, 623 .nv_temp_target_min = 75, 624 .nv_temp_target_max = 87, 625 .nv_tgp_min = 55, 626 .nv_tgp_max = 115, 627 }, 628 .dc_data = &(struct power_limits) { 629 .ppt_pl1_spl_min = 15, 630 .ppt_pl1_spl_def = 45, 631 .ppt_pl1_spl_max = 65, 632 .ppt_pl2_sppt_min = 35, 633 .ppt_pl2_sppt_def = 54, 634 .ppt_pl2_sppt_max = 65, 635 .ppt_pl3_fppt_min = 35, 636 .ppt_pl3_fppt_def = 65, 637 .ppt_pl3_fppt_max = 65, 638 .nv_temp_target_min = 75, 639 .nv_temp_target_max = 87, 640 }, 641 }, 642 }, 643 { 644 .matches = { 645 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 646 }, 647 .driver_data = &(struct power_data) { 648 .ac_data = &(struct power_limits) { 649 .ppt_apu_sppt_min = 15, 650 .ppt_apu_sppt_max = 80, 651 .ppt_platform_sppt_min = 30, 652 .ppt_platform_sppt_max = 120, 653 }, 654 .dc_data = &(struct power_limits) { 655 .ppt_apu_sppt_min = 25, 656 .ppt_apu_sppt_max = 35, 657 .ppt_platform_sppt_min = 45, 658 .ppt_platform_sppt_max = 100, 659 }, 660 }, 661 }, 662 { 663 .matches = { 664 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 665 }, 666 .driver_data = &(struct power_data) { 667 .ac_data = &(struct power_limits) { 668 .ppt_apu_sppt_min = 15, 669 .ppt_apu_sppt_max = 80, 670 .ppt_platform_sppt_min = 30, 671 .ppt_platform_sppt_max = 115, 672 }, 673 .dc_data = &(struct power_limits) { 674 .ppt_apu_sppt_min = 15, 675 .ppt_apu_sppt_max = 45, 676 .ppt_platform_sppt_min = 30, 677 .ppt_platform_sppt_max = 50, 678 }, 679 }, 680 }, 681 { 682 .matches = { 683 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 684 }, 685 .driver_data = &(struct power_data) { 686 .ac_data = &(struct power_limits) { 687 .ppt_apu_sppt_min = 15, 688 .ppt_apu_sppt_max = 80, 689 .ppt_platform_sppt_min = 30, 690 .ppt_platform_sppt_max = 120, 691 .nv_temp_target_min = 75, 692 .nv_temp_target_max = 87, 693 }, 694 .dc_data = &(struct power_limits) { 695 .ppt_apu_sppt_min = 25, 696 .ppt_apu_sppt_max = 35, 697 .ppt_platform_sppt_min = 45, 698 .ppt_platform_sppt_max = 100, 699 .nv_temp_target_min = 75, 700 .nv_temp_target_max = 87, 701 }, 702 }, 703 }, 704 { 705 .matches = { 706 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 707 }, 708 .driver_data = &(struct power_data) { 709 .ac_data = &(struct power_limits) { 710 .ppt_pl1_spl_min = 28, 711 .ppt_pl1_spl_max = 135, 712 .ppt_pl2_sppt_min = 28, 713 .ppt_pl2_sppt_max = 135, 714 .nv_dynamic_boost_min = 5, 715 .nv_dynamic_boost_max = 25, 716 .nv_temp_target_min = 75, 717 .nv_temp_target_max = 87, 718 }, 719 .dc_data = &(struct power_limits) { 720 .ppt_pl1_spl_min = 25, 721 .ppt_pl1_spl_max = 45, 722 .ppt_pl2_sppt_min = 35, 723 .ppt_pl2_sppt_max = 60, 724 .nv_temp_target_min = 75, 725 .nv_temp_target_max = 87, 726 }, 727 .requires_fan_curve = true, 728 }, 729 }, 730 { 731 .matches = { 732 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 733 }, 734 .driver_data = &(struct power_data) { 735 .ac_data = &(struct power_limits) { 736 .ppt_pl1_spl_min = 28, 737 .ppt_pl1_spl_def = 115, 738 .ppt_pl1_spl_max = 135, 739 .ppt_pl2_sppt_min = 28, 740 .ppt_pl2_sppt_max = 135, 741 .nv_dynamic_boost_min = 5, 742 .nv_dynamic_boost_max = 25, 743 .nv_temp_target_min = 75, 744 .nv_temp_target_max = 87, 745 }, 746 .dc_data = &(struct power_limits) { 747 .ppt_pl1_spl_min = 25, 748 .ppt_pl1_spl_max = 45, 749 .ppt_pl2_sppt_min = 35, 750 .ppt_pl2_sppt_max = 60, 751 .nv_temp_target_min = 75, 752 .nv_temp_target_max = 87, 753 }, 754 .requires_fan_curve = true, 755 }, 756 }, 757 { 758 .matches = { 759 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 760 }, 761 .driver_data = &(struct power_data) { 762 .ac_data = &(struct power_limits) { 763 .ppt_pl1_spl_min = 28, 764 .ppt_pl1_spl_max = 90, 765 .ppt_pl2_sppt_min = 28, 766 .ppt_pl2_sppt_max = 135, 767 .nv_dynamic_boost_min = 5, 768 .nv_dynamic_boost_max = 15, 769 }, 770 .dc_data = &(struct power_limits) { 771 .ppt_pl1_spl_min = 25, 772 .ppt_pl1_spl_max = 45, 773 .ppt_pl2_sppt_min = 35, 774 .ppt_pl2_sppt_max = 60, 775 }, 776 .requires_fan_curve = true, 777 }, 778 }, 779 { 780 .matches = { 781 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 782 }, 783 .driver_data = &(struct power_data) { 784 .ac_data = &(struct power_limits) { 785 .ppt_pl1_spl_min = 15, 786 .ppt_pl1_spl_max = 80, 787 .ppt_pl2_sppt_min = 15, 788 .ppt_pl2_sppt_max = 80, 789 }, 790 .dc_data = NULL, 791 }, 792 }, 793 { 794 .matches = { 795 // This model is full AMD. No Nvidia dGPU. 796 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 797 }, 798 .driver_data = &(struct power_data) { 799 .ac_data = &(struct power_limits) { 800 .ppt_apu_sppt_min = 15, 801 .ppt_apu_sppt_max = 80, 802 .ppt_platform_sppt_min = 30, 803 .ppt_platform_sppt_max = 115, 804 }, 805 .dc_data = &(struct power_limits) { 806 .ppt_apu_sppt_min = 25, 807 .ppt_apu_sppt_def = 30, 808 .ppt_apu_sppt_max = 45, 809 .ppt_platform_sppt_min = 40, 810 .ppt_platform_sppt_max = 60, 811 }, 812 }, 813 }, 814 { 815 .matches = { 816 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 817 }, 818 .driver_data = &(struct power_data) { 819 .ac_data = &(struct power_limits) { 820 .ppt_pl1_spl_min = 15, 821 .ppt_pl1_spl_def = 35, 822 .ppt_pl1_spl_max = 80, 823 .ppt_pl2_sppt_min = 25, 824 .ppt_pl2_sppt_def = 65, 825 .ppt_pl2_sppt_max = 80, 826 .ppt_pl3_fppt_min = 35, 827 .ppt_pl3_fppt_max = 80, 828 .nv_temp_target_min = 75, 829 .nv_temp_target_max = 87, 830 }, 831 .dc_data = &(struct power_limits) { 832 .ppt_pl1_spl_min = 15, 833 .ppt_pl1_spl_max = 35, 834 .ppt_pl2_sppt_min = 25, 835 .ppt_pl2_sppt_max = 35, 836 .ppt_pl3_fppt_min = 35, 837 .ppt_pl3_fppt_max = 65, 838 .nv_temp_target_min = 75, 839 .nv_temp_target_max = 87, 840 }, 841 .requires_fan_curve = true, 842 }, 843 }, 844 { 845 .matches = { 846 DMI_MATCH(DMI_BOARD_NAME, "GA403U"), 847 }, 848 .driver_data = &(struct power_data) { 849 .ac_data = &(struct power_limits) { 850 .ppt_pl1_spl_min = 15, 851 .ppt_pl1_spl_max = 80, 852 .ppt_pl2_sppt_min = 25, 853 .ppt_pl2_sppt_max = 80, 854 .ppt_pl3_fppt_min = 35, 855 .ppt_pl3_fppt_max = 80, 856 .nv_dynamic_boost_min = 5, 857 .nv_dynamic_boost_max = 25, 858 .nv_temp_target_min = 75, 859 .nv_temp_target_max = 87, 860 .nv_tgp_min = 55, 861 .nv_tgp_max = 65, 862 }, 863 .dc_data = &(struct power_limits) { 864 .ppt_pl1_spl_min = 15, 865 .ppt_pl1_spl_max = 35, 866 .ppt_pl2_sppt_min = 25, 867 .ppt_pl2_sppt_max = 35, 868 .ppt_pl3_fppt_min = 35, 869 .ppt_pl3_fppt_max = 65, 870 .nv_temp_target_min = 75, 871 .nv_temp_target_max = 87, 872 }, 873 .requires_fan_curve = true, 874 }, 875 }, 876 { 877 .matches = { 878 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 879 }, 880 .driver_data = &(struct power_data) { 881 .ac_data = &(struct power_limits) { 882 .ppt_pl1_spl_min = 15, 883 .ppt_pl1_spl_max = 80, 884 .ppt_pl2_sppt_min = 25, 885 .ppt_pl2_sppt_max = 80, 886 .ppt_pl3_fppt_min = 35, 887 .ppt_pl3_fppt_max = 80, 888 .nv_dynamic_boost_min = 0, 889 .nv_dynamic_boost_max = 25, 890 .nv_temp_target_min = 75, 891 .nv_temp_target_max = 87, 892 .nv_tgp_min = 80, 893 .nv_tgp_max = 95, 894 }, 895 .dc_data = &(struct power_limits) { 896 .ppt_pl1_spl_min = 15, 897 .ppt_pl1_spl_max = 35, 898 .ppt_pl2_sppt_min = 25, 899 .ppt_pl2_sppt_max = 35, 900 .ppt_pl3_fppt_min = 35, 901 .ppt_pl3_fppt_max = 65, 902 .nv_temp_target_min = 75, 903 .nv_temp_target_max = 87, 904 }, 905 .requires_fan_curve = true, 906 }, 907 }, 908 { 909 .matches = { 910 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 911 }, 912 .driver_data = &(struct power_data) { 913 .ac_data = &(struct power_limits) { 914 .ppt_pl1_spl_min = 15, 915 .ppt_pl1_spl_def = 35, 916 .ppt_pl1_spl_max = 80, 917 .ppt_pl2_sppt_min = 65, 918 .ppt_pl2_sppt_max = 80, 919 }, 920 }, 921 }, 922 { 923 .matches = { 924 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 925 }, 926 .driver_data = &(struct power_data) { 927 .ac_data = &(struct power_limits) { 928 .ppt_pl1_spl_min = 15, 929 .ppt_pl1_spl_def = 35, 930 .ppt_pl1_spl_max = 80, 931 .ppt_pl2_sppt_min = 35, 932 .ppt_pl2_sppt_def = 65, 933 .ppt_pl2_sppt_max = 80, 934 .ppt_pl3_fppt_min = 35, 935 .ppt_pl3_fppt_max = 80, 936 .nv_dynamic_boost_min = 5, 937 .nv_dynamic_boost_max = 20, 938 .nv_temp_target_min = 75, 939 .nv_temp_target_max = 87, 940 }, 941 .dc_data = &(struct power_limits) { 942 .ppt_pl1_spl_min = 15, 943 .ppt_pl1_spl_def = 25, 944 .ppt_pl1_spl_max = 65, 945 .ppt_pl2_sppt_min = 35, 946 .ppt_pl2_sppt_def = 54, 947 .ppt_pl2_sppt_max = 60, 948 .ppt_pl3_fppt_min = 35, 949 .ppt_pl3_fppt_max = 65, 950 }, 951 }, 952 }, 953 { 954 .matches = { 955 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 956 }, 957 .driver_data = &(struct power_data) { 958 .ac_data = &(struct power_limits) { 959 .ppt_pl1_spl_min = 15, 960 .ppt_pl1_spl_max = 80, 961 .ppt_pl2_sppt_min = 35, 962 .ppt_pl2_sppt_max = 80, 963 .ppt_pl3_fppt_min = 35, 964 .ppt_pl3_fppt_max = 80, 965 .nv_dynamic_boost_min = 5, 966 .nv_dynamic_boost_max = 20, 967 .nv_temp_target_min = 75, 968 .nv_temp_target_max = 87, 969 .nv_tgp_min = 55, 970 .nv_tgp_max = 85, 971 }, 972 .dc_data = &(struct power_limits) { 973 .ppt_pl1_spl_min = 25, 974 .ppt_pl1_spl_max = 35, 975 .ppt_pl2_sppt_min = 31, 976 .ppt_pl2_sppt_max = 44, 977 .ppt_pl3_fppt_min = 45, 978 .ppt_pl3_fppt_max = 65, 979 .nv_temp_target_min = 75, 980 .nv_temp_target_max = 87, 981 }, 982 .requires_fan_curve = true, 983 }, 984 }, 985 { 986 .matches = { 987 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 988 }, 989 .driver_data = &(struct power_data) { 990 .ac_data = &(struct power_limits) { 991 .ppt_pl1_spl_min = 25, 992 .ppt_pl1_spl_max = 60, 993 .ppt_pl2_sppt_min = 25, 994 .ppt_pl2_sppt_max = 135, 995 .nv_dynamic_boost_min = 5, 996 .nv_dynamic_boost_max = 20, 997 .nv_temp_target_min = 75, 998 .nv_temp_target_max = 87, 999 }, 1000 .dc_data = &(struct power_limits) { 1001 .ppt_pl1_spl_min = 25, 1002 .ppt_pl1_spl_max = 40, 1003 .ppt_pl2_sppt_min = 25, 1004 .ppt_pl2_sppt_max = 40, 1005 .nv_temp_target_min = 75, 1006 .nv_temp_target_max = 87, 1007 } 1008 }, 1009 }, 1010 { 1011 .matches = { 1012 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1013 }, 1014 .driver_data = &(struct power_data) { 1015 .ac_data = &(struct power_limits) { 1016 .ppt_pl1_spl_min = 65, 1017 .ppt_pl1_spl_max = 120, 1018 .ppt_pl2_sppt_min = 65, 1019 .ppt_pl2_sppt_max = 150, 1020 .nv_dynamic_boost_min = 5, 1021 .nv_dynamic_boost_max = 25, 1022 .nv_temp_target_min = 75, 1023 .nv_temp_target_max = 87, 1024 }, 1025 .dc_data = &(struct power_limits) { 1026 .ppt_pl1_spl_min = 25, 1027 .ppt_pl1_spl_max = 40, 1028 .ppt_pl2_sppt_min = 35, 1029 .ppt_pl2_sppt_def = 40, 1030 .ppt_pl2_sppt_max = 60, 1031 .nv_temp_target_min = 75, 1032 .nv_temp_target_max = 87, 1033 }, 1034 }, 1035 }, 1036 { 1037 .matches = { 1038 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1039 }, 1040 .driver_data = &(struct power_data) { 1041 .ac_data = &(struct power_limits) { 1042 .ppt_pl1_spl_min = 30, 1043 .ppt_pl1_spl_max = 85, 1044 .ppt_pl2_sppt_min = 38, 1045 .ppt_pl2_sppt_max = 110, 1046 .nv_dynamic_boost_min = 5, 1047 .nv_dynamic_boost_max = 20, 1048 .nv_temp_target_min = 75, 1049 .nv_temp_target_max = 87, 1050 .nv_tgp_min = 80, 1051 .nv_tgp_def = 90, 1052 .nv_tgp_max = 105, 1053 }, 1054 .dc_data = &(struct power_limits) { 1055 .ppt_pl1_spl_min = 30, 1056 .ppt_pl1_spl_max = 85, 1057 .ppt_pl2_sppt_min = 38, 1058 .ppt_pl2_sppt_max = 110, 1059 .nv_temp_target_min = 75, 1060 .nv_temp_target_max = 87, 1061 }, 1062 .requires_fan_curve = true, 1063 }, 1064 }, 1065 { 1066 .matches = { 1067 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1068 }, 1069 .driver_data = &(struct power_data) { 1070 .ac_data = &(struct power_limits) { 1071 .ppt_pl1_spl_min = 45, 1072 .ppt_pl1_spl_max = 85, 1073 .ppt_pl2_sppt_min = 56, 1074 .ppt_pl2_sppt_max = 110, 1075 .nv_dynamic_boost_min = 5, 1076 .nv_dynamic_boost_max = 20, 1077 .nv_temp_target_min = 75, 1078 .nv_temp_target_max = 87, 1079 .nv_tgp_min = 80, 1080 .nv_tgp_def = 90, 1081 .nv_tgp_max = 110, 1082 }, 1083 .dc_data = &(struct power_limits) { 1084 .ppt_pl1_spl_min = 25, 1085 .ppt_pl1_spl_max = 85, 1086 .ppt_pl2_sppt_min = 32, 1087 .ppt_pl2_sppt_max = 110, 1088 .nv_temp_target_min = 75, 1089 .nv_temp_target_max = 87, 1090 }, 1091 .requires_fan_curve = true, 1092 }, 1093 }, 1094 { 1095 .matches = { 1096 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1097 }, 1098 .driver_data = &(struct power_data) { 1099 .ac_data = &(struct power_limits) { 1100 .ppt_pl1_spl_min = 45, 1101 .ppt_pl1_spl_max = 85, 1102 .ppt_pl2_sppt_min = 56, 1103 .ppt_pl2_sppt_max = 110, 1104 .nv_dynamic_boost_min = 5, 1105 .nv_dynamic_boost_max = 20, 1106 .nv_temp_target_min = 7, 1107 .nv_temp_target_max = 87, 1108 .nv_tgp_min = 95, 1109 .nv_tgp_def = 100, 1110 .nv_tgp_max = 110, 1111 }, 1112 .dc_data = &(struct power_limits) { 1113 .ppt_pl1_spl_min = 25, 1114 .ppt_pl1_spl_max = 85, 1115 .ppt_pl2_sppt_min = 32, 1116 .ppt_pl2_sppt_max = 110, 1117 .nv_temp_target_min = 75, 1118 .nv_temp_target_max = 87, 1119 }, 1120 .requires_fan_curve = true, 1121 }, 1122 }, 1123 { 1124 .matches = { 1125 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1126 }, 1127 .driver_data = &(struct power_data) { 1128 .ac_data = &(struct power_limits) { 1129 .ppt_pl1_spl_min = 28, 1130 .ppt_pl1_spl_max = 90, 1131 .ppt_pl2_sppt_min = 28, 1132 .ppt_pl2_sppt_max = 135, 1133 .nv_dynamic_boost_min = 5, 1134 .nv_dynamic_boost_max = 20, 1135 .nv_temp_target_min = 75, 1136 .nv_temp_target_max = 87, 1137 }, 1138 .dc_data = &(struct power_limits) { 1139 .ppt_pl1_spl_min = 25, 1140 .ppt_pl1_spl_max = 35, 1141 .ppt_pl2_sppt_min = 38, 1142 .ppt_pl2_sppt_max = 53, 1143 .nv_temp_target_min = 75, 1144 .nv_temp_target_max = 87, 1145 }, 1146 .requires_fan_curve = true, 1147 }, 1148 }, 1149 { 1150 .matches = { 1151 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1152 }, 1153 .driver_data = &(struct power_data) { 1154 .ac_data = &(struct power_limits) { 1155 .ppt_pl1_spl_min = 15, 1156 .ppt_pl1_spl_max = 45, 1157 .ppt_pl2_sppt_min = 65, 1158 .ppt_pl2_sppt_max = 80, 1159 }, 1160 .dc_data = NULL, 1161 }, 1162 }, 1163 { 1164 .matches = { 1165 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1166 }, 1167 .driver_data = &(struct power_data) { 1168 .ac_data = &(struct power_limits) { 1169 .ppt_pl1_spl_min = 15, 1170 .ppt_pl1_spl_max = 45, 1171 .ppt_pl2_sppt_min = 25, 1172 .ppt_pl2_sppt_max = 54, 1173 .ppt_pl3_fppt_min = 35, 1174 .ppt_pl3_fppt_max = 65, 1175 .nv_temp_target_min = 75, 1176 .nv_temp_target_max = 87, 1177 }, 1178 .dc_data = &(struct power_limits) { 1179 .ppt_pl1_spl_min = 15, 1180 .ppt_pl1_spl_max = 35, 1181 .ppt_pl2_sppt_min = 25, 1182 .ppt_pl2_sppt_max = 35, 1183 .ppt_pl3_fppt_min = 35, 1184 .ppt_pl3_fppt_max = 65, 1185 .nv_temp_target_min = 75, 1186 .nv_temp_target_max = 87, 1187 }, 1188 }, 1189 }, 1190 { 1191 .matches = { 1192 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1193 }, 1194 .driver_data = &(struct power_data) { 1195 .ac_data = &(struct power_limits) { 1196 .ppt_pl1_spl_min = 15, 1197 .ppt_pl1_spl_def = 35, 1198 .ppt_pl1_spl_max = 90, 1199 .ppt_pl2_sppt_min = 35, 1200 .ppt_pl2_sppt_def = 54, 1201 .ppt_pl2_sppt_max = 100, 1202 .ppt_pl3_fppt_min = 35, 1203 .ppt_pl3_fppt_def = 80, 1204 .ppt_pl3_fppt_max = 125, 1205 .nv_dynamic_boost_min = 5, 1206 .nv_dynamic_boost_max = 25, 1207 .nv_temp_target_min = 75, 1208 .nv_temp_target_max = 87, 1209 }, 1210 .dc_data = &(struct power_limits) { 1211 .ppt_pl1_spl_min = 15, 1212 .ppt_pl1_spl_def = 28, 1213 .ppt_pl1_spl_max = 65, 1214 .ppt_pl2_sppt_min = 35, 1215 .ppt_pl2_sppt_def = 54, 1216 .ppt_pl2_sppt_max = 60, 1217 .ppt_pl3_fppt_min = 35, 1218 .ppt_pl3_fppt_def = 80, 1219 .ppt_pl3_fppt_max = 65, 1220 .nv_temp_target_min = 75, 1221 .nv_temp_target_max = 87, 1222 }, 1223 }, 1224 }, 1225 { 1226 .matches = { 1227 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1228 }, 1229 .driver_data = &(struct power_data) { 1230 .ac_data = &(struct power_limits) { 1231 .ppt_pl1_spl_min = 28, 1232 .ppt_pl1_spl_def = 100, 1233 .ppt_pl1_spl_max = 110, 1234 .ppt_pl2_sppt_min = 28, 1235 .ppt_pl2_sppt_max = 135, 1236 .nv_dynamic_boost_min = 5, 1237 .nv_dynamic_boost_max = 20, 1238 .nv_temp_target_min = 75, 1239 .nv_temp_target_max = 87, 1240 }, 1241 .dc_data = &(struct power_limits) { 1242 .ppt_pl1_spl_min = 25, 1243 .ppt_pl1_spl_max = 40, 1244 .ppt_pl2_sppt_min = 35, 1245 .ppt_pl2_sppt_def = 40, 1246 .ppt_pl2_sppt_max = 60, 1247 .nv_temp_target_min = 75, 1248 .nv_temp_target_max = 87, 1249 }, 1250 }, 1251 }, 1252 { 1253 .matches = { 1254 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1255 }, 1256 .driver_data = &(struct power_data) { 1257 .ac_data = &(struct power_limits) { 1258 .ppt_pl1_spl_min = 15, 1259 .ppt_pl1_spl_def = 110, 1260 .ppt_pl1_spl_max = 130, 1261 .ppt_pl2_sppt_min = 35, 1262 .ppt_pl2_sppt_def = 125, 1263 .ppt_pl2_sppt_max = 130, 1264 .ppt_pl3_fppt_min = 35, 1265 .ppt_pl3_fppt_def = 125, 1266 .ppt_pl3_fppt_max = 135, 1267 .nv_dynamic_boost_min = 5, 1268 .nv_dynamic_boost_max = 25, 1269 .nv_temp_target_min = 75, 1270 .nv_temp_target_max = 87, 1271 }, 1272 .dc_data = &(struct power_limits) { 1273 .ppt_pl1_spl_min = 15, 1274 .ppt_pl1_spl_def = 25, 1275 .ppt_pl1_spl_max = 65, 1276 .ppt_pl2_sppt_min = 35, 1277 .ppt_pl2_sppt_def = 35, 1278 .ppt_pl2_sppt_max = 65, 1279 .ppt_pl3_fppt_min = 35, 1280 .ppt_pl3_fppt_def = 42, 1281 .ppt_pl3_fppt_max = 65, 1282 .nv_temp_target_min = 75, 1283 .nv_temp_target_max = 87, 1284 }, 1285 }, 1286 }, 1287 { 1288 .matches = { 1289 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1290 }, 1291 .driver_data = &(struct power_data) { 1292 .ac_data = &(struct power_limits) { 1293 /* Yes this laptop is very limited */ 1294 .ppt_pl1_spl_min = 15, 1295 .ppt_pl1_spl_max = 80, 1296 .ppt_pl2_sppt_min = 15, 1297 .ppt_pl2_sppt_max = 80, 1298 }, 1299 .dc_data = NULL, 1300 .requires_fan_curve = true, 1301 }, 1302 }, 1303 { 1304 .matches = { 1305 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1306 }, 1307 .driver_data = &(struct power_data) { 1308 .ac_data = &(struct power_limits) { 1309 /* Yes this laptop is very limited */ 1310 .ppt_pl1_spl_min = 15, 1311 .ppt_pl1_spl_max = 100, 1312 .ppt_pl2_sppt_min = 15, 1313 .ppt_pl2_sppt_max = 190, 1314 }, 1315 .dc_data = NULL, 1316 .requires_fan_curve = true, 1317 }, 1318 }, 1319 { 1320 .matches = { 1321 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1322 }, 1323 .driver_data = &(struct power_data) { 1324 .ac_data = &(struct power_limits) { 1325 .ppt_pl1_spl_min = 35, 1326 .ppt_pl1_spl_max = 90, 1327 .ppt_pl2_sppt_min = 54, 1328 .ppt_pl2_sppt_max = 100, 1329 .ppt_pl3_fppt_min = 54, 1330 .ppt_pl3_fppt_max = 125, 1331 .nv_dynamic_boost_min = 5, 1332 .nv_dynamic_boost_max = 25, 1333 .nv_temp_target_min = 75, 1334 .nv_temp_target_max = 87, 1335 }, 1336 .dc_data = &(struct power_limits) { 1337 .ppt_pl1_spl_min = 28, 1338 .ppt_pl1_spl_max = 50, 1339 .ppt_pl2_sppt_min = 28, 1340 .ppt_pl2_sppt_max = 50, 1341 .ppt_pl3_fppt_min = 28, 1342 .ppt_pl3_fppt_max = 65, 1343 .nv_temp_target_min = 75, 1344 .nv_temp_target_max = 87, 1345 }, 1346 .requires_fan_curve = true, 1347 }, 1348 }, 1349 { 1350 .matches = { 1351 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 1352 }, 1353 .driver_data = &(struct power_data) { 1354 .ac_data = &(struct power_limits) { 1355 .ppt_pl1_spl_min = 28, 1356 .ppt_pl1_spl_max = 140, 1357 .ppt_pl2_sppt_min = 28, 1358 .ppt_pl2_sppt_max = 175, 1359 .nv_temp_target_min = 75, 1360 .nv_temp_target_max = 87, 1361 .nv_dynamic_boost_min = 5, 1362 .nv_dynamic_boost_max = 25, 1363 }, 1364 .dc_data = &(struct power_limits) { 1365 .ppt_pl1_spl_min = 25, 1366 .ppt_pl1_spl_max = 55, 1367 .ppt_pl2_sppt_min = 25, 1368 .ppt_pl2_sppt_max = 70, 1369 .nv_temp_target_min = 75, 1370 .nv_temp_target_max = 87, 1371 }, 1372 .requires_fan_curve = true, 1373 }, 1374 }, 1375 { 1376 .matches = { 1377 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 1378 }, 1379 .driver_data = &(struct power_data) { 1380 .ac_data = &(struct power_limits) { 1381 .ppt_pl1_spl_min = 28, 1382 .ppt_pl1_spl_def = 140, 1383 .ppt_pl1_spl_max = 175, 1384 .ppt_pl2_sppt_min = 28, 1385 .ppt_pl2_sppt_max = 175, 1386 .nv_temp_target_min = 75, 1387 .nv_temp_target_max = 87, 1388 .nv_dynamic_boost_min = 5, 1389 .nv_dynamic_boost_max = 25, 1390 .nv_tgp_min = 65, 1391 .nv_tgp_max = 115, 1392 }, 1393 .dc_data = &(struct power_limits) { 1394 .ppt_pl1_spl_min = 25, 1395 .ppt_pl1_spl_max = 55, 1396 .ppt_pl2_sppt_min = 25, 1397 .ppt_pl2_sppt_max = 70, 1398 .nv_temp_target_min = 75, 1399 .nv_temp_target_max = 87, 1400 }, 1401 .requires_fan_curve = true, 1402 }, 1403 }, 1404 { 1405 .matches = { 1406 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 1407 }, 1408 .driver_data = &(struct power_data) { 1409 .ac_data = &(struct power_limits) { 1410 .ppt_pl1_spl_min = 28, 1411 .ppt_pl1_spl_max = 140, 1412 .ppt_pl2_sppt_min = 28, 1413 .ppt_pl2_sppt_max = 175, 1414 .nv_temp_target_min = 75, 1415 .nv_temp_target_max = 87, 1416 .nv_dynamic_boost_min = 5, 1417 .nv_dynamic_boost_max = 25, 1418 }, 1419 .dc_data = &(struct power_limits) { 1420 .ppt_pl1_spl_min = 25, 1421 .ppt_pl1_spl_max = 55, 1422 .ppt_pl2_sppt_min = 25, 1423 .ppt_pl2_sppt_max = 70, 1424 .nv_temp_target_min = 75, 1425 .nv_temp_target_max = 87, 1426 }, 1427 .requires_fan_curve = true, 1428 }, 1429 }, 1430 { 1431 .matches = { 1432 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 1433 }, 1434 .driver_data = &(struct power_data) { 1435 .ac_data = &(struct power_limits) { 1436 .ppt_pl1_spl_min = 30, 1437 .ppt_pl1_spl_def = 120, 1438 .ppt_pl1_spl_max = 130, 1439 .ppt_pl2_sppt_min = 65, 1440 .ppt_pl2_sppt_def = 125, 1441 .ppt_pl2_sppt_max = 130, 1442 .ppt_pl3_fppt_min = 65, 1443 .ppt_pl3_fppt_def = 125, 1444 .ppt_pl3_fppt_max = 130, 1445 .nv_temp_target_min = 75, 1446 .nv_temp_target_max = 87, 1447 .nv_dynamic_boost_min = 5, 1448 .nv_dynamic_boost_max = 25, 1449 }, 1450 .dc_data = &(struct power_limits) { 1451 .ppt_pl1_spl_min = 25, 1452 .ppt_pl1_spl_max = 65, 1453 .ppt_pl2_sppt_min = 25, 1454 .ppt_pl2_sppt_max = 65, 1455 .ppt_pl3_fppt_min = 35, 1456 .ppt_pl3_fppt_max = 75, 1457 .nv_temp_target_min = 75, 1458 .nv_temp_target_max = 87, 1459 }, 1460 .requires_fan_curve = true, 1461 }, 1462 }, 1463 { 1464 .matches = { 1465 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 1466 }, 1467 .driver_data = &(struct power_data) { 1468 .ac_data = &(struct power_limits) { 1469 .ppt_pl1_spl_min = 28, 1470 .ppt_pl1_spl_max = 170, 1471 .ppt_pl2_sppt_min = 28, 1472 .ppt_pl2_sppt_max = 175, 1473 .nv_temp_target_min = 75, 1474 .nv_temp_target_max = 87, 1475 .nv_dynamic_boost_min = 5, 1476 .nv_dynamic_boost_max = 25, 1477 }, 1478 .dc_data = &(struct power_limits) { 1479 .ppt_pl1_spl_min = 28, 1480 .ppt_pl1_spl_max = 35, 1481 .ppt_pl2_sppt_min = 28, 1482 .ppt_pl2_sppt_max = 35, 1483 .nv_temp_target_min = 75, 1484 .nv_temp_target_max = 87, 1485 }, 1486 .requires_fan_curve = true, 1487 }, 1488 }, 1489 { 1490 .matches = { 1491 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 1492 }, 1493 .driver_data = &(struct power_data) { 1494 .ac_data = &(struct power_limits) { 1495 .ppt_pl1_spl_min = 30, 1496 .ppt_pl1_spl_def = 100, 1497 .ppt_pl1_spl_max = 130, 1498 .ppt_pl2_sppt_min = 65, 1499 .ppt_pl2_sppt_def = 125, 1500 .ppt_pl2_sppt_max = 130, 1501 .ppt_pl3_fppt_min = 65, 1502 .ppt_pl3_fppt_def = 125, 1503 .ppt_pl3_fppt_max = 130, 1504 .nv_temp_target_min = 75, 1505 .nv_temp_target_max = 87, 1506 .nv_dynamic_boost_min = 5, 1507 .nv_dynamic_boost_max = 25, 1508 }, 1509 .dc_data = &(struct power_limits) { 1510 .ppt_pl1_spl_min = 25, 1511 .ppt_pl1_spl_max = 65, 1512 .ppt_pl2_sppt_min = 25, 1513 .ppt_pl2_sppt_max = 65, 1514 .ppt_pl3_fppt_min = 35, 1515 .ppt_pl3_fppt_max = 75, 1516 .nv_temp_target_min = 75, 1517 .nv_temp_target_max = 87, 1518 }, 1519 .requires_fan_curve = true, 1520 }, 1521 }, 1522 { 1523 .matches = { 1524 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 1525 }, 1526 .driver_data = &(struct power_data) { 1527 .ac_data = &(struct power_limits) { 1528 .ppt_pl1_spl_min = 28, 1529 .ppt_pl1_spl_max = 140, 1530 .ppt_pl2_sppt_min = 28, 1531 .ppt_pl2_sppt_max = 140, 1532 .nv_dynamic_boost_min = 5, 1533 .nv_dynamic_boost_max = 25, 1534 }, 1535 .dc_data = &(struct power_limits) { 1536 .ppt_pl1_spl_min = 25, 1537 .ppt_pl1_spl_max = 55, 1538 .ppt_pl2_sppt_min = 25, 1539 .ppt_pl2_sppt_max = 70, 1540 }, 1541 .requires_fan_curve = true, 1542 }, 1543 }, 1544 { 1545 .matches = { 1546 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 1547 }, 1548 .driver_data = &(struct power_data) { 1549 .ac_data = &(struct power_limits) { 1550 .ppt_pl1_spl_min = 28, 1551 .ppt_pl1_spl_max = 140, 1552 .ppt_pl2_sppt_min = 28, 1553 .ppt_pl2_sppt_max = 175, 1554 .nv_dynamic_boost_min = 5, 1555 .nv_dynamic_boost_max = 25, 1556 .nv_temp_target_min = 75, 1557 .nv_temp_target_max = 87, 1558 }, 1559 .dc_data = &(struct power_limits) { 1560 .ppt_pl1_spl_min = 25, 1561 .ppt_pl1_spl_max = 55, 1562 .ppt_pl2_sppt_min = 25, 1563 .ppt_pl2_sppt_max = 70, 1564 .nv_temp_target_min = 75, 1565 .nv_temp_target_max = 87, 1566 }, 1567 .requires_fan_curve = true, 1568 }, 1569 }, 1570 { 1571 .matches = { 1572 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 1573 }, 1574 .driver_data = &(struct power_data) { 1575 .ac_data = &(struct power_limits) { 1576 .ppt_pl1_spl_min = 28, 1577 .ppt_pl1_spl_def = 140, 1578 .ppt_pl1_spl_max = 175, 1579 .ppt_pl2_sppt_min = 28, 1580 .ppt_pl2_sppt_max = 175, 1581 .nv_dynamic_boost_min = 5, 1582 .nv_dynamic_boost_max = 25, 1583 .nv_temp_target_min = 75, 1584 .nv_temp_target_max = 87, 1585 .nv_tgp_min = 80, 1586 .nv_tgp_max = 150, 1587 }, 1588 .dc_data = &(struct power_limits) { 1589 .ppt_pl1_spl_min = 25, 1590 .ppt_pl1_spl_max = 55, 1591 .ppt_pl2_sppt_min = 25, 1592 .ppt_pl2_sppt_max = 70, 1593 .nv_temp_target_min = 75, 1594 .nv_temp_target_max = 87, 1595 }, 1596 .requires_fan_curve = true, 1597 }, 1598 }, 1599 { 1600 .matches = { 1601 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 1602 }, 1603 .driver_data = &(struct power_data) { 1604 .ac_data = &(struct power_limits) { 1605 .ppt_pl1_spl_min = 15, 1606 .ppt_pl1_spl_max = 80, 1607 .ppt_pl2_sppt_min = 35, 1608 .ppt_pl2_sppt_max = 80, 1609 .ppt_pl3_fppt_min = 35, 1610 .ppt_pl3_fppt_max = 80, 1611 .nv_dynamic_boost_min = 5, 1612 .nv_dynamic_boost_max = 20, 1613 .nv_temp_target_min = 75, 1614 .nv_temp_target_max = 87, 1615 .nv_tgp_min = 55, 1616 .nv_tgp_max = 85, 1617 }, 1618 .dc_data = &(struct power_limits) { 1619 .ppt_pl1_spl_min = 25, 1620 .ppt_pl1_spl_max = 35, 1621 .ppt_pl2_sppt_min = 31, 1622 .ppt_pl2_sppt_max = 44, 1623 .ppt_pl3_fppt_min = 45, 1624 .ppt_pl3_fppt_max = 65, 1625 .nv_temp_target_min = 75, 1626 .nv_temp_target_max = 87, 1627 }, 1628 }, 1629 }, 1630 { 1631 .matches = { 1632 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 1633 }, 1634 .driver_data = &(struct power_data) { 1635 .ac_data = &(struct power_limits) { 1636 .ppt_pl1_spl_min = 7, 1637 .ppt_pl1_spl_max = 30, 1638 .ppt_pl2_sppt_min = 15, 1639 .ppt_pl2_sppt_max = 43, 1640 .ppt_pl3_fppt_min = 15, 1641 .ppt_pl3_fppt_max = 53, 1642 }, 1643 .dc_data = &(struct power_limits) { 1644 .ppt_pl1_spl_min = 7, 1645 .ppt_pl1_spl_def = 15, 1646 .ppt_pl1_spl_max = 25, 1647 .ppt_pl2_sppt_min = 15, 1648 .ppt_pl2_sppt_def = 20, 1649 .ppt_pl2_sppt_max = 30, 1650 .ppt_pl3_fppt_min = 15, 1651 .ppt_pl3_fppt_def = 25, 1652 .ppt_pl3_fppt_max = 35, 1653 }, 1654 }, 1655 }, 1656 { 1657 .matches = { 1658 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 1659 }, 1660 .driver_data = &(struct power_data) { 1661 .ac_data = &(struct power_limits) { 1662 .ppt_pl1_spl_min = 7, 1663 .ppt_pl1_spl_max = 30, 1664 .ppt_pl2_sppt_min = 15, 1665 .ppt_pl2_sppt_max = 43, 1666 .ppt_pl3_fppt_min = 15, 1667 .ppt_pl3_fppt_max = 53, 1668 }, 1669 .dc_data = &(struct power_limits) { 1670 .ppt_pl1_spl_min = 7, 1671 .ppt_pl1_spl_def = 17, 1672 .ppt_pl1_spl_max = 25, 1673 .ppt_pl2_sppt_min = 15, 1674 .ppt_pl2_sppt_def = 24, 1675 .ppt_pl2_sppt_max = 30, 1676 .ppt_pl3_fppt_min = 15, 1677 .ppt_pl3_fppt_def = 30, 1678 .ppt_pl3_fppt_max = 35, 1679 }, 1680 }, 1681 }, 1682 { 1683 .matches = { 1684 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 1685 }, 1686 .driver_data = &(struct power_data) { 1687 .ac_data = &(struct power_limits) { 1688 .ppt_pl1_spl_min = 7, 1689 .ppt_pl1_spl_max = 35, 1690 .ppt_pl2_sppt_min = 14, 1691 .ppt_pl2_sppt_max = 45, 1692 .ppt_pl3_fppt_min = 19, 1693 .ppt_pl3_fppt_max = 55, 1694 }, 1695 .dc_data = &(struct power_limits) { 1696 .ppt_pl1_spl_min = 7, 1697 .ppt_pl1_spl_def = 17, 1698 .ppt_pl1_spl_max = 35, 1699 .ppt_pl2_sppt_min = 13, 1700 .ppt_pl2_sppt_def = 21, 1701 .ppt_pl2_sppt_max = 45, 1702 .ppt_pl3_fppt_min = 19, 1703 .ppt_pl3_fppt_def = 26, 1704 .ppt_pl3_fppt_max = 55, 1705 }, 1706 }, 1707 }, 1708 {} 1709 }; 1710 1711 #endif /* _ASUS_ARMOURY_H_ */ 1712