1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car X5H (R8A78000) SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "renesas,r8a78000"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu-map { 21 cluster0 { 22 core0 { 23 cpu = <&a720_0>; 24 }; 25 core1 { 26 cpu = <&a720_1>; 27 }; 28 core2 { 29 cpu = <&a720_2>; 30 }; 31 core3 { 32 cpu = <&a720_3>; 33 }; 34 }; 35 36 cluster1 { 37 core0 { 38 cpu = <&a720_4>; 39 }; 40 core1 { 41 cpu = <&a720_5>; 42 }; 43 core2 { 44 cpu = <&a720_6>; 45 }; 46 core3 { 47 cpu = <&a720_7>; 48 }; 49 }; 50 51 cluster2 { 52 core0 { 53 cpu = <&a720_8>; 54 }; 55 core1 { 56 cpu = <&a720_9>; 57 }; 58 core2 { 59 cpu = <&a720_10>; 60 }; 61 core3 { 62 cpu = <&a720_11>; 63 }; 64 }; 65 66 cluster3 { 67 core0 { 68 cpu = <&a720_12>; 69 }; 70 core1 { 71 cpu = <&a720_13>; 72 }; 73 core2 { 74 cpu = <&a720_14>; 75 }; 76 core3 { 77 cpu = <&a720_15>; 78 }; 79 }; 80 81 cluster4 { 82 core0 { 83 cpu = <&a720_16>; 84 }; 85 core1 { 86 cpu = <&a720_17>; 87 }; 88 core2 { 89 cpu = <&a720_18>; 90 }; 91 core3 { 92 cpu = <&a720_19>; 93 }; 94 }; 95 96 cluster5 { 97 core0 { 98 cpu = <&a720_20>; 99 }; 100 core1 { 101 cpu = <&a720_21>; 102 }; 103 core2 { 104 cpu = <&a720_22>; 105 }; 106 core3 { 107 cpu = <&a720_23>; 108 }; 109 }; 110 111 cluster6 { 112 core0 { 113 cpu = <&a720_24>; 114 }; 115 core1 { 116 cpu = <&a720_25>; 117 }; 118 core2 { 119 cpu = <&a720_26>; 120 }; 121 core3 { 122 cpu = <&a720_27>; 123 }; 124 }; 125 126 cluster7 { 127 core0 { 128 cpu = <&a720_28>; 129 }; 130 core1 { 131 cpu = <&a720_29>; 132 }; 133 core2 { 134 cpu = <&a720_30>; 135 }; 136 core3 { 137 cpu = <&a720_31>; 138 }; 139 }; 140 }; 141 142 a720_0: cpu@0 { 143 compatible = "arm,cortex-a720ae"; 144 reg = <0x0 0x0>; 145 device_type = "cpu"; 146 next-level-cache = <&L2_CA720_0>; 147 }; 148 149 a720_1: cpu@100 { 150 compatible = "arm,cortex-a720ae"; 151 reg = <0x0 0x100>; 152 device_type = "cpu"; 153 next-level-cache = <&L2_CA720_1>; 154 }; 155 156 a720_2: cpu@200 { 157 compatible = "arm,cortex-a720ae"; 158 reg = <0x0 0x200>; 159 device_type = "cpu"; 160 next-level-cache = <&L2_CA720_2>; 161 }; 162 163 a720_3: cpu@300 { 164 compatible = "arm,cortex-a720ae"; 165 reg = <0x0 0x300>; 166 device_type = "cpu"; 167 next-level-cache = <&L2_CA720_3>; 168 }; 169 170 a720_4: cpu@10000 { 171 compatible = "arm,cortex-a720ae"; 172 reg = <0x0 0x10000>; 173 device_type = "cpu"; 174 next-level-cache = <&L2_CA720_4>; 175 }; 176 177 a720_5: cpu@10100 { 178 compatible = "arm,cortex-a720ae"; 179 reg = <0x0 0x10100>; 180 device_type = "cpu"; 181 next-level-cache = <&L2_CA720_5>; 182 }; 183 184 a720_6: cpu@10200 { 185 compatible = "arm,cortex-a720ae"; 186 reg = <0x0 0x10200>; 187 device_type = "cpu"; 188 next-level-cache = <&L2_CA720_6>; 189 }; 190 191 a720_7: cpu@10300 { 192 compatible = "arm,cortex-a720ae"; 193 reg = <0x0 0x10300>; 194 device_type = "cpu"; 195 next-level-cache = <&L2_CA720_7>; 196 }; 197 198 a720_8: cpu@20000 { 199 compatible = "arm,cortex-a720ae"; 200 reg = <0x0 0x20000>; 201 device_type = "cpu"; 202 next-level-cache = <&L2_CA720_8>; 203 }; 204 205 a720_9: cpu@20100 { 206 compatible = "arm,cortex-a720ae"; 207 reg = <0x0 0x20100>; 208 device_type = "cpu"; 209 next-level-cache = <&L2_CA720_9>; 210 }; 211 212 a720_10: cpu@20200 { 213 compatible = "arm,cortex-a720ae"; 214 reg = <0x0 0x20200>; 215 device_type = "cpu"; 216 next-level-cache = <&L2_CA720_10>; 217 }; 218 219 a720_11: cpu@20300 { 220 compatible = "arm,cortex-a720ae"; 221 reg = <0x0 0x20300>; 222 device_type = "cpu"; 223 next-level-cache = <&L2_CA720_11>; 224 }; 225 226 a720_12: cpu@30000 { 227 compatible = "arm,cortex-a720ae"; 228 reg = <0x0 0x30000>; 229 device_type = "cpu"; 230 next-level-cache = <&L2_CA720_12>; 231 }; 232 233 a720_13: cpu@30100 { 234 compatible = "arm,cortex-a720ae"; 235 reg = <0x0 0x30100>; 236 device_type = "cpu"; 237 next-level-cache = <&L2_CA720_13>; 238 }; 239 240 a720_14: cpu@30200 { 241 compatible = "arm,cortex-a720ae"; 242 reg = <0x0 0x30200>; 243 device_type = "cpu"; 244 next-level-cache = <&L2_CA720_14>; 245 }; 246 247 a720_15: cpu@30300 { 248 compatible = "arm,cortex-a720ae"; 249 reg = <0x0 0x30300>; 250 device_type = "cpu"; 251 next-level-cache = <&L2_CA720_15>; 252 }; 253 254 a720_16: cpu@40000 { 255 compatible = "arm,cortex-a720ae"; 256 reg = <0x0 0x40000>; 257 device_type = "cpu"; 258 next-level-cache = <&L2_CA720_16>; 259 }; 260 261 a720_17: cpu@40100 { 262 compatible = "arm,cortex-a720ae"; 263 reg = <0x0 0x40100>; 264 device_type = "cpu"; 265 next-level-cache = <&L2_CA720_17>; 266 }; 267 268 a720_18: cpu@40200 { 269 compatible = "arm,cortex-a720ae"; 270 reg = <0x0 0x40200>; 271 device_type = "cpu"; 272 next-level-cache = <&L2_CA720_18>; 273 }; 274 275 a720_19: cpu@40300 { 276 compatible = "arm,cortex-a720ae"; 277 reg = <0x0 0x40300>; 278 device_type = "cpu"; 279 next-level-cache = <&L2_CA720_19>; 280 }; 281 282 a720_20: cpu@50000 { 283 compatible = "arm,cortex-a720ae"; 284 reg = <0x0 0x50000>; 285 device_type = "cpu"; 286 next-level-cache = <&L2_CA720_20>; 287 }; 288 289 a720_21: cpu@50100 { 290 compatible = "arm,cortex-a720ae"; 291 reg = <0x0 0x50100>; 292 device_type = "cpu"; 293 next-level-cache = <&L2_CA720_21>; 294 }; 295 296 a720_22: cpu@50200 { 297 compatible = "arm,cortex-a720ae"; 298 reg = <0x0 0x50200>; 299 device_type = "cpu"; 300 next-level-cache = <&L2_CA720_22>; 301 }; 302 303 a720_23: cpu@50300 { 304 compatible = "arm,cortex-a720ae"; 305 reg = <0x0 0x50300>; 306 device_type = "cpu"; 307 next-level-cache = <&L2_CA720_23>; 308 }; 309 310 a720_24: cpu@60000 { 311 compatible = "arm,cortex-a720ae"; 312 reg = <0x0 0x60000>; 313 device_type = "cpu"; 314 next-level-cache = <&L2_CA720_24>; 315 }; 316 317 a720_25: cpu@60100 { 318 compatible = "arm,cortex-a720ae"; 319 reg = <0x0 0x60100>; 320 device_type = "cpu"; 321 next-level-cache = <&L2_CA720_25>; 322 }; 323 324 a720_26: cpu@60200 { 325 compatible = "arm,cortex-a720ae"; 326 reg = <0x0 0x60200>; 327 device_type = "cpu"; 328 next-level-cache = <&L2_CA720_26>; 329 }; 330 331 a720_27: cpu@60300 { 332 compatible = "arm,cortex-a720ae"; 333 reg = <0x0 0x60300>; 334 device_type = "cpu"; 335 next-level-cache = <&L2_CA720_27>; 336 }; 337 338 a720_28: cpu@70000 { 339 compatible = "arm,cortex-a720ae"; 340 reg = <0x0 0x70000>; 341 device_type = "cpu"; 342 next-level-cache = <&L2_CA720_28>; 343 }; 344 345 a720_29: cpu@70100 { 346 compatible = "arm,cortex-a720ae"; 347 reg = <0x0 0x70100>; 348 device_type = "cpu"; 349 next-level-cache = <&L2_CA720_29>; 350 }; 351 352 a720_30: cpu@70200 { 353 compatible = "arm,cortex-a720ae"; 354 reg = <0x0 0x70200>; 355 device_type = "cpu"; 356 next-level-cache = <&L2_CA720_30>; 357 }; 358 359 a720_31: cpu@70300 { 360 compatible = "arm,cortex-a720ae"; 361 reg = <0x0 0x70300>; 362 device_type = "cpu"; 363 next-level-cache = <&L2_CA720_31>; 364 }; 365 366 L2_CA720_0: cache-controller-200 { 367 compatible = "cache"; 368 cache-unified; 369 cache-level = <2>; 370 next-level-cache = <&L3_CA720_0>; 371 }; 372 373 L2_CA720_1: cache-controller-201 { 374 compatible = "cache"; 375 cache-unified; 376 cache-level = <2>; 377 next-level-cache = <&L3_CA720_0>; 378 }; 379 380 L2_CA720_2: cache-controller-202 { 381 compatible = "cache"; 382 cache-unified; 383 cache-level = <2>; 384 next-level-cache = <&L3_CA720_0>; 385 }; 386 387 L2_CA720_3: cache-controller-203 { 388 compatible = "cache"; 389 cache-unified; 390 cache-level = <2>; 391 next-level-cache = <&L3_CA720_0>; 392 }; 393 394 L2_CA720_4: cache-controller-204 { 395 compatible = "cache"; 396 cache-unified; 397 cache-level = <2>; 398 next-level-cache = <&L3_CA720_1>; 399 }; 400 401 L2_CA720_5: cache-controller-205 { 402 compatible = "cache"; 403 cache-unified; 404 cache-level = <2>; 405 next-level-cache = <&L3_CA720_1>; 406 }; 407 408 L2_CA720_6: cache-controller-206 { 409 compatible = "cache"; 410 cache-unified; 411 cache-level = <2>; 412 next-level-cache = <&L3_CA720_1>; 413 }; 414 415 L2_CA720_7: cache-controller-207 { 416 compatible = "cache"; 417 cache-unified; 418 cache-level = <2>; 419 next-level-cache = <&L3_CA720_1>; 420 }; 421 422 L2_CA720_8: cache-controller-208 { 423 compatible = "cache"; 424 cache-unified; 425 cache-level = <2>; 426 next-level-cache = <&L3_CA720_2>; 427 }; 428 429 L2_CA720_9: cache-controller-209 { 430 compatible = "cache"; 431 cache-unified; 432 cache-level = <2>; 433 next-level-cache = <&L3_CA720_2>; 434 }; 435 436 L2_CA720_10: cache-controller-210 { 437 compatible = "cache"; 438 cache-unified; 439 cache-level = <2>; 440 next-level-cache = <&L3_CA720_2>; 441 }; 442 443 L2_CA720_11: cache-controller-211 { 444 compatible = "cache"; 445 cache-unified; 446 cache-level = <2>; 447 next-level-cache = <&L3_CA720_2>; 448 }; 449 450 L2_CA720_12: cache-controller-212 { 451 compatible = "cache"; 452 cache-unified; 453 cache-level = <2>; 454 next-level-cache = <&L3_CA720_3>; 455 }; 456 457 L2_CA720_13: cache-controller-213 { 458 compatible = "cache"; 459 cache-unified; 460 cache-level = <2>; 461 next-level-cache = <&L3_CA720_3>; 462 }; 463 464 L2_CA720_14: cache-controller-214 { 465 compatible = "cache"; 466 cache-unified; 467 cache-level = <2>; 468 next-level-cache = <&L3_CA720_3>; 469 }; 470 471 L2_CA720_15: cache-controller-215 { 472 compatible = "cache"; 473 cache-unified; 474 cache-level = <2>; 475 next-level-cache = <&L3_CA720_3>; 476 }; 477 478 L2_CA720_16: cache-controller-216 { 479 compatible = "cache"; 480 cache-unified; 481 cache-level = <2>; 482 next-level-cache = <&L3_CA720_4>; 483 }; 484 485 L2_CA720_17: cache-controller-217 { 486 compatible = "cache"; 487 cache-unified; 488 cache-level = <2>; 489 next-level-cache = <&L3_CA720_4>; 490 }; 491 492 L2_CA720_18: cache-controller-218 { 493 compatible = "cache"; 494 cache-unified; 495 cache-level = <2>; 496 next-level-cache = <&L3_CA720_4>; 497 }; 498 499 L2_CA720_19: cache-controller-219 { 500 compatible = "cache"; 501 cache-unified; 502 cache-level = <2>; 503 next-level-cache = <&L3_CA720_4>; 504 }; 505 506 L2_CA720_20: cache-controller-220 { 507 compatible = "cache"; 508 cache-unified; 509 cache-level = <2>; 510 next-level-cache = <&L3_CA720_5>; 511 }; 512 513 L2_CA720_21: cache-controller-221 { 514 compatible = "cache"; 515 cache-unified; 516 cache-level = <2>; 517 next-level-cache = <&L3_CA720_5>; 518 }; 519 520 L2_CA720_22: cache-controller-222 { 521 compatible = "cache"; 522 cache-unified; 523 cache-level = <2>; 524 next-level-cache = <&L3_CA720_5>; 525 }; 526 527 L2_CA720_23: cache-controller-223 { 528 compatible = "cache"; 529 cache-unified; 530 cache-level = <2>; 531 next-level-cache = <&L3_CA720_5>; 532 }; 533 534 L2_CA720_24: cache-controller-224 { 535 compatible = "cache"; 536 cache-unified; 537 cache-level = <2>; 538 next-level-cache = <&L3_CA720_6>; 539 }; 540 541 L2_CA720_25: cache-controller-225 { 542 compatible = "cache"; 543 cache-unified; 544 cache-level = <2>; 545 next-level-cache = <&L3_CA720_6>; 546 }; 547 548 L2_CA720_26: cache-controller-226 { 549 compatible = "cache"; 550 cache-unified; 551 cache-level = <2>; 552 next-level-cache = <&L3_CA720_6>; 553 }; 554 555 L2_CA720_27: cache-controller-227 { 556 compatible = "cache"; 557 cache-unified; 558 cache-level = <2>; 559 next-level-cache = <&L3_CA720_6>; 560 }; 561 562 L2_CA720_28: cache-controller-228 { 563 compatible = "cache"; 564 cache-unified; 565 cache-level = <2>; 566 next-level-cache = <&L3_CA720_7>; 567 }; 568 569 L2_CA720_29: cache-controller-229 { 570 compatible = "cache"; 571 cache-unified; 572 cache-level = <2>; 573 next-level-cache = <&L3_CA720_7>; 574 }; 575 576 L2_CA720_30: cache-controller-230 { 577 compatible = "cache"; 578 cache-unified; 579 cache-level = <2>; 580 next-level-cache = <&L3_CA720_7>; 581 }; 582 583 L2_CA720_31: cache-controller-231 { 584 compatible = "cache"; 585 cache-unified; 586 cache-level = <2>; 587 next-level-cache = <&L3_CA720_7>; 588 }; 589 590 L3_CA720_0: cache-controller-30 { 591 compatible = "cache"; 592 cache-unified; 593 cache-level = <3>; 594 }; 595 596 L3_CA720_1: cache-controller-31 { 597 compatible = "cache"; 598 cache-unified; 599 cache-level = <3>; 600 }; 601 602 L3_CA720_2: cache-controller-32 { 603 compatible = "cache"; 604 cache-unified; 605 cache-level = <3>; 606 }; 607 608 L3_CA720_3: cache-controller-33 { 609 compatible = "cache"; 610 cache-unified; 611 cache-level = <3>; 612 }; 613 614 L3_CA720_4: cache-controller-34 { 615 compatible = "cache"; 616 cache-unified; 617 cache-level = <3>; 618 }; 619 620 L3_CA720_5: cache-controller-35 { 621 compatible = "cache"; 622 cache-unified; 623 cache-level = <3>; 624 }; 625 626 L3_CA720_6: cache-controller-36 { 627 compatible = "cache"; 628 cache-unified; 629 cache-level = <3>; 630 }; 631 632 L3_CA720_7: cache-controller-37 { 633 compatible = "cache"; 634 cache-unified; 635 cache-level = <3>; 636 }; 637 }; 638 639 /* 640 * In the early phase, there is no clock control support, 641 * so assume that the clocks are enabled by default. 642 * Therefore, dummy clocks are used. 643 */ 644 dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { 645 compatible = "fixed-clock"; 646 #clock-cells = <0>; 647 clock-frequency = <66666000>; 648 }; 649 650 dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { 651 compatible = "fixed-clock"; 652 #clock-cells = <0>; 653 clock-frequency = <266660000>; 654 }; 655 656 extal_clk: extal-clk { 657 compatible = "fixed-clock"; 658 #clock-cells = <0>; 659 /* clock-frequency must be set on board */ 660 }; 661 662 extalr_clk: extalr-clk { 663 compatible = "fixed-clock"; 664 #clock-cells = <0>; 665 /* clock-frequency must be set on board */ 666 }; 667 668 psci { 669 compatible = "arm,psci-1.0"; 670 method = "smc"; 671 }; 672 673 /* External SCIF clock - to be overridden by boards that provide it */ 674 scif_clk: scif-clk { 675 compatible = "fixed-clock"; 676 #clock-cells = <0>; 677 clock-frequency = <0>; /* optional */ 678 }; 679 680 soc: soc { 681 compatible = "simple-bus"; 682 #address-cells = <2>; 683 #size-cells = <2>; 684 ranges; 685 686 mfis: system-controller@189e0000 { 687 compatible = "renesas,r8a78000-mfis"; 688 reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>; 689 reg-names = "common", "mboxes"; 690 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", 755 "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", 756 "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", 757 "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", 758 "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", 759 "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", 760 "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", 761 "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", 762 "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", 763 "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", 764 "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", 765 "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", 766 "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", 767 "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", 768 "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", 769 "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; 770 #mbox-cells = <2>; 771 #hwlock-cells = <1>; 772 status = "disabled"; 773 }; 774 775 mfis_scp: system-controller@189e1000 { 776 compatible = "renesas,r8a78000-mfis-scp"; 777 reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>; 778 reg-names = "common", "mboxes"; 779 interrupts = <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_ESPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 321 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_ESPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 323 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_ESPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 325 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_ESPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 327 IRQ_TYPE_LEVEL_HIGH>; 795 /* SCP uses I side IRQ only */ 796 interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i", 797 "ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i", 798 "ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i", 799 "ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i"; 800 #mbox-cells = <2>; 801 #hwlock-cells = <1>; 802 status = "disabled"; 803 }; 804 805 /* Application Processors manage View-1 of a GIC-720AE */ 806 gic: interrupt-controller@39000000 { 807 compatible = "arm,gic-v3"; 808 #interrupt-cells = <3>; 809 #address-cells = <0>; 810 interrupt-controller; 811 #redistributor-regions = <32>; 812 reg = <0x0 0x39000000 0x0 0x10000>, 813 <0x0 0x39080000 0x0 0x40000>, 814 <0x0 0x390c0000 0x0 0x40000>, 815 <0x0 0x39100000 0x0 0x40000>, 816 <0x0 0x39140000 0x0 0x40000>, 817 <0x0 0x39180000 0x0 0x40000>, 818 <0x0 0x391c0000 0x0 0x40000>, 819 <0x0 0x39200000 0x0 0x40000>, 820 <0x0 0x39240000 0x0 0x40000>, 821 <0x0 0x39280000 0x0 0x40000>, 822 <0x0 0x392c0000 0x0 0x40000>, 823 <0x0 0x39300000 0x0 0x40000>, 824 <0x0 0x39340000 0x0 0x40000>, 825 <0x0 0x39380000 0x0 0x40000>, 826 <0x0 0x393c0000 0x0 0x40000>, 827 <0x0 0x39400000 0x0 0x40000>, 828 <0x0 0x39440000 0x0 0x40000>, 829 <0x0 0x39480000 0x0 0x40000>, 830 <0x0 0x394c0000 0x0 0x40000>, 831 <0x0 0x39500000 0x0 0x40000>, 832 <0x0 0x39540000 0x0 0x40000>, 833 <0x0 0x39580000 0x0 0x40000>, 834 <0x0 0x395c0000 0x0 0x40000>, 835 <0x0 0x39600000 0x0 0x40000>, 836 <0x0 0x39640000 0x0 0x40000>, 837 <0x0 0x39680000 0x0 0x40000>, 838 <0x0 0x396c0000 0x0 0x40000>, 839 <0x0 0x39700000 0x0 0x40000>, 840 <0x0 0x39740000 0x0 0x40000>, 841 <0x0 0x39780000 0x0 0x40000>, 842 <0x0 0x397c0000 0x0 0x40000>, 843 <0x0 0x39800000 0x0 0x40000>, 844 <0x0 0x39840000 0x0 0x40000>; 845 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 846 }; 847 848 scif0: serial@c0700000 { 849 compatible = "renesas,scif-r8a78000", 850 "renesas,rcar-gen5-scif", "renesas,scif"; 851 reg = <0 0xc0700000 0 0x40>; 852 interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 854 clock-names = "fck", "brg_int", "scif_clk"; 855 status = "disabled"; 856 }; 857 858 scif1: serial@c0704000 { 859 compatible = "renesas,scif-r8a78000", 860 "renesas,rcar-gen5-scif", "renesas,scif"; 861 reg = <0 0xc0704000 0 0x40>; 862 interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 864 clock-names = "fck", "brg_int", "scif_clk"; 865 status = "disabled"; 866 }; 867 868 scif3: serial@c0708000 { 869 compatible = "renesas,scif-r8a78000", 870 "renesas,rcar-gen5-scif", "renesas,scif"; 871 reg = <0 0xc0708000 0 0x40>; 872 interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 874 clock-names = "fck", "brg_int", "scif_clk"; 875 status = "disabled"; 876 }; 877 878 scif4: serial@c070c000 { 879 compatible = "renesas,scif-r8a78000", 880 "renesas,rcar-gen5-scif", "renesas,scif"; 881 reg = <0 0xc070c000 0 0x40>; 882 interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 884 clock-names = "fck", "brg_int", "scif_clk"; 885 status = "disabled"; 886 }; 887 888 hscif0: serial@c0710000 { 889 compatible = "renesas,hscif-r8a78000", 890 "renesas,rcar-gen5-hscif", "renesas,hscif"; 891 reg = <0 0xc0710000 0 0x60>; 892 interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 894 clock-names = "fck", "brg_int", "scif_clk"; 895 status = "disabled"; 896 }; 897 898 hscif1: serial@c0714000 { 899 compatible = "renesas,hscif-r8a78000", 900 "renesas,rcar-gen5-hscif", "renesas,hscif"; 901 reg = <0 0xc0714000 0 0x60>; 902 interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 904 clock-names = "fck", "brg_int", "scif_clk"; 905 status = "disabled"; 906 }; 907 908 hscif2: serial@c0718000 { 909 compatible = "renesas,hscif-r8a78000", 910 "renesas,rcar-gen5-hscif", "renesas,hscif"; 911 reg = <0 0xc0718000 0 0x60>; 912 interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 914 clock-names = "fck", "brg_int", "scif_clk"; 915 status = "disabled"; 916 }; 917 918 hscif3: serial@c071c000 { 919 compatible = "renesas,hscif-r8a78000", 920 "renesas,rcar-gen5-hscif", "renesas,hscif"; 921 reg = <0 0xc071c000 0 0x60>; 922 interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 924 clock-names = "fck", "brg_int", "scif_clk"; 925 status = "disabled"; 926 }; 927 928 stcm_transport: sram@c1060000 { 929 compatible = "mmio-sram"; 930 reg = <0x0 0xc1060000 0x0 0x1c00>; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 ranges = <0 0x0 0xc1060000 0x1c00>; 934 /* actual transport nodes must be set per board file */ 935 }; 936 }; 937 938 timer { 939 compatible = "arm,armv8-timer"; 940 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 941 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 942 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 943 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 944 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 945 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 946 }; 947}; 948