1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "msm_perfcntr.h" 9 #include "a6xx_gpu.h" 10 #include "a6xx_gmu.xml.h" 11 12 #include <linux/bitfield.h> 13 #include <linux/devfreq.h> 14 #include <linux/pm_domain.h> 15 #include <linux/soc/qcom/llcc-qcom.h> 16 17 #define GPU_PAS_ID 13 18 19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) 20 { 21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 23 u64 count_hi, count_lo, temp; 24 25 do { 26 if (adreno_is_a750_family(adreno_gpu)) { 27 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); 28 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L); 29 temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); 30 } else { 31 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 32 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); 33 temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); 34 } 35 } while (unlikely(count_hi != temp)); 36 37 return (count_hi << 32) | count_lo; 38 } 39 40 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) 41 { 42 /* Success if !writedropped0/1 */ 43 if (!(status & mask)) 44 return true; 45 46 udelay(10); 47 48 /* Try to update fenced register again */ 49 gpu_write(gpu, offset, value); 50 51 /* We can't do a posted write here because the power domain could be 52 * in collapse state. So use the heaviest barrier instead 53 */ 54 mb(); 55 return false; 56 } 57 58 static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask) 59 { 60 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 61 struct msm_gpu *gpu = &adreno_gpu->base; 62 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 63 u32 status; 64 65 gpu_write(gpu, offset, value); 66 67 /* Nothing else to be done in the case of no-GMU */ 68 if (adreno_has_gmu_wrapper(adreno_gpu)) 69 return 0; 70 71 /* We can't do a posted write here because the power domain could be 72 * in collapse state. So use the heaviest barrier instead 73 */ 74 mb(); 75 76 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 77 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) 78 return 0; 79 80 /* Try again for another 1ms before failing */ 81 gpu_write(gpu, offset, value); 82 mb(); 83 84 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, 85 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) { 86 /* 87 * The 'delay' warning is here because the pause to print this 88 * warning will allow gpu to move to power collapse which 89 * defeats the purpose of continuous polling for 2 ms 90 */ 91 dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", 92 offset); 93 return 0; 94 } 95 96 dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", 97 offset); 98 99 return -ETIMEDOUT; 100 } 101 102 int a6xx_fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u64 value, u32 mask, bool is_64b) 103 { 104 int ret; 105 106 ret = fenced_write(a6xx_gpu, offset, lower_32_bits(value), mask); 107 if (ret) 108 return ret; 109 110 if (!is_64b) 111 return 0; 112 113 ret = fenced_write(a6xx_gpu, offset + 1, upper_32_bits(value), mask); 114 115 return ret; 116 } 117 118 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 119 { 120 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 121 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 122 123 /* Check that the GMU is idle */ 124 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 125 return false; 126 127 /* Check tha the CX master is idle */ 128 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 129 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 130 return false; 131 132 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 133 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 134 } 135 136 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 137 { 138 /* wait for CP to drain ringbuffer: */ 139 if (!adreno_idle(gpu, ring)) 140 return false; 141 142 if (spin_until(_a6xx_check_idle(gpu))) { 143 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 144 gpu->name, __builtin_return_address(0), 145 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 146 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 147 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 148 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 149 return false; 150 } 151 152 return true; 153 } 154 155 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 156 { 157 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 158 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 159 160 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 161 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 162 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 163 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 164 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 165 } 166 } 167 168 void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 169 { 170 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 171 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 172 uint32_t wptr; 173 unsigned long flags; 174 175 update_shadow_rptr(gpu, ring); 176 177 spin_lock_irqsave(&ring->preempt_lock, flags); 178 179 /* Copy the shadow to the actual register */ 180 ring->cur = ring->next; 181 182 /* Make sure to wrap wptr if we need to */ 183 wptr = get_wptr(ring); 184 185 /* Update HW if this is the current ring and we are not in preempt*/ 186 if (!a6xx_in_preempt(a6xx_gpu)) { 187 if (a6xx_gpu->cur_ring == ring) 188 a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false); 189 else 190 ring->restore_wptr = true; 191 } else { 192 ring->restore_wptr = true; 193 } 194 195 spin_unlock_irqrestore(&ring->preempt_lock, flags); 196 } 197 198 void 199 a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 200 { 201 /* If preemption is enabled */ 202 if (gpu->nr_rings > 1) { 203 /* Yield the floor on command completion */ 204 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); 205 206 /* 207 * If dword[2:1] are non zero, they specify an address for 208 * the CP to write the value of dword[3] to on preemption 209 * complete. Write 0 to skip the write 210 */ 211 OUT_RING(ring, 0x00); 212 OUT_RING(ring, 0x00); 213 /* Data value - not used if the address above is 0 */ 214 OUT_RING(ring, 0x01); 215 /* generate interrupt on preemption completion */ 216 OUT_RING(ring, 0x00); 217 } 218 219 a6xx_flush(gpu, ring); 220 } 221 222 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 223 u64 iova) 224 { 225 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 226 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 227 CP_REG_TO_MEM_0_CNT(2) | 228 CP_REG_TO_MEM_0_IS_64B); 229 OUT_RING(ring, lower_32_bits(iova)); 230 OUT_RING(ring, upper_32_bits(iova)); 231 } 232 233 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 234 struct msm_ringbuffer *ring, struct msm_gem_submit *submit) 235 { 236 bool sysprof = msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base); 237 struct msm_context *ctx = submit->queue->ctx; 238 struct drm_gpuvm *vm = ctx->vm; 239 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 240 phys_addr_t ttbr; 241 u32 asid; 242 u64 memptr = rbmemptr(ring, ttbr0); 243 244 if (ctx->seqno == ring->cur_ctx_seqno) 245 return; 246 247 if (msm_iommu_pagetable_params(to_msm_vm(vm)->mmu, &ttbr, &asid)) 248 return; 249 250 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) { 251 /* Wait for previous submit to complete before continuing: */ 252 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 253 OUT_RING(ring, 0); 254 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 255 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 256 OUT_RING(ring, submit->seqno - 1); 257 258 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 259 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); 260 261 /* Reset state used to synchronize BR and BV */ 262 OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1); 263 OUT_RING(ring, 264 CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS | 265 CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE | 266 CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER | 267 CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS); 268 269 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 270 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); 271 272 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 273 OUT_RING(ring, LRZ_FLUSH_INVALIDATE); 274 275 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 276 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 277 } 278 279 if (!sysprof) { 280 if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) { 281 /* Turn off protected mode to write to special registers */ 282 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 283 OUT_RING(ring, 0); 284 } 285 286 if (adreno_is_a8xx(adreno_gpu)) { 287 OUT_PKT4(ring, REG_A8XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 288 OUT_RING(ring, 1); 289 OUT_PKT4(ring, REG_A8XX_RBBM_SLICE_PERFCTR_SRAM_INIT_CMD, 1); 290 OUT_RING(ring, 1); 291 } else { 292 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 293 OUT_RING(ring, 1); 294 } 295 } 296 297 /* Execute the table update */ 298 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 299 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 300 301 OUT_RING(ring, 302 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 303 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 304 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 305 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 306 307 /* 308 * Write the new TTBR0 to the memstore. This is good for debugging. 309 * Needed for preemption 310 */ 311 OUT_PKT7(ring, CP_MEM_WRITE, 5); 312 OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_LO(lower_32_bits(memptr))); 313 OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_HI(upper_32_bits(memptr))); 314 OUT_RING(ring, lower_32_bits(ttbr)); 315 OUT_RING(ring, upper_32_bits(ttbr)); 316 OUT_RING(ring, ctx->seqno); 317 318 /* 319 * Sync both threads after switching pagetables and enable BR only 320 * to make sure BV doesn't race ahead while BR is still switching 321 * pagetables. 322 */ 323 if (adreno_is_a7xx(&a6xx_gpu->base) || adreno_is_a8xx(&a6xx_gpu->base)) { 324 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 325 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 326 } 327 328 /* 329 * And finally, trigger a uche flush to be sure there isn't anything 330 * lingering in that part of the GPU 331 */ 332 333 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 334 OUT_RING(ring, CACHE_INVALIDATE); 335 336 if (!sysprof) { 337 u32 reg_status = adreno_is_a8xx(adreno_gpu) ? 338 REG_A8XX_RBBM_PERFCTR_SRAM_INIT_STATUS : 339 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS; 340 /* 341 * Wait for SRAM clear after the pgtable update, so the 342 * two can happen in parallel: 343 */ 344 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 345 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 346 OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO(reg_status)); 347 OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0)); 348 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 349 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 350 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 351 352 if (!(adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu))) { 353 /* Re-enable protected mode: */ 354 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 355 OUT_RING(ring, 1); 356 } 357 } 358 } 359 360 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 361 { 362 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 363 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 364 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 365 struct msm_ringbuffer *ring = submit->ring; 366 unsigned int i, ibs = 0; 367 368 adreno_check_and_reenable_stall(adreno_gpu); 369 370 a6xx_set_pagetable(a6xx_gpu, ring, submit); 371 372 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 373 rbmemptr_stats(ring, index, cpcycles_start)); 374 375 /* 376 * For PM4 the GMU register offsets are calculated from the base of the 377 * GPU registers so we need to add 0x1a800 to the register value on A630 378 * to get the right value from PM4. 379 */ 380 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, 381 rbmemptr_stats(ring, index, alwayson_start)); 382 383 /* Invalidate CCU depth and color */ 384 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 385 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 386 387 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 388 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 389 390 /* Submit the commands */ 391 for (i = 0; i < submit->nr_cmds; i++) { 392 switch (submit->cmd[i].type) { 393 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 394 break; 395 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 396 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 397 break; 398 fallthrough; 399 case MSM_SUBMIT_CMD_BUF: 400 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 401 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 402 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 403 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 404 ibs++; 405 break; 406 } 407 408 /* 409 * Periodically update shadow-wptr if needed, so that we 410 * can see partial progress of submits with large # of 411 * cmds.. otherwise we could needlessly stall waiting for 412 * ringbuffer state, simply due to looking at a shadow 413 * rptr value that has not been updated 414 */ 415 if ((ibs % 32) == 0) 416 update_shadow_rptr(gpu, ring); 417 } 418 419 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 420 rbmemptr_stats(ring, index, cpcycles_end)); 421 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT, 422 rbmemptr_stats(ring, index, alwayson_end)); 423 424 /* Write the fence to the scratch register */ 425 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); 426 OUT_RING(ring, submit->seqno); 427 428 /* 429 * Execute a CACHE_FLUSH_TS event. This will ensure that the 430 * timestamp is written to the memory and then triggers the interrupt 431 */ 432 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 433 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 434 CP_EVENT_WRITE_0_IRQ); 435 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 436 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 437 OUT_RING(ring, submit->seqno); 438 439 trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); 440 441 a6xx_flush(gpu, ring); 442 } 443 444 void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, 445 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) 446 { 447 u64 preempt_postamble; 448 449 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); 450 451 OUT_RING(ring, SMMU_INFO); 452 /* don't save SMMU, we write the record from the kernel instead */ 453 OUT_RING(ring, 0); 454 OUT_RING(ring, 0); 455 456 /* privileged and non secure buffer save */ 457 OUT_RING(ring, NON_SECURE_SAVE_ADDR); 458 OUT_RING(ring, lower_32_bits( 459 a6xx_gpu->preempt_iova[ring->id])); 460 OUT_RING(ring, upper_32_bits( 461 a6xx_gpu->preempt_iova[ring->id])); 462 463 /* user context buffer save, seems to be unnused by fw */ 464 OUT_RING(ring, NON_PRIV_SAVE_ADDR); 465 OUT_RING(ring, 0); 466 OUT_RING(ring, 0); 467 468 OUT_RING(ring, COUNTER); 469 /* seems OK to set to 0 to disable it */ 470 OUT_RING(ring, 0); 471 OUT_RING(ring, 0); 472 473 /* Emit postamble to clear perfcounters */ 474 preempt_postamble = a6xx_gpu->preempt_postamble_iova; 475 476 OUT_PKT7(ring, CP_SET_AMBLE, 3); 477 OUT_RING(ring, lower_32_bits(preempt_postamble)); 478 OUT_RING(ring, upper_32_bits(preempt_postamble)); 479 OUT_RING(ring, CP_SET_AMBLE_2_DWORDS( 480 a6xx_gpu->preempt_postamble_len) | 481 CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE)); 482 } 483 484 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 485 { 486 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 487 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 488 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 489 struct msm_ringbuffer *ring = submit->ring; 490 u32 rbbm_perfctr_cp0, cp_always_on_context; 491 unsigned int i, ibs = 0; 492 493 adreno_check_and_reenable_stall(adreno_gpu); 494 495 /* 496 * Toggle concurrent binning for pagetable switch and set the thread to 497 * BR since only it can execute the pagetable switch packets. 498 */ 499 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 500 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); 501 502 a6xx_set_pagetable(a6xx_gpu, ring, submit); 503 504 /* 505 * If preemption is enabled, then set the pseudo register for the save 506 * sequence 507 */ 508 if (gpu->nr_rings > 1) 509 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); 510 511 if (adreno_is_a8xx(adreno_gpu)) { 512 rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0); 513 cp_always_on_context = REG_A8XX_CP_ALWAYS_ON_CONTEXT; 514 } else { 515 rbbm_perfctr_cp0 = REG_A7XX_RBBM_PERFCTR_CP(0); 516 cp_always_on_context = REG_A6XX_CP_ALWAYS_ON_CONTEXT; 517 } 518 519 get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_start)); 520 get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_start)); 521 522 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 523 OUT_RING(ring, CP_SET_THREAD_BOTH); 524 525 OUT_PKT7(ring, CP_SET_MARKER, 1); 526 OUT_RING(ring, 0x101); /* IFPC disable */ 527 528 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 529 OUT_PKT7(ring, CP_SET_MARKER, 1); 530 OUT_RING(ring, 0x00d); /* IB1LIST start */ 531 } 532 533 /* Submit the commands */ 534 for (i = 0; i < submit->nr_cmds; i++) { 535 switch (submit->cmd[i].type) { 536 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 537 break; 538 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 539 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno) 540 break; 541 fallthrough; 542 case MSM_SUBMIT_CMD_BUF: 543 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3); 544 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 545 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 546 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size)); 547 ibs++; 548 break; 549 } 550 551 /* 552 * Periodically update shadow-wptr if needed, so that we 553 * can see partial progress of submits with large # of 554 * cmds.. otherwise we could needlessly stall waiting for 555 * ringbuffer state, simply due to looking at a shadow 556 * rptr value that has not been updated 557 */ 558 if ((ibs % 32) == 0) 559 update_shadow_rptr(gpu, ring); 560 } 561 562 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) { 563 OUT_PKT7(ring, CP_SET_MARKER, 1); 564 OUT_RING(ring, 0x00e); /* IB1LIST end */ 565 } 566 567 get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_end)); 568 get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_end)); 569 570 /* Write the fence to the scratch register */ 571 if (adreno_is_a8xx(adreno_gpu)) { 572 OUT_PKT4(ring, REG_A8XX_CP_SCRATCH_GLOBAL(2), 1); 573 OUT_RING(ring, submit->seqno); 574 } else { 575 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); 576 OUT_RING(ring, submit->seqno); 577 } 578 579 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 580 OUT_RING(ring, CP_SET_THREAD_BR); 581 582 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 583 OUT_RING(ring, CCU_INVALIDATE_DEPTH); 584 585 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 586 OUT_RING(ring, CCU_INVALIDATE_COLOR); 587 588 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 589 OUT_RING(ring, CP_SET_THREAD_BV); 590 591 /* 592 * Make sure the timestamp is committed once BV pipe is 593 * completely done with this submission. 594 */ 595 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 596 OUT_RING(ring, CACHE_CLEAN | BIT(27)); 597 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 598 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 599 OUT_RING(ring, submit->seqno); 600 601 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 602 OUT_RING(ring, CP_SET_THREAD_BR); 603 604 /* 605 * This makes sure that BR doesn't race ahead and commit 606 * timestamp to memstore while BV is still processing 607 * this submission. 608 */ 609 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4); 610 OUT_RING(ring, 0); 611 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence))); 612 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); 613 OUT_RING(ring, submit->seqno); 614 615 a6xx_gpu->last_seqno[ring->id] = submit->seqno; 616 617 /* write the ringbuffer timestamp */ 618 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 619 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); 620 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 621 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 622 OUT_RING(ring, submit->seqno); 623 624 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 625 OUT_RING(ring, CP_SET_THREAD_BOTH); 626 627 OUT_PKT7(ring, CP_SET_MARKER, 1); 628 OUT_RING(ring, 0x100); /* IFPC enable */ 629 630 trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); 631 632 a6xx_flush_yield(gpu, ring); 633 634 /* Check to see if we need to start preemption */ 635 if (adreno_is_a8xx(adreno_gpu)) 636 a8xx_preempt_trigger(gpu); 637 else 638 a6xx_preempt_trigger(gpu); 639 } 640 641 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 642 { 643 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 644 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 645 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 646 const struct adreno_reglist *reg; 647 unsigned int i; 648 u32 cgc_delay, cgc_hyst; 649 u32 val, clock_cntl_on; 650 651 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 652 return; 653 654 if (adreno_is_a630(adreno_gpu)) 655 clock_cntl_on = 0x8aa8aa02; 656 else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) 657 clock_cntl_on = 0xaaa8aa82; 658 else if (adreno_is_a702(adreno_gpu)) 659 clock_cntl_on = 0xaaaaaa82; 660 else 661 clock_cntl_on = 0x8aa8aa82; 662 663 if (adreno_is_a612(adreno_gpu)) 664 cgc_delay = 0x11; 665 else if (adreno_is_a615_family(adreno_gpu)) 666 cgc_delay = 0x111; 667 else 668 cgc_delay = 0x10111; 669 670 if (adreno_is_a612(adreno_gpu)) 671 cgc_hyst = 0x55; 672 else if (adreno_is_a615_family(adreno_gpu)) 673 cgc_hyst = 0x555; 674 else 675 cgc_hyst = 0x5555; 676 677 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 678 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 679 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 680 state ? cgc_delay : 0); 681 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 682 state ? cgc_hyst : 0); 683 684 if (!adreno_gpu->info->a6xx->hwcg) { 685 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); 686 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); 687 688 if (state) { 689 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); 690 691 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, 692 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { 693 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); 694 return; 695 } 696 697 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); 698 } 699 700 return; 701 } 702 703 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 704 705 /* Don't re-program the registers if they are already correct */ 706 if ((!state && !val) || (state && (val == clock_cntl_on))) 707 return; 708 709 /* Disable SP clock before programming HWCG registers */ 710 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 711 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 712 713 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++) 714 gpu_write(gpu, reg->offset, state ? reg->value : 0); 715 716 /* Enable SP clock */ 717 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) 718 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 719 720 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 721 } 722 723 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 724 { 725 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 726 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 727 unsigned i; 728 729 /* 730 * Enable access protection to privileged registers, fault on an access 731 * protect violation and select the last span to protect from the start 732 * address all the way to the end of the register address space 733 */ 734 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 735 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | 736 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | 737 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); 738 739 for (i = 0; i < protect->count - 1; i++) { 740 /* Intentionally skip writing to some registers */ 741 if (protect->regs[i]) 742 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); 743 } 744 /* last CP_PROTECT to have "infinite" length on the last entry */ 745 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]); 746 } 747 748 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 749 { 750 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 751 const struct qcom_ubwc_cfg_data *cfg = adreno_gpu->ubwc_config; 752 /* 753 * We subtract 13 from the highest bank bit (13 is the minimum value 754 * allowed by hw) and write the lowest two bits of the remaining value 755 * as hbb_lo and the one above it as hbb_hi to the hardware. 756 */ 757 BUG_ON(cfg->highest_bank_bit < 13); 758 u32 hbb = cfg->highest_bank_bit - 13; 759 bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0; 760 u32 level2_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL2); 761 bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg); 762 bool amsbc = qcom_ubwc_enable_amsbc(cfg); 763 bool min_acc_len_64b; 764 u8 uavflagprd_inv = 0; 765 u32 hbb_hi = hbb >> 2; 766 u32 hbb_lo = hbb & 3; 767 768 if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) 769 uavflagprd_inv = 2; 770 771 min_acc_len_64b = qcom_ubwc_min_acc_length_64b(cfg); 772 773 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 774 level2_swizzling_dis << 12 | 775 rgb565_predicator << 11 | 776 hbb_hi << 10 | amsbc << 4 | 777 min_acc_len_64b << 3 | 778 hbb_lo << 1 | ubwc_mode); 779 780 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 781 level2_swizzling_dis << 6 | hbb_hi << 4 | 782 min_acc_len_64b << 3 | 783 hbb_lo << 1 | ubwc_mode); 784 785 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 786 level2_swizzling_dis << 12 | hbb_hi << 10 | 787 uavflagprd_inv << 4 | 788 min_acc_len_64b << 3 | 789 hbb_lo << 1 | ubwc_mode); 790 791 if (adreno_is_a7xx(adreno_gpu)) { 792 for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) { 793 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 794 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 795 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL, 796 FIELD_PREP(GENMASK(8, 5), hbb_lo)); 797 } 798 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 799 A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); 800 } 801 802 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 803 min_acc_len_64b << 23 | hbb_lo << 21); 804 805 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL, 806 qcom_ubwc_macrotile_mode(cfg)); 807 } 808 809 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) 810 { 811 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 812 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 813 const struct adreno_reglist_list *reglist; 814 const struct adreno_reglist_pipe_list *dyn_pwrup_reglist; 815 void *ptr = a6xx_gpu->pwrup_reglist_ptr; 816 struct cpu_gpu_lock *lock = ptr; 817 u32 *dest = (u32 *)&lock->regs[0]; 818 u32 dyn_pwrup_reglist_count = 0; 819 int i; 820 821 lock->gpu_req = lock->cpu_req = lock->turn = 0; 822 823 reglist = adreno_gpu->info->a6xx->ifpc_reglist; 824 if (reglist) { 825 lock->ifpc_list_len = reglist->count; 826 827 /* 828 * For each entry in each of the lists, write the offset and the current 829 * register value into the GPU buffer 830 */ 831 for (i = 0; i < reglist->count; i++) { 832 *dest++ = reglist->regs[i]; 833 *dest++ = gpu_read(gpu, reglist->regs[i]); 834 } 835 } 836 837 reglist = adreno_gpu->info->a6xx->pwrup_reglist; 838 lock->preemption_list_len = reglist->count; 839 840 for (i = 0; i < reglist->count; i++) { 841 *dest++ = reglist->regs[i]; 842 *dest++ = gpu_read(gpu, reglist->regs[i]); 843 } 844 845 /* 846 * The overall register list is composed of 847 * 1. Static IFPC-only registers 848 * 2. Static IFPC + preemption registers 849 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) 850 * 851 * The first two lists are static. Size of these lists are stored as 852 * number of pairs in ifpc_list_len and preemption_list_len 853 * respectively. With concurrent binning, Some of the perfcounter 854 * registers being virtualized, CP needs to know the pipe id to program 855 * the aperture inorder to restore the same. Thus, third list is a 856 * dynamic list with triplets as 857 * (<aperture, shifted 12 bits> <address> <data>), and the length is 858 * stored as number for triplets in dynamic_list_len. 859 */ 860 dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist; 861 if (dyn_pwrup_reglist) { 862 for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_BV; pipe_id++) { 863 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 864 A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id)); 865 for (i = 0; i < dyn_pwrup_reglist->count; i++) { 866 if ((dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)) == 0) 867 continue; 868 *dest++ = A7XX_CP_APERTURE_CNTL_HOST_PIPE(pipe_id); 869 *dest++ = dyn_pwrup_reglist->regs[i].offset; 870 *dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset); 871 dyn_pwrup_reglist_count++; 872 } 873 } 874 gpu_write(gpu, REG_A7XX_CP_APERTURE_CNTL_HOST, 875 A7XX_CP_APERTURE_CNTL_HOST_PIPE(PIPE_NONE)); 876 } 877 lock->dynamic_list_len = dyn_pwrup_reglist_count; 878 a6xx_gpu->dynamic_sel_reglist_offset = dyn_pwrup_reglist_count; 879 } 880 881 static int a7xx_preempt_start(struct msm_gpu *gpu) 882 { 883 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 884 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 885 struct msm_ringbuffer *ring = gpu->rb[0]; 886 887 if (gpu->nr_rings <= 1) 888 return 0; 889 890 /* Turn CP protection off */ 891 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 892 OUT_RING(ring, 0); 893 894 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); 895 896 a6xx_flush_yield(gpu, ring); 897 898 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 899 } 900 901 static int a6xx_cp_init(struct msm_gpu *gpu) 902 { 903 struct msm_ringbuffer *ring = gpu->rb[0]; 904 905 OUT_PKT7(ring, CP_ME_INIT, 8); 906 907 OUT_RING(ring, 0x0000002f); 908 909 /* Enable multiple hardware contexts */ 910 OUT_RING(ring, 0x00000003); 911 912 /* Enable error detection */ 913 OUT_RING(ring, 0x20000000); 914 915 /* Don't enable header dump */ 916 OUT_RING(ring, 0x00000000); 917 OUT_RING(ring, 0x00000000); 918 919 /* No workarounds enabled */ 920 OUT_RING(ring, 0x00000000); 921 922 /* Pad rest of the cmds with 0's */ 923 OUT_RING(ring, 0x00000000); 924 OUT_RING(ring, 0x00000000); 925 926 a6xx_flush(gpu, ring); 927 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 928 } 929 930 static int a7xx_cp_init(struct msm_gpu *gpu) 931 { 932 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 933 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 934 struct msm_ringbuffer *ring = gpu->rb[0]; 935 u32 mask; 936 937 /* Disable concurrent binning before sending CP init */ 938 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 939 OUT_RING(ring, BIT(27)); 940 941 OUT_PKT7(ring, CP_ME_INIT, 7); 942 943 /* Use multiple HW contexts */ 944 mask = BIT(0); 945 946 /* Enable error detection */ 947 mask |= BIT(1); 948 949 /* Set default reset state */ 950 mask |= BIT(3); 951 952 /* Disable save/restore of performance counters across preemption */ 953 mask |= BIT(6); 954 955 /* Enable the register init list with the spinlock */ 956 mask |= BIT(8); 957 958 OUT_RING(ring, mask); 959 960 /* Enable multiple hardware contexts */ 961 OUT_RING(ring, 0x00000003); 962 963 /* Enable error detection */ 964 OUT_RING(ring, 0x20000000); 965 966 /* Operation mode mask */ 967 OUT_RING(ring, 0x00000002); 968 969 /* *Don't* send a power up reg list for concurrent binning (TODO) */ 970 /* Lo address */ 971 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); 972 /* Hi address */ 973 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); 974 /* BIT(31) set => read the regs from the list */ 975 OUT_RING(ring, BIT(31)); 976 977 a6xx_flush(gpu, ring); 978 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 979 } 980 981 /* 982 * Check that the microcode version is new enough to include several key 983 * security fixes. Return true if the ucode is safe. 984 */ 985 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 986 struct drm_gem_object *obj) 987 { 988 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 989 struct msm_gpu *gpu = &adreno_gpu->base; 990 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 991 u32 *buf = msm_gem_get_vaddr(obj); 992 bool ret = false; 993 994 if (IS_ERR(buf)) 995 return false; 996 997 /* A7xx is safe! */ 998 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) 999 return true; 1000 1001 /* 1002 * Targets up to a640 (a618, a630 and a640) need to check for a 1003 * microcode version that is patched to support the whereami opcode or 1004 * one that is new enough to include it by default. 1005 * 1006 * a650 tier targets don't need whereami but still need to be 1007 * equal to or newer than 0.95 for other security fixes 1008 * 1009 * a660 targets have all the critical security fixes from the start 1010 */ 1011 if (!strcmp(sqe_name, "a630_sqe.fw")) { 1012 /* 1013 * If the lowest nibble is 0xa that is an indication that this 1014 * microcode has been patched. The actual version is in dword 1015 * [3] but we only care about the patchlevel which is the lowest 1016 * nibble of dword [3] 1017 * 1018 * Otherwise check that the firmware is greater than or equal 1019 * to 1.90 which was the first version that had this fix built 1020 * in 1021 */ 1022 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 1023 (buf[0] & 0xfff) >= 0x190) { 1024 a6xx_gpu->has_whereami = true; 1025 ret = true; 1026 goto out; 1027 } 1028 1029 DRM_DEV_ERROR(&gpu->pdev->dev, 1030 "a630 SQE ucode is too old. Have version %x need at least %x\n", 1031 buf[0] & 0xfff, 0x190); 1032 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 1033 if ((buf[0] & 0xfff) >= 0x095) { 1034 ret = true; 1035 goto out; 1036 } 1037 1038 DRM_DEV_ERROR(&gpu->pdev->dev, 1039 "a650 SQE ucode is too old. Have version %x need at least %x\n", 1040 buf[0] & 0xfff, 0x095); 1041 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 1042 ret = true; 1043 } else { 1044 DRM_DEV_ERROR(&gpu->pdev->dev, 1045 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 1046 } 1047 out: 1048 msm_gem_put_vaddr(obj); 1049 return ret; 1050 } 1051 1052 static int a6xx_ucode_load(struct msm_gpu *gpu) 1053 { 1054 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1055 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1056 1057 if (!a6xx_gpu->sqe_bo) { 1058 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 1059 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 1060 1061 if (IS_ERR(a6xx_gpu->sqe_bo)) { 1062 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 1063 1064 a6xx_gpu->sqe_bo = NULL; 1065 DRM_DEV_ERROR(&gpu->pdev->dev, 1066 "Could not allocate SQE ucode: %d\n", ret); 1067 1068 return ret; 1069 } 1070 1071 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 1072 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 1073 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm); 1074 drm_gem_object_put(a6xx_gpu->sqe_bo); 1075 1076 a6xx_gpu->sqe_bo = NULL; 1077 return -EPERM; 1078 } 1079 } 1080 1081 if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) { 1082 a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu, 1083 adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova); 1084 1085 if (IS_ERR(a6xx_gpu->aqe_bo)) { 1086 int ret = PTR_ERR(a6xx_gpu->aqe_bo); 1087 1088 a6xx_gpu->aqe_bo = NULL; 1089 DRM_DEV_ERROR(&gpu->pdev->dev, 1090 "Could not allocate AQE ucode: %d\n", ret); 1091 1092 return ret; 1093 } 1094 1095 msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw"); 1096 } 1097 1098 /* 1099 * Expanded APRIV and targets that support WHERE_AM_I both need a 1100 * privileged buffer to store the RPTR shadow 1101 */ 1102 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 1103 !a6xx_gpu->shadow_bo) { 1104 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 1105 sizeof(u32) * gpu->nr_rings, 1106 MSM_BO_WC | MSM_BO_MAP_PRIV, 1107 gpu->vm, &a6xx_gpu->shadow_bo, 1108 &a6xx_gpu->shadow_iova); 1109 1110 if (IS_ERR(a6xx_gpu->shadow)) 1111 return PTR_ERR(a6xx_gpu->shadow); 1112 1113 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 1114 } 1115 1116 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PWRUP_REGLIST_SIZE, 1117 MSM_BO_WC | MSM_BO_MAP_PRIV, 1118 gpu->vm, &a6xx_gpu->pwrup_reglist_bo, 1119 &a6xx_gpu->pwrup_reglist_iova); 1120 1121 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) 1122 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); 1123 1124 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); 1125 1126 return 0; 1127 } 1128 1129 int a6xx_zap_shader_init(struct msm_gpu *gpu) 1130 { 1131 static bool loaded; 1132 int ret; 1133 1134 if (loaded) 1135 return 0; 1136 1137 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 1138 1139 loaded = !ret; 1140 return ret; 1141 } 1142 1143 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1144 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1145 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1146 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 1147 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 1148 A6XX_RBBM_INT_0_MASK_CP_RB | \ 1149 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1150 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1151 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1152 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1153 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1154 1155 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1156 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1157 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \ 1158 A6XX_RBBM_INT_0_MASK_CP_SW | \ 1159 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1160 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \ 1161 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \ 1162 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1163 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1164 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1165 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1166 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ 1167 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ 1168 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1169 1170 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ 1171 A6XX_CP_APRIV_CNTL_RBFETCH | \ 1172 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \ 1173 A6XX_CP_APRIV_CNTL_RBRPWB) 1174 1175 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \ 1176 A6XX_CP_APRIV_CNTL_CDREAD | \ 1177 A6XX_CP_APRIV_CNTL_CDWRITE) 1178 1179 static int hw_init(struct msm_gpu *gpu) 1180 { 1181 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1182 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1183 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1184 u64 gmem_range_min; 1185 unsigned int i; 1186 int ret; 1187 1188 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1189 /* Make sure the GMU keeps the GPU on while we set it up */ 1190 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1191 if (ret) 1192 return ret; 1193 } 1194 1195 /* Clear GBIF halt in case GX domain was not collapsed */ 1196 if (adreno_is_a619_holi(adreno_gpu)) { 1197 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1198 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1199 1200 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1201 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL); 1202 } else if (a6xx_has_gbif(adreno_gpu)) { 1203 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1204 gpu_read(gpu, REG_A6XX_GBIF_HALT); 1205 1206 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1207 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT); 1208 } 1209 1210 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1211 1212 if (adreno_is_a619_holi(adreno_gpu)) 1213 a6xx_sptprac_enable(gmu); 1214 1215 /* 1216 * Disable the trusted memory range - we don't actually supported secure 1217 * memory rendering at this point in time and we don't want to block off 1218 * part of the virtual memory space. 1219 */ 1220 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1221 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1222 1223 if (!adreno_is_a7xx(adreno_gpu)) { 1224 /* Turn on 64 bit addressing for all blocks */ 1225 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1226 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1227 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1228 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1229 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1230 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1231 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1232 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1233 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1234 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1235 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1236 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1237 } 1238 1239 /* enable hardware clockgating */ 1240 a6xx_set_hwcg(gpu, true); 1241 1242 /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */ 1243 if (adreno_is_a610_family(adreno_gpu)) { 1244 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1245 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1246 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1247 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1248 } 1249 1250 if (adreno_is_a610_family(adreno_gpu) || 1251 adreno_is_a640_family(adreno_gpu) || 1252 adreno_is_a650_family(adreno_gpu)) { 1253 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 1254 } else if (adreno_is_a7xx(adreno_gpu)) { 1255 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212); 1256 } else { 1257 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1258 } 1259 1260 if (adreno_is_a630(adreno_gpu)) 1261 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1262 1263 if (adreno_is_a7xx(adreno_gpu)) 1264 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0); 1265 1266 /* Make all blocks contribute to the GPU BUSY perf counter */ 1267 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1268 1269 /* Disable L2 bypass in the UCHE */ 1270 if (adreno_is_a7xx(adreno_gpu)) { 1271 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1272 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1273 } else { 1274 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0); 1275 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); 1276 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); 1277 } 1278 1279 if (!(adreno_is_a650_family(adreno_gpu) || 1280 adreno_is_a702(adreno_gpu) || 1281 adreno_is_a730(adreno_gpu))) { 1282 gmem_range_min = (adreno_is_a740_family(adreno_gpu) || 1283 adreno_is_a722(adreno_gpu)) ? SZ_16M : SZ_1M; 1284 1285 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1286 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); 1287 1288 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1289 gmem_range_min + adreno_gpu->info->gmem - 1); 1290 } 1291 1292 if (adreno_is_a7xx(adreno_gpu)) 1293 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23)); 1294 else { 1295 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1296 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1297 } 1298 1299 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1300 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1301 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1302 } else if (adreno_is_a610_family(adreno_gpu)) { 1303 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1304 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1305 } else if (!adreno_is_a7xx(adreno_gpu)) { 1306 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1307 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1308 } 1309 1310 if (adreno_is_a660_family(adreno_gpu)) 1311 gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1312 1313 /* Setting the mem pool size */ 1314 if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { 1315 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1316 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1317 } else if (adreno_is_a702(adreno_gpu)) { 1318 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); 1319 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); 1320 } else if (!adreno_is_a7xx(adreno_gpu)) 1321 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1322 1323 1324 /* Set the default primFifo threshold values */ 1325 if (adreno_gpu->info->a6xx->prim_fifo_threshold) 1326 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 1327 adreno_gpu->info->a6xx->prim_fifo_threshold); 1328 1329 /* Set the AHB default slave response to "ERROR" */ 1330 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1331 1332 /* Turn on performance counters */ 1333 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1334 1335 if (adreno_is_a7xx(adreno_gpu)) { 1336 /* Turn on the IFPC counter (countable 4 on XOCLK4) */ 1337 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1338 FIELD_PREP(GENMASK(7, 0), 0x4)); 1339 } 1340 1341 /* Select CP0 to always count cycles */ 1342 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1343 1344 a6xx_set_ubwc_config(gpu); 1345 1346 /* Enable fault detection */ 1347 if (adreno_is_a612(adreno_gpu) || 1348 adreno_is_a722(adreno_gpu) || 1349 adreno_is_a730(adreno_gpu) || 1350 adreno_is_a740_family(adreno_gpu)) 1351 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); 1352 else if (adreno_is_a690(adreno_gpu)) 1353 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); 1354 else if (adreno_is_a619(adreno_gpu)) 1355 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1356 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) 1357 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1358 else 1359 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1360 1361 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1362 1363 /* Set weights for bicubic filtering */ 1364 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) { 1365 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(0), 0); 1366 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), 1367 0x3fe05ff4); 1368 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), 1369 0x3fa0ebee); 1370 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), 1371 0x3f5193ed); 1372 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), 1373 0x3f0243f0); 1374 } 1375 1376 /* Set up the CX GMU counter 0 to count busy ticks */ 1377 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1378 1379 /* Enable the power counter */ 1380 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1381 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1382 1383 /* Protect registers from the CP */ 1384 a6xx_set_cp_protect(gpu); 1385 1386 if (adreno_is_a660_family(adreno_gpu)) { 1387 if (adreno_is_a690(adreno_gpu)) 1388 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801); 1389 else 1390 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1391 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1392 } else if (adreno_is_a702(adreno_gpu)) { 1393 /* Something to do with the HLSQ cluster */ 1394 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); 1395 } 1396 1397 if (adreno_is_a690(adreno_gpu)) 1398 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90); 1399 /* Set dualQ + disable afull for A660 GPU */ 1400 else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu)) 1401 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1402 else if (adreno_is_a7xx(adreno_gpu)) 1403 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 1404 FIELD_PREP(GENMASK(19, 16), 6) | 1405 FIELD_PREP(GENMASK(15, 12), 6) | 1406 FIELD_PREP(GENMASK(11, 8), 9) | 1407 BIT(3) | BIT(2) | 1408 FIELD_PREP(GENMASK(1, 0), 2)); 1409 1410 /* Enable expanded apriv for targets that support it */ 1411 if (gpu->hw_apriv) { 1412 if (adreno_is_a7xx(adreno_gpu)) { 1413 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1414 A7XX_BR_APRIVMASK); 1415 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL, 1416 A7XX_APRIV_MASK); 1417 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL, 1418 A7XX_APRIV_MASK); 1419 } else 1420 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1421 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); 1422 } 1423 1424 if (adreno_is_a750(adreno_gpu)) { 1425 /* Disable ubwc merged UFC request feature */ 1426 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); 1427 1428 /* Enable TP flaghint and other performance settings */ 1429 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); 1430 } else if (adreno_is_a7xx(adreno_gpu)) { 1431 /* Disable non-ubwc read reqs from passing write reqs */ 1432 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); 1433 } 1434 1435 /* Enable interrupts */ 1436 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 1437 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); 1438 1439 ret = adreno_hw_init(gpu); 1440 if (ret) 1441 goto out; 1442 1443 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1444 1445 /* Set the ringbuffer address */ 1446 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1447 1448 /* Targets that support extended APRIV can use the RPTR shadow from 1449 * hardware but all the other ones need to disable the feature. Targets 1450 * that support the WHERE_AM_I opcode can use that instead 1451 */ 1452 if (adreno_gpu->base.hw_apriv) 1453 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1454 else 1455 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1456 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1457 1458 /* Configure the RPTR shadow if needed: */ 1459 if (a6xx_gpu->shadow_bo) { 1460 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1461 shadowptr(a6xx_gpu, gpu->rb[0])); 1462 for (unsigned int i = 0; i < gpu->nr_rings; i++) 1463 a6xx_gpu->shadow[i] = 0; 1464 } 1465 1466 /* ..which means "always" on A7xx, also for BV shadow */ 1467 if (adreno_is_a7xx(adreno_gpu)) { 1468 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, 1469 rbmemptr(gpu->rb[0], bv_rptr)); 1470 } 1471 1472 a6xx_preempt_hw_init(gpu); 1473 1474 /* Always come up on rb 0 */ 1475 a6xx_gpu->cur_ring = gpu->rb[0]; 1476 1477 for (i = 0; i < gpu->nr_rings; i++) 1478 gpu->rb[i]->cur_ctx_seqno = 0; 1479 1480 /* Enable the SQE_to start the CP engine */ 1481 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1482 1483 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { 1484 a7xx_patch_pwrup_reglist(gpu); 1485 a6xx_gpu->pwrup_reglist_emitted = true; 1486 } 1487 1488 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu); 1489 if (ret) 1490 goto out; 1491 1492 /* 1493 * Try to load a zap shader into the secure world. If successful 1494 * we can use the CP to switch out of secure mode. If not then we 1495 * have no resource but to try to switch ourselves out manually. If we 1496 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1497 * be blocked and a permissions violation will soon follow. 1498 */ 1499 ret = a6xx_zap_shader_init(gpu); 1500 if (!ret) { 1501 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1502 OUT_RING(gpu->rb[0], 0x00000000); 1503 1504 a6xx_flush(gpu, gpu->rb[0]); 1505 if (!a6xx_idle(gpu, gpu->rb[0])) 1506 return -EINVAL; 1507 } else if (ret == -ENODEV) { 1508 /* 1509 * This device does not use zap shader (but print a warning 1510 * just in case someone got their dt wrong.. hopefully they 1511 * have a debug UART to realize the error of their ways... 1512 * if you mess this up you are about to crash horribly) 1513 */ 1514 dev_warn_once(gpu->dev->dev, 1515 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1516 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1517 ret = 0; 1518 } else { 1519 return ret; 1520 } 1521 1522 out: 1523 if (adreno_has_gmu_wrapper(adreno_gpu)) 1524 return ret; 1525 1526 /* Last step - yield the ringbuffer */ 1527 a7xx_preempt_start(gpu); 1528 1529 /* 1530 * Tell the GMU that we are done touching the GPU and it can start power 1531 * management 1532 */ 1533 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1534 1535 if (a6xx_gpu->gmu.legacy) { 1536 /* Take the GMU out of its special boot mode */ 1537 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1538 } 1539 1540 if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { 1541 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1542 if (!ret) 1543 set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 1544 } 1545 1546 return ret; 1547 } 1548 1549 static int a6xx_hw_init(struct msm_gpu *gpu) 1550 { 1551 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1552 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1553 int ret; 1554 1555 mutex_lock(&a6xx_gpu->gmu.lock); 1556 ret = hw_init(gpu); 1557 mutex_unlock(&a6xx_gpu->gmu.lock); 1558 1559 return ret; 1560 } 1561 1562 static void a6xx_dump(struct msm_gpu *gpu) 1563 { 1564 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1565 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1566 adreno_dump(gpu); 1567 } 1568 1569 static void a6xx_recover(struct msm_gpu *gpu) 1570 { 1571 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1572 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1573 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1574 int active_submits; 1575 1576 adreno_dump_info(gpu); 1577 1578 if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { 1579 /* Sometimes crashstate capture is skipped, so SQE should be halted here again */ 1580 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1581 1582 if (hang_debug) 1583 a6xx_dump(gpu); 1584 1585 } 1586 1587 /* 1588 * To handle recovery specific sequences during the rpm suspend we are 1589 * about to trigger 1590 */ 1591 1592 a6xx_gpu->hung = true; 1593 1594 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1595 1596 /* active_submit won't change until we make a submission */ 1597 mutex_lock(&gpu->active_lock); 1598 active_submits = gpu->active_submits; 1599 1600 /* 1601 * Temporarily clear active_submits count to silence a WARN() in the 1602 * runtime suspend cb 1603 */ 1604 gpu->active_submits = 0; 1605 1606 if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) { 1607 /* Drain the outstanding traffic on memory buses */ 1608 adreno_gpu->funcs->bus_halt(adreno_gpu, true); 1609 1610 /* Reset the GPU to a clean state */ 1611 a6xx_gpu_sw_reset(gpu, true); 1612 a6xx_gpu_sw_reset(gpu, false); 1613 } 1614 1615 reinit_completion(&gmu->pd_gate); 1616 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1617 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1618 1619 /* Drop the rpm refcount from active submits */ 1620 if (active_submits) 1621 pm_runtime_put(&gpu->pdev->dev); 1622 1623 /* And the final one from recover worker */ 1624 pm_runtime_put_sync(&gpu->pdev->dev); 1625 1626 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1627 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1628 1629 dev_pm_genpd_remove_notifier(gmu->cxpd); 1630 1631 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1632 1633 if (active_submits) 1634 pm_runtime_get(&gpu->pdev->dev); 1635 1636 pm_runtime_get_sync(&gpu->pdev->dev); 1637 1638 gpu->active_submits = active_submits; 1639 mutex_unlock(&gpu->active_lock); 1640 1641 msm_gpu_hw_init(gpu); 1642 a6xx_gpu->hung = false; 1643 } 1644 1645 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1646 { 1647 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1648 static const char *uche_clients[7] = { 1649 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1650 }; 1651 u32 val; 1652 1653 if (adreno_is_a7xx(adreno_gpu)) { 1654 if (mid != 1 && mid != 2 && mid != 3 && mid != 8) 1655 return "UNKNOWN"; 1656 } else { 1657 if (mid < 1 || mid > 3) 1658 return "UNKNOWN"; 1659 } 1660 1661 /* 1662 * The source of the data depends on the mid ID read from FSYNR1. 1663 * and the client ID read from the UCHE block 1664 */ 1665 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1666 1667 if (adreno_is_a7xx(adreno_gpu)) { 1668 /* Bit 3 for mid=3 indicates BR or BV */ 1669 static const char *uche_clients_a7xx[16] = { 1670 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", 1671 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", 1672 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", 1673 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", 1674 }; 1675 1676 /* LPAC has the same clients as BR and BV, but because it is 1677 * compute-only some of them do not exist and there are holes 1678 * in the array. 1679 */ 1680 static const char *uche_clients_lpac_a7xx[8] = { 1681 "-", "LPAC_SP", "-", "-", 1682 "LPAC_HLSQ", "-", "-", "LPAC_TP", 1683 }; 1684 1685 val &= GENMASK(6, 0); 1686 1687 /* mid=3 refers to BR or BV */ 1688 if (mid == 3) { 1689 if (val < ARRAY_SIZE(uche_clients_a7xx)) 1690 return uche_clients_a7xx[val]; 1691 else 1692 return "UCHE"; 1693 } 1694 1695 /* mid=8 refers to LPAC */ 1696 if (mid == 8) { 1697 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) 1698 return uche_clients_lpac_a7xx[val]; 1699 else 1700 return "UCHE_LPAC"; 1701 } 1702 1703 /* mid=2 is a catchall for everything else in LPAC */ 1704 if (mid == 2) 1705 return "UCHE_LPAC"; 1706 1707 /* mid=1 is a catchall for everything else in BR/BV */ 1708 return "UCHE"; 1709 } else if (adreno_is_a660_family(adreno_gpu)) { 1710 static const char *uche_clients_a660[8] = { 1711 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", 1712 }; 1713 1714 static const char *uche_clients_a660_not[8] = { 1715 "not VFD", "not SP", "not VSC", "not VPC", 1716 "not HLSQ", "not PC", "not LRZ", "not TP", 1717 }; 1718 1719 val &= GENMASK(6, 0); 1720 1721 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) 1722 return uche_clients_a660[val]; 1723 1724 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) 1725 return uche_clients_a660_not[val]; 1726 1727 return "UCHE"; 1728 } else { 1729 /* mid = 3 is most precise and refers to only one block per client */ 1730 if (mid == 3) 1731 return uche_clients[val & 7]; 1732 1733 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1734 if (mid == 2) 1735 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1736 1737 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1738 return "UCHE"; 1739 } 1740 } 1741 1742 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1743 { 1744 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1745 1746 if (id == 0) 1747 return "CP"; 1748 else if (id == 4) 1749 return "CCU"; 1750 else if (id == 6) 1751 return "CDP Prefetch"; 1752 else if (id == 7) 1753 return "GMU"; 1754 else if (id == 5 && adreno_is_a7xx(adreno_gpu)) 1755 return "Flag cache"; 1756 1757 return a6xx_uche_fault_block(gpu, id); 1758 } 1759 1760 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1761 { 1762 struct msm_gpu *gpu = arg; 1763 struct adreno_smmu_fault_info *info = data; 1764 const char *block = "unknown"; 1765 1766 u32 scratch[] = { 1767 gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)), 1768 gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)), 1769 gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)), 1770 gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)), 1771 }; 1772 1773 if (info) 1774 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1775 1776 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1777 } 1778 1779 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1780 { 1781 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1782 1783 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1784 u32 val; 1785 1786 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1787 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1788 dev_err_ratelimited(&gpu->pdev->dev, 1789 "CP | opcode error | possible opcode=0x%8.8X\n", 1790 val); 1791 } 1792 1793 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1794 dev_err_ratelimited(&gpu->pdev->dev, 1795 "CP ucode error interrupt\n"); 1796 1797 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1798 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1799 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1800 1801 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1802 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1803 1804 dev_err_ratelimited(&gpu->pdev->dev, 1805 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1806 val & (1 << 20) ? "READ" : "WRITE", 1807 (val & 0x3ffff), val); 1808 } 1809 1810 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu))) 1811 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1812 1813 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1814 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1815 1816 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1817 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1818 1819 } 1820 1821 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1822 { 1823 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1824 1825 /* 1826 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1827 * but the fault handler will trigger the devcore dump, and we want 1828 * to otherwise resume normally rather than killing the submit, so 1829 * just bail. 1830 */ 1831 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1832 return; 1833 1834 DRM_DEV_ERROR(&gpu->pdev->dev, 1835 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1836 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1837 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1838 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1839 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1840 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1841 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1842 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1843 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1844 1845 /* Turn off the hangcheck timer to keep it from bothering us */ 1846 timer_delete(&gpu->hangcheck_timer); 1847 1848 /* Turn off interrupts to avoid triggering recovery again */ 1849 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, 0); 1850 1851 kthread_queue_work(gpu->worker, &gpu->recover_work); 1852 } 1853 1854 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) 1855 { 1856 u32 status; 1857 1858 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); 1859 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); 1860 1861 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); 1862 1863 /* 1864 * Ignore FASTBLEND violations, because the HW will silently fall back 1865 * to legacy blending. 1866 */ 1867 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | 1868 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { 1869 timer_delete(&gpu->hangcheck_timer); 1870 1871 kthread_queue_work(gpu->worker, &gpu->recover_work); 1872 } 1873 } 1874 1875 static void a6xx_gpu_keepalive_vote(struct msm_gpu *gpu, bool on) 1876 { 1877 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1878 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1879 1880 if (adreno_has_gmu_wrapper(adreno_gpu)) 1881 return; 1882 1883 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, on); 1884 } 1885 1886 static int irq_poll_fence(struct msm_gpu *gpu) 1887 { 1888 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1889 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1890 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1891 u32 status; 1892 1893 if (adreno_has_gmu_wrapper(adreno_gpu)) 1894 return 0; 1895 1896 if (gmu_poll_timeout_atomic(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, status, !status, 1, 100)) { 1897 u32 rbbm_unmasked = gmu_read(gmu, REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS); 1898 1899 dev_err_ratelimited(&gpu->pdev->dev, 1900 "irq fence poll timeout, fence_ctrl=0x%x, unmasked_status=0x%x\n", 1901 status, rbbm_unmasked); 1902 return -ETIMEDOUT; 1903 } 1904 1905 return 0; 1906 } 1907 1908 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1909 { 1910 struct msm_drm_private *priv = gpu->dev->dev_private; 1911 1912 /* Set keepalive vote to avoid power collapse after RBBM_INT_0_STATUS is read */ 1913 a6xx_gpu_keepalive_vote(gpu, true); 1914 1915 if (irq_poll_fence(gpu)) 1916 goto done; 1917 1918 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1919 1920 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1921 1922 if (priv->disable_err_irq) { 1923 /* Turn off interrupts to avoid interrupt storm */ 1924 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS); 1925 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1926 } 1927 1928 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1929 a6xx_fault_detect_irq(gpu); 1930 1931 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1932 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1933 1934 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1935 a6xx_cp_hw_err_irq(gpu); 1936 1937 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1938 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1939 1940 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1941 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1942 1943 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1944 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1945 1946 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) 1947 a7xx_sw_fuse_violation_irq(gpu); 1948 1949 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { 1950 msm_gpu_retire(gpu); 1951 a6xx_preempt_trigger(gpu); 1952 } 1953 1954 if (status & A6XX_RBBM_INT_0_MASK_CP_SW) 1955 a6xx_preempt_irq(gpu); 1956 1957 done: 1958 a6xx_gpu_keepalive_vote(gpu, false); 1959 1960 return IRQ_HANDLED; 1961 } 1962 1963 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1964 { 1965 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1966 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1967 } 1968 1969 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1970 { 1971 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1972 struct msm_gpu *gpu = &adreno_gpu->base; 1973 u32 cntl1_regval = 0; 1974 1975 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1976 return; 1977 1978 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1979 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1980 1981 gpu_scid &= 0x1f; 1982 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1983 (gpu_scid << 15) | (gpu_scid << 20); 1984 1985 /* On A660, the SCID programming for UCHE traffic is done in 1986 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1987 */ 1988 if (adreno_is_a660_family(adreno_gpu)) 1989 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1990 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1991 } 1992 1993 /* 1994 * For targets with a MMU500, activate the slice but don't program the 1995 * register. The XBL will take care of that. 1996 */ 1997 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1998 if (!a6xx_gpu->have_mmu500) { 1999 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 2000 2001 gpuhtw_scid &= 0x1f; 2002 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 2003 } 2004 } 2005 2006 if (!cntl1_regval) 2007 return; 2008 2009 /* 2010 * Program the slice IDs for the various GPU blocks and GPU MMU 2011 * pagetables 2012 */ 2013 if (!a6xx_gpu->have_mmu500) { 2014 a6xx_cx_misc_write(a6xx_gpu, 2015 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 2016 2017 /* 2018 * Program cacheability overrides to not allocate cache 2019 * lines on a write miss 2020 */ 2021 a6xx_cx_misc_rmw(a6xx_gpu, 2022 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 2023 return; 2024 } 2025 2026 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 2027 } 2028 2029 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 2030 { 2031 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 2032 struct msm_gpu *gpu = &adreno_gpu->base; 2033 2034 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 2035 return; 2036 2037 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 2038 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 2039 2040 gpu_scid &= GENMASK(4, 0); 2041 2042 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, 2043 FIELD_PREP(GENMASK(29, 25), gpu_scid) | 2044 FIELD_PREP(GENMASK(24, 20), gpu_scid) | 2045 FIELD_PREP(GENMASK(19, 15), gpu_scid) | 2046 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 2047 FIELD_PREP(GENMASK(9, 5), gpu_scid) | 2048 FIELD_PREP(GENMASK(4, 0), gpu_scid)); 2049 2050 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, 2051 FIELD_PREP(GENMASK(14, 10), gpu_scid) | 2052 BIT(8)); 2053 } 2054 2055 llcc_slice_activate(a6xx_gpu->htw_llc_slice); 2056 } 2057 2058 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 2059 { 2060 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 2061 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 2062 return; 2063 2064 llcc_slice_putd(a6xx_gpu->llc_slice); 2065 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 2066 } 2067 2068 static void a6xx_llc_slices_init(struct platform_device *pdev, 2069 struct a6xx_gpu *a6xx_gpu, bool is_a7xx) 2070 { 2071 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 2072 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 2073 return; 2074 2075 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 2076 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 2077 } 2078 2079 #define GBIF_CLIENT_HALT_MASK BIT(0) 2080 #define GBIF_ARB_HALT_MASK BIT(1) 2081 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 2082 #define VBIF_RESET_ACK_MASK 0xF0 2083 #define GPR0_GBIF_HALT_REQUEST 0x1E0 2084 2085 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 2086 { 2087 struct msm_gpu *gpu = &adreno_gpu->base; 2088 2089 if (adreno_is_a619_holi(adreno_gpu)) { 2090 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 2091 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 2092 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 2093 } else if (!a6xx_has_gbif(adreno_gpu)) { 2094 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 2095 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 2096 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 2097 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 2098 2099 return; 2100 } 2101 2102 if (gx_off) { 2103 /* Halt the gx side of GBIF */ 2104 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 2105 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 2106 } 2107 2108 /* Halt new client requests on GBIF */ 2109 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 2110 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 2111 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 2112 2113 /* Halt all AXI requests on GBIF */ 2114 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 2115 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 2116 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 2117 2118 /* The GBIF halt needs to be explicitly cleared */ 2119 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 2120 } 2121 2122 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 2123 { 2124 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 2125 if (adreno_is_a610(to_adreno_gpu(gpu)) || adreno_is_a8xx(to_adreno_gpu(gpu))) 2126 return; 2127 2128 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 2129 /* Perform a bogus read and add a brief delay to ensure ordering. */ 2130 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 2131 udelay(1); 2132 2133 /* The reset line needs to be asserted for at least 100 us */ 2134 if (assert) 2135 udelay(100); 2136 } 2137 2138 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 2139 { 2140 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2141 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2142 int ret; 2143 2144 gpu->needs_hw_init = true; 2145 2146 trace_msm_gpu_resume(0); 2147 2148 mutex_lock(&a6xx_gpu->gmu.lock); 2149 ret = a6xx_gmu_resume(a6xx_gpu); 2150 mutex_unlock(&a6xx_gpu->gmu.lock); 2151 if (ret) 2152 return ret; 2153 2154 msm_devfreq_resume(gpu); 2155 2156 if (adreno_is_a8xx(adreno_gpu)) 2157 a8xx_llc_activate(a6xx_gpu); 2158 else if (adreno_is_a7xx(adreno_gpu)) 2159 a7xx_llc_activate(a6xx_gpu); 2160 else 2161 a6xx_llc_activate(a6xx_gpu); 2162 2163 return ret; 2164 } 2165 2166 static int a6xx_pm_resume(struct msm_gpu *gpu) 2167 { 2168 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2169 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2170 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2171 unsigned long freq = gpu->fast_rate; 2172 struct dev_pm_opp *opp; 2173 int ret; 2174 2175 gpu->needs_hw_init = true; 2176 2177 trace_msm_gpu_resume(0); 2178 2179 mutex_lock(&a6xx_gpu->gmu.lock); 2180 2181 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 2182 if (IS_ERR(opp)) { 2183 ret = PTR_ERR(opp); 2184 goto err_unlock; 2185 } 2186 2187 /* Set the core clock and bus bw, having VDD scaling in mind */ 2188 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 2189 dev_pm_opp_put(opp); 2190 2191 ret = pm_runtime_resume_and_get(gmu->dev); 2192 if (ret < 0) 2193 goto err_opp_clear; 2194 ret = pm_runtime_resume_and_get(gmu->gxpd); 2195 if (ret < 0) 2196 goto err_put_dev; 2197 2198 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 2199 if (ret) 2200 goto err_put_gxpd; 2201 2202 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 2203 if (ret) { 2204 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2205 goto err_put_gxpd; 2206 } 2207 2208 if (adreno_is_a619_holi(adreno_gpu)) 2209 a6xx_sptprac_enable(gmu); 2210 2211 mutex_unlock(&a6xx_gpu->gmu.lock); 2212 msm_devfreq_resume(gpu); 2213 a6xx_llc_activate(a6xx_gpu); 2214 2215 return 0; 2216 2217 /* If anything goes south, tear the GPU down piece by piece.. */ 2218 err_put_gxpd: 2219 pm_runtime_put(gmu->gxpd); 2220 err_put_dev: 2221 pm_runtime_put(gmu->dev); 2222 err_opp_clear: 2223 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2224 err_unlock: 2225 mutex_unlock(&a6xx_gpu->gmu.lock); 2226 return ret; 2227 } 2228 2229 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 2230 { 2231 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2232 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2233 int i, ret; 2234 2235 trace_msm_gpu_suspend(0); 2236 2237 a6xx_llc_deactivate(a6xx_gpu); 2238 2239 msm_devfreq_suspend(gpu); 2240 2241 mutex_lock(&a6xx_gpu->gmu.lock); 2242 ret = a6xx_gmu_stop(a6xx_gpu); 2243 mutex_unlock(&a6xx_gpu->gmu.lock); 2244 if (ret) 2245 return ret; 2246 2247 if (a6xx_gpu->shadow_bo) 2248 for (i = 0; i < gpu->nr_rings; i++) 2249 a6xx_gpu->shadow[i] = 0; 2250 2251 gpu->suspend_count++; 2252 2253 return 0; 2254 } 2255 2256 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2257 { 2258 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2259 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2260 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2261 int i; 2262 2263 trace_msm_gpu_suspend(0); 2264 2265 a6xx_llc_deactivate(a6xx_gpu); 2266 2267 msm_devfreq_suspend(gpu); 2268 2269 mutex_lock(&a6xx_gpu->gmu.lock); 2270 2271 /* Drain the outstanding traffic on memory buses */ 2272 adreno_gpu->funcs->bus_halt(adreno_gpu, true); 2273 2274 if (adreno_is_a619_holi(adreno_gpu)) 2275 a6xx_sptprac_disable(gmu); 2276 2277 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2278 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 2279 2280 pm_runtime_put_sync(gmu->gxpd); 2281 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2282 pm_runtime_put_sync(gmu->dev); 2283 2284 mutex_unlock(&a6xx_gpu->gmu.lock); 2285 2286 if (a6xx_gpu->shadow_bo) 2287 for (i = 0; i < gpu->nr_rings; i++) 2288 a6xx_gpu->shadow[i] = 0; 2289 2290 gpu->suspend_count++; 2291 2292 return 0; 2293 } 2294 2295 static u64 a6xx_get_timestamp(struct msm_gpu *gpu) 2296 { 2297 return gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2298 } 2299 2300 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2301 { 2302 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2303 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2304 2305 return a6xx_gpu->cur_ring; 2306 } 2307 2308 static void a6xx_destroy(struct msm_gpu *gpu) 2309 { 2310 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2311 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2312 2313 if (a6xx_gpu->sqe_bo) { 2314 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->vm); 2315 drm_gem_object_put(a6xx_gpu->sqe_bo); 2316 } 2317 2318 if (a6xx_gpu->aqe_bo) { 2319 msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm); 2320 drm_gem_object_put(a6xx_gpu->aqe_bo); 2321 } 2322 2323 if (a6xx_gpu->shadow_bo) { 2324 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->vm); 2325 drm_gem_object_put(a6xx_gpu->shadow_bo); 2326 } 2327 2328 a6xx_llc_slices_destroy(a6xx_gpu); 2329 2330 a6xx_gmu_remove(a6xx_gpu); 2331 2332 adreno_gpu_cleanup(adreno_gpu); 2333 2334 kfree(a6xx_gpu); 2335 } 2336 2337 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2338 { 2339 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2340 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2341 u64 busy_cycles; 2342 2343 /* 19.2MHz */ 2344 *out_sample_rate = 19200000; 2345 2346 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2347 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2348 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2349 2350 return busy_cycles; 2351 } 2352 2353 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2354 bool suspended) 2355 { 2356 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2357 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2358 2359 mutex_lock(&a6xx_gpu->gmu.lock); 2360 a6xx_gmu_set_freq(gpu, opp, suspended); 2361 mutex_unlock(&a6xx_gpu->gmu.lock); 2362 } 2363 2364 static struct drm_gpuvm * 2365 a6xx_create_vm(struct msm_gpu *gpu, struct platform_device *pdev) 2366 { 2367 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2368 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2369 unsigned long quirks = 0; 2370 2371 /* 2372 * This allows GPU to set the bus attributes required to use system 2373 * cache on behalf of the iommu page table walker. 2374 */ 2375 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2376 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2377 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2378 2379 return adreno_iommu_create_vm(gpu, pdev, quirks); 2380 } 2381 2382 static struct drm_gpuvm * 2383 a6xx_create_private_vm(struct msm_gpu *gpu, bool kernel_managed) 2384 { 2385 struct msm_mmu *mmu; 2386 2387 mmu = msm_iommu_pagetable_create(to_msm_vm(gpu->vm)->mmu, kernel_managed); 2388 2389 if (IS_ERR(mmu)) 2390 return ERR_CAST(mmu); 2391 2392 return msm_gem_vm_create(gpu->dev, mmu, "gpu", ADRENO_VM_START, 2393 adreno_private_vm_size(gpu), kernel_managed); 2394 } 2395 2396 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2397 { 2398 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2399 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2400 2401 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2402 return a6xx_gpu->shadow[ring->id]; 2403 2404 /* 2405 * This is true only on an A6XX_GEN1 with GMU, has IFPC enabled and a super old SQE firmware 2406 * without 'whereami' support 2407 */ 2408 WARN_ONCE((to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC), 2409 "Can't read CP_RB_RPTR register reliably\n"); 2410 2411 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2412 } 2413 2414 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2415 { 2416 struct msm_cp_state cp_state; 2417 bool progress; 2418 2419 /* 2420 * With IFPC, KMD doesn't know whether GX power domain is collapsed 2421 * or not. So, we can't blindly read the below registers in GX domain. 2422 * Lets trust the hang detection in HW and lie to the caller that 2423 * there was progress. 2424 */ 2425 if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC) 2426 return true; 2427 2428 cp_state = (struct msm_cp_state) { 2429 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2430 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2431 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2432 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2433 }; 2434 2435 /* 2436 * Adjust the remaining data to account for what has already been 2437 * fetched from memory, but not yet consumed by the SQE. 2438 * 2439 * This is not *technically* correct, the amount buffered could 2440 * exceed the IB size due to hw prefetching ahead, but: 2441 * 2442 * (1) We aren't trying to find the exact position, just whether 2443 * progress has been made 2444 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2445 * to prevent prefetching into an unrelated submit. (And 2446 * either way, at some point the ROQ will be full.) 2447 */ 2448 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2449 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2450 2451 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2452 2453 ring->last_cp_state = cp_state; 2454 2455 return progress; 2456 } 2457 2458 static void 2459 perfcntr_select(struct msm_ringbuffer *ring, enum adreno_pipe pipe, 2460 uint32_t regidx, uint32_t *countables, uint32_t nr, 2461 uint32_t **reglist) 2462 { 2463 OUT_PKT4(ring, regidx, nr); 2464 for (unsigned i = 0; i < nr; i++) 2465 OUT_RING(ring, countables[i]); 2466 2467 if (!*reglist) 2468 return; 2469 2470 for (unsigned i = 0; i < nr; i++) { 2471 /* 2472 * Bitfield is in same position on a7xx, but only 2 bits.. 2473 * which is sufficient for NONE/BR/BV: 2474 */ 2475 *(*reglist)++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe); 2476 *(*reglist)++ = regidx + i; 2477 *(*reglist)++ = countables[i]; 2478 } 2479 } 2480 2481 static void 2482 a6xx_perfcntr_configure(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 2483 const struct msm_perfcntr_stream *stream) 2484 { 2485 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2486 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2487 enum adreno_pipe pipe = PIPE_NONE; 2488 uint32_t *reglist = NULL; 2489 uint32_t *reglist_sel_start; 2490 2491 if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) { 2492 WARN_ON(!a6xx_gpu->pwrup_reglist_emitted); 2493 2494 struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; 2495 int off = (2 * lock->ifpc_list_len) + 2496 (2 * lock->preemption_list_len) + 2497 (3 * a6xx_gpu->dynamic_sel_reglist_offset); 2498 2499 reglist = (uint32_t *)&lock->regs[0]; 2500 reglist += off; 2501 reglist_sel_start = reglist; 2502 2503 /* Clear any previously configured SEL reg entries: */ 2504 lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset; 2505 2506 /* 2507 * Ensure CP sees the dynamic_list_len update before we 2508 * start modifying the SEL entries: 2509 */ 2510 dma_wmb(); 2511 } 2512 2513 for (unsigned i = 0; i < stream->nr_groups; i++) { 2514 unsigned group_idx = msm_perfcntr_group_idx(stream, i); 2515 unsigned base = msm_perfcntr_counter_base(stream, group_idx); 2516 2517 const struct msm_perfcntr_group *group = 2518 &gpu->perfcntr_groups[group_idx]; 2519 2520 struct msm_perfcntr_group_state *group_state = 2521 gpu->perfcntrs->groups[group_idx]; 2522 2523 if (group->pipe != pipe) { 2524 pipe = group->pipe; 2525 2526 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 2527 2528 if (pipe == PIPE_BR) { 2529 OUT_RING(ring, CP_SET_THREAD_BR); 2530 } else if (pipe == PIPE_BV) { 2531 OUT_RING(ring, CP_SET_THREAD_BV); 2532 } else { 2533 OUT_RING(ring, CP_SET_THREAD_BOTH); 2534 } 2535 } 2536 2537 const struct msm_perfcntr_counter *counter = &group->counters[base]; 2538 unsigned nr = group_state->allocated_counters; 2539 perfcntr_select(ring, pipe, counter->select_reg, 2540 group_state->countables, nr, ®list); 2541 2542 for (unsigned s = 0; s < ARRAY_SIZE(counter->slice_select_regs); s++) { 2543 if (!counter->slice_select_regs[s]) 2544 break; 2545 2546 perfcntr_select(ring, pipe, counter->slice_select_regs[s], 2547 group_state->countables, nr, ®list); 2548 } 2549 } 2550 2551 if (pipe != PIPE_NONE) { 2552 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 2553 OUT_RING(ring, CP_SET_THREAD_BOTH); 2554 } 2555 2556 OUT_PKT7(ring, CP_MEM_WRITE, 3); 2557 OUT_RING(ring, lower_32_bits(rbmemptr(ring, perfcntr_fence))); 2558 OUT_RING(ring, upper_32_bits(rbmemptr(ring, perfcntr_fence))); 2559 OUT_RING(ring, stream->sel_fence); 2560 2561 /* 2562 * Update the pwrup reglist size before flushing. Kgsl does a shared- 2563 * memory spinlock dance with SQE to avoid racing with IFPC exit. But 2564 * we can skip that since the ringbuffer programming will be executed 2565 * by SQE after dynamic reglist size is updated. So even if we lose 2566 * the race, the register programming in the rb will overwrite/correct 2567 * the SEL regs restored by SQE on IFPC exit, before sampling begins. 2568 */ 2569 if (reglist) { 2570 struct cpu_gpu_lock *lock = a6xx_gpu->pwrup_reglist_ptr; 2571 unsigned nr_regs = (reglist - reglist_sel_start) / 3; 2572 2573 /* 2574 * Ensure CP sees updates to the pwrup_reglist before it 2575 * sees the new (increased) length: 2576 */ 2577 dma_wmb(); 2578 2579 /* Update dynamic reglist len to include new SEL reg programming: */ 2580 lock->dynamic_list_len = a6xx_gpu->dynamic_sel_reglist_offset + nr_regs; 2581 2582 WARN_ON_ONCE(reglist > (uint32_t *)((uint8_t *)lock + PWRUP_REGLIST_SIZE)); 2583 } 2584 2585 a6xx_flush_yield(gpu, ring); 2586 2587 /* Check to see if we need to start preemption */ 2588 if (adreno_is_a8xx(to_adreno_gpu(gpu))) 2589 a8xx_preempt_trigger(gpu); 2590 else 2591 a6xx_preempt_trigger(gpu); 2592 } 2593 2594 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) 2595 { 2596 if (!info->speedbins) 2597 return UINT_MAX; 2598 2599 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) 2600 if (info->speedbins[i].fuse == fuse) 2601 return BIT(info->speedbins[i].speedbin); 2602 2603 return UINT_MAX; 2604 } 2605 2606 static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu, 2607 const struct adreno_info *info, u32 *speedbin) 2608 { 2609 int ret; 2610 2611 /* Use speedbin fuse if present. Otherwise, fallback to softfuse */ 2612 ret = adreno_read_speedbin(dev, speedbin); 2613 if (ret != -ENOENT) 2614 return ret; 2615 2616 if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { 2617 *speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS); 2618 *speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin); 2619 return 0; 2620 } 2621 2622 return -ENOENT; 2623 } 2624 2625 static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, 2626 const struct adreno_info *info) 2627 { 2628 u32 supp_hw; 2629 u32 speedbin; 2630 int ret; 2631 2632 ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin); 2633 /* 2634 * -ENOENT means that the platform doesn't support speedbin which is 2635 * fine 2636 */ 2637 if (ret == -ENOENT) { 2638 return 0; 2639 } else if (ret) { 2640 dev_err_probe(dev, ret, 2641 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2642 return ret; 2643 } 2644 2645 supp_hw = fuse_to_supp_hw(info, speedbin); 2646 2647 if (supp_hw == UINT_MAX) { 2648 DRM_DEV_ERROR(dev, 2649 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2650 speedbin); 2651 supp_hw = BIT(0); /* Default */ 2652 } 2653 2654 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2655 if (ret) 2656 return ret; 2657 2658 return 0; 2659 } 2660 2661 static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu) 2662 { 2663 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2664 2665 /* 2666 * AQE uses preemption context record as scratch pad, so check if 2667 * preemption is enabled 2668 */ 2669 return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo; 2670 } 2671 2672 static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2673 { 2674 struct msm_drm_private *priv = dev->dev_private; 2675 struct platform_device *pdev = priv->gpu_pdev; 2676 struct adreno_platform_config *config = pdev->dev.platform_data; 2677 const struct adreno_info *info = config->info; 2678 struct device_node *phandle; 2679 struct a6xx_gpu *a6xx_gpu; 2680 struct adreno_gpu *adreno_gpu; 2681 struct msm_gpu *gpu; 2682 extern int enable_preemption; 2683 u32 speedbin; 2684 bool is_a7xx; 2685 int ret, nr_rings = 1; 2686 2687 a6xx_gpu = kzalloc_obj(*a6xx_gpu); 2688 if (!a6xx_gpu) 2689 return ERR_PTR(-ENOMEM); 2690 2691 adreno_gpu = &a6xx_gpu->base; 2692 gpu = &adreno_gpu->base; 2693 2694 if ((ADRENO_6XX_GEN1 <= config->info->family) && 2695 (config->info->family <= ADRENO_6XX_GEN4)) { 2696 gpu->perfcntr_groups = a6xx_perfcntr_groups; 2697 gpu->num_perfcntr_groups = a6xx_num_perfcntr_groups; 2698 } else if ((ADRENO_7XX_GEN1 <= config->info->family) && 2699 (config->info->family <= ADRENO_7XX_GEN3)) { 2700 gpu->perfcntr_groups = a7xx_perfcntr_groups; 2701 gpu->num_perfcntr_groups = a7xx_num_perfcntr_groups; 2702 } else if ((ADRENO_8XX_GEN1 <= config->info->family) && 2703 (config->info->family <= ADRENO_8XX_GEN2)) { 2704 gpu->perfcntr_groups = a8xx_perfcntr_groups; 2705 gpu->num_perfcntr_groups = a8xx_num_perfcntr_groups; 2706 } 2707 2708 mutex_init(&a6xx_gpu->gmu.lock); 2709 spin_lock_init(&a6xx_gpu->aperture_lock); 2710 2711 adreno_gpu->registers = NULL; 2712 2713 /* Check if there is a GMU phandle and set it up */ 2714 struct device_node *node __free(device_node) = 2715 of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2716 /* FIXME: How do we gracefully handle this? */ 2717 BUG_ON(!node); 2718 2719 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2720 2721 adreno_gpu->base.hw_apriv = 2722 !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); 2723 2724 /* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */ 2725 is_a7xx = info->family >= ADRENO_7XX_GEN1; 2726 2727 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); 2728 2729 /* 2730 * There is a different programming path for A6xx targets with an 2731 * mmu500 attached, so detect if that is the case 2732 */ 2733 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 2734 a6xx_gpu->have_mmu500 = (phandle && 2735 of_device_is_compatible(phandle, "arm,mmu-500")); 2736 of_node_put(phandle); 2737 2738 if (is_a7xx || !a6xx_gpu->have_mmu500) 2739 a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem"); 2740 else 2741 a6xx_gpu->cx_misc_mmio = NULL; 2742 2743 ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); 2744 if (ret) { 2745 a6xx_llc_slices_destroy(a6xx_gpu); 2746 kfree(a6xx_gpu); 2747 return ERR_PTR(ret); 2748 } 2749 2750 if ((enable_preemption == 1) || (enable_preemption == -1 && 2751 (info->quirks & ADRENO_QUIRK_PREEMPTION))) 2752 nr_rings = 4; 2753 2754 ret = adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings); 2755 if (ret) { 2756 a6xx_destroy(&(a6xx_gpu->base.base)); 2757 return ERR_PTR(ret); 2758 } 2759 2760 /* Set the speedbin value that is passed to userspace */ 2761 if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin) 2762 speedbin = 0xffff; 2763 adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); 2764 2765 /* 2766 * For now only clamp to idle freq for devices where this is known not 2767 * to cause power supply issues: 2768 */ 2769 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2770 priv->gpu_clamp_to_idle = true; 2771 2772 if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) 2773 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2774 else 2775 ret = a6xx_gmu_init(a6xx_gpu, node); 2776 if (ret) { 2777 a6xx_destroy(&(a6xx_gpu->base.base)); 2778 return ERR_PTR(ret); 2779 } 2780 2781 adreno_gpu->uche_trap_base = 0x1fffffffff000ull; 2782 2783 msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, 2784 adreno_gpu->funcs->mmu_fault_handler); 2785 2786 adreno_gpu->ubwc_config = qcom_ubwc_config_get_data(); 2787 if (IS_ERR(adreno_gpu->ubwc_config)) { 2788 ret = PTR_ERR(adreno_gpu->ubwc_config); 2789 a6xx_destroy(&(a6xx_gpu->base.base)); 2790 return ERR_PTR(ret); 2791 } 2792 2793 /* Set up the preemption specific bits and pieces for each ringbuffer */ 2794 a6xx_preempt_init(gpu); 2795 2796 return gpu; 2797 } 2798 2799 const struct adreno_gpu_funcs a6xx_gpu_funcs = { 2800 .base = { 2801 .get_param = adreno_get_param, 2802 .set_param = adreno_set_param, 2803 .hw_init = a6xx_hw_init, 2804 .ucode_load = a6xx_ucode_load, 2805 .pm_suspend = a6xx_gmu_pm_suspend, 2806 .pm_resume = a6xx_gmu_pm_resume, 2807 .recover = a6xx_recover, 2808 .submit = a6xx_submit, 2809 .active_ring = a6xx_active_ring, 2810 .irq = a6xx_irq, 2811 .destroy = a6xx_destroy, 2812 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2813 .show = a6xx_show, 2814 #endif 2815 .gpu_busy = a6xx_gpu_busy, 2816 .gpu_get_freq = a6xx_gmu_get_freq, 2817 .gpu_set_freq = a6xx_gpu_set_freq, 2818 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2819 .gpu_state_get = a6xx_gpu_state_get, 2820 .gpu_state_put = a6xx_gpu_state_put, 2821 #endif 2822 .create_vm = a6xx_create_vm, 2823 .create_private_vm = a6xx_create_private_vm, 2824 .get_rptr = a6xx_get_rptr, 2825 .progress = a6xx_progress, 2826 .sysprof_setup = a6xx_gmu_sysprof_setup, 2827 .perfcntr_configure = a6xx_perfcntr_configure, 2828 }, 2829 .init = a6xx_gpu_init, 2830 .get_timestamp = a6xx_gmu_get_timestamp, 2831 .bus_halt = a6xx_bus_clear_pending_transactions, 2832 .mmu_fault_handler = a6xx_fault_handler, 2833 .gx_is_on = a6xx_gmu_gx_is_on, 2834 }; 2835 2836 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = { 2837 .base = { 2838 .get_param = adreno_get_param, 2839 .set_param = adreno_set_param, 2840 .hw_init = a6xx_hw_init, 2841 .ucode_load = a6xx_ucode_load, 2842 .pm_suspend = a6xx_pm_suspend, 2843 .pm_resume = a6xx_pm_resume, 2844 .recover = a6xx_recover, 2845 .submit = a6xx_submit, 2846 .active_ring = a6xx_active_ring, 2847 .irq = a6xx_irq, 2848 .destroy = a6xx_destroy, 2849 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2850 .show = a6xx_show, 2851 #endif 2852 .gpu_busy = a6xx_gpu_busy, 2853 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2854 .gpu_state_get = a6xx_gpu_state_get, 2855 .gpu_state_put = a6xx_gpu_state_put, 2856 #endif 2857 .create_vm = a6xx_create_vm, 2858 .create_private_vm = a6xx_create_private_vm, 2859 .get_rptr = a6xx_get_rptr, 2860 .progress = a6xx_progress, 2861 .perfcntr_configure = a6xx_perfcntr_configure, 2862 }, 2863 .init = a6xx_gpu_init, 2864 .get_timestamp = a6xx_get_timestamp, 2865 .bus_halt = a6xx_bus_clear_pending_transactions, 2866 .mmu_fault_handler = a6xx_fault_handler, 2867 .gx_is_on = a6xx_gmu_gx_is_on, 2868 }; 2869 2870 const struct adreno_gpu_funcs a7xx_gpu_funcs = { 2871 .base = { 2872 .get_param = adreno_get_param, 2873 .set_param = adreno_set_param, 2874 .hw_init = a6xx_hw_init, 2875 .ucode_load = a6xx_ucode_load, 2876 .pm_suspend = a6xx_gmu_pm_suspend, 2877 .pm_resume = a6xx_gmu_pm_resume, 2878 .recover = a6xx_recover, 2879 .submit = a7xx_submit, 2880 .active_ring = a6xx_active_ring, 2881 .irq = a6xx_irq, 2882 .destroy = a6xx_destroy, 2883 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2884 .show = a6xx_show, 2885 #endif 2886 .gpu_busy = a6xx_gpu_busy, 2887 .gpu_get_freq = a6xx_gmu_get_freq, 2888 .gpu_set_freq = a6xx_gpu_set_freq, 2889 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2890 .gpu_state_get = a6xx_gpu_state_get, 2891 .gpu_state_put = a6xx_gpu_state_put, 2892 #endif 2893 .create_vm = a6xx_create_vm, 2894 .create_private_vm = a6xx_create_private_vm, 2895 .get_rptr = a6xx_get_rptr, 2896 .progress = a6xx_progress, 2897 .sysprof_setup = a6xx_gmu_sysprof_setup, 2898 .perfcntr_configure = a6xx_perfcntr_configure, 2899 }, 2900 .init = a6xx_gpu_init, 2901 .get_timestamp = a6xx_gmu_get_timestamp, 2902 .bus_halt = a6xx_bus_clear_pending_transactions, 2903 .mmu_fault_handler = a6xx_fault_handler, 2904 .gx_is_on = a7xx_gmu_gx_is_on, 2905 .aqe_is_enabled = a6xx_aqe_is_enabled, 2906 }; 2907 2908 const struct adreno_gpu_funcs a8xx_gpu_funcs = { 2909 .base = { 2910 .get_param = adreno_get_param, 2911 .set_param = adreno_set_param, 2912 .hw_init = a8xx_hw_init, 2913 .ucode_load = a6xx_ucode_load, 2914 .pm_suspend = a6xx_gmu_pm_suspend, 2915 .pm_resume = a6xx_gmu_pm_resume, 2916 .recover = a8xx_recover, 2917 .submit = a7xx_submit, 2918 .active_ring = a6xx_active_ring, 2919 .irq = a8xx_irq, 2920 .destroy = a6xx_destroy, 2921 .gpu_busy = a8xx_gpu_busy, 2922 .gpu_get_freq = a6xx_gmu_get_freq, 2923 .gpu_set_freq = a6xx_gpu_set_freq, 2924 .create_vm = a6xx_create_vm, 2925 .create_private_vm = a6xx_create_private_vm, 2926 .get_rptr = a6xx_get_rptr, 2927 .progress = a8xx_progress, 2928 .sysprof_setup = a6xx_gmu_sysprof_setup, 2929 .perfcntr_configure = a6xx_perfcntr_configure, 2930 .perfcntr_flush = a8xx_perfcntr_flush, 2931 }, 2932 .init = a6xx_gpu_init, 2933 .get_timestamp = a8xx_gmu_get_timestamp, 2934 .bus_halt = a8xx_bus_clear_pending_transactions, 2935 .mmu_fault_handler = a8xx_fault_handler, 2936 .gx_is_on = a8xx_gmu_gx_is_on, 2937 .aqe_is_enabled = a6xx_aqe_is_enabled, 2938 }; 2939