1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD4062 I3C ADC driver 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 #include <linux/array_size.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/devm-helpers.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i3c/device.h> 16 #include <linux/i3c/master.h> 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/events.h> 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/trigger.h> 22 #include <linux/iio/trigger_consumer.h> 23 #include <linux/iio/triggered_buffer.h> 24 #include <linux/interrupt.h> 25 #include <linux/jiffies.h> 26 #include <linux/math.h> 27 #include <linux/minmax.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/property.h> 30 #include <linux/regmap.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/string.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 #include <linux/unaligned.h> 36 #include <linux/util_macros.h> 37 38 #define AD4062_REG_INTERFACE_CONFIG_A 0x00 39 #define AD4062_REG_DEVICE_CONFIG 0x02 40 #define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0) 41 #define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3 42 #define AD4062_REG_PROD_ID_1 0x05 43 #define AD4062_REG_DEVICE_GRADE 0x06 44 #define AD4062_REG_SCRATCH_PAD 0x0A 45 #define AD4062_REG_VENDOR_H 0x0D 46 #define AD4062_REG_STREAM_MODE 0x0E 47 #define AD4062_REG_INTERFACE_STATUS 0x11 48 #define AD4062_REG_MODE_SET 0x20 49 #define AD4062_REG_MODE_SET_ENTER_ADC BIT(0) 50 #define AD4062_REG_ADC_MODES 0x21 51 #define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0) 52 #define AD4062_REG_ADC_CONFIG 0x22 53 #define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5) 54 #define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4) 55 #define AD4062_REG_AVG_CONFIG 0x23 56 #define AD4062_REG_GP_CONF 0x24 57 #define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0) 58 #define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4) 59 #define AD4062_REG_INTR_CONF 0x25 60 #define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0) 61 #define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4) 62 #define AD4062_REG_TIMER_CONFIG 0x27 63 #define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4) 64 #define AD4062_REG_MAX_LIMIT 0x29 65 #define AD4062_REG_MIN_LIMIT 0x2B 66 #define AD4062_REG_MAX_HYST 0x2C 67 #define AD4062_REG_MIN_HYST 0x2D 68 #define AD4062_REG_MON_VAL 0x2F 69 #define AD4062_REG_ADC_IBI_EN 0x31 70 #define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2) 71 #define AD4062_REG_ADC_IBI_EN_MAX BIT(1) 72 #define AD4062_REG_ADC_IBI_EN_MIN BIT(0) 73 #define AD4062_REG_FUSE_CRC 0x40 74 #define AD4062_REG_DEVICE_STATUS 0x41 75 #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) 76 #define AD4062_REG_IBI_STATUS 0x48 77 #define AD4062_REG_CONV_READ_LSB 0x50 78 #define AD4062_REG_CONV_READ_16BITS 0x51 79 #define AD4062_REG_CONV_READ_32BITS 0x53 80 #define AD4062_REG_CONV_TRIGGER_16BITS 0x57 81 #define AD4062_REG_CONV_TRIGGER_32BITS 0x59 82 #define AD4062_REG_CONV_AUTO 0x61 83 #define AD4062_MAX_REG AD4062_REG_CONV_AUTO 84 85 #define AD4062_MON_VAL_MIDDLE_POINT 0x8000 86 87 #define AD4062_I3C_VENDOR 0x0177 88 #define AD4062_SOFT_RESET 0x81 89 #define AD4060_PROD_ID 0x7A 90 #define AD4062_PROD_ID 0x7C 91 92 #define AD4062_GP_DISABLED 0x0 93 #define AD4062_GP_INTR 0x1 94 #define AD4062_GP_DRDY 0x2 95 #define AD4062_GP_STATIC_LOW 0x5 96 #define AD4062_GP_STATIC_HIGH 0x6 97 98 #define AD4062_LIMIT_BITS 12 99 100 #define AD4062_INTR_EN_NEITHER 0x0 101 #define AD4062_INTR_EN_EITHER 0x3 102 103 #define AD4062_TCONV_NS 270 104 105 enum ad4062_operation_mode { 106 AD4062_SAMPLE_MODE = 0x0, 107 AD4062_BURST_AVERAGING_MODE = 0x1, 108 AD4062_MONITOR_MODE = 0x3, 109 }; 110 111 struct ad4062_chip_info { 112 const struct iio_chan_spec channels[1]; 113 const char *name; 114 u16 prod_id; 115 u16 avg_max; 116 }; 117 118 enum { 119 AD4062_SCAN_TYPE_SAMPLE, 120 AD4062_SCAN_TYPE_BURST_AVG, 121 }; 122 123 static const struct iio_scan_type ad4062_scan_type_12_s[] = { 124 [AD4062_SCAN_TYPE_SAMPLE] = { 125 .sign = 's', 126 .realbits = 12, 127 .storagebits = 16, 128 .endianness = IIO_BE, 129 }, 130 [AD4062_SCAN_TYPE_BURST_AVG] = { 131 .sign = 's', 132 .realbits = 14, 133 .storagebits = 16, 134 .endianness = IIO_BE, 135 }, 136 }; 137 138 static const struct iio_scan_type ad4062_scan_type_16_s[] = { 139 [AD4062_SCAN_TYPE_SAMPLE] = { 140 .sign = 's', 141 .realbits = 16, 142 .storagebits = 16, 143 .endianness = IIO_BE, 144 }, 145 [AD4062_SCAN_TYPE_BURST_AVG] = { 146 .sign = 's', 147 .realbits = 20, 148 .storagebits = 32, 149 .endianness = IIO_BE, 150 }, 151 }; 152 153 static const unsigned int ad4062_conversion_freqs[] = { 154 2000000, 1000000, 300000, 100000, /* 0 - 3 */ 155 33300, 10000, 3000, 500, /* 4 - 7 */ 156 333, 250, 200, 166, /* 8 - 11 */ 157 140, 124, 111, /* 12 - 15 */ 158 }; 159 160 struct ad4062_state { 161 const struct ad4062_chip_info *chip; 162 const struct ad4062_bus_ops *ops; 163 enum ad4062_operation_mode mode; 164 struct work_struct trig_conv; 165 struct completion completion; 166 struct iio_trigger *trigger; 167 struct iio_dev *indio_dev; 168 struct i3c_device *i3cdev; 169 struct regmap *regmap; 170 bool wait_event; 171 int vref_uV; 172 unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; 173 bool gpo_irq[2]; 174 u16 sampling_frequency; 175 u16 events_frequency; 176 u8 oversamp_ratio; 177 u8 conv_sizeof; 178 u8 conv_addr; 179 union { 180 __be32 be32; 181 __be16 be16; 182 } buf __aligned(IIO_DMA_MINALIGN); 183 }; 184 185 static const struct regmap_range ad4062_regmap_rd_ranges[] = { 186 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE), 187 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS), 188 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 189 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS), 190 regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO), 191 }; 192 193 static const struct regmap_access_table ad4062_regmap_rd_table = { 194 .yes_ranges = ad4062_regmap_rd_ranges, 195 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_rd_ranges), 196 }; 197 198 static const struct regmap_range ad4062_regmap_wr_ranges[] = { 199 regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG), 200 regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD), 201 regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS), 202 regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), 203 regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS), 204 }; 205 206 static const struct regmap_access_table ad4062_regmap_wr_table = { 207 .yes_ranges = ad4062_regmap_wr_ranges, 208 .n_yes_ranges = ARRAY_SIZE(ad4062_regmap_wr_ranges), 209 }; 210 211 static const struct iio_event_spec ad4062_events[] = { 212 { 213 .type = IIO_EV_TYPE_THRESH, 214 .dir = IIO_EV_DIR_EITHER, 215 .mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE), 216 }, 217 { 218 .type = IIO_EV_TYPE_THRESH, 219 .dir = IIO_EV_DIR_RISING, 220 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 221 BIT(IIO_EV_INFO_HYSTERESIS), 222 }, 223 { 224 .type = IIO_EV_TYPE_THRESH, 225 .dir = IIO_EV_DIR_FALLING, 226 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) | 227 BIT(IIO_EV_INFO_HYSTERESIS), 228 }, 229 }; 230 231 #define AD4062_CHAN(bits) { \ 232 .type = IIO_VOLTAGE, \ 233 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \ 234 BIT(IIO_CHAN_INFO_SCALE) | \ 235 BIT(IIO_CHAN_INFO_CALIBSCALE) | \ 236 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 237 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 238 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 239 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 240 .indexed = 1, \ 241 .channel = 0, \ 242 .event_spec = ad4062_events, \ 243 .num_event_specs = ARRAY_SIZE(ad4062_events), \ 244 .has_ext_scan_type = 1, \ 245 .ext_scan_type = ad4062_scan_type_##bits##_s, \ 246 .num_ext_scan_type = ARRAY_SIZE(ad4062_scan_type_##bits##_s), \ 247 } 248 249 static const struct ad4062_chip_info ad4060_chip_info = { 250 .name = "ad4060", 251 .channels = { AD4062_CHAN(12) }, 252 .prod_id = AD4060_PROD_ID, 253 .avg_max = 256, 254 }; 255 256 static const struct ad4062_chip_info ad4062_chip_info = { 257 .name = "ad4062", 258 .channels = { AD4062_CHAN(16) }, 259 .prod_id = AD4062_PROD_ID, 260 .avg_max = 4096, 261 }; 262 263 static ssize_t sampling_frequency_show(struct device *dev, 264 struct device_attribute *attr, char *buf) 265 { 266 struct ad4062_state *st = iio_priv(dev_to_iio_dev(dev)); 267 268 return sysfs_emit(buf, "%d\n", ad4062_conversion_freqs[st->events_frequency]); 269 } 270 271 static int sampling_frequency_store_dispatch(struct iio_dev *indio_dev, 272 const char *buf) 273 { 274 struct ad4062_state *st = iio_priv(indio_dev); 275 int val, ret; 276 277 if (st->wait_event) 278 return -EBUSY; 279 280 ret = kstrtoint(buf, 10, &val); 281 if (ret) 282 return ret; 283 284 st->events_frequency = find_closest_descending(val, ad4062_conversion_freqs, 285 ARRAY_SIZE(ad4062_conversion_freqs)); 286 return 0; 287 } 288 289 static ssize_t sampling_frequency_store(struct device *dev, 290 struct device_attribute *attr, 291 const char *buf, size_t len) 292 { 293 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 294 int ret; 295 296 if (!iio_device_claim_direct(indio_dev)) 297 return -EBUSY; 298 299 ret = sampling_frequency_store_dispatch(indio_dev, buf); 300 iio_device_release_direct(indio_dev); 301 return ret ?: len; 302 } 303 304 static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); 305 306 static ssize_t sampling_frequency_available_show(struct device *dev, 307 struct device_attribute *attr, 308 char *buf) 309 { 310 int ret = 0; 311 312 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 313 ret += sysfs_emit_at(buf, ret, "%d%s", ad4062_conversion_freqs[i], 314 i != (ARRAY_SIZE(ad4062_conversion_freqs) - 1) ? " " : "\n"); 315 return ret; 316 } 317 318 static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0); 319 320 static struct attribute *ad4062_event_attributes[] = { 321 &iio_dev_attr_sampling_frequency.dev_attr.attr, 322 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 323 NULL 324 }; 325 326 static const struct attribute_group ad4062_event_attribute_group = { 327 .attrs = ad4062_event_attributes, 328 }; 329 330 static int ad4062_set_oversampling_ratio(struct ad4062_state *st, int val, int val2) 331 { 332 const u32 _max = st->chip->avg_max; 333 const u32 _min = 1; 334 int ret; 335 336 if (!in_range(val, _min, _max) || val2 != 0) 337 return -EINVAL; 338 339 /* 1 disables oversampling */ 340 val = ilog2(val); 341 if (val == 0) { 342 st->mode = AD4062_SAMPLE_MODE; 343 } else { 344 st->mode = AD4062_BURST_AVERAGING_MODE; 345 ret = regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1); 346 if (ret) 347 return ret; 348 } 349 st->oversamp_ratio = val; 350 351 return 0; 352 } 353 354 static int ad4062_get_oversampling_ratio(struct ad4062_state *st, int *val) 355 { 356 int ret, buf; 357 358 if (st->mode == AD4062_SAMPLE_MODE) { 359 *val = 1; 360 return 0; 361 } 362 363 ret = regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf); 364 if (ret) 365 return ret; 366 367 *val = BIT(buf + 1); 368 return 0; 369 } 370 371 static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int oversamp_ratio) 372 { 373 /* From datasheet p.31: (n_avg - 1)/fosc + tconv */ 374 u32 n_avg = BIT(oversamp_ratio) - 1; 375 u32 period_ns = NSEC_PER_SEC / fosc; 376 377 /* Result is less than 1 Hz */ 378 if (n_avg >= fosc) 379 return 1; 380 381 return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS); 382 } 383 384 static int ad4062_populate_sampling_frequency(struct ad4062_state *st) 385 { 386 for (u8 i = 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) 387 st->samp_freqs[i] = 388 ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i], 389 st->oversamp_ratio); 390 return 0; 391 } 392 393 static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val) 394 { 395 int freq = ad4062_conversion_freqs[st->sampling_frequency]; 396 397 *val = ad4062_calc_sampling_frequency(freq, st->oversamp_ratio); 398 return IIO_VAL_INT; 399 } 400 401 static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val, int val2) 402 { 403 int ret; 404 405 if (val2 != 0) 406 return -EINVAL; 407 408 ret = ad4062_populate_sampling_frequency(st); 409 if (ret) 410 return ret; 411 412 st->sampling_frequency = 413 find_closest_descending(val, st->samp_freqs, 414 ARRAY_SIZE(ad4062_conversion_freqs)); 415 return 0; 416 } 417 418 static int ad4062_check_ids(struct ad4062_state *st) 419 { 420 struct device *dev = &st->i3cdev->dev; 421 int ret; 422 u16 val; 423 424 ret = regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1, 425 &st->buf.be16, sizeof(st->buf.be16)); 426 if (ret) 427 return ret; 428 429 val = be16_to_cpu(st->buf.be16); 430 if (val != st->chip->prod_id) 431 dev_warn(dev, "Production ID x%x does not match known values", val); 432 433 ret = regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H, 434 &st->buf.be16, sizeof(st->buf.be16)); 435 if (ret) 436 return ret; 437 438 val = be16_to_cpu(st->buf.be16); 439 if (val != AD4062_I3C_VENDOR) 440 return dev_err_probe(dev, -ENODEV, 441 "Vendor ID x%x does not match expected value\n", val); 442 443 return 0; 444 } 445 446 static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val) 447 { 448 return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG, 449 FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val)); 450 } 451 452 static int ad4062_set_operation_mode(struct ad4062_state *st, 453 enum ad4062_operation_mode mode) 454 { 455 const unsigned int samp_freq = mode == AD4062_MONITOR_MODE ? 456 st->events_frequency : st->sampling_frequency; 457 int ret; 458 459 ret = ad4062_conversion_frequency_set(st, samp_freq); 460 if (ret) 461 return ret; 462 463 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES, 464 AD4062_REG_ADC_MODES_MODE_MSK, mode); 465 if (ret) 466 return ret; 467 468 if (mode == AD4062_MONITOR_MODE) { 469 /* Change address pointer to enter monitor mode */ 470 struct i3c_xfer xfer_trigger = { 471 .data.out = &st->conv_addr, 472 .len = sizeof(st->conv_addr), 473 .rnw = false, 474 }; 475 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 476 return i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 477 } 478 479 return regmap_write(st->regmap, AD4062_REG_MODE_SET, 480 AD4062_REG_MODE_SET_ENTER_ADC); 481 } 482 483 static int ad4062_soft_reset(struct ad4062_state *st) 484 { 485 u8 val = AD4062_SOFT_RESET; 486 int ret; 487 488 ret = regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val); 489 if (ret) 490 return ret; 491 492 /* Wait AD4062 treset time, datasheet p8 */ 493 ndelay(60); 494 495 return 0; 496 } 497 498 static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, 499 const bool *ref_sel) 500 { 501 struct ad4062_state *st = iio_priv(indio_dev); 502 const struct iio_scan_type *scan_type; 503 int ret; 504 505 scan_type = iio_get_current_scan_type(indio_dev, chan); 506 if (IS_ERR(scan_type)) 507 return PTR_ERR(scan_type); 508 509 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 510 AD4062_REG_GP_CONF_MODE_MSK_0, 511 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, 512 AD4062_GP_INTR)); 513 if (ret) 514 return ret; 515 516 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 517 AD4062_REG_GP_CONF_MODE_MSK_1, 518 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, 519 AD4062_GP_DRDY)); 520 if (ret) 521 return ret; 522 523 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 524 AD4062_REG_ADC_CONFIG_REF_EN_MSK, 525 FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK, 526 *ref_sel)); 527 if (ret) 528 return ret; 529 530 ret = regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS, 531 AD4062_REG_DEVICE_STATUS_DEVICE_RESET); 532 if (ret) 533 return ret; 534 535 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 536 AD4062_REG_INTR_CONF_EN_MSK_0, 537 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_0, 538 AD4062_INTR_EN_EITHER)); 539 if (ret) 540 return ret; 541 542 ret = regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, 543 AD4062_REG_INTR_CONF_EN_MSK_1, 544 FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, 545 AD4062_INTR_EN_NEITHER)); 546 if (ret) 547 return ret; 548 549 st->buf.be16 = cpu_to_be16(AD4062_MON_VAL_MIDDLE_POINT); 550 return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 551 &st->buf.be16, sizeof(st->buf.be16)); 552 } 553 554 static irqreturn_t ad4062_irq_handler_thresh(int irq, void *private) 555 { 556 struct iio_dev *indio_dev = private; 557 558 iio_push_event(indio_dev, 559 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 560 IIO_EV_TYPE_THRESH, 561 IIO_EV_DIR_EITHER), 562 iio_get_time_ns(indio_dev)); 563 564 return IRQ_HANDLED; 565 } 566 567 static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private) 568 { 569 struct iio_dev *indio_dev = private; 570 struct ad4062_state *st = iio_priv(indio_dev); 571 572 if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) 573 iio_trigger_poll(st->trigger); 574 else 575 complete(&st->completion); 576 577 return IRQ_HANDLED; 578 } 579 580 static void ad4062_ibi_handler(struct i3c_device *i3cdev, 581 const struct i3c_ibi_payload *payload) 582 { 583 struct ad4062_state *st = i3cdev_get_drvdata(i3cdev); 584 585 if (st->wait_event) { 586 iio_push_event(st->indio_dev, 587 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, 588 IIO_EV_TYPE_THRESH, 589 IIO_EV_DIR_EITHER), 590 iio_get_time_ns(st->indio_dev)); 591 return; 592 } 593 if (iio_buffer_enabled(st->indio_dev)) 594 iio_trigger_poll_nested(st->trigger); 595 else 596 complete(&st->completion); 597 } 598 599 static void ad4062_trigger_work(struct work_struct *work) 600 { 601 struct ad4062_state *st = 602 container_of(work, struct ad4062_state, trig_conv); 603 int ret; 604 605 /* 606 * Read current conversion, if at reg CONV_READ, stop bit triggers 607 * next sample and does not need writing the address. 608 */ 609 struct i3c_xfer xfer_sample = { 610 .data.in = &st->buf.be32, 611 .len = st->conv_sizeof, 612 .rnw = true, 613 }; 614 struct i3c_xfer xfer_trigger = { 615 .data.out = &st->conv_addr, 616 .len = sizeof(st->conv_addr), 617 .rnw = false, 618 }; 619 620 ret = i3c_device_do_xfers(st->i3cdev, &xfer_sample, 1, I3C_SDR); 621 if (ret) 622 return; 623 624 iio_push_to_buffers_with_ts(st->indio_dev, &st->buf.be32, st->conv_sizeof, 625 iio_get_time_ns(st->indio_dev)); 626 if (st->gpo_irq[1]) 627 return; 628 629 i3c_device_do_xfers(st->i3cdev, &xfer_trigger, 1, I3C_SDR); 630 } 631 632 static irqreturn_t ad4062_poll_handler(int irq, void *p) 633 { 634 struct iio_poll_func *pf = p; 635 struct iio_dev *indio_dev = pf->indio_dev; 636 struct ad4062_state *st = iio_priv(indio_dev); 637 638 iio_trigger_notify_done(indio_dev->trig); 639 schedule_work(&st->trig_conv); 640 641 return IRQ_HANDLED; 642 } 643 644 static void ad4062_disable_ibi(void *data) 645 { 646 struct i3c_device *i3cdev = data; 647 648 i3c_device_disable_ibi(i3cdev); 649 } 650 651 static void ad4062_free_ibi(void *data) 652 { 653 struct i3c_device *i3cdev = data; 654 655 i3c_device_free_ibi(i3cdev); 656 } 657 658 static int ad4062_request_ibi(struct i3c_device *i3cdev) 659 { 660 const struct i3c_ibi_setup ibireq = { 661 .max_payload_len = 1, 662 .num_slots = 1, 663 .handler = ad4062_ibi_handler, 664 }; 665 int ret; 666 667 ret = i3c_device_request_ibi(i3cdev, &ibireq); 668 if (ret) 669 return ret; 670 671 ret = devm_add_action_or_reset(&i3cdev->dev, ad4062_free_ibi, i3cdev); 672 if (ret) 673 return ret; 674 675 ret = i3c_device_enable_ibi(i3cdev); 676 if (ret) 677 return ret; 678 679 return devm_add_action_or_reset(&i3cdev->dev, ad4062_disable_ibi, i3cdev); 680 } 681 682 static int ad4062_request_irq(struct iio_dev *indio_dev) 683 { 684 struct ad4062_state *st = iio_priv(indio_dev); 685 struct device *dev = &st->i3cdev->dev; 686 int ret; 687 688 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp0"); 689 if (ret == -EPROBE_DEFER) 690 return ret; 691 692 if (ret < 0) { 693 st->gpo_irq[0] = false; 694 ret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 695 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, 696 AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); 697 if (ret) 698 return ret; 699 } else { 700 st->gpo_irq[0] = true; 701 ret = devm_request_threaded_irq(dev, ret, NULL, 702 ad4062_irq_handler_thresh, 703 IRQF_ONESHOT, indio_dev->name, 704 indio_dev); 705 if (ret) 706 return ret; 707 } 708 709 ret = fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1"); 710 if (ret == -EPROBE_DEFER) 711 return ret; 712 713 if (ret < 0) { 714 st->gpo_irq[1] = false; 715 return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, 716 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER, 717 AD4062_REG_ADC_IBI_EN_CONV_TRIGGER); 718 } 719 st->gpo_irq[1] = true; 720 721 return devm_request_irq(dev, ret, ad4062_irq_handler_drdy, 722 IRQF_NO_THREAD, indio_dev->name, indio_dev); 723 } 724 725 static const struct iio_trigger_ops ad4062_trigger_ops = { 726 .validate_device = &iio_trigger_validate_own_device, 727 }; 728 729 static int ad4062_request_trigger(struct iio_dev *indio_dev) 730 { 731 struct ad4062_state *st = iio_priv(indio_dev); 732 struct device *dev = &st->i3cdev->dev; 733 int ret; 734 735 st->trigger = devm_iio_trigger_alloc(dev, "%s-dev%d", 736 indio_dev->name, 737 iio_device_id(indio_dev)); 738 if (!st->trigger) 739 return -ENOMEM; 740 741 st->trigger->ops = &ad4062_trigger_ops; 742 iio_trigger_set_drvdata(st->trigger, indio_dev); 743 744 ret = devm_iio_trigger_register(dev, st->trigger); 745 if (ret) 746 return ret; 747 748 indio_dev->trig = iio_trigger_get(st->trigger); 749 750 return 0; 751 } 752 753 static const int ad4062_oversampling_avail[] = { 754 1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */ 755 256, 512, 1024, 2048, 4096, /* 8 - 12 */ 756 }; 757 758 static int ad4062_read_avail(struct iio_dev *indio_dev, 759 struct iio_chan_spec const *chan, const int **vals, 760 int *type, int *len, long mask) 761 { 762 struct ad4062_state *st = iio_priv(indio_dev); 763 int ret; 764 765 switch (mask) { 766 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 767 *vals = ad4062_oversampling_avail; 768 *len = ARRAY_SIZE(ad4062_oversampling_avail); 769 *len -= st->chip->avg_max == 256 ? 4 : 0; 770 *type = IIO_VAL_INT; 771 772 return IIO_AVAIL_LIST; 773 case IIO_CHAN_INFO_SAMP_FREQ: 774 ret = ad4062_populate_sampling_frequency(st); 775 if (ret) 776 return ret; 777 *vals = st->samp_freqs; 778 *len = st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1; 779 *type = IIO_VAL_INT; 780 781 return IIO_AVAIL_LIST; 782 default: 783 return -EINVAL; 784 } 785 } 786 787 static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int *val2) 788 { 789 struct ad4062_state *st = iio_priv(indio_dev); 790 const struct iio_scan_type *scan_type; 791 792 /* 793 * In burst averaging mode the averaging filter accumulates resulting 794 * in a sample with increased precision. 795 */ 796 scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels); 797 if (IS_ERR(scan_type)) 798 return PTR_ERR(scan_type); 799 800 *val = (st->vref_uV * 2) / (MICRO / MILLI); /* signed */ 801 *val2 = scan_type->realbits - 1; 802 803 return IIO_VAL_FRACTIONAL_LOG2; 804 } 805 806 static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, int *val2) 807 { 808 int ret; 809 810 ret = regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL, 811 &st->buf.be16, sizeof(st->buf.be16)); 812 if (ret) 813 return ret; 814 815 /* From datasheet: code out = code in × mon_val/0x8000 */ 816 *val = be16_to_cpu(st->buf.be16) * 2; 817 *val2 = 16; 818 819 return IIO_VAL_FRACTIONAL_LOG2; 820 } 821 822 static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_int, 823 int gain_frac) 824 { 825 /* Divide numerator and denumerator by known great common divider */ 826 const u32 mon_val = AD4062_MON_VAL_MIDDLE_POINT / 64; 827 const u32 micro = MICRO / 64; 828 const u32 gain_fp = gain_int * MICRO + gain_frac; 829 const u32 reg_val = DIV_ROUND_CLOSEST(gain_fp * mon_val, micro); 830 int ret; 831 832 /* Checks if the gain is in range and the value fits the field */ 833 if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1) 834 return -EINVAL; 835 836 st->buf.be16 = cpu_to_be16(reg_val); 837 ret = regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, 838 &st->buf.be16, sizeof(st->buf.be16)); 839 if (ret) 840 return ret; 841 842 /* Enable scale if gain is not equal to one */ 843 return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, 844 AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 845 FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, 846 !(gain_int == 1 && gain_frac == 0))); 847 } 848 849 static int ad4062_read_chan_raw(struct ad4062_state *st, int *val) 850 { 851 struct i3c_device *i3cdev = st->i3cdev; 852 struct i3c_xfer xfer_trigger = { 853 .data.out = &st->conv_addr, 854 .len = sizeof(st->conv_addr), 855 .rnw = false, 856 }; 857 struct i3c_xfer xfer_sample = { 858 .data.in = &st->buf.be32, 859 .len = sizeof(st->buf.be32), 860 .rnw = true, 861 }; 862 int ret; 863 864 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 865 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 866 if (ret) 867 return ret; 868 869 ret = ad4062_set_operation_mode(st, st->mode); 870 if (ret) 871 return ret; 872 873 reinit_completion(&st->completion); 874 /* Change address pointer to trigger conversion */ 875 st->conv_addr = AD4062_REG_CONV_TRIGGER_32BITS; 876 ret = i3c_device_do_xfers(i3cdev, &xfer_trigger, 1, I3C_SDR); 877 if (ret) 878 return ret; 879 /* 880 * Single sample read should be used only for oversampling and 881 * sampling frequency pairs that take less than 1 sec. 882 */ 883 ret = wait_for_completion_timeout(&st->completion, 884 msecs_to_jiffies(1000)); 885 if (!ret) 886 return -ETIMEDOUT; 887 888 ret = i3c_device_do_xfers(i3cdev, &xfer_sample, 1, I3C_SDR); 889 if (ret) 890 return ret; 891 *val = be32_to_cpu(st->buf.be32); 892 return 0; 893 } 894 895 static int ad4062_read_raw_dispatch(struct ad4062_state *st, 896 int *val, int *val2, long info) 897 { 898 if (st->wait_event) 899 return -EBUSY; 900 901 switch (info) { 902 case IIO_CHAN_INFO_RAW: 903 return ad4062_read_chan_raw(st, val); 904 905 case IIO_CHAN_INFO_CALIBSCALE: 906 return ad4062_get_chan_calibscale(st, val, val2); 907 908 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 909 return ad4062_get_oversampling_ratio(st, val); 910 911 default: 912 return -EINVAL; 913 } 914 } 915 916 static int ad4062_read_raw(struct iio_dev *indio_dev, 917 struct iio_chan_spec const *chan, 918 int *val, int *val2, long info) 919 { 920 struct ad4062_state *st = iio_priv(indio_dev); 921 int ret; 922 923 switch (info) { 924 case IIO_CHAN_INFO_SCALE: 925 return ad4062_get_chan_scale(indio_dev, val, val2); 926 927 case IIO_CHAN_INFO_SAMP_FREQ: 928 return ad4062_get_sampling_frequency(st, val); 929 } 930 931 if (!iio_device_claim_direct(indio_dev)) 932 return -EBUSY; 933 934 ret = ad4062_read_raw_dispatch(st, val, val2, info); 935 iio_device_release_direct(indio_dev); 936 return ret ?: IIO_VAL_INT; 937 } 938 939 static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int val2, 940 long info) 941 { 942 if (st->wait_event) 943 return -EBUSY; 944 945 switch (info) { 946 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 947 return ad4062_set_oversampling_ratio(st, val, val2); 948 949 case IIO_CHAN_INFO_CALIBSCALE: 950 return ad4062_set_chan_calibscale(st, val, val2); 951 952 default: 953 return -EINVAL; 954 } 955 } 956 957 static int ad4062_write_raw(struct iio_dev *indio_dev, 958 struct iio_chan_spec const *chan, int val, 959 int val2, long info) 960 { 961 struct ad4062_state *st = iio_priv(indio_dev); 962 int ret; 963 964 switch (info) { 965 case IIO_CHAN_INFO_SAMP_FREQ: 966 return ad4062_set_sampling_frequency(st, val, val2); 967 } 968 969 if (!iio_device_claim_direct(indio_dev)) 970 return -EBUSY; 971 972 ret = ad4062_write_raw_dispatch(st, val, val2, info); 973 iio_device_release_direct(indio_dev); 974 return ret; 975 } 976 977 static int pm_ad4062_monitor_mode_enable(struct ad4062_state *st) 978 { 979 int ret; 980 981 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 982 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 983 if (ret) 984 return ret; 985 986 return ad4062_set_operation_mode(st, AD4062_MONITOR_MODE); 987 } 988 989 static int ad4062_monitor_mode_enable(struct ad4062_state *st) 990 { 991 int ret; 992 993 ret = pm_ad4062_monitor_mode_enable(st); 994 if (ret) 995 return ret; 996 997 pm_runtime_get_noresume(&st->i3cdev->dev); 998 return 0; 999 } 1000 1001 static int ad4062_monitor_mode_disable(struct ad4062_state *st) 1002 { 1003 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1004 return 0; 1005 } 1006 1007 static int ad4062_read_event_config(struct iio_dev *indio_dev, 1008 const struct iio_chan_spec *chan, 1009 enum iio_event_type type, 1010 enum iio_event_direction dir) 1011 { 1012 struct ad4062_state *st = iio_priv(indio_dev); 1013 1014 return st->wait_event; 1015 } 1016 1017 static int ad4062_write_event_config_dispatch(struct iio_dev *indio_dev, 1018 bool state) 1019 { 1020 struct ad4062_state *st = iio_priv(indio_dev); 1021 int ret; 1022 1023 if (st->wait_event == state) 1024 ret = 0; 1025 else if (state) 1026 ret = ad4062_monitor_mode_enable(st); 1027 else 1028 ret = ad4062_monitor_mode_disable(st); 1029 if (ret) 1030 return ret; 1031 1032 st->wait_event = state; 1033 return 0; 1034 } 1035 1036 static int ad4062_write_event_config(struct iio_dev *indio_dev, 1037 const struct iio_chan_spec *chan, 1038 enum iio_event_type type, 1039 enum iio_event_direction dir, 1040 bool state) 1041 { 1042 int ret; 1043 1044 if (!iio_device_claim_direct(indio_dev)) 1045 return -EBUSY; 1046 1047 ret = ad4062_write_event_config_dispatch(indio_dev, state); 1048 iio_device_release_direct(indio_dev); 1049 return ret; 1050 } 1051 1052 static int __ad4062_read_event_info_value(struct ad4062_state *st, 1053 enum iio_event_direction dir, int *val) 1054 { 1055 int ret; 1056 u8 reg; 1057 1058 if (dir == IIO_EV_DIR_RISING) 1059 reg = AD4062_REG_MAX_LIMIT; 1060 else 1061 reg = AD4062_REG_MIN_LIMIT; 1062 1063 ret = regmap_bulk_read(st->regmap, reg, &st->buf.be16, 1064 sizeof(st->buf.be16)); 1065 if (ret) 1066 return ret; 1067 1068 *val = sign_extend32(be16_to_cpu(st->buf.be16), AD4062_LIMIT_BITS - 1); 1069 1070 return 0; 1071 } 1072 1073 static int __ad4062_read_event_info_hysteresis(struct ad4062_state *st, 1074 enum iio_event_direction dir, int *val) 1075 { 1076 u8 reg; 1077 1078 if (dir == IIO_EV_DIR_RISING) 1079 reg = AD4062_REG_MAX_HYST; 1080 else 1081 reg = AD4062_REG_MIN_HYST; 1082 return regmap_read(st->regmap, reg, val); 1083 } 1084 1085 static int ad4062_read_event_config_dispatch(struct iio_dev *indio_dev, 1086 enum iio_event_direction dir, 1087 enum iio_event_info info, int *val) 1088 { 1089 struct ad4062_state *st = iio_priv(indio_dev); 1090 1091 if (st->wait_event) 1092 return -EBUSY; 1093 1094 switch (info) { 1095 case IIO_EV_INFO_VALUE: 1096 return __ad4062_read_event_info_value(st, dir, val); 1097 case IIO_EV_INFO_HYSTERESIS: 1098 return __ad4062_read_event_info_hysteresis(st, dir, val); 1099 default: 1100 return -EINVAL; 1101 } 1102 } 1103 1104 static int ad4062_read_event_value(struct iio_dev *indio_dev, 1105 const struct iio_chan_spec *chan, 1106 enum iio_event_type type, 1107 enum iio_event_direction dir, 1108 enum iio_event_info info, int *val, 1109 int *val2) 1110 { 1111 int ret; 1112 1113 if (!iio_device_claim_direct(indio_dev)) 1114 return -EBUSY; 1115 1116 ret = ad4062_read_event_config_dispatch(indio_dev, dir, info, val); 1117 iio_device_release_direct(indio_dev); 1118 return ret ?: IIO_VAL_INT; 1119 } 1120 1121 static int __ad4062_write_event_info_value(struct ad4062_state *st, 1122 enum iio_event_direction dir, int val) 1123 { 1124 u8 reg; 1125 1126 if (val != sign_extend32(val, AD4062_LIMIT_BITS - 1)) 1127 return -EINVAL; 1128 if (dir == IIO_EV_DIR_RISING) 1129 reg = AD4062_REG_MAX_LIMIT; 1130 else 1131 reg = AD4062_REG_MIN_LIMIT; 1132 st->buf.be16 = cpu_to_be16(val); 1133 1134 return regmap_bulk_write(st->regmap, reg, &st->buf.be16, 1135 sizeof(st->buf.be16)); 1136 } 1137 1138 static int __ad4062_write_event_info_hysteresis(struct ad4062_state *st, 1139 enum iio_event_direction dir, int val) 1140 { 1141 u8 reg; 1142 1143 if (val > BIT(7) - 1) 1144 return -EINVAL; 1145 if (dir == IIO_EV_DIR_RISING) 1146 reg = AD4062_REG_MAX_HYST; 1147 else 1148 reg = AD4062_REG_MIN_HYST; 1149 1150 return regmap_write(st->regmap, reg, val); 1151 } 1152 1153 static int ad4062_write_event_value_dispatch(struct iio_dev *indio_dev, 1154 enum iio_event_type type, 1155 enum iio_event_direction dir, 1156 enum iio_event_info info, int val) 1157 { 1158 struct ad4062_state *st = iio_priv(indio_dev); 1159 1160 if (st->wait_event) 1161 return -EBUSY; 1162 1163 switch (type) { 1164 case IIO_EV_TYPE_THRESH: 1165 switch (info) { 1166 case IIO_EV_INFO_VALUE: 1167 return __ad4062_write_event_info_value(st, dir, val); 1168 case IIO_EV_INFO_HYSTERESIS: 1169 return __ad4062_write_event_info_hysteresis(st, dir, val); 1170 default: 1171 return -EINVAL; 1172 } 1173 default: 1174 return -EINVAL; 1175 } 1176 } 1177 1178 static int ad4062_write_event_value(struct iio_dev *indio_dev, 1179 const struct iio_chan_spec *chan, 1180 enum iio_event_type type, 1181 enum iio_event_direction dir, 1182 enum iio_event_info info, int val, 1183 int val2) 1184 { 1185 int ret; 1186 1187 if (!iio_device_claim_direct(indio_dev)) 1188 return -EBUSY; 1189 1190 ret = ad4062_write_event_value_dispatch(indio_dev, type, dir, info, val); 1191 iio_device_release_direct(indio_dev); 1192 return ret; 1193 } 1194 1195 /* 1196 * The AD4062 in burst averaging mode increases realbits from 16-bits to 1197 * 20-bits, increasing the storagebits from 16-bits to 32-bits. 1198 */ 1199 static inline int ad4062_sizeof_storagebits(struct ad4062_state *st) 1200 { 1201 const struct iio_scan_type *scan_type = 1202 iio_get_current_scan_type(st->indio_dev, st->chip->channels); 1203 1204 if (IS_ERR(scan_type)) 1205 return PTR_ERR(scan_type); 1206 1207 return BITS_TO_BYTES(scan_type->storagebits); 1208 } 1209 1210 /* Read registers only with realbits (no sign extension bytes) */ 1211 static inline size_t ad4062_get_conv_addr(struct ad4062_state *st, size_t _sizeof) 1212 { 1213 if (st->gpo_irq[1]) 1214 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_READ_32BITS : 1215 AD4062_REG_CONV_READ_16BITS; 1216 return _sizeof == sizeof(u32) ? AD4062_REG_CONV_TRIGGER_32BITS : 1217 AD4062_REG_CONV_TRIGGER_16BITS; 1218 } 1219 1220 static int pm_ad4062_triggered_buffer_postenable(struct ad4062_state *st) 1221 { 1222 int ret; 1223 1224 PM_RUNTIME_ACQUIRE(&st->i3cdev->dev, pm); 1225 ret = PM_RUNTIME_ACQUIRE_ERR(&pm); 1226 if (ret) 1227 return ret; 1228 1229 if (st->wait_event) 1230 return -EBUSY; 1231 1232 ret = ad4062_set_operation_mode(st, st->mode); 1233 if (ret) 1234 return ret; 1235 1236 ret = ad4062_sizeof_storagebits(st); 1237 if (ret < 0) 1238 return ret; 1239 1240 st->conv_sizeof = ret; 1241 1242 st->conv_addr = ad4062_get_conv_addr(st, st->conv_sizeof); 1243 /* CONV_READ requires read to trigger first sample. */ 1244 struct i3c_xfer xfer_sample[2] = { 1245 { 1246 .data.out = &st->conv_addr, 1247 .len = sizeof(st->conv_addr), 1248 .rnw = false, 1249 }, 1250 { 1251 .data.in = &st->buf.be32, 1252 .len = sizeof(st->buf.be32), 1253 .rnw = true, 1254 } 1255 }; 1256 1257 return i3c_device_do_xfers(st->i3cdev, xfer_sample, 1258 st->gpo_irq[1] ? 2 : 1, I3C_SDR); 1259 } 1260 1261 static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev) 1262 { 1263 struct ad4062_state *st = iio_priv(indio_dev); 1264 int ret; 1265 1266 ret = pm_ad4062_triggered_buffer_postenable(st); 1267 if (ret) 1268 return ret; 1269 1270 pm_runtime_get_noresume(&st->i3cdev->dev); 1271 return 0; 1272 } 1273 1274 static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev) 1275 { 1276 struct ad4062_state *st = iio_priv(indio_dev); 1277 1278 pm_runtime_put_autosuspend(&st->i3cdev->dev); 1279 return 0; 1280 } 1281 1282 static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops = { 1283 .postenable = &ad4062_triggered_buffer_postenable, 1284 .predisable = &ad4062_triggered_buffer_predisable, 1285 }; 1286 1287 static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1288 unsigned int writeval, unsigned int *readval) 1289 { 1290 struct ad4062_state *st = iio_priv(indio_dev); 1291 1292 if (readval) 1293 return regmap_read(st->regmap, reg, readval); 1294 else 1295 return regmap_write(st->regmap, reg, writeval); 1296 } 1297 1298 static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev, 1299 const struct iio_chan_spec *chan) 1300 { 1301 struct ad4062_state *st = iio_priv(indio_dev); 1302 1303 return st->mode == AD4062_BURST_AVERAGING_MODE ? 1304 AD4062_SCAN_TYPE_BURST_AVG : 1305 AD4062_SCAN_TYPE_SAMPLE; 1306 } 1307 1308 static const struct iio_info ad4062_info = { 1309 .read_raw = ad4062_read_raw, 1310 .write_raw = ad4062_write_raw, 1311 .read_avail = ad4062_read_avail, 1312 .read_event_config = ad4062_read_event_config, 1313 .write_event_config = ad4062_write_event_config, 1314 .read_event_value = ad4062_read_event_value, 1315 .write_event_value = ad4062_write_event_value, 1316 .event_attrs = &ad4062_event_attribute_group, 1317 .get_current_scan_type = ad4062_get_current_scan_type, 1318 .debugfs_reg_access = ad4062_debugfs_reg_access, 1319 }; 1320 1321 static const struct regmap_config ad4062_regmap_config = { 1322 .name = "ad4062", 1323 .reg_bits = 8, 1324 .val_bits = 8, 1325 .max_register = AD4062_MAX_REG, 1326 .rd_table = &ad4062_regmap_rd_table, 1327 .wr_table = &ad4062_regmap_wr_table, 1328 .can_sleep = true, 1329 }; 1330 1331 static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel) 1332 { 1333 struct device *dev = &st->i3cdev->dev; 1334 int ret; 1335 1336 ret = devm_regulator_get_enable(dev, "vio"); 1337 if (ret) 1338 return dev_err_probe(dev, ret, "Failed to enable vio voltage\n"); 1339 1340 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref"); 1341 *ref_sel = st->vref_uV == -ENODEV; 1342 if (st->vref_uV < 0 && !*ref_sel) 1343 return dev_err_probe(dev, st->vref_uV, 1344 "Failed to enable and read ref voltage\n"); 1345 1346 if (*ref_sel) { 1347 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "vdd"); 1348 if (st->vref_uV < 0) 1349 return dev_err_probe(dev, st->vref_uV, 1350 "Failed to enable and read vdd voltage\n"); 1351 } else { 1352 ret = devm_regulator_get_enable(dev, "vdd"); 1353 if (ret) 1354 return dev_err_probe(dev, ret, 1355 "Failed to enable vdd regulator\n"); 1356 } 1357 1358 return 0; 1359 } 1360 1361 static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1362 { 1363 return GPIO_LINE_DIRECTION_OUT; 1364 } 1365 1366 static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1367 { 1368 struct ad4062_state *st = gpiochip_get_data(gc); 1369 unsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW; 1370 1371 if (offset) 1372 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1373 AD4062_REG_GP_CONF_MODE_MSK_1, 1374 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val)); 1375 else 1376 return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1377 AD4062_REG_GP_CONF_MODE_MSK_0, 1378 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val)); 1379 } 1380 1381 static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset) 1382 { 1383 struct ad4062_state *st = gpiochip_get_data(gc); 1384 unsigned int reg_val; 1385 int ret; 1386 1387 ret = regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val); 1388 if (ret) 1389 return ret; 1390 1391 if (offset) 1392 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val); 1393 else 1394 reg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val); 1395 1396 return reg_val == AD4062_GP_STATIC_HIGH; 1397 } 1398 1399 static void ad4062_gpio_disable(void *data) 1400 { 1401 struct ad4062_state *st = data; 1402 u8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) | 1403 FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED); 1404 1405 regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1406 AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, 1407 val); 1408 } 1409 1410 static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc, 1411 unsigned long *valid_mask, 1412 unsigned int ngpios) 1413 { 1414 struct ad4062_state *st = gpiochip_get_data(gc); 1415 1416 bitmap_zero(valid_mask, ngpios); 1417 1418 for (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++) 1419 __assign_bit(i, valid_mask, !st->gpo_irq[i]); 1420 1421 return 0; 1422 } 1423 1424 static int ad4062_gpio_init(struct ad4062_state *st) 1425 { 1426 struct device *dev = &st->i3cdev->dev; 1427 struct gpio_chip *gc; 1428 u8 val, mask; 1429 int ret; 1430 1431 if (!device_property_read_bool(dev, "gpio-controller")) 1432 return 0; 1433 1434 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1435 if (!gc) 1436 return -ENOMEM; 1437 1438 val = 0; 1439 mask = 0; 1440 if (!st->gpo_irq[0]) { 1441 mask |= AD4062_REG_GP_CONF_MODE_MSK_0; 1442 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW); 1443 } 1444 if (!st->gpo_irq[1]) { 1445 mask |= AD4062_REG_GP_CONF_MODE_MSK_1; 1446 val |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW); 1447 } 1448 1449 ret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, 1450 mask, val); 1451 if (ret) 1452 return ret; 1453 1454 ret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st); 1455 if (ret) 1456 return ret; 1457 1458 gc->parent = dev; 1459 gc->label = st->chip->name; 1460 gc->owner = THIS_MODULE; 1461 gc->base = -1; 1462 gc->ngpio = 2; 1463 gc->init_valid_mask = ad4062_gpio_init_valid_mask; 1464 gc->get_direction = ad4062_gpio_get_direction; 1465 gc->set = ad4062_gpio_set; 1466 gc->get = ad4062_gpio_get; 1467 gc->can_sleep = true; 1468 1469 ret = devm_gpiochip_add_data(dev, gc, st); 1470 if (ret) 1471 return dev_err_probe(dev, ret, "Unable to register GPIO chip\n"); 1472 1473 return 0; 1474 } 1475 1476 static const struct i3c_device_id ad4062_id_table[] = { 1477 I3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info), 1478 I3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info), 1479 { } 1480 }; 1481 MODULE_DEVICE_TABLE(i3c, ad4062_id_table); 1482 1483 static int ad4062_probe(struct i3c_device *i3cdev) 1484 { 1485 const struct i3c_device_id *id = i3c_device_match_id(i3cdev, ad4062_id_table); 1486 const struct ad4062_chip_info *chip = id->data; 1487 struct device *dev = &i3cdev->dev; 1488 struct iio_dev *indio_dev; 1489 struct ad4062_state *st; 1490 bool ref_sel; 1491 int ret; 1492 1493 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1494 if (!indio_dev) 1495 return -ENOMEM; 1496 1497 st = iio_priv(indio_dev); 1498 st->i3cdev = i3cdev; 1499 i3cdev_set_drvdata(i3cdev, st); 1500 init_completion(&st->completion); 1501 1502 ret = ad4062_regulators_get(st, &ref_sel); 1503 if (ret) 1504 return ret; 1505 1506 st->regmap = devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config); 1507 if (IS_ERR(st->regmap)) 1508 return dev_err_probe(dev, PTR_ERR(st->regmap), 1509 "Failed to initialize regmap\n"); 1510 1511 st->mode = AD4062_SAMPLE_MODE; 1512 st->wait_event = false; 1513 st->chip = chip; 1514 st->sampling_frequency = 0; 1515 st->events_frequency = 0; 1516 st->oversamp_ratio = 0; 1517 st->indio_dev = indio_dev; 1518 1519 indio_dev->modes = INDIO_DIRECT_MODE; 1520 indio_dev->num_channels = 1; 1521 indio_dev->info = &ad4062_info; 1522 indio_dev->name = chip->name; 1523 indio_dev->channels = chip->channels; 1524 1525 ret = ad4062_soft_reset(st); 1526 if (ret) 1527 return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n"); 1528 1529 ret = ad4062_check_ids(st); 1530 if (ret) 1531 return ret; 1532 1533 ret = ad4062_setup(indio_dev, indio_dev->channels, &ref_sel); 1534 if (ret) 1535 return ret; 1536 1537 ret = ad4062_request_irq(indio_dev); 1538 if (ret) 1539 return ret; 1540 1541 ret = ad4062_request_trigger(indio_dev); 1542 if (ret) 1543 return ret; 1544 1545 ret = devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev, 1546 iio_pollfunc_store_time, 1547 ad4062_poll_handler, 1548 &ad4062_triggered_buffer_setup_ops); 1549 if (ret) 1550 return ret; 1551 1552 pm_runtime_set_active(dev); 1553 ret = devm_pm_runtime_enable(dev); 1554 if (ret) 1555 return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n"); 1556 1557 pm_runtime_set_autosuspend_delay(dev, 1000); 1558 pm_runtime_use_autosuspend(dev); 1559 1560 ret = ad4062_request_ibi(i3cdev); 1561 if (ret) 1562 return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); 1563 1564 ret = ad4062_gpio_init(st); 1565 if (ret) 1566 return ret; 1567 1568 ret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); 1569 if (ret) 1570 return ret; 1571 1572 return devm_iio_device_register(dev, indio_dev); 1573 } 1574 1575 static int ad4062_runtime_suspend(struct device *dev) 1576 { 1577 struct ad4062_state *st = dev_get_drvdata(dev); 1578 1579 return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG, 1580 FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK, 1581 AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE)); 1582 } 1583 1584 static int ad4062_runtime_resume(struct device *dev) 1585 { 1586 struct ad4062_state *st = dev_get_drvdata(dev); 1587 int ret; 1588 1589 ret = regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG, 1590 AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK); 1591 if (ret) 1592 return ret; 1593 1594 /* Wait device functional blocks to power up */ 1595 fsleep(3 * USEC_PER_MSEC); 1596 return 0; 1597 } 1598 1599 static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops, 1600 ad4062_runtime_suspend, ad4062_runtime_resume, NULL); 1601 1602 static struct i3c_driver ad4062_driver = { 1603 .driver = { 1604 .name = "ad4062", 1605 .pm = pm_ptr(&ad4062_pm_ops), 1606 }, 1607 .probe = ad4062_probe, 1608 .id_table = ad4062_id_table, 1609 }; 1610 module_i3c_driver(ad4062_driver); 1611 1612 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1613 MODULE_DESCRIPTION("Analog Devices AD4062"); 1614 MODULE_LICENSE("GPL"); 1615