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Searched defs:_offset (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/clk/bcm/
H A Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
195 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
211 #define HYST(_offset, _en_bit, _val_bit) \ argument
291 #define DIVIDER(_offset, _shift, _width) \ argument
301 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
342 #define SELECTOR(_offset, _shift, _width) \ argument
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/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Ditem.h270 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
288 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
313 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
331 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
356 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
410 #define MLXSW_ITEM32_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
435 #define MLXSW_ITEM64(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
453 #define MLXSW_ITEM64_INDEXED(_type, _cname, _iname, _offset, _shift, \ argument
478 #define MLXSW_ITEM_BUF(_type, _cname, _iname, _offset, _sizebytes) \ argument
502 #define MLXSW_ITEM_BUF_INDEXED(_type, _cname, _iname, _offset, _sizebytes, \ argument
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H A Dspectrum_acl.c532 #define MLXSW_SP_ACL_MANGLE_ACTION(_htype, _offset, _mask, _shift, _field) \ argument
541 #define MLXSW_SP_ACL_MANGLE_ACTION_IP4(_offset, _mask, _shift, _field) \ argument
545 #define MLXSW_SP_ACL_MANGLE_ACTION_IP6(_offset, _mask, _shift, _field) \ argument
549 #define MLXSW_SP_ACL_MANGLE_ACTION_TCP(_offset, _mask, _shift, _field) \ argument
552 #define MLXSW_SP_ACL_MANGLE_ACTION_UDP(_offset, _mask, _shift, _field) \ argument
H A Dspectrum_acl_flex_keys.c263 #define MLXSW_SP2_AFK_BLOCK_LAYOUT(_block, _offset, _shift) \ argument
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
146 #define MUX8(_name, _parents, _offset, \ argument
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
165 #define INT(_name, _parents, _offset, \ argument
172 #define INT_FLAGS(_name, _parents, _offset,\ argument
179 #define INT8(_name, _parents, _offset,\ argument
186 #define UART(_name, _parents, _offset,\ argument
193 #define UART8(_name, _parents, _offset,\ argument
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H A Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
71 #define AUDIO2X(_name, _num, _offset) \ argument
H A Dclk-tegra124.c97 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
103 #define NODIV(_name, _parents, _offset, \ argument
/linux/drivers/clk/
H A Dclk-loongson2.c59 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ argument
70 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ argument
84 #define CLK_SCALE(_id, _name, _pname, _offset, \ argument
96 #define CLK_SCALE_MODE(_id, _name, _pname, _offset, \ argument
109 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ argument
119 #define CLK_GATE_FLAGS(_id, _name, _pname, _offset, _bidx, \ argument
/linux/drivers/bcma/
H A Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/linux/drivers/clk/sprd/
H A Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
/linux/drivers/clk/sunxi-ng/
H A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
/linux/drivers/ssb/
H A Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c140 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ argument
147 #define CFG_GATE(_id, _offset, _bit_idx)\ argument
150 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ argument
290 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
352 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ argument
361 #define CFG_MUX(_id, _offset, _shift, _witdh)\ argument
364 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\ argument
471 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ argument
H A Dclk-stm32mp1.c1173 #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1200 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument
1217 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument
1221 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1314 #define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ argument
1347 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1360 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1701 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument
1714 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument
1718 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ argument
H A Dclk-stm32mp21.c165 #define MUX_CFG(id, _offset, _shift, _width) \ argument
278 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ argument
1441 #define RESET_MP21(id, _offset, _bit_idx, _set_clr) \ argument
H A Dclk-stm32mp25.c199 #define MUX_CFG(id, _offset, _shift, _witdh) \ argument
342 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ argument
1829 #define RESET_MP25(id, _offset, _bit_idx, _set_clr) \ argument
/linux/tools/testing/selftests/vfio/lib/include/libvfio/
H A Dvfio_pci_device.h49 vfio_pci_config_read(_device,_offset,_type) global() argument
59 vfio_pci_config_write(_device,_offset,_value,_type) global() argument
/linux/drivers/clk/st/
H A Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
/linux/drivers/pinctrl/berlin/
H A Dberlin.h31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c166 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
205 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
299 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
/linux/drivers/clk/renesas/
H A Dr8a779a0-cpg-mssr.c61 #define DEF_PLL(_name, _id, _offset) \ argument
/linux/drivers/clk/keystone/
H A Dsyscon-clk.c171 #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx) \ argument
/linux/net/rxrpc/
H A Drecvmsg.c282 rxrpc_recvmsg_data(struct socket * sock,struct rxrpc_call * call,struct msghdr * msg,struct iov_iter * iter,size_t len,int flags,size_t * _offset) rxrpc_recvmsg_data() argument
/linux/include/linux/cdx/
H A Dmcdi.h185 #define _MCDI_PTR(_buf, _offset) \ argument

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