xref: /linux/drivers/gpu/drm/i915/display/intel_display_power_map.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "i915_reg.h"
7 #include "intel_display_core.h"
8 #include "intel_display_power_map.h"
9 #include "intel_display_power_well.h"
10 #include "intel_display_types.h"
11 #include "vlv_sideband_reg.h"
12 
13 #define __LIST_INLINE_ELEMS(__elem_type, ...) \
14 	((__elem_type[]) { __VA_ARGS__ })
15 
16 #define __LIST(__elems) { \
17 	.list = __elems, \
18 	.count = ARRAY_SIZE(__elems), \
19 }
20 
21 #define I915_PW_DOMAINS(...) \
22 	(const struct i915_power_domain_list) \
23 		__LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__))
24 
25 #define I915_DECL_PW_DOMAINS(__name, ...) \
26 	static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
27 
28 /* Zero-length list assigns all power domains, a NULL list assigns none. */
29 #define I915_PW_DOMAINS_NONE	NULL
30 #define I915_PW_DOMAINS_ALL	/* zero-length list */
31 
32 #define I915_PW_INSTANCES(...) \
33 	(const struct i915_power_well_instance_list) \
34 		__LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__))
35 
36 #define I915_PW(_name, _domain_list, ...) \
37 	{ .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
38 
39 
40 struct i915_power_well_desc_list {
41 	const struct i915_power_well_desc *list;
42 	u8 count;
43 };
44 
45 #define I915_PW_DESCRIPTORS(x) __LIST(x)
46 
47 
48 I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
49 
50 static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
51 	{
52 		.instances = &I915_PW_INSTANCES(
53 			I915_PW("always-on", &i9xx_pwdoms_always_on),
54 		),
55 		.ops = &i9xx_always_on_power_well_ops,
56 		.always_on = true,
57 	},
58 };
59 
60 static const struct i915_power_well_desc_list i9xx_power_wells[] = {
61 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
62 };
63 
64 I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
65 	POWER_DOMAIN_PIPE_A,
66 	POWER_DOMAIN_PIPE_B,
67 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
68 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
69 	POWER_DOMAIN_TRANSCODER_A,
70 	POWER_DOMAIN_TRANSCODER_B,
71 	POWER_DOMAIN_INIT);
72 
73 static const struct i915_power_well_desc i830_power_wells_main[] = {
74 	{
75 		.instances = &I915_PW_INSTANCES(
76 			I915_PW("pipes", &i830_pwdoms_pipes),
77 		),
78 		.ops = &i830_pipes_power_well_ops,
79 	},
80 };
81 
82 static const struct i915_power_well_desc_list i830_power_wells[] = {
83 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
84 	I915_PW_DESCRIPTORS(i830_power_wells_main),
85 };
86 
87 I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
88 	POWER_DOMAIN_PIPE_B,
89 	POWER_DOMAIN_PIPE_C,
90 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
91 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
92 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
93 	POWER_DOMAIN_TRANSCODER_A,
94 	POWER_DOMAIN_TRANSCODER_B,
95 	POWER_DOMAIN_TRANSCODER_C,
96 	POWER_DOMAIN_PORT_DDI_LANES_B,
97 	POWER_DOMAIN_PORT_DDI_LANES_C,
98 	POWER_DOMAIN_PORT_DDI_LANES_D,
99 	POWER_DOMAIN_PORT_CRT, /* DDI E */
100 	POWER_DOMAIN_VGA,
101 	POWER_DOMAIN_AUDIO_MMIO,
102 	POWER_DOMAIN_AUDIO_PLAYBACK,
103 	POWER_DOMAIN_INIT);
104 
105 static const struct i915_power_well_desc hsw_power_wells_main[] = {
106 	{
107 		.instances = &I915_PW_INSTANCES(
108 			I915_PW("display", &hsw_pwdoms_display,
109 				.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
110 				.id = HSW_DISP_PW_GLOBAL),
111 		),
112 		.ops = &hsw_power_well_ops,
113 		.has_vga = true,
114 	},
115 };
116 
117 static const struct i915_power_well_desc_list hsw_power_wells[] = {
118 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
119 	I915_PW_DESCRIPTORS(hsw_power_wells_main),
120 };
121 
122 I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
123 	POWER_DOMAIN_PIPE_B,
124 	POWER_DOMAIN_PIPE_C,
125 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
126 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
127 	POWER_DOMAIN_TRANSCODER_A,
128 	POWER_DOMAIN_TRANSCODER_B,
129 	POWER_DOMAIN_TRANSCODER_C,
130 	POWER_DOMAIN_PORT_DDI_LANES_B,
131 	POWER_DOMAIN_PORT_DDI_LANES_C,
132 	POWER_DOMAIN_PORT_DDI_LANES_D,
133 	POWER_DOMAIN_PORT_CRT, /* DDI E */
134 	POWER_DOMAIN_VGA,
135 	POWER_DOMAIN_AUDIO_MMIO,
136 	POWER_DOMAIN_AUDIO_PLAYBACK,
137 	POWER_DOMAIN_INIT);
138 
139 static const struct i915_power_well_desc bdw_power_wells_main[] = {
140 	{
141 		.instances = &I915_PW_INSTANCES(
142 			I915_PW("display", &bdw_pwdoms_display,
143 				.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
144 				.id = HSW_DISP_PW_GLOBAL),
145 		),
146 		.ops = &hsw_power_well_ops,
147 		.has_vga = true,
148 		.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
149 	},
150 };
151 
152 static const struct i915_power_well_desc_list bdw_power_wells[] = {
153 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
154 	I915_PW_DESCRIPTORS(bdw_power_wells_main),
155 };
156 
157 I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
158 	POWER_DOMAIN_DISPLAY_CORE,
159 	POWER_DOMAIN_PIPE_A,
160 	POWER_DOMAIN_PIPE_B,
161 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
162 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
163 	POWER_DOMAIN_TRANSCODER_A,
164 	POWER_DOMAIN_TRANSCODER_B,
165 	POWER_DOMAIN_PORT_DDI_LANES_B,
166 	POWER_DOMAIN_PORT_DDI_LANES_C,
167 	POWER_DOMAIN_PORT_DSI,
168 	POWER_DOMAIN_PORT_CRT,
169 	POWER_DOMAIN_VGA,
170 	POWER_DOMAIN_AUDIO_MMIO,
171 	POWER_DOMAIN_AUDIO_PLAYBACK,
172 	POWER_DOMAIN_AUX_IO_B,
173 	POWER_DOMAIN_AUX_IO_C,
174 	POWER_DOMAIN_AUX_B,
175 	POWER_DOMAIN_AUX_C,
176 	POWER_DOMAIN_GMBUS,
177 	POWER_DOMAIN_INIT);
178 
179 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
180 	POWER_DOMAIN_PORT_DDI_LANES_B,
181 	POWER_DOMAIN_PORT_DDI_LANES_C,
182 	POWER_DOMAIN_PORT_CRT,
183 	POWER_DOMAIN_AUX_IO_B,
184 	POWER_DOMAIN_AUX_IO_C,
185 	POWER_DOMAIN_AUX_B,
186 	POWER_DOMAIN_AUX_C,
187 	POWER_DOMAIN_INIT);
188 
189 I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
190 	POWER_DOMAIN_PORT_DDI_LANES_B,
191 	POWER_DOMAIN_PORT_DDI_LANES_C,
192 	POWER_DOMAIN_AUX_IO_B,
193 	POWER_DOMAIN_AUX_IO_C,
194 	POWER_DOMAIN_AUX_B,
195 	POWER_DOMAIN_AUX_C,
196 	POWER_DOMAIN_INIT);
197 
198 static const struct i915_power_well_desc vlv_power_wells_main[] = {
199 	{
200 		.instances = &I915_PW_INSTANCES(
201 			I915_PW("display", &vlv_pwdoms_display,
202 				.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
203 				.id = VLV_DISP_PW_DISP2D),
204 		),
205 		.ops = &vlv_display_power_well_ops,
206 	}, {
207 		.instances = &I915_PW_INSTANCES(
208 			I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes,
209 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
210 			I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes,
211 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
212 			I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes,
213 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
214 			I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes,
215 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
216 		),
217 		.ops = &vlv_dpio_power_well_ops,
218 	}, {
219 		.instances = &I915_PW_INSTANCES(
220 			I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc,
221 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
222 				.id = VLV_DISP_PW_DPIO_CMN_BC),
223 		),
224 		.ops = &vlv_dpio_cmn_power_well_ops,
225 	},
226 };
227 
228 static const struct i915_power_well_desc_list vlv_power_wells[] = {
229 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
230 	I915_PW_DESCRIPTORS(vlv_power_wells_main),
231 };
232 
233 I915_DECL_PW_DOMAINS(chv_pwdoms_display,
234 	POWER_DOMAIN_DISPLAY_CORE,
235 	POWER_DOMAIN_PIPE_A,
236 	POWER_DOMAIN_PIPE_B,
237 	POWER_DOMAIN_PIPE_C,
238 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
239 	POWER_DOMAIN_PIPE_PANEL_FITTER_B,
240 	POWER_DOMAIN_PIPE_PANEL_FITTER_C,
241 	POWER_DOMAIN_TRANSCODER_A,
242 	POWER_DOMAIN_TRANSCODER_B,
243 	POWER_DOMAIN_TRANSCODER_C,
244 	POWER_DOMAIN_PORT_DDI_LANES_B,
245 	POWER_DOMAIN_PORT_DDI_LANES_C,
246 	POWER_DOMAIN_PORT_DDI_LANES_D,
247 	POWER_DOMAIN_PORT_DSI,
248 	POWER_DOMAIN_VGA,
249 	POWER_DOMAIN_AUDIO_MMIO,
250 	POWER_DOMAIN_AUDIO_PLAYBACK,
251 	POWER_DOMAIN_AUX_IO_B,
252 	POWER_DOMAIN_AUX_IO_C,
253 	POWER_DOMAIN_AUX_IO_D,
254 	POWER_DOMAIN_AUX_B,
255 	POWER_DOMAIN_AUX_C,
256 	POWER_DOMAIN_AUX_D,
257 	POWER_DOMAIN_GMBUS,
258 	POWER_DOMAIN_INIT);
259 
260 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
261 	POWER_DOMAIN_PORT_DDI_LANES_B,
262 	POWER_DOMAIN_PORT_DDI_LANES_C,
263 	POWER_DOMAIN_AUX_IO_B,
264 	POWER_DOMAIN_AUX_IO_C,
265 	POWER_DOMAIN_AUX_B,
266 	POWER_DOMAIN_AUX_C,
267 	POWER_DOMAIN_INIT);
268 
269 I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
270 	POWER_DOMAIN_PORT_DDI_LANES_D,
271 	POWER_DOMAIN_AUX_IO_D,
272 	POWER_DOMAIN_AUX_D,
273 	POWER_DOMAIN_INIT);
274 
275 static const struct i915_power_well_desc chv_power_wells_main[] = {
276 	{
277 		/*
278 		 * Pipe A power well is the new disp2d well. Pipe B and C
279 		 * power wells don't actually exist. Pipe A power well is
280 		 * required for any pipe to work.
281 		 */
282 		.instances = &I915_PW_INSTANCES(
283 			I915_PW("display", &chv_pwdoms_display),
284 		),
285 		.ops = &chv_pipe_power_well_ops,
286 	}, {
287 		.instances = &I915_PW_INSTANCES(
288 			I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc,
289 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
290 				.id = VLV_DISP_PW_DPIO_CMN_BC),
291 			I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d,
292 				.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
293 				.id = CHV_DISP_PW_DPIO_CMN_D),
294 		),
295 		.ops = &chv_dpio_cmn_power_well_ops,
296 	},
297 };
298 
299 static const struct i915_power_well_desc_list chv_power_wells[] = {
300 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
301 	I915_PW_DESCRIPTORS(chv_power_wells_main),
302 };
303 
304 #define SKL_PW_2_POWER_DOMAINS \
305 	POWER_DOMAIN_PIPE_B, \
306 	POWER_DOMAIN_PIPE_C, \
307 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
308 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
309 	POWER_DOMAIN_TRANSCODER_A, \
310 	POWER_DOMAIN_TRANSCODER_B, \
311 	POWER_DOMAIN_TRANSCODER_C, \
312 	POWER_DOMAIN_PORT_DDI_LANES_B, \
313 	POWER_DOMAIN_PORT_DDI_LANES_C, \
314 	POWER_DOMAIN_PORT_DDI_LANES_D, \
315 	POWER_DOMAIN_PORT_DDI_LANES_E, \
316 	POWER_DOMAIN_VGA, \
317 	POWER_DOMAIN_AUDIO_MMIO, \
318 	POWER_DOMAIN_AUDIO_PLAYBACK, \
319 	POWER_DOMAIN_AUX_IO_B, \
320 	POWER_DOMAIN_AUX_IO_C, \
321 	POWER_DOMAIN_AUX_IO_D, \
322 	POWER_DOMAIN_AUX_B, \
323 	POWER_DOMAIN_AUX_C, \
324 	POWER_DOMAIN_AUX_D
325 
326 I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
327 	SKL_PW_2_POWER_DOMAINS,
328 	POWER_DOMAIN_INIT);
329 
330 I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
331 	SKL_PW_2_POWER_DOMAINS,
332 	POWER_DOMAIN_AUX_A,
333 	POWER_DOMAIN_GT_IRQ,
334 	POWER_DOMAIN_DC_OFF,
335 	POWER_DOMAIN_INIT);
336 
337 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
338 	POWER_DOMAIN_PORT_DDI_IO_A,
339 	POWER_DOMAIN_PORT_DDI_IO_E,
340 	POWER_DOMAIN_INIT);
341 
342 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
343 	POWER_DOMAIN_PORT_DDI_IO_B,
344 	POWER_DOMAIN_INIT);
345 
346 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
347 	POWER_DOMAIN_PORT_DDI_IO_C,
348 	POWER_DOMAIN_INIT);
349 
350 I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
351 	POWER_DOMAIN_PORT_DDI_IO_D,
352 	POWER_DOMAIN_INIT);
353 
354 static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
355 	{
356 		/* Handled by the DMC firmware */
357 		.instances = &I915_PW_INSTANCES(
358 			I915_PW("PW_1", I915_PW_DOMAINS_NONE,
359 				.hsw.idx = SKL_PW_CTL_IDX_PW_1,
360 				.id = SKL_DISP_PW_1),
361 		),
362 		.ops = &hsw_power_well_ops,
363 		.always_on = true,
364 		.has_fuses = true,
365 	},
366 };
367 
368 static const struct i915_power_well_desc skl_power_wells_main[] = {
369 	{
370 		/* Handled by the DMC firmware */
371 		.instances = &I915_PW_INSTANCES(
372 			I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
373 				.hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
374 				.id = SKL_DISP_PW_MISC_IO),
375 		),
376 		.ops = &hsw_power_well_ops,
377 		.always_on = true,
378 	}, {
379 		.instances = &I915_PW_INSTANCES(
380 			I915_PW("DC_off", &skl_pwdoms_dc_off,
381 				.id = SKL_DISP_DC_OFF),
382 		),
383 		.ops = &gen9_dc_off_power_well_ops,
384 	}, {
385 		.instances = &I915_PW_INSTANCES(
386 			I915_PW("PW_2", &skl_pwdoms_pw_2,
387 				.hsw.idx = SKL_PW_CTL_IDX_PW_2,
388 				.id = SKL_DISP_PW_2),
389 		),
390 		.ops = &hsw_power_well_ops,
391 		.has_vga = true,
392 		.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
393 		.has_fuses = true,
394 	}, {
395 		.instances = &I915_PW_INSTANCES(
396 			I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
397 			I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
398 			I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
399 			I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
400 		),
401 		.ops = &hsw_power_well_ops,
402 	},
403 };
404 
405 static const struct i915_power_well_desc_list skl_power_wells[] = {
406 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
407 	I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
408 	I915_PW_DESCRIPTORS(skl_power_wells_main),
409 };
410 
411 #define BXT_PW_2_POWER_DOMAINS \
412 	POWER_DOMAIN_PIPE_B, \
413 	POWER_DOMAIN_PIPE_C, \
414 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
415 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
416 	POWER_DOMAIN_TRANSCODER_A, \
417 	POWER_DOMAIN_TRANSCODER_B, \
418 	POWER_DOMAIN_TRANSCODER_C, \
419 	POWER_DOMAIN_PORT_DDI_LANES_B, \
420 	POWER_DOMAIN_PORT_DDI_LANES_C, \
421 	POWER_DOMAIN_VGA, \
422 	POWER_DOMAIN_AUDIO_MMIO, \
423 	POWER_DOMAIN_AUDIO_PLAYBACK, \
424 	POWER_DOMAIN_AUX_IO_B, \
425 	POWER_DOMAIN_AUX_IO_C, \
426 	POWER_DOMAIN_AUX_B, \
427 	POWER_DOMAIN_AUX_C
428 
429 I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
430 	BXT_PW_2_POWER_DOMAINS,
431 	POWER_DOMAIN_INIT);
432 
433 I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
434 	BXT_PW_2_POWER_DOMAINS,
435 	POWER_DOMAIN_AUX_A,
436 	POWER_DOMAIN_GMBUS,
437 	POWER_DOMAIN_GT_IRQ,
438 	POWER_DOMAIN_DC_OFF,
439 	POWER_DOMAIN_INIT);
440 
441 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
442 	POWER_DOMAIN_PORT_DDI_LANES_A,
443 	POWER_DOMAIN_AUX_IO_A,
444 	POWER_DOMAIN_AUX_A,
445 	POWER_DOMAIN_INIT);
446 
447 I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
448 	POWER_DOMAIN_PORT_DDI_LANES_B,
449 	POWER_DOMAIN_PORT_DDI_LANES_C,
450 	POWER_DOMAIN_AUX_IO_B,
451 	POWER_DOMAIN_AUX_IO_C,
452 	POWER_DOMAIN_AUX_B,
453 	POWER_DOMAIN_AUX_C,
454 	POWER_DOMAIN_INIT);
455 
456 static const struct i915_power_well_desc bxt_power_wells_main[] = {
457 	{
458 		.instances = &I915_PW_INSTANCES(
459 			I915_PW("DC_off", &bxt_pwdoms_dc_off,
460 				.id = SKL_DISP_DC_OFF),
461 		),
462 		.ops = &gen9_dc_off_power_well_ops,
463 	}, {
464 		.instances = &I915_PW_INSTANCES(
465 			I915_PW("PW_2", &bxt_pwdoms_pw_2,
466 				.hsw.idx = SKL_PW_CTL_IDX_PW_2,
467 				.id = SKL_DISP_PW_2),
468 		),
469 		.ops = &hsw_power_well_ops,
470 		.has_vga = true,
471 		.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
472 		.has_fuses = true,
473 	}, {
474 		.instances = &I915_PW_INSTANCES(
475 			I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a,
476 				.bxt.phy = DPIO_PHY1,
477 				.id = BXT_DISP_PW_DPIO_CMN_A),
478 			I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc,
479 				.bxt.phy = DPIO_PHY0,
480 				.id = VLV_DISP_PW_DPIO_CMN_BC),
481 		),
482 		.ops = &bxt_dpio_cmn_power_well_ops,
483 	},
484 };
485 
486 static const struct i915_power_well_desc_list bxt_power_wells[] = {
487 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
488 	I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
489 	I915_PW_DESCRIPTORS(bxt_power_wells_main),
490 };
491 
492 #define GLK_PW_2_POWER_DOMAINS \
493 	POWER_DOMAIN_PIPE_B, \
494 	POWER_DOMAIN_PIPE_C, \
495 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
496 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
497 	POWER_DOMAIN_TRANSCODER_A, \
498 	POWER_DOMAIN_TRANSCODER_B, \
499 	POWER_DOMAIN_TRANSCODER_C, \
500 	POWER_DOMAIN_PORT_DDI_LANES_B, \
501 	POWER_DOMAIN_PORT_DDI_LANES_C, \
502 	POWER_DOMAIN_VGA, \
503 	POWER_DOMAIN_AUDIO_MMIO, \
504 	POWER_DOMAIN_AUDIO_PLAYBACK, \
505 	POWER_DOMAIN_AUX_IO_B, \
506 	POWER_DOMAIN_AUX_IO_C, \
507 	POWER_DOMAIN_AUX_B, \
508 	POWER_DOMAIN_AUX_C
509 
510 I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
511 	GLK_PW_2_POWER_DOMAINS,
512 	POWER_DOMAIN_INIT);
513 
514 I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
515 	GLK_PW_2_POWER_DOMAINS,
516 	POWER_DOMAIN_AUX_A,
517 	POWER_DOMAIN_GMBUS,
518 	POWER_DOMAIN_GT_IRQ,
519 	POWER_DOMAIN_DC_OFF,
520 	POWER_DOMAIN_INIT);
521 
522 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a,	POWER_DOMAIN_PORT_DDI_IO_A);
523 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b,	POWER_DOMAIN_PORT_DDI_IO_B);
524 I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c,	POWER_DOMAIN_PORT_DDI_IO_C);
525 
526 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
527 	POWER_DOMAIN_PORT_DDI_LANES_A,
528 	POWER_DOMAIN_AUX_IO_A,
529 	POWER_DOMAIN_AUX_A,
530 	POWER_DOMAIN_INIT);
531 
532 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
533 	POWER_DOMAIN_PORT_DDI_LANES_B,
534 	POWER_DOMAIN_AUX_IO_B,
535 	POWER_DOMAIN_AUX_B,
536 	POWER_DOMAIN_INIT);
537 
538 I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
539 	POWER_DOMAIN_PORT_DDI_LANES_C,
540 	POWER_DOMAIN_AUX_IO_C,
541 	POWER_DOMAIN_AUX_C,
542 	POWER_DOMAIN_INIT);
543 
544 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
545 	POWER_DOMAIN_AUX_IO_A,
546 	POWER_DOMAIN_AUX_A,
547 	POWER_DOMAIN_INIT);
548 
549 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
550 	POWER_DOMAIN_AUX_IO_B,
551 	POWER_DOMAIN_AUX_B,
552 	POWER_DOMAIN_INIT);
553 
554 I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
555 	POWER_DOMAIN_AUX_IO_C,
556 	POWER_DOMAIN_AUX_C,
557 	POWER_DOMAIN_INIT);
558 
559 static const struct i915_power_well_desc glk_power_wells_main[] = {
560 	{
561 		.instances = &I915_PW_INSTANCES(
562 			I915_PW("DC_off", &glk_pwdoms_dc_off,
563 				.id = SKL_DISP_DC_OFF),
564 		),
565 		.ops = &gen9_dc_off_power_well_ops,
566 	}, {
567 		.instances = &I915_PW_INSTANCES(
568 			I915_PW("PW_2", &glk_pwdoms_pw_2,
569 				.hsw.idx = SKL_PW_CTL_IDX_PW_2,
570 				.id = SKL_DISP_PW_2),
571 		),
572 		.ops = &hsw_power_well_ops,
573 		.has_vga = true,
574 		.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
575 		.has_fuses = true,
576 	}, {
577 		.instances = &I915_PW_INSTANCES(
578 			I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a,
579 				.bxt.phy = DPIO_PHY1,
580 				.id = BXT_DISP_PW_DPIO_CMN_A),
581 			I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b,
582 				.bxt.phy = DPIO_PHY0,
583 				.id = VLV_DISP_PW_DPIO_CMN_BC),
584 			I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c,
585 				.bxt.phy = DPIO_PHY2,
586 				.id = GLK_DISP_PW_DPIO_CMN_C),
587 		),
588 		.ops = &bxt_dpio_cmn_power_well_ops,
589 	}, {
590 		.instances = &I915_PW_INSTANCES(
591 			I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A),
592 			I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B),
593 			I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C),
594 			I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A),
595 			I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
596 			I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
597 		),
598 		.ops = &hsw_power_well_ops,
599 	},
600 };
601 
602 static const struct i915_power_well_desc_list glk_power_wells[] = {
603 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
604 	I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
605 	I915_PW_DESCRIPTORS(glk_power_wells_main),
606 };
607 
608 /*
609  * ICL PW_0/PG_0 domains (HW/DMC control):
610  * - PCI
611  * - clocks except port PLL
612  * - central power except FBC
613  * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
614  * ICL PW_1/PG_1 domains (HW/DMC control):
615  * - DBUF function
616  * - PIPE_A and its planes, except VGA
617  * - transcoder EDP + PSR
618  * - transcoder DSI
619  * - DDI_A
620  * - FBC
621  */
622 #define ICL_PW_4_POWER_DOMAINS \
623 	POWER_DOMAIN_PIPE_C, \
624 	POWER_DOMAIN_PIPE_PANEL_FITTER_C
625 
626 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
627 	ICL_PW_4_POWER_DOMAINS,
628 	POWER_DOMAIN_INIT);
629 	/* VDSC/joining */
630 
631 #define ICL_PW_3_POWER_DOMAINS \
632 	ICL_PW_4_POWER_DOMAINS, \
633 	POWER_DOMAIN_PIPE_B, \
634 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
635 	POWER_DOMAIN_TRANSCODER_A, \
636 	POWER_DOMAIN_TRANSCODER_B, \
637 	POWER_DOMAIN_TRANSCODER_C, \
638 	POWER_DOMAIN_PORT_DDI_LANES_B, \
639 	POWER_DOMAIN_PORT_DDI_LANES_C, \
640 	POWER_DOMAIN_PORT_DDI_LANES_D, \
641 	POWER_DOMAIN_PORT_DDI_LANES_E, \
642 	POWER_DOMAIN_PORT_DDI_LANES_F, \
643 	POWER_DOMAIN_VGA, \
644 	POWER_DOMAIN_AUDIO_MMIO, \
645 	POWER_DOMAIN_AUDIO_PLAYBACK, \
646 	POWER_DOMAIN_AUX_IO_B, \
647 	POWER_DOMAIN_AUX_IO_C, \
648 	POWER_DOMAIN_AUX_IO_D, \
649 	POWER_DOMAIN_AUX_IO_E, \
650 	POWER_DOMAIN_AUX_IO_F, \
651 	POWER_DOMAIN_AUX_B, \
652 	POWER_DOMAIN_AUX_C, \
653 	POWER_DOMAIN_AUX_D, \
654 	POWER_DOMAIN_AUX_E, \
655 	POWER_DOMAIN_AUX_F, \
656 	POWER_DOMAIN_AUX_TBT1, \
657 	POWER_DOMAIN_AUX_TBT2, \
658 	POWER_DOMAIN_AUX_TBT3, \
659 	POWER_DOMAIN_AUX_TBT4
660 
661 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
662 	ICL_PW_3_POWER_DOMAINS,
663 	POWER_DOMAIN_INIT);
664 	/*
665 	 * - transcoder WD
666 	 * - KVMR (HW control)
667 	 */
668 
669 #define ICL_PW_2_POWER_DOMAINS \
670 	ICL_PW_3_POWER_DOMAINS, \
671 	POWER_DOMAIN_TRANSCODER_VDSC_PW2
672 
673 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
674 	ICL_PW_2_POWER_DOMAINS,
675 	POWER_DOMAIN_INIT);
676 	/*
677 	 * - KVMR (HW control)
678 	 */
679 
680 I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
681 	ICL_PW_2_POWER_DOMAINS,
682 	POWER_DOMAIN_AUX_A,
683 	POWER_DOMAIN_DC_OFF,
684 	POWER_DOMAIN_INIT);
685 
686 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d,	POWER_DOMAIN_PORT_DDI_IO_D);
687 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e,	POWER_DOMAIN_PORT_DDI_IO_E);
688 I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f,	POWER_DOMAIN_PORT_DDI_IO_F);
689 
690 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
691 	POWER_DOMAIN_AUX_IO_A,
692 	POWER_DOMAIN_AUX_A);
693 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b,
694 	POWER_DOMAIN_AUX_IO_B,
695 	POWER_DOMAIN_AUX_B);
696 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c,
697 	POWER_DOMAIN_AUX_IO_C,
698 	POWER_DOMAIN_AUX_C);
699 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d,
700 	POWER_DOMAIN_AUX_IO_D,
701 	POWER_DOMAIN_AUX_D);
702 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e,
703 	POWER_DOMAIN_AUX_IO_E,
704 	POWER_DOMAIN_AUX_E);
705 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f,
706 	POWER_DOMAIN_AUX_IO_F,
707 	POWER_DOMAIN_AUX_F);
708 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1,	POWER_DOMAIN_AUX_TBT1);
709 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2,	POWER_DOMAIN_AUX_TBT2);
710 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3,	POWER_DOMAIN_AUX_TBT3);
711 I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4,	POWER_DOMAIN_AUX_TBT4);
712 
713 static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
714 	{
715 		/* Handled by the DMC firmware */
716 		.instances = &I915_PW_INSTANCES(
717 			I915_PW("PW_1", I915_PW_DOMAINS_NONE,
718 				.hsw.idx = ICL_PW_CTL_IDX_PW_1,
719 				.id = SKL_DISP_PW_1),
720 		),
721 		.ops = &hsw_power_well_ops,
722 		.always_on = true,
723 		.has_fuses = true,
724 	},
725 };
726 
727 static const struct i915_power_well_desc icl_power_wells_main[] = {
728 	{
729 		.instances = &I915_PW_INSTANCES(
730 			I915_PW("DC_off", &icl_pwdoms_dc_off,
731 				.id = SKL_DISP_DC_OFF),
732 		),
733 		.ops = &gen9_dc_off_power_well_ops,
734 	}, {
735 		.instances = &I915_PW_INSTANCES(
736 			I915_PW("PW_2", &icl_pwdoms_pw_2,
737 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
738 				.id = SKL_DISP_PW_2),
739 		),
740 		.ops = &hsw_power_well_ops,
741 		.has_fuses = true,
742 	}, {
743 		.instances = &I915_PW_INSTANCES(
744 			I915_PW("PW_3", &icl_pwdoms_pw_3,
745 				.hsw.idx = ICL_PW_CTL_IDX_PW_3,
746 				.id = ICL_DISP_PW_3),
747 		),
748 		.ops = &hsw_power_well_ops,
749 		.has_vga = true,
750 		.irq_pipe_mask = BIT(PIPE_B),
751 		.has_fuses = true,
752 	}, {
753 		.instances = &I915_PW_INSTANCES(
754 			I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
755 			I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
756 			I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
757 			I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
758 			I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
759 			I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
760 		),
761 		.ops = &icl_ddi_power_well_ops,
762 	}, {
763 		.instances = &I915_PW_INSTANCES(
764 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
765 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
766 			I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
767 			I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D),
768 			I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E),
769 			I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F),
770 		),
771 		.ops = &icl_aux_power_well_ops,
772 	}, {
773 		.instances = &I915_PW_INSTANCES(
774 			I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1),
775 			I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2),
776 			I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3),
777 			I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4),
778 		),
779 		.ops = &icl_aux_power_well_ops,
780 		.is_tc_tbt = true,
781 	}, {
782 		.instances = &I915_PW_INSTANCES(
783 			I915_PW("PW_4", &icl_pwdoms_pw_4,
784 				.hsw.idx = ICL_PW_CTL_IDX_PW_4),
785 		),
786 		.ops = &hsw_power_well_ops,
787 		.irq_pipe_mask = BIT(PIPE_C),
788 		.has_fuses = true,
789 	},
790 };
791 
792 static const struct i915_power_well_desc_list icl_power_wells[] = {
793 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
794 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
795 	I915_PW_DESCRIPTORS(icl_power_wells_main),
796 };
797 
798 #define TGL_PW_5_POWER_DOMAINS \
799 	POWER_DOMAIN_PIPE_D, \
800 	POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
801 	POWER_DOMAIN_TRANSCODER_D
802 
803 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
804 	TGL_PW_5_POWER_DOMAINS,
805 	POWER_DOMAIN_INIT);
806 
807 #define TGL_PW_4_POWER_DOMAINS \
808 	TGL_PW_5_POWER_DOMAINS, \
809 	POWER_DOMAIN_PIPE_C, \
810 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
811 	POWER_DOMAIN_TRANSCODER_C
812 
813 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
814 	TGL_PW_4_POWER_DOMAINS,
815 	POWER_DOMAIN_INIT);
816 
817 #define TGL_PW_3_POWER_DOMAINS \
818 	TGL_PW_4_POWER_DOMAINS, \
819 	POWER_DOMAIN_PIPE_B, \
820 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
821 	POWER_DOMAIN_TRANSCODER_B, \
822 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
823 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
824 	POWER_DOMAIN_PORT_DDI_LANES_TC3, \
825 	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
826 	POWER_DOMAIN_PORT_DDI_LANES_TC5, \
827 	POWER_DOMAIN_PORT_DDI_LANES_TC6, \
828 	POWER_DOMAIN_VGA, \
829 	POWER_DOMAIN_AUDIO_MMIO, \
830 	POWER_DOMAIN_AUDIO_PLAYBACK, \
831 	POWER_DOMAIN_AUX_USBC1, \
832 	POWER_DOMAIN_AUX_USBC2, \
833 	POWER_DOMAIN_AUX_USBC3, \
834 	POWER_DOMAIN_AUX_USBC4, \
835 	POWER_DOMAIN_AUX_USBC5, \
836 	POWER_DOMAIN_AUX_USBC6, \
837 	POWER_DOMAIN_AUX_TBT1, \
838 	POWER_DOMAIN_AUX_TBT2, \
839 	POWER_DOMAIN_AUX_TBT3, \
840 	POWER_DOMAIN_AUX_TBT4, \
841 	POWER_DOMAIN_AUX_TBT5, \
842 	POWER_DOMAIN_AUX_TBT6
843 
844 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
845 	TGL_PW_3_POWER_DOMAINS,
846 	POWER_DOMAIN_INIT);
847 
848 I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
849 	TGL_PW_3_POWER_DOMAINS,
850 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
851 	POWER_DOMAIN_INIT);
852 
853 I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
854 	TGL_PW_3_POWER_DOMAINS,
855 	POWER_DOMAIN_AUX_A,
856 	POWER_DOMAIN_AUX_B,
857 	POWER_DOMAIN_AUX_C,
858 	POWER_DOMAIN_DC_OFF,
859 	POWER_DOMAIN_INIT);
860 
861 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1,	POWER_DOMAIN_PORT_DDI_IO_TC1);
862 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2,	POWER_DOMAIN_PORT_DDI_IO_TC2);
863 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3,	POWER_DOMAIN_PORT_DDI_IO_TC3);
864 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4,	POWER_DOMAIN_PORT_DDI_IO_TC4);
865 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5,	POWER_DOMAIN_PORT_DDI_IO_TC5);
866 I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6,	POWER_DOMAIN_PORT_DDI_IO_TC6);
867 
868 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1,	POWER_DOMAIN_AUX_USBC1);
869 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2,	POWER_DOMAIN_AUX_USBC2);
870 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3,	POWER_DOMAIN_AUX_USBC3);
871 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4,	POWER_DOMAIN_AUX_USBC4);
872 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5,	POWER_DOMAIN_AUX_USBC5);
873 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6,	POWER_DOMAIN_AUX_USBC6);
874 
875 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5,	POWER_DOMAIN_AUX_TBT5);
876 I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6,	POWER_DOMAIN_AUX_TBT6);
877 
878 I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
879 	POWER_DOMAIN_AUX_USBC1,
880 	POWER_DOMAIN_AUX_USBC2,
881 	POWER_DOMAIN_AUX_USBC3,
882 	POWER_DOMAIN_AUX_USBC4,
883 	POWER_DOMAIN_AUX_USBC5,
884 	POWER_DOMAIN_AUX_USBC6,
885 	POWER_DOMAIN_AUX_TBT1,
886 	POWER_DOMAIN_AUX_TBT2,
887 	POWER_DOMAIN_AUX_TBT3,
888 	POWER_DOMAIN_AUX_TBT4,
889 	POWER_DOMAIN_AUX_TBT5,
890 	POWER_DOMAIN_AUX_TBT6,
891 	POWER_DOMAIN_TC_COLD_OFF);
892 
893 static const struct i915_power_well_desc tgl_power_wells_main[] = {
894 	{
895 		.instances = &I915_PW_INSTANCES(
896 			I915_PW("DC_off", &tgl_pwdoms_dc_off,
897 				.id = SKL_DISP_DC_OFF),
898 		),
899 		.ops = &gen9_dc_off_power_well_ops,
900 	}, {
901 		.instances = &I915_PW_INSTANCES(
902 			I915_PW("PW_2", &tgl_pwdoms_pw_2,
903 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
904 				.id = SKL_DISP_PW_2),
905 		),
906 		.ops = &hsw_power_well_ops,
907 		.has_fuses = true,
908 	}, {
909 		.instances = &I915_PW_INSTANCES(
910 			I915_PW("PW_3", &tgl_pwdoms_pw_3,
911 				.hsw.idx = ICL_PW_CTL_IDX_PW_3,
912 				.id = ICL_DISP_PW_3),
913 		),
914 		.ops = &hsw_power_well_ops,
915 		.has_vga = true,
916 		.irq_pipe_mask = BIT(PIPE_B),
917 		.has_fuses = true,
918 	}, {
919 		.instances = &I915_PW_INSTANCES(
920 			I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
921 			I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
922 			I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
923 			I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
924 			I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
925 			I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
926 			I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
927 			I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5),
928 			I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6),
929 		),
930 		.ops = &icl_ddi_power_well_ops,
931 	}, {
932 		.instances = &I915_PW_INSTANCES(
933 			I915_PW("PW_4", &tgl_pwdoms_pw_4,
934 				.hsw.idx = ICL_PW_CTL_IDX_PW_4),
935 		),
936 		.ops = &hsw_power_well_ops,
937 		.has_fuses = true,
938 		.irq_pipe_mask = BIT(PIPE_C),
939 	}, {
940 		.instances = &I915_PW_INSTANCES(
941 			I915_PW("PW_5", &tgl_pwdoms_pw_5,
942 				.hsw.idx = TGL_PW_CTL_IDX_PW_5),
943 		),
944 		.ops = &hsw_power_well_ops,
945 		.has_fuses = true,
946 		.irq_pipe_mask = BIT(PIPE_D),
947 	},
948 };
949 
950 static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
951 	{
952 		.instances = &I915_PW_INSTANCES(
953 			I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
954 				.id = TGL_DISP_PW_TC_COLD_OFF),
955 		),
956 		.ops = &tgl_tc_cold_off_ops,
957 	},
958 };
959 
960 static const struct i915_power_well_desc tgl_power_wells_aux[] = {
961 	{
962 		.instances = &I915_PW_INSTANCES(
963 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
964 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
965 			I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
966 			I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
967 			I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
968 			I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
969 			I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
970 			I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5),
971 			I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6),
972 		),
973 		.ops = &icl_aux_power_well_ops,
974 	}, {
975 		.instances = &I915_PW_INSTANCES(
976 			I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
977 			I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
978 			I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
979 			I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
980 			I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
981 			I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
982 		),
983 		.ops = &icl_aux_power_well_ops,
984 		.is_tc_tbt = true,
985 	},
986 };
987 
988 static const struct i915_power_well_desc_list tgl_power_wells[] = {
989 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
990 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
991 	I915_PW_DESCRIPTORS(tgl_power_wells_main),
992 	I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
993 	I915_PW_DESCRIPTORS(tgl_power_wells_aux),
994 };
995 
996 static const struct i915_power_well_desc_list adls_power_wells[] = {
997 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
998 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
999 	I915_PW_DESCRIPTORS(tgl_power_wells_main),
1000 	I915_PW_DESCRIPTORS(tgl_power_wells_aux),
1001 };
1002 
1003 #define RKL_PW_4_POWER_DOMAINS \
1004 	POWER_DOMAIN_PIPE_C, \
1005 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
1006 	POWER_DOMAIN_TRANSCODER_C
1007 
1008 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
1009 	RKL_PW_4_POWER_DOMAINS,
1010 	POWER_DOMAIN_INIT);
1011 
1012 #define RKL_PW_3_POWER_DOMAINS \
1013 	RKL_PW_4_POWER_DOMAINS, \
1014 	POWER_DOMAIN_PIPE_B, \
1015 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1016 	POWER_DOMAIN_TRANSCODER_B, \
1017 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1018 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1019 	POWER_DOMAIN_VGA, \
1020 	POWER_DOMAIN_AUDIO_MMIO, \
1021 	POWER_DOMAIN_AUDIO_PLAYBACK, \
1022 	POWER_DOMAIN_AUX_USBC1, \
1023 	POWER_DOMAIN_AUX_USBC2
1024 
1025 I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
1026 	RKL_PW_3_POWER_DOMAINS,
1027 	POWER_DOMAIN_INIT);
1028 
1029 /*
1030  * There is no PW_2/PG_2 on RKL.
1031  *
1032  * RKL PW_1/PG_1 domains (under HW/DMC control):
1033  * - DBUF function (note: registers are in PW0)
1034  * - PIPE_A and its planes and VDSC/joining, except VGA
1035  * - transcoder A
1036  * - DDI_A and DDI_B
1037  * - FBC
1038  *
1039  * RKL PW_0/PG_0 domains (under HW/DMC control):
1040  * - PCI
1041  * - clocks except port PLL
1042  * - shared functions:
1043  *     * interrupts except pipe interrupts
1044  *     * MBus except PIPE_MBUS_DBOX_CTL
1045  *     * DBUF registers
1046  * - central power except FBC
1047  * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
1048  */
1049 
1050 I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
1051 	RKL_PW_3_POWER_DOMAINS,
1052 	POWER_DOMAIN_AUX_A,
1053 	POWER_DOMAIN_AUX_B,
1054 	POWER_DOMAIN_DC_OFF,
1055 	POWER_DOMAIN_INIT);
1056 
1057 static const struct i915_power_well_desc rkl_power_wells_main[] = {
1058 	{
1059 		.instances = &I915_PW_INSTANCES(
1060 			I915_PW("DC_off", &rkl_pwdoms_dc_off,
1061 				.id = SKL_DISP_DC_OFF),
1062 		),
1063 		.ops = &gen9_dc_off_power_well_ops,
1064 	}, {
1065 		.instances = &I915_PW_INSTANCES(
1066 			I915_PW("PW_3", &rkl_pwdoms_pw_3,
1067 				.hsw.idx = ICL_PW_CTL_IDX_PW_3,
1068 				.id = ICL_DISP_PW_3),
1069 		),
1070 		.ops = &hsw_power_well_ops,
1071 		.irq_pipe_mask = BIT(PIPE_B),
1072 		.has_vga = true,
1073 		.has_fuses = true,
1074 	}, {
1075 		.instances = &I915_PW_INSTANCES(
1076 			I915_PW("PW_4", &rkl_pwdoms_pw_4,
1077 				.hsw.idx = ICL_PW_CTL_IDX_PW_4),
1078 		),
1079 		.ops = &hsw_power_well_ops,
1080 		.has_fuses = true,
1081 		.irq_pipe_mask = BIT(PIPE_C),
1082 	},
1083 };
1084 
1085 static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
1086 	{
1087 		.instances = &I915_PW_INSTANCES(
1088 			I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1089 			I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1090 			I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1091 			I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1092 		),
1093 		.ops = &icl_ddi_power_well_ops,
1094 	}, {
1095 		.instances = &I915_PW_INSTANCES(
1096 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1097 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1098 			I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1099 			I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1100 		),
1101 		.ops = &icl_aux_power_well_ops,
1102 	},
1103 };
1104 
1105 static const struct i915_power_well_desc_list rkl_power_wells[] = {
1106 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1107 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1108 	I915_PW_DESCRIPTORS(rkl_power_wells_main),
1109 	I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1110 };
1111 
1112 /*
1113  * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
1114  */
1115 #define DG1_PW_3_POWER_DOMAINS \
1116 	TGL_PW_4_POWER_DOMAINS, \
1117 	POWER_DOMAIN_PIPE_B, \
1118 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1119 	POWER_DOMAIN_TRANSCODER_B, \
1120 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1121 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1122 	POWER_DOMAIN_VGA, \
1123 	POWER_DOMAIN_AUDIO_PLAYBACK, \
1124 	POWER_DOMAIN_AUX_USBC1, \
1125 	POWER_DOMAIN_AUX_USBC2
1126 
1127 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
1128 	DG1_PW_3_POWER_DOMAINS,
1129 	POWER_DOMAIN_INIT);
1130 
1131 I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
1132 	DG1_PW_3_POWER_DOMAINS,
1133 	POWER_DOMAIN_AUDIO_MMIO,
1134 	POWER_DOMAIN_AUX_A,
1135 	POWER_DOMAIN_AUX_B,
1136 	POWER_DOMAIN_DC_OFF,
1137 	POWER_DOMAIN_INIT);
1138 
1139 I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
1140 	DG1_PW_3_POWER_DOMAINS,
1141 	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
1142 	POWER_DOMAIN_INIT);
1143 
1144 static const struct i915_power_well_desc dg1_power_wells_main[] = {
1145 	{
1146 		.instances = &I915_PW_INSTANCES(
1147 			I915_PW("DC_off", &dg1_pwdoms_dc_off,
1148 				.id = SKL_DISP_DC_OFF),
1149 		),
1150 		.ops = &gen9_dc_off_power_well_ops,
1151 	}, {
1152 		.instances = &I915_PW_INSTANCES(
1153 			I915_PW("PW_2", &dg1_pwdoms_pw_2,
1154 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1155 				.id = SKL_DISP_PW_2),
1156 		),
1157 		.ops = &hsw_power_well_ops,
1158 		.has_fuses = true,
1159 	}, {
1160 		.instances = &I915_PW_INSTANCES(
1161 			I915_PW("PW_3", &dg1_pwdoms_pw_3,
1162 				.hsw.idx = ICL_PW_CTL_IDX_PW_3,
1163 				.id = ICL_DISP_PW_3),
1164 		),
1165 		.ops = &hsw_power_well_ops,
1166 		.irq_pipe_mask = BIT(PIPE_B),
1167 		.has_vga = true,
1168 		.has_fuses = true,
1169 	}, {
1170 		.instances = &I915_PW_INSTANCES(
1171 			I915_PW("PW_4", &tgl_pwdoms_pw_4,
1172 				.hsw.idx = ICL_PW_CTL_IDX_PW_4),
1173 		),
1174 		.ops = &hsw_power_well_ops,
1175 		.has_fuses = true,
1176 		.irq_pipe_mask = BIT(PIPE_C),
1177 	}, {
1178 		.instances = &I915_PW_INSTANCES(
1179 			I915_PW("PW_5", &tgl_pwdoms_pw_5,
1180 				.hsw.idx = TGL_PW_CTL_IDX_PW_5),
1181 		),
1182 		.ops = &hsw_power_well_ops,
1183 		.has_fuses = true,
1184 		.irq_pipe_mask = BIT(PIPE_D),
1185 	},
1186 };
1187 
1188 static const struct i915_power_well_desc_list dg1_power_wells[] = {
1189 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1190 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1191 	I915_PW_DESCRIPTORS(dg1_power_wells_main),
1192 	I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
1193 };
1194 
1195 /*
1196  * XE_LPD Power Domains
1197  *
1198  * Previous platforms required that PG(n-1) be enabled before PG(n).  That
1199  * dependency chain turns into a dependency tree on XE_LPD:
1200  *
1201  *       PG0
1202  *        |
1203  *     --PG1--
1204  *    /       \
1205  *  PGA     --PG2--
1206  *         /   |   \
1207  *       PGB  PGC  PGD
1208  *
1209  * Power wells must be enabled from top to bottom and disabled from bottom
1210  * to top.  This allows pipes to be power gated independently.
1211  */
1212 
1213 #define XELPD_PW_D_POWER_DOMAINS \
1214 	POWER_DOMAIN_PIPE_D, \
1215 	POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
1216 	POWER_DOMAIN_TRANSCODER_D
1217 
1218 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
1219 	XELPD_PW_D_POWER_DOMAINS,
1220 	POWER_DOMAIN_INIT);
1221 
1222 #define XELPD_PW_C_POWER_DOMAINS \
1223 	POWER_DOMAIN_PIPE_C, \
1224 	POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
1225 	POWER_DOMAIN_TRANSCODER_C
1226 
1227 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
1228 	XELPD_PW_C_POWER_DOMAINS,
1229 	POWER_DOMAIN_INIT);
1230 
1231 #define XELPD_PW_B_POWER_DOMAINS \
1232 	POWER_DOMAIN_PIPE_B, \
1233 	POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
1234 	POWER_DOMAIN_TRANSCODER_B
1235 
1236 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
1237 	XELPD_PW_B_POWER_DOMAINS,
1238 	POWER_DOMAIN_INIT);
1239 
1240 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
1241 	POWER_DOMAIN_PIPE_A,
1242 	POWER_DOMAIN_PIPE_PANEL_FITTER_A,
1243 	POWER_DOMAIN_INIT);
1244 
1245 #define XELPD_DC_OFF_PORT_POWER_DOMAINS \
1246 	POWER_DOMAIN_PORT_DDI_LANES_C, \
1247 	POWER_DOMAIN_PORT_DDI_LANES_D, \
1248 	POWER_DOMAIN_PORT_DDI_LANES_E, \
1249 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1250 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1251 	POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1252 	POWER_DOMAIN_PORT_DDI_LANES_TC4, \
1253 	POWER_DOMAIN_VGA, \
1254 	POWER_DOMAIN_AUDIO_PLAYBACK, \
1255 	POWER_DOMAIN_AUX_IO_C, \
1256 	POWER_DOMAIN_AUX_IO_D, \
1257 	POWER_DOMAIN_AUX_IO_E, \
1258 	POWER_DOMAIN_AUX_C, \
1259 	POWER_DOMAIN_AUX_D, \
1260 	POWER_DOMAIN_AUX_E, \
1261 	POWER_DOMAIN_AUX_USBC1, \
1262 	POWER_DOMAIN_AUX_USBC2, \
1263 	POWER_DOMAIN_AUX_USBC3, \
1264 	POWER_DOMAIN_AUX_USBC4, \
1265 	POWER_DOMAIN_AUX_TBT1, \
1266 	POWER_DOMAIN_AUX_TBT2, \
1267 	POWER_DOMAIN_AUX_TBT3, \
1268 	POWER_DOMAIN_AUX_TBT4
1269 
1270 #define XELPD_PW_2_POWER_DOMAINS \
1271 	XELPD_PW_B_POWER_DOMAINS, \
1272 	XELPD_PW_C_POWER_DOMAINS, \
1273 	XELPD_PW_D_POWER_DOMAINS, \
1274 	XELPD_DC_OFF_PORT_POWER_DOMAINS
1275 
1276 I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
1277 	XELPD_PW_2_POWER_DOMAINS,
1278 	POWER_DOMAIN_INIT);
1279 
1280 /*
1281  * XELPD PW_1/PG_1 domains (under HW/DMC control):
1282  *  - DBUF function (registers are in PW0)
1283  *  - Transcoder A
1284  *  - DDI_A and DDI_B
1285  *
1286  * XELPD PW_0/PW_1 domains (under HW/DMC control):
1287  *  - PCI
1288  *  - Clocks except port PLL
1289  *  - Shared functions:
1290  *     * interrupts except pipe interrupts
1291  *     * MBus except PIPE_MBUS_DBOX_CTL
1292  *     * DBUF registers
1293  *  - Central power except FBC
1294  *  - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
1295  */
1296 
1297 I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
1298 	XELPD_DC_OFF_PORT_POWER_DOMAINS,
1299 	XELPD_PW_C_POWER_DOMAINS,
1300 	XELPD_PW_D_POWER_DOMAINS,
1301 	POWER_DOMAIN_PORT_DSI,
1302 	POWER_DOMAIN_AUDIO_MMIO,
1303 	POWER_DOMAIN_AUX_A,
1304 	POWER_DOMAIN_AUX_B,
1305 	POWER_DOMAIN_DC_OFF,
1306 	POWER_DOMAIN_INIT);
1307 
1308 static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = {
1309 	{
1310 		.instances = &I915_PW_INSTANCES(
1311 			I915_PW("DC_off", &xelpd_pwdoms_dc_off,
1312 				.id = SKL_DISP_DC_OFF),
1313 		),
1314 		.ops = &gen9_dc_off_power_well_ops,
1315 	}
1316 };
1317 
1318 static const struct i915_power_well_desc xelpd_power_wells_main[] = {
1319 	{
1320 		.instances = &I915_PW_INSTANCES(
1321 			I915_PW("PW_2", &xelpd_pwdoms_pw_2,
1322 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1323 				.id = SKL_DISP_PW_2),
1324 		),
1325 		.ops = &hsw_power_well_ops,
1326 		.has_vga = true,
1327 		.has_fuses = true,
1328 	}, {
1329 		.instances = &I915_PW_INSTANCES(
1330 			I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1331 				.hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1332 		),
1333 		.ops = &hsw_power_well_ops,
1334 		.irq_pipe_mask = BIT(PIPE_A),
1335 		.has_fuses = true,
1336 	}, {
1337 		.instances = &I915_PW_INSTANCES(
1338 			I915_PW("PW_B", &xelpd_pwdoms_pw_b,
1339 				.hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1340 		),
1341 		.ops = &hsw_power_well_ops,
1342 		.irq_pipe_mask = BIT(PIPE_B),
1343 		.has_fuses = true,
1344 	}, {
1345 		.instances = &I915_PW_INSTANCES(
1346 			I915_PW("PW_C", &xelpd_pwdoms_pw_c,
1347 				.hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1348 		),
1349 		.ops = &hsw_power_well_ops,
1350 		.irq_pipe_mask = BIT(PIPE_C),
1351 		.has_fuses = true,
1352 	}, {
1353 		.instances = &I915_PW_INSTANCES(
1354 			I915_PW("PW_D", &xelpd_pwdoms_pw_d,
1355 				.hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1356 		),
1357 		.ops = &hsw_power_well_ops,
1358 		.irq_pipe_mask = BIT(PIPE_D),
1359 		.has_fuses = true,
1360 	}, {
1361 		.instances = &I915_PW_INSTANCES(
1362 			I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
1363 			I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
1364 			I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
1365 			I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
1366 			I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
1367 			I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
1368 			I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
1369 			I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
1370 			I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
1371 		),
1372 		.ops = &icl_ddi_power_well_ops,
1373 	}, {
1374 		.instances = &I915_PW_INSTANCES(
1375 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
1376 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
1377 			I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
1378 			I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
1379 			I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
1380 		),
1381 		.ops = &icl_aux_power_well_ops,
1382 		.fixed_enable_delay = true,
1383 	}, {
1384 		.instances = &I915_PW_INSTANCES(
1385 			I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
1386 			I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
1387 			I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
1388 			I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
1389 		),
1390 		.ops = &icl_aux_power_well_ops,
1391 		.fixed_enable_delay = true,
1392 		/* WA_14017248603: adlp */
1393 		.enable_timeout = 500,
1394 	}, {
1395 		.instances = &I915_PW_INSTANCES(
1396 			I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
1397 			I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
1398 			I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
1399 			I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
1400 		),
1401 		.ops = &icl_aux_power_well_ops,
1402 		.is_tc_tbt = true,
1403 	},
1404 };
1405 
1406 static const struct i915_power_well_desc_list xelpd_power_wells[] = {
1407 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1408 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1409 	I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
1410 	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
1411 };
1412 
1413 I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off,
1414 	XELPD_PW_2_POWER_DOMAINS,
1415 	POWER_DOMAIN_PORT_DSI,
1416 	POWER_DOMAIN_AUDIO_MMIO,
1417 	POWER_DOMAIN_AUX_A,
1418 	POWER_DOMAIN_AUX_B,
1419 	POWER_DOMAIN_DC_OFF,
1420 	POWER_DOMAIN_INIT);
1421 
1422 static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = {
1423 	{
1424 		.instances = &I915_PW_INSTANCES(
1425 			I915_PW("DC_off", &xehpd_pwdoms_dc_off,
1426 				.id = SKL_DISP_DC_OFF),
1427 		),
1428 		.ops = &gen9_dc_off_power_well_ops,
1429 	}
1430 };
1431 
1432 static const struct i915_power_well_desc_list xehpd_power_wells[] = {
1433 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1434 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1435 	I915_PW_DESCRIPTORS(xehpd_power_wells_dc_off),
1436 	I915_PW_DESCRIPTORS(xelpd_power_wells_main),
1437 };
1438 
1439 /*
1440  * MTL is based on XELPD power domains with the exception of power gating for:
1441  * - DDI_IO (moved to PLL logic)
1442  * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on)
1443  */
1444 #define XELPDP_PW_2_POWER_DOMAINS \
1445 	XELPD_PW_B_POWER_DOMAINS, \
1446 	XELPD_PW_C_POWER_DOMAINS, \
1447 	XELPD_PW_D_POWER_DOMAINS, \
1448 	POWER_DOMAIN_AUDIO_PLAYBACK, \
1449 	POWER_DOMAIN_VGA, \
1450 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1451 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1452 	POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1453 	POWER_DOMAIN_PORT_DDI_LANES_TC4
1454 
1455 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2,
1456 	XELPDP_PW_2_POWER_DOMAINS,
1457 	POWER_DOMAIN_INIT);
1458 
1459 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1,
1460 	POWER_DOMAIN_AUX_USBC1,
1461 	POWER_DOMAIN_AUX_TBT1);
1462 
1463 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2,
1464 	POWER_DOMAIN_AUX_USBC2,
1465 	POWER_DOMAIN_AUX_TBT2);
1466 
1467 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3,
1468 	POWER_DOMAIN_AUX_USBC3,
1469 	POWER_DOMAIN_AUX_TBT3);
1470 
1471 I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4,
1472 	POWER_DOMAIN_AUX_USBC4,
1473 	POWER_DOMAIN_AUX_TBT4);
1474 
1475 static const struct i915_power_well_desc xelpdp_power_wells_main[] = {
1476 	{
1477 		.instances = &I915_PW_INSTANCES(
1478 			I915_PW("PW_2", &xelpdp_pwdoms_pw_2,
1479 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1480 				.id = SKL_DISP_PW_2),
1481 		),
1482 		.ops = &hsw_power_well_ops,
1483 		.has_vga = true,
1484 		.has_fuses = true,
1485 	}, {
1486 		.instances = &I915_PW_INSTANCES(
1487 			I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1488 				.hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1489 		),
1490 		.ops = &hsw_power_well_ops,
1491 		.irq_pipe_mask = BIT(PIPE_A),
1492 		.has_fuses = true,
1493 	}, {
1494 		.instances = &I915_PW_INSTANCES(
1495 			I915_PW("PW_B", &xelpd_pwdoms_pw_b,
1496 				.hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1497 		),
1498 		.ops = &hsw_power_well_ops,
1499 		.irq_pipe_mask = BIT(PIPE_B),
1500 		.has_fuses = true,
1501 	}, {
1502 		.instances = &I915_PW_INSTANCES(
1503 			I915_PW("PW_C", &xelpd_pwdoms_pw_c,
1504 				.hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1505 		),
1506 		.ops = &hsw_power_well_ops,
1507 		.irq_pipe_mask = BIT(PIPE_C),
1508 		.has_fuses = true,
1509 	}, {
1510 		.instances = &I915_PW_INSTANCES(
1511 			I915_PW("PW_D", &xelpd_pwdoms_pw_d,
1512 				.hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1513 		),
1514 		.ops = &hsw_power_well_ops,
1515 		.irq_pipe_mask = BIT(PIPE_D),
1516 		.has_fuses = true,
1517 	}, {
1518 		.instances = &I915_PW_INSTANCES(
1519 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
1520 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
1521 			I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
1522 			I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
1523 			I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
1524 			I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
1525 		),
1526 		.ops = &xelpdp_aux_power_well_ops,
1527 	},
1528 };
1529 
1530 static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
1531 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1532 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1533 	I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
1534 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
1535 };
1536 
1537 I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
1538 		     POWER_DOMAIN_PORT_DDI_LANES_TC1,
1539 		     POWER_DOMAIN_PORT_DDI_LANES_TC2,
1540 		     POWER_DOMAIN_PORT_DDI_LANES_TC3,
1541 		     POWER_DOMAIN_PORT_DDI_LANES_TC4,
1542 		     POWER_DOMAIN_AUX_USBC1,
1543 		     POWER_DOMAIN_AUX_USBC2,
1544 		     POWER_DOMAIN_AUX_USBC3,
1545 		     POWER_DOMAIN_AUX_USBC4,
1546 		     POWER_DOMAIN_AUX_TBT1,
1547 		     POWER_DOMAIN_AUX_TBT2,
1548 		     POWER_DOMAIN_AUX_TBT3,
1549 		     POWER_DOMAIN_AUX_TBT4,
1550 		     POWER_DOMAIN_INIT);
1551 
1552 static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
1553 	{
1554 		.instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
1555 							&xe2lpd_pwdoms_pica_tc,
1556 							.id = DISP_PW_ID_NONE),
1557 					       ),
1558 		.ops = &xe2lpd_pica_power_well_ops,
1559 	},
1560 };
1561 
1562 I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
1563 	POWER_DOMAIN_DC_OFF,
1564 	XELPD_PW_C_POWER_DOMAINS,
1565 	XELPD_PW_D_POWER_DOMAINS,
1566 	POWER_DOMAIN_AUDIO_MMIO,
1567 	POWER_DOMAIN_INIT);
1568 
1569 static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
1570 	{
1571 		.instances = &I915_PW_INSTANCES(
1572 			I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
1573 				.id = SKL_DISP_DC_OFF),
1574 		),
1575 		.ops = &gen9_dc_off_power_well_ops,
1576 	},
1577 };
1578 
1579 static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
1580 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1581 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1582 	I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
1583 	I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
1584 	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1585 };
1586 
1587 /*
1588  * Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now
1589  * depends on PG1 instead of PG2:
1590  *
1591  *       PG0
1592  *        |
1593  *     --PG1--
1594  *    /   |   \
1595  *  PGA  PGB  PG2
1596  *           /   \
1597  *         PGC   PGD
1598  */
1599 
1600 #define XE3LPD_PW_C_POWER_DOMAINS \
1601 	POWER_DOMAIN_PIPE_C, \
1602 	POWER_DOMAIN_PIPE_PANEL_FITTER_C
1603 
1604 #define XE3LPD_PW_D_POWER_DOMAINS \
1605 	POWER_DOMAIN_PIPE_D, \
1606 	POWER_DOMAIN_PIPE_PANEL_FITTER_D
1607 
1608 #define XE3LPD_PW_2_POWER_DOMAINS \
1609 	XE3LPD_PW_C_POWER_DOMAINS, \
1610 	XE3LPD_PW_D_POWER_DOMAINS, \
1611 	POWER_DOMAIN_TRANSCODER_C, \
1612 	POWER_DOMAIN_TRANSCODER_D, \
1613 	POWER_DOMAIN_VGA, \
1614 	POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1615 	POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1616 	POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1617 	POWER_DOMAIN_PORT_DDI_LANES_TC4
1618 
1619 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2,
1620 		     XE3LPD_PW_2_POWER_DOMAINS,
1621 		     POWER_DOMAIN_INIT);
1622 
1623 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b,
1624 		     POWER_DOMAIN_PIPE_B,
1625 		     POWER_DOMAIN_PIPE_PANEL_FITTER_B,
1626 		     POWER_DOMAIN_INIT);
1627 
1628 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c,
1629 		     XE3LPD_PW_C_POWER_DOMAINS,
1630 		     POWER_DOMAIN_INIT);
1631 
1632 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d,
1633 		     XE3LPD_PW_D_POWER_DOMAINS,
1634 		     POWER_DOMAIN_INIT);
1635 
1636 static const struct i915_power_well_desc xe3lpd_power_wells_main[] = {
1637 	{
1638 		.instances = &I915_PW_INSTANCES(
1639 			I915_PW("PW_2", &xe3lpd_pwdoms_pw_2,
1640 				.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1641 				.id = SKL_DISP_PW_2),
1642 		),
1643 		.ops = &hsw_power_well_ops,
1644 		.has_vga = true,
1645 		.has_fuses = true,
1646 	}, {
1647 		.instances = &I915_PW_INSTANCES(
1648 			I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1649 				.hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1650 		),
1651 		.ops = &hsw_power_well_ops,
1652 		.irq_pipe_mask = BIT(PIPE_A),
1653 		.has_fuses = true,
1654 	}, {
1655 		.instances = &I915_PW_INSTANCES(
1656 			I915_PW("PW_B", &xe3lpd_pwdoms_pw_b,
1657 				.hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1658 		),
1659 		.ops = &hsw_power_well_ops,
1660 		.irq_pipe_mask = BIT(PIPE_B),
1661 		.has_fuses = true,
1662 	}, {
1663 		.instances = &I915_PW_INSTANCES(
1664 			I915_PW("PW_C", &xe3lpd_pwdoms_pw_c,
1665 				.hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1666 		),
1667 		.ops = &hsw_power_well_ops,
1668 		.irq_pipe_mask = BIT(PIPE_C),
1669 		.has_fuses = true,
1670 	}, {
1671 		.instances = &I915_PW_INSTANCES(
1672 			I915_PW("PW_D", &xe3lpd_pwdoms_pw_d,
1673 				.hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1674 		),
1675 		.ops = &hsw_power_well_ops,
1676 		.irq_pipe_mask = BIT(PIPE_D),
1677 		.has_fuses = true,
1678 	}, {
1679 		.instances = &I915_PW_INSTANCES(
1680 			I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
1681 			I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
1682 			I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
1683 			I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
1684 			I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
1685 			I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
1686 		),
1687 		.ops = &xelpdp_aux_power_well_ops,
1688 	},
1689 };
1690 
1691 I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off,
1692 	POWER_DOMAIN_DC_OFF,
1693 	XE3LPD_PW_2_POWER_DOMAINS,
1694 	XE3LPD_PW_C_POWER_DOMAINS,
1695 	XE3LPD_PW_D_POWER_DOMAINS,
1696 	POWER_DOMAIN_AUDIO_MMIO,
1697 	POWER_DOMAIN_INIT);
1698 
1699 static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = {
1700 	{
1701 		.instances = &I915_PW_INSTANCES(
1702 			I915_PW("DC_off", &xe3lpd_pwdoms_dc_off,
1703 				.id = SKL_DISP_DC_OFF),
1704 		),
1705 		.ops = &gen9_dc_off_power_well_ops,
1706 	},
1707 };
1708 
1709 static const struct i915_power_well_desc_list xe3lpd_power_wells[] = {
1710 	I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1711 	I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1712 	I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff),
1713 	I915_PW_DESCRIPTORS(xe3lpd_power_wells_main),
1714 	I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1715 };
1716 
init_power_well_domains(const struct i915_power_well_instance * inst,struct i915_power_well * power_well)1717 static void init_power_well_domains(const struct i915_power_well_instance *inst,
1718 				    struct i915_power_well *power_well)
1719 {
1720 	int j;
1721 
1722 	if (!inst->domain_list)
1723 		return;
1724 
1725 	if (inst->domain_list->count == 0) {
1726 		bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
1727 
1728 		return;
1729 	}
1730 
1731 	for (j = 0; j < inst->domain_list->count; j++)
1732 		set_bit(inst->domain_list->list[j], power_well->domains.bits);
1733 }
1734 
1735 #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
1736 	for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
1737 		for ((_inst) = (_desc)->instances->list; \
1738 		     (_inst) - (_desc)->instances->list < (_desc)->instances->count; \
1739 		     (_inst)++)
1740 
1741 #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
1742 	for ((_descs) = (_desc_list); \
1743 	     (_descs) - (_desc_list) < (_desc_count); \
1744 	     (_descs)++) \
1745 		for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
1746 							  (_desc), (_inst))
1747 
1748 static int
__set_power_wells(struct i915_power_domains * power_domains,const struct i915_power_well_desc_list * power_well_descs,int power_well_descs_sz)1749 __set_power_wells(struct i915_power_domains *power_domains,
1750 		  const struct i915_power_well_desc_list *power_well_descs,
1751 		  int power_well_descs_sz)
1752 {
1753 	struct intel_display *display = container_of(power_domains,
1754 						     struct intel_display,
1755 						     power.domains);
1756 	u64 power_well_ids = 0;
1757 	const struct i915_power_well_desc_list *desc_list;
1758 	const struct i915_power_well_desc *desc;
1759 	const struct i915_power_well_instance *inst;
1760 	int power_well_count = 0;
1761 	int plt_idx = 0;
1762 
1763 	for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
1764 		power_well_count++;
1765 
1766 	power_domains->power_well_count = power_well_count;
1767 	power_domains->power_wells =
1768 				kcalloc(power_well_count,
1769 					sizeof(*power_domains->power_wells),
1770 					GFP_KERNEL);
1771 	if (!power_domains->power_wells)
1772 		return -ENOMEM;
1773 
1774 	for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
1775 		struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
1776 		enum i915_power_well_id id = inst->id;
1777 
1778 		pw->desc = desc;
1779 		drm_WARN_ON(display->drm,
1780 			    overflows_type(inst - desc->instances->list, pw->instance_idx));
1781 		pw->instance_idx = inst - desc->instances->list;
1782 
1783 		init_power_well_domains(inst, pw);
1784 
1785 		plt_idx++;
1786 
1787 		if (id == DISP_PW_ID_NONE)
1788 			continue;
1789 
1790 		drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8);
1791 		drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id));
1792 		power_well_ids |= BIT_ULL(id);
1793 	}
1794 
1795 	return 0;
1796 }
1797 
1798 #define set_power_wells(power_domains, __power_well_descs) \
1799 	__set_power_wells(power_domains, __power_well_descs, \
1800 			  ARRAY_SIZE(__power_well_descs))
1801 
1802 /**
1803  * intel_display_power_map_init - initialize power domain -> power well mappings
1804  * @power_domains: power domain state
1805  *
1806  * Creates all the power wells for the current platform, initializes the
1807  * dynamic state for them and initializes the mapping of each power well to
1808  * all the power domains the power well belongs to.
1809  */
intel_display_power_map_init(struct i915_power_domains * power_domains)1810 int intel_display_power_map_init(struct i915_power_domains *power_domains)
1811 {
1812 	struct intel_display *display = container_of(power_domains,
1813 						     struct intel_display,
1814 						     power.domains);
1815 	/*
1816 	 * The enabling order will be from lower to higher indexed wells,
1817 	 * the disabling order is reversed.
1818 	 */
1819 	if (!HAS_DISPLAY(display)) {
1820 		power_domains->power_well_count = 0;
1821 		return 0;
1822 	}
1823 
1824 	if (DISPLAY_VER(display) >= 30)
1825 		return set_power_wells(power_domains, xe3lpd_power_wells);
1826 	else if (DISPLAY_VER(display) >= 20)
1827 		return set_power_wells(power_domains, xe2lpd_power_wells);
1828 	else if (DISPLAY_VER(display) >= 14)
1829 		return set_power_wells(power_domains, xelpdp_power_wells);
1830 	else if (display->platform.dg2)
1831 		return set_power_wells(power_domains, xehpd_power_wells);
1832 	else if (DISPLAY_VER(display) >= 13)
1833 		return set_power_wells(power_domains, xelpd_power_wells);
1834 	else if (display->platform.dg1)
1835 		return set_power_wells(power_domains, dg1_power_wells);
1836 	else if (display->platform.alderlake_s)
1837 		return set_power_wells(power_domains, adls_power_wells);
1838 	else if (display->platform.rocketlake)
1839 		return set_power_wells(power_domains, rkl_power_wells);
1840 	else if (DISPLAY_VER(display) == 12)
1841 		return set_power_wells(power_domains, tgl_power_wells);
1842 	else if (DISPLAY_VER(display) == 11)
1843 		return set_power_wells(power_domains, icl_power_wells);
1844 	else if (display->platform.geminilake)
1845 		return set_power_wells(power_domains, glk_power_wells);
1846 	else if (display->platform.broxton)
1847 		return set_power_wells(power_domains, bxt_power_wells);
1848 	else if (DISPLAY_VER(display) == 9)
1849 		return set_power_wells(power_domains, skl_power_wells);
1850 	else if (display->platform.cherryview)
1851 		return set_power_wells(power_domains, chv_power_wells);
1852 	else if (display->platform.broadwell)
1853 		return set_power_wells(power_domains, bdw_power_wells);
1854 	else if (display->platform.haswell)
1855 		return set_power_wells(power_domains, hsw_power_wells);
1856 	else if (display->platform.valleyview)
1857 		return set_power_wells(power_domains, vlv_power_wells);
1858 	else if (display->platform.i830)
1859 		return set_power_wells(power_domains, i830_power_wells);
1860 	else
1861 		return set_power_wells(power_domains, i9xx_power_wells);
1862 }
1863 
1864 /**
1865  * intel_display_power_map_cleanup - clean up power domain -> power well mappings
1866  * @power_domains: power domain state
1867  *
1868  * Cleans up all the state that was initialized by intel_display_power_map_init().
1869  */
intel_display_power_map_cleanup(struct i915_power_domains * power_domains)1870 void intel_display_power_map_cleanup(struct i915_power_domains *power_domains)
1871 {
1872 	kfree(power_domains->power_wells);
1873 }
1874