1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_table.h"
13 #include "txrx.h"
14
15 #define RTW8852A_FW_FORMAT_MAX 1
16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
17 #define RTW8852A_MODULE_FIRMWARE \
18 RTW89_GEN_MODULE_FWNAME(RTW8852A_FW_BASENAME, RTW8852A_FW_FORMAT_MAX)
19
20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
21 {128, 1896, grp_0}, /* ACH 0 */
22 {128, 1896, grp_0}, /* ACH 1 */
23 {128, 1896, grp_0}, /* ACH 2 */
24 {128, 1896, grp_0}, /* ACH 3 */
25 {128, 1896, grp_1}, /* ACH 4 */
26 {128, 1896, grp_1}, /* ACH 5 */
27 {128, 1896, grp_1}, /* ACH 6 */
28 {128, 1896, grp_1}, /* ACH 7 */
29 {32, 1896, grp_0}, /* B0MGQ */
30 {128, 1896, grp_0}, /* B0HIQ */
31 {32, 1896, grp_1}, /* B1MGQ */
32 {128, 1896, grp_1}, /* B1HIQ */
33 {40, 0, 0} /* FWCMDQ */
34 };
35
36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
37 1896, /* Group 0 */
38 1896, /* Group 1 */
39 3792, /* Public Max */
40 0 /* WP threshold */
41 };
42
43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
47 RTW89_HCIFC_POH},
48 [RTW89_QTA_INVALID] = {NULL},
49 };
50
51 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_usb[] = {
52 {22, 402, grp_0}, /* ACH 0 */
53 {0, 0, grp_0}, /* ACH 1 */
54 {22, 402, grp_0}, /* ACH 2 */
55 {0, 0, grp_0}, /* ACH 3 */
56 {22, 402, grp_0}, /* ACH 4 */
57 {0, 0, grp_0}, /* ACH 5 */
58 {22, 402, grp_0}, /* ACH 6 */
59 {0, 0, grp_0}, /* ACH 7 */
60 {22, 402, grp_0}, /* B0MGQ */
61 {0, 0, grp_0}, /* B0HIQ */
62 {22, 402, grp_0}, /* B1MGQ */
63 {0, 0, grp_0}, /* B1HIQ */
64 {0, 0, 0} /* FWCMDQ */
65 };
66
67 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_usb = {
68 512, /* Group 0 */
69 0, /* Group 1 */
70 512, /* Public Max */
71 104 /* WP threshold */
72 };
73
74 static const struct rtw89_hfc_prec_cfg rtw8852a_hfc_preccfg_usb = {
75 11, /* CH 0-11 pre-cost */
76 32, /* H2C pre-cost */
77 76, /* WP CH 0-7 pre-cost */
78 25, /* WP CH 8-11 pre-cost */
79 1, /* CH 0-11 full condition */
80 1, /* H2C full condition */
81 1, /* WP CH 0-7 full condition */
82 1, /* WP CH 8-11 full condition */
83 };
84
85 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_usb[] = {
86 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_usb, &rtw8852a_hfc_pubcfg_usb,
87 &rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF},
88 [RTW89_QTA_DLFW] = {NULL, NULL,
89 &rtw8852a_hfc_preccfg_usb, RTW89_HCIFC_STF},
90 [RTW89_QTA_INVALID] = {NULL},
91 };
92
93 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
94 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
95 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
96 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
97 &rtw89_mac_size.ple_qt5},
98 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
99 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
100 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
101 &rtw89_mac_size.ple_qt_52a_wow},
102 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
103 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
104 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
105 &rtw89_mac_size.ple_qt13},
106 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
107 NULL},
108 };
109
110 static const struct rtw89_dle_mem rtw8852a_dle_mem_usb[] = {
111 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size1,
112 &rtw89_mac_size.ple_size1, &rtw89_mac_size.wde_qt1,
113 &rtw89_mac_size.wde_qt1, &rtw89_mac_size.ple_qt25,
114 &rtw89_mac_size.ple_qt26},
115 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
116 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
117 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
118 &rtw89_mac_size.ple_qt13},
119 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
120 NULL},
121 };
122
123 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
124 {0x44AC, 0x00000000},
125 {0x44B0, 0x00000000},
126 {0x44B4, 0x00000000},
127 {0x44B8, 0x00000000},
128 {0x44BC, 0x00000000},
129 {0x44C0, 0x00000000},
130 {0x44C4, 0x00000000},
131 {0x44C8, 0x00000000},
132 {0x44CC, 0x00000000},
133 {0x44D0, 0x00000000},
134 {0x44D4, 0x00000000},
135 {0x44D8, 0x00000000},
136 {0x44DC, 0x00000000},
137 {0x44E0, 0x00000000},
138 {0x44E4, 0x00000000},
139 {0x44E8, 0x00000000},
140 {0x44EC, 0x00000000},
141 {0x44F0, 0x00000000},
142 {0x44F4, 0x00000000},
143 {0x44F8, 0x00000000},
144 {0x44FC, 0x00000000},
145 {0x4500, 0x00000000},
146 {0x4504, 0x00000000},
147 {0x4508, 0x00000000},
148 {0x450C, 0x00000000},
149 {0x4510, 0x00000000},
150 {0x4514, 0x00000000},
151 {0x4518, 0x00000000},
152 {0x451C, 0x00000000},
153 {0x4520, 0x00000000},
154 {0x4524, 0x00000000},
155 {0x4528, 0x00000000},
156 {0x452C, 0x00000000},
157 {0x4530, 0x4E1F3E81},
158 {0x4534, 0x00000000},
159 {0x4538, 0x0000005A},
160 {0x453C, 0x00000000},
161 {0x4540, 0x00000000},
162 {0x4544, 0x00000000},
163 {0x4548, 0x00000000},
164 {0x454C, 0x00000000},
165 {0x4550, 0x00000000},
166 {0x4554, 0x00000000},
167 {0x4558, 0x00000000},
168 {0x455C, 0x00000000},
169 {0x4560, 0x4060001A},
170 {0x4564, 0x40000000},
171 {0x4568, 0x00000000},
172 {0x456C, 0x00000000},
173 {0x4570, 0x04000007},
174 {0x4574, 0x0000DC87},
175 {0x4578, 0x00000BAB},
176 {0x457C, 0x03E00000},
177 {0x4580, 0x00000048},
178 {0x4584, 0x00000000},
179 {0x4588, 0x000003E8},
180 {0x458C, 0x30000000},
181 {0x4590, 0x00000000},
182 {0x4594, 0x10000000},
183 {0x4598, 0x00000001},
184 {0x459C, 0x00030000},
185 {0x45A0, 0x01000000},
186 {0x45A4, 0x03000200},
187 {0x45A8, 0xC00001C0},
188 {0x45AC, 0x78018000},
189 {0x45B0, 0x80000000},
190 {0x45B4, 0x01C80600},
191 {0x45B8, 0x00000002},
192 {0x4594, 0x10000000}
193 };
194
195 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
196 {0x4624, GENMASK(20, 14), 0x40},
197 {0x46f8, GENMASK(20, 14), 0x40},
198 {0x4674, GENMASK(20, 19), 0x2},
199 {0x4748, GENMASK(20, 19), 0x2},
200 {0x4650, GENMASK(14, 10), 0x18},
201 {0x4724, GENMASK(14, 10), 0x18},
202 {0x4688, GENMASK(1, 0), 0x3},
203 {0x475c, GENMASK(1, 0), 0x3},
204 };
205
206 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
207
208 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
209 {0x4624, GENMASK(20, 14), 0x1a},
210 {0x46f8, GENMASK(20, 14), 0x1a},
211 {0x4674, GENMASK(20, 19), 0x1},
212 {0x4748, GENMASK(20, 19), 0x1},
213 {0x4650, GENMASK(14, 10), 0x12},
214 {0x4724, GENMASK(14, 10), 0x12},
215 {0x4688, GENMASK(1, 0), 0x0},
216 {0x475c, GENMASK(1, 0), 0x0},
217 };
218
219 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
220
221 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
222 {0x00C6,
223 PWR_CV_MSK_B,
224 PWR_INTF_MSK_PCIE,
225 PWR_BASE_MAC,
226 PWR_CMD_WRITE, BIT(6), BIT(6)},
227 {0x1086,
228 PWR_CV_MSK_ALL,
229 PWR_INTF_MSK_SDIO,
230 PWR_BASE_MAC,
231 PWR_CMD_WRITE, BIT(0), 0},
232 {0x1086,
233 PWR_CV_MSK_ALL,
234 PWR_INTF_MSK_SDIO,
235 PWR_BASE_MAC,
236 PWR_CMD_POLL, BIT(1), BIT(1)},
237 {0x0005,
238 PWR_CV_MSK_ALL,
239 PWR_INTF_MSK_ALL,
240 PWR_BASE_MAC,
241 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
242 {0x0005,
243 PWR_CV_MSK_ALL,
244 PWR_INTF_MSK_ALL,
245 PWR_BASE_MAC,
246 PWR_CMD_WRITE, BIT(7), 0},
247 {0x0005,
248 PWR_CV_MSK_ALL,
249 PWR_INTF_MSK_ALL,
250 PWR_BASE_MAC,
251 PWR_CMD_WRITE, BIT(2), 0},
252 {0x0006,
253 PWR_CV_MSK_ALL,
254 PWR_INTF_MSK_ALL,
255 PWR_BASE_MAC,
256 PWR_CMD_POLL, BIT(1), BIT(1)},
257 {0x0006,
258 PWR_CV_MSK_ALL,
259 PWR_INTF_MSK_ALL,
260 PWR_BASE_MAC,
261 PWR_CMD_WRITE, BIT(0), BIT(0)},
262 {0x0005,
263 PWR_CV_MSK_ALL,
264 PWR_INTF_MSK_ALL,
265 PWR_BASE_MAC,
266 PWR_CMD_WRITE, BIT(0), BIT(0)},
267 {0x0005,
268 PWR_CV_MSK_ALL,
269 PWR_INTF_MSK_ALL,
270 PWR_BASE_MAC,
271 PWR_CMD_POLL, BIT(0), 0},
272 {0x106D,
273 PWR_CV_MSK_B | PWR_CV_MSK_C,
274 PWR_INTF_MSK_USB,
275 PWR_BASE_MAC,
276 PWR_CMD_WRITE, BIT(6), 0},
277 {0x0088,
278 PWR_CV_MSK_ALL,
279 PWR_INTF_MSK_ALL,
280 PWR_BASE_MAC,
281 PWR_CMD_WRITE, BIT(0), BIT(0)},
282 {0x0088,
283 PWR_CV_MSK_ALL,
284 PWR_INTF_MSK_ALL,
285 PWR_BASE_MAC,
286 PWR_CMD_WRITE, BIT(0), 0},
287 {0x0088,
288 PWR_CV_MSK_ALL,
289 PWR_INTF_MSK_ALL,
290 PWR_BASE_MAC,
291 PWR_CMD_WRITE, BIT(0), BIT(0)},
292 {0x0088,
293 PWR_CV_MSK_ALL,
294 PWR_INTF_MSK_ALL,
295 PWR_BASE_MAC,
296 PWR_CMD_WRITE, BIT(0), 0},
297 {0x0088,
298 PWR_CV_MSK_ALL,
299 PWR_INTF_MSK_ALL,
300 PWR_BASE_MAC,
301 PWR_CMD_WRITE, BIT(0), BIT(0)},
302 {0x0083,
303 PWR_CV_MSK_ALL,
304 PWR_INTF_MSK_ALL,
305 PWR_BASE_MAC,
306 PWR_CMD_WRITE, BIT(6), 0},
307 {0x0080,
308 PWR_CV_MSK_ALL,
309 PWR_INTF_MSK_ALL,
310 PWR_BASE_MAC,
311 PWR_CMD_WRITE, BIT(5), BIT(5)},
312 {0x0024,
313 PWR_CV_MSK_ALL,
314 PWR_INTF_MSK_ALL,
315 PWR_BASE_MAC,
316 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
317 {0x02A0,
318 PWR_CV_MSK_ALL,
319 PWR_INTF_MSK_ALL,
320 PWR_BASE_MAC,
321 PWR_CMD_WRITE, BIT(1), BIT(1)},
322 {0x02A2,
323 PWR_CV_MSK_ALL,
324 PWR_INTF_MSK_ALL,
325 PWR_BASE_MAC,
326 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
327 {0x0071,
328 PWR_CV_MSK_ALL,
329 PWR_INTF_MSK_PCIE,
330 PWR_BASE_MAC,
331 PWR_CMD_WRITE, BIT(4), 0},
332 {0x0010,
333 PWR_CV_MSK_A,
334 PWR_INTF_MSK_PCIE,
335 PWR_BASE_MAC,
336 PWR_CMD_WRITE, BIT(2), BIT(2)},
337 {0x02A0,
338 PWR_CV_MSK_A,
339 PWR_INTF_MSK_ALL,
340 PWR_BASE_MAC,
341 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
342 {0xFFFF,
343 PWR_CV_MSK_ALL,
344 PWR_INTF_MSK_ALL,
345 0,
346 PWR_CMD_END, 0, 0},
347 };
348
349 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
350 {0x02F0,
351 PWR_CV_MSK_ALL,
352 PWR_INTF_MSK_ALL,
353 PWR_BASE_MAC,
354 PWR_CMD_WRITE, 0xFF, 0},
355 {0x02F1,
356 PWR_CV_MSK_ALL,
357 PWR_INTF_MSK_ALL,
358 PWR_BASE_MAC,
359 PWR_CMD_WRITE, 0xFF, 0},
360 {0x0006,
361 PWR_CV_MSK_ALL,
362 PWR_INTF_MSK_ALL,
363 PWR_BASE_MAC,
364 PWR_CMD_WRITE, BIT(0), BIT(0)},
365 {0x0002,
366 PWR_CV_MSK_ALL,
367 PWR_INTF_MSK_ALL,
368 PWR_BASE_MAC,
369 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
370 {0x0082,
371 PWR_CV_MSK_ALL,
372 PWR_INTF_MSK_ALL,
373 PWR_BASE_MAC,
374 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
375 {0x106D,
376 PWR_CV_MSK_B | PWR_CV_MSK_C,
377 PWR_INTF_MSK_USB,
378 PWR_BASE_MAC,
379 PWR_CMD_WRITE, BIT(6), BIT(6)},
380 {0x0005,
381 PWR_CV_MSK_ALL,
382 PWR_INTF_MSK_ALL,
383 PWR_BASE_MAC,
384 PWR_CMD_WRITE, BIT(1), BIT(1)},
385 {0x0005,
386 PWR_CV_MSK_ALL,
387 PWR_INTF_MSK_ALL,
388 PWR_BASE_MAC,
389 PWR_CMD_POLL, BIT(1), 0},
390 {0x0091,
391 PWR_CV_MSK_ALL,
392 PWR_INTF_MSK_PCIE,
393 PWR_BASE_MAC,
394 PWR_CMD_WRITE, BIT(0), 0},
395 {0x0092,
396 PWR_CV_MSK_ALL,
397 PWR_INTF_MSK_PCIE,
398 PWR_BASE_MAC,
399 PWR_CMD_WRITE, BIT(4), BIT(4)},
400 {0x0005,
401 PWR_CV_MSK_ALL,
402 PWR_INTF_MSK_PCIE,
403 PWR_BASE_MAC,
404 PWR_CMD_WRITE, BIT(2), BIT(2)},
405 {0x0007,
406 PWR_CV_MSK_ALL,
407 PWR_INTF_MSK_USB,
408 PWR_BASE_MAC,
409 PWR_CMD_WRITE, BIT(4), 0},
410 {0x0007,
411 PWR_CV_MSK_ALL,
412 PWR_INTF_MSK_SDIO,
413 PWR_BASE_MAC,
414 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
415 {0x0005,
416 PWR_CV_MSK_ALL,
417 PWR_INTF_MSK_SDIO,
418 PWR_BASE_MAC,
419 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
420 {0x0005,
421 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
422 PWR_CV_MSK_G,
423 PWR_INTF_MSK_USB,
424 PWR_BASE_MAC,
425 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
426 {0x1086,
427 PWR_CV_MSK_ALL,
428 PWR_INTF_MSK_SDIO,
429 PWR_BASE_MAC,
430 PWR_CMD_WRITE, BIT(0), BIT(0)},
431 {0x1086,
432 PWR_CV_MSK_ALL,
433 PWR_INTF_MSK_SDIO,
434 PWR_BASE_MAC,
435 PWR_CMD_POLL, BIT(1), 0},
436 {0xFFFF,
437 PWR_CV_MSK_ALL,
438 PWR_INTF_MSK_ALL,
439 0,
440 PWR_CMD_END, 0, 0},
441 };
442
443 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
444 rtw8852a_pwron, NULL
445 };
446
447 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
448 rtw8852a_pwroff, NULL
449 };
450
451 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
452 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
453 R_AX_H2CREG_DATA3
454 };
455
456 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
457 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
458 R_AX_C2HREG_DATA3
459 };
460
461 static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
462 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
463 };
464
465 static const struct rtw89_page_regs rtw8852a_page_regs = {
466 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
467 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
468 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
469 .ach_page_info = R_AX_ACH0_PAGE_INFO,
470 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
471 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
472 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
473 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
474 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
475 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
476 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
477 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
478 };
479
480 static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
481 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
482 };
483
484 static const struct rtw89_reg_def rtw8852a_nhm_th[RTW89_NHM_TH_NUM] = {
485 {R_NHM_CFG, B_NHM_TH0_MSK},
486 {R_NHM_TH1, B_NHM_TH1_MSK},
487 {R_NHM_TH1, B_NHM_TH2_MSK},
488 {R_NHM_TH1, B_NHM_TH3_MSK},
489 {R_NHM_TH1, B_NHM_TH4_MSK},
490 {R_NHM_TH5, B_NHM_TH5_MSK},
491 {R_NHM_TH5, B_NHM_TH6_MSK},
492 {R_NHM_TH5, B_NHM_TH7_MSK},
493 {R_NHM_TH5, B_NHM_TH8_MSK},
494 {R_NHM_TH9, B_NHM_TH9_MSK},
495 {R_NHM_TH9, B_NHM_TH10_MSK},
496 };
497
498 static const struct rtw89_reg_def rtw8852a_nhm_rpt[RTW89_NHM_RPT_NUM] = {
499 {R_NHM_CNT0, B_NHM_CNT0_MSK},
500 {R_NHM_CNT0, B_NHM_CNT1_MSK},
501 {R_NHM_CNT2, B_NHM_CNT2_MSK},
502 {R_NHM_CNT2, B_NHM_CNT3_MSK},
503 {R_NHM_CNT4, B_NHM_CNT4_MSK},
504 {R_NHM_CNT4, B_NHM_CNT5_MSK},
505 {R_NHM_CNT6, B_NHM_CNT6_MSK},
506 {R_NHM_CNT6, B_NHM_CNT7_MSK},
507 {R_NHM_CNT8, B_NHM_CNT8_MSK},
508 {R_NHM_CNT8, B_NHM_CNT9_MSK},
509 {R_NHM_CNT10, B_NHM_CNT10_MSK},
510 {R_NHM_CNT10, B_NHM_CNT11_MSK},
511 };
512
513 static const struct rtw89_imr_info rtw8852a_imr_info = {
514 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
515 .wsec_imr_reg = R_AX_SEC_DEBUG,
516 .wsec_imr_set = B_AX_IMR_ERROR,
517 .mpdu_tx_imr_set = 0,
518 .mpdu_rx_imr_set = 0,
519 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
520 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
521 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
522 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
523 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
524 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
525 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
526 .wde_imr_clr = B_AX_WDE_IMR_CLR,
527 .wde_imr_set = B_AX_WDE_IMR_SET,
528 .ple_imr_clr = B_AX_PLE_IMR_CLR,
529 .ple_imr_set = B_AX_PLE_IMR_SET,
530 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
531 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
532 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
533 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
534 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
535 .other_disp_imr_set = 0,
536 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
537 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
538 .bbrpt_err_imr_set = 0,
539 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
540 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
541 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
542 .cdma_imr_0_reg = R_AX_DLE_CTRL,
543 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
544 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
545 .cdma_imr_1_reg = 0,
546 .cdma_imr_1_clr = 0,
547 .cdma_imr_1_set = 0,
548 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
549 .phy_intf_imr_clr = 0,
550 .phy_intf_imr_set = 0,
551 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
552 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
553 .rmac_imr_set = B_AX_RMAC_IMR_SET,
554 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
555 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
556 .tmac_imr_set = B_AX_TMAC_IMR_SET,
557 };
558
559 static const struct rtw89_xtal_info rtw8852a_xtal_info = {
560 .xcap_reg = R_AX_XTAL_ON_CTRL0,
561 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
562 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
563 };
564
565 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
566 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
567 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
568 };
569
570 static const struct rtw89_rfkill_regs rtw8852a_rfkill_regs = {
571 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
572 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
573 0xf},
574 .mode = {R_AX_GPIO_EXT_CTRL + 2,
575 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
576 0x0},
577 };
578
579 static const struct rtw89_dig_regs rtw8852a_dig_regs = {
580 .seg0_pd_reg = R_SEG0R_PD,
581 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
582 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
583 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
584 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
585 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
586 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
587 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
588 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
589 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
590 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
591 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
592 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
593 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
594 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
595 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
596 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
597 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
598 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
599 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
600 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
601 };
602
603 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
604 .edcca_level = R_SEG0R_EDCCA_LVL,
605 .edcca_mask = B_EDCCA_LVL_MSK0,
606 .edcca_p_mask = B_EDCCA_LVL_MSK1,
607 .ppdu_level = R_SEG0R_EDCCA_LVL,
608 .ppdu_mask = B_EDCCA_LVL_MSK3,
609 .p = {{
610 .rpt_a = R_EDCCA_RPT_A,
611 .rpt_b = R_EDCCA_RPT_B,
612 .rpt_sel = R_EDCCA_RPT_SEL,
613 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
614 }, {
615 .rpt_a = R_EDCCA_RPT_P1_A,
616 .rpt_b = R_EDCCA_RPT_P1_B,
617 .rpt_sel = R_EDCCA_RPT_SEL,
618 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
619 }},
620 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
621 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
622 };
623
624 static const struct rtw89_pmac_regs rtw8852a_pmac_regs = {
625 .cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
626 .cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
627 .cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
628 .cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
629 .cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
630 .cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
631 .cck_brk = {},
632 .brk = {R_CNT_BRK, B_CNT_BRK},
633 .brk_option = {},
634 .search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
635 .lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
636 .lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
637 .rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
638 .rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
639 .ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
640 .cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
641 .ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
642 .r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
643 .r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
644 .enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
645 .rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
646 .cck_crc32 = R_CNT_CCK_CRC32_P0,
647 .cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
648 .cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
649 .ofdm_txon = R_CNT_OFDMTXON,
650 .ofdm_txon_mask = B_CNT_OFDMTXON,
651 .ofdm_txen_mask = B_CNT_OFDMTXEN,
652 .l_crc = R_CNT_L_CRC,
653 .l_crc_ok_mask = B_CNT_L_CRC_OK,
654 .l_crc_err_mask = B_CNT_L_CRC_ERR,
655 .ht_crc = R_CNT_HT_CRC,
656 .ht_crc_ok_mask = B_CNT_HT_CRC_OK,
657 .ht_crc_err_mask = B_CNT_HT_CRC_ERR,
658 .vht_crc = R_CNT_VHT_CRC,
659 .vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
660 .vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
661 .he_crc = R_CNT_HE_CRC,
662 .he_crc_ok_mask = B_CNT_HE_CRC_OK,
663 .he_crc_err_mask = B_CNT_HE_CRC_ERR,
664 .eht_crc = 0,
665 .eht_crc_ok_mask = 0,
666 .eht_crc_err_mask = 0,
667 .ampdu_crc = R_CNT_AMPDU_RX_CRC32,
668 .ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
669 .ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
670 };
671
rtw8852a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852a_efuse * map)672 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
673 struct rtw8852a_efuse *map)
674 {
675 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
676 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
677 u8 i, j;
678
679 tssi->thermal[RF_PATH_A] = map->path_a_therm;
680 tssi->thermal[RF_PATH_B] = map->path_b_therm;
681
682 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
683 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
684 sizeof(ofst[i]->cck_tssi));
685
686 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
687 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
688 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
689 i, j, tssi->tssi_cck[i][j]);
690
691 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
692 sizeof(ofst[i]->bw40_tssi));
693 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
694 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
695
696 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
697 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
698 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
699 i, j, tssi->tssi_mcs[i][j]);
700 }
701 }
702
rtw8852a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)703 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
704 enum rtw89_efuse_block block)
705 {
706 struct rtw89_efuse *efuse = &rtwdev->efuse;
707 struct rtw8852a_efuse *map;
708
709 map = (struct rtw8852a_efuse *)log_map;
710
711 efuse->country_code[0] = map->country_code[0];
712 efuse->country_code[1] = map->country_code[1];
713 rtw8852a_efuse_parsing_tssi(rtwdev, map);
714
715 switch (rtwdev->hci.type) {
716 case RTW89_HCI_TYPE_PCIE:
717 ether_addr_copy(efuse->addr, map->e.mac_addr);
718 break;
719 case RTW89_HCI_TYPE_USB:
720 ether_addr_copy(efuse->addr, map->u.mac_addr);
721 break;
722 default:
723 return -ENOTSUPP;
724 }
725
726 efuse->rfe_type = map->rfe_type;
727 efuse->xtal_cap = map->xtal_k;
728
729 return 0;
730 }
731
rtw8852a_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)732 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
733 {
734 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
735 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
736 u32 addr = rtwdev->chip->phycap_addr;
737 bool pg = false;
738 u32 ofst;
739 u8 i, j;
740
741 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
742 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
743 /* addrs are in decreasing order */
744 ofst = tssi_trim_addr[i] - addr - j;
745 tssi->tssi_trim[i][j] = phycap_map[ofst];
746
747 if (phycap_map[ofst] != 0xff)
748 pg = true;
749 }
750 }
751
752 if (!pg) {
753 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
754 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
755 "[TSSI][TRIM] no PG, set all trim info to 0\n");
756 }
757
758 for (i = 0; i < RF_PATH_NUM_8852A; i++)
759 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
760 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
761 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
762 i, j, tssi->tssi_trim[i][j],
763 tssi_trim_addr[i] - j);
764 }
765
rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)766 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
767 u8 *phycap_map)
768 {
769 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
770 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
771 u32 addr = rtwdev->chip->phycap_addr;
772 u8 i;
773
774 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
775 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
776
777 rtw89_debug(rtwdev, RTW89_DBG_RFK,
778 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
779 i, info->thermal_trim[i]);
780
781 if (info->thermal_trim[i] != 0xff)
782 info->pg_thermal_trim = true;
783 }
784 }
785
rtw8852a_thermal_trim(struct rtw89_dev * rtwdev)786 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
787 {
788 #define __thm_setting(raw) \
789 ({ \
790 u8 __v = (raw); \
791 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
792 })
793 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
794 u8 i, val;
795
796 if (!info->pg_thermal_trim) {
797 rtw89_debug(rtwdev, RTW89_DBG_RFK,
798 "[THERMAL][TRIM] no PG, do nothing\n");
799
800 return;
801 }
802
803 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
804 val = __thm_setting(info->thermal_trim[i]);
805 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
806
807 rtw89_debug(rtwdev, RTW89_DBG_RFK,
808 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
809 i, val);
810 }
811 #undef __thm_setting
812 }
813
rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)814 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
815 u8 *phycap_map)
816 {
817 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
818 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
819 u32 addr = rtwdev->chip->phycap_addr;
820 u8 i;
821
822 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
823 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
824
825 rtw89_debug(rtwdev, RTW89_DBG_RFK,
826 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
827 i, info->pa_bias_trim[i]);
828
829 if (info->pa_bias_trim[i] != 0xff)
830 info->pg_pa_bias_trim = true;
831 }
832 }
833
rtw8852a_pa_bias_trim(struct rtw89_dev * rtwdev)834 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
835 {
836 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
837 u8 pabias_2g, pabias_5g;
838 u8 i;
839
840 if (!info->pg_pa_bias_trim) {
841 rtw89_debug(rtwdev, RTW89_DBG_RFK,
842 "[PA_BIAS][TRIM] no PG, do nothing\n");
843
844 return;
845 }
846
847 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
848 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
849 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
850
851 rtw89_debug(rtwdev, RTW89_DBG_RFK,
852 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
853 i, pabias_2g, pabias_5g);
854
855 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
856 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
857 }
858 }
859
rtw8852a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)860 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
861 {
862 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
863 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
864 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
865
866 return 0;
867 }
868
rtw8852a_power_trim(struct rtw89_dev * rtwdev)869 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
870 {
871 rtw8852a_thermal_trim(rtwdev);
872 rtw8852a_pa_bias_trim(rtwdev);
873 }
874
rtw8852a_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)875 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
876 const struct rtw89_chan *chan,
877 u8 mac_idx)
878 {
879 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
880 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
881 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
882 u8 txsc20 = 0, txsc40 = 0;
883
884 switch (chan->band_width) {
885 case RTW89_CHANNEL_WIDTH_80:
886 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
887 RTW89_CHANNEL_WIDTH_40);
888 fallthrough;
889 case RTW89_CHANNEL_WIDTH_40:
890 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
891 RTW89_CHANNEL_WIDTH_20);
892 break;
893 default:
894 break;
895 }
896
897 switch (chan->band_width) {
898 case RTW89_CHANNEL_WIDTH_80:
899 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
900 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
901 break;
902 case RTW89_CHANNEL_WIDTH_40:
903 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
904 rtw89_write32(rtwdev, sub_carr, txsc20);
905 break;
906 case RTW89_CHANNEL_WIDTH_20:
907 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
908 rtw89_write32(rtwdev, sub_carr, 0);
909 break;
910 default:
911 break;
912 }
913
914 if (chan->channel > 14)
915 rtw89_write8_set(rtwdev, chk_rate,
916 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
917 else
918 rtw89_write8_clr(rtwdev, chk_rate,
919 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
920 }
921
922 static const u32 rtw8852a_sco_barker_threshold[14] = {
923 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
924 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
925 };
926
927 static const u32 rtw8852a_sco_cck_threshold[14] = {
928 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
929 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
930 };
931
rtw8852a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 central_ch,u8 primary_ch,enum rtw89_bandwidth bw)932 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
933 u8 primary_ch, enum rtw89_bandwidth bw)
934 {
935 u8 ch_element;
936
937 if (bw == RTW89_CHANNEL_WIDTH_20) {
938 ch_element = central_ch - 1;
939 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
940 if (primary_ch == 1)
941 ch_element = central_ch - 1 + 2;
942 else
943 ch_element = central_ch - 1 - 2;
944 } else {
945 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
946 return -EINVAL;
947 }
948 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
949 rtw8852a_sco_barker_threshold[ch_element]);
950 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
951 rtw8852a_sco_cck_threshold[ch_element]);
952
953 return 0;
954 }
955
rtw8852a_ch_setting(struct rtw89_dev * rtwdev,u8 central_ch,u8 path)956 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
957 u8 path)
958 {
959 u32 val;
960
961 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
962 if (val == INV_RF_DATA) {
963 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
964 return;
965 }
966 val &= ~0x303ff;
967 val |= central_ch;
968 if (central_ch > 14)
969 val |= (BIT(16) | BIT(8));
970 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
971 }
972
rtw8852a_sco_mapping(u8 central_ch)973 static u8 rtw8852a_sco_mapping(u8 central_ch)
974 {
975 if (central_ch == 1)
976 return 109;
977 else if (central_ch >= 2 && central_ch <= 6)
978 return 108;
979 else if (central_ch >= 7 && central_ch <= 10)
980 return 107;
981 else if (central_ch >= 11 && central_ch <= 14)
982 return 106;
983 else if (central_ch == 36 || central_ch == 38)
984 return 51;
985 else if (central_ch >= 40 && central_ch <= 58)
986 return 50;
987 else if (central_ch >= 60 && central_ch <= 64)
988 return 49;
989 else if (central_ch == 100 || central_ch == 102)
990 return 48;
991 else if (central_ch >= 104 && central_ch <= 126)
992 return 47;
993 else if (central_ch >= 128 && central_ch <= 151)
994 return 46;
995 else if (central_ch >= 153 && central_ch <= 177)
996 return 45;
997 else
998 return 0;
999 }
1000
rtw8852a_ctrl_ch(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)1001 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
1002 enum rtw89_phy_idx phy_idx)
1003 {
1004 u8 sco_comp;
1005 bool is_2g = central_ch <= 14;
1006
1007 if (phy_idx == RTW89_PHY_0) {
1008 /* Path A */
1009 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
1010 if (is_2g)
1011 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
1012 B_PATH0_TIA_ERR_G1_SEL, 1,
1013 phy_idx);
1014 else
1015 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
1016 B_PATH0_TIA_ERR_G1_SEL, 0,
1017 phy_idx);
1018
1019 /* Path B */
1020 if (!rtwdev->dbcc_en) {
1021 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
1022 if (is_2g)
1023 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
1024 B_P1_MODE_SEL,
1025 1, phy_idx);
1026 else
1027 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
1028 B_P1_MODE_SEL,
1029 0, phy_idx);
1030 } else {
1031 if (is_2g)
1032 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
1033 B_2P4G_BAND_SEL);
1034 else
1035 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
1036 B_2P4G_BAND_SEL);
1037 }
1038 /* SCO compensate FC setting */
1039 sco_comp = rtw8852a_sco_mapping(central_ch);
1040 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
1041 sco_comp, phy_idx);
1042 } else {
1043 /* Path B */
1044 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
1045 if (is_2g)
1046 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
1047 B_P1_MODE_SEL,
1048 1, phy_idx);
1049 else
1050 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
1051 B_P1_MODE_SEL,
1052 0, phy_idx);
1053 /* SCO compensate FC setting */
1054 sco_comp = rtw8852a_sco_mapping(central_ch);
1055 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
1056 sco_comp, phy_idx);
1057 }
1058
1059 /* Band edge */
1060 if (is_2g)
1061 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
1062 phy_idx);
1063 else
1064 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
1065 phy_idx);
1066
1067 /* CCK parameters */
1068 if (central_ch == 14) {
1069 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
1070 0x3b13ff);
1071 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
1072 0x1c42de);
1073 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
1074 0xfdb0ad);
1075 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
1076 0xf60f6e);
1077 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
1078 0xfd8f92);
1079 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1080 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1081 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
1082 0xfff00a);
1083 } else {
1084 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
1085 0x3d23ff);
1086 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
1087 0x29b354);
1088 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1089 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
1090 0xfdb053);
1091 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
1092 0xf86f9a);
1093 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
1094 0xfaef92);
1095 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
1096 0xfe5fcc);
1097 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
1098 0xffdff5);
1099 }
1100 }
1101
rtw8852a_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)1102 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1103 {
1104 u32 val = 0;
1105 u32 adc_sel[2] = {0x12d0, 0x32d0};
1106 u32 wbadc_sel[2] = {0x12ec, 0x32ec};
1107
1108 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
1109 if (val == INV_RF_DATA) {
1110 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
1111 return;
1112 }
1113 val &= ~(BIT(11) | BIT(10));
1114 switch (bw) {
1115 case RTW89_CHANNEL_WIDTH_5:
1116 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1117 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1118 val |= (BIT(11) | BIT(10));
1119 break;
1120 case RTW89_CHANNEL_WIDTH_10:
1121 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1122 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1123 val |= (BIT(11) | BIT(10));
1124 break;
1125 case RTW89_CHANNEL_WIDTH_20:
1126 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1127 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1128 val |= (BIT(11) | BIT(10));
1129 break;
1130 case RTW89_CHANNEL_WIDTH_40:
1131 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1132 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1133 val |= BIT(11);
1134 break;
1135 case RTW89_CHANNEL_WIDTH_80:
1136 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1137 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1138 val |= BIT(10);
1139 break;
1140 default:
1141 rtw89_warn(rtwdev, "Fail to set ADC\n");
1142 }
1143
1144 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
1145 }
1146
1147 static void
rtw8852a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1148 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1149 enum rtw89_phy_idx phy_idx)
1150 {
1151 /* Switch bandwidth */
1152 switch (bw) {
1153 case RTW89_CHANNEL_WIDTH_5:
1154 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1155 phy_idx);
1156 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
1157 phy_idx);
1158 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1159 0x0, phy_idx);
1160 break;
1161 case RTW89_CHANNEL_WIDTH_10:
1162 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1163 phy_idx);
1164 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
1165 phy_idx);
1166 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1167 0x0, phy_idx);
1168 break;
1169 case RTW89_CHANNEL_WIDTH_20:
1170 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1171 phy_idx);
1172 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1173 phy_idx);
1174 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1175 0x0, phy_idx);
1176 break;
1177 case RTW89_CHANNEL_WIDTH_40:
1178 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1179 phy_idx);
1180 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1181 phy_idx);
1182 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1183 pri_ch,
1184 phy_idx);
1185 if (pri_ch == RTW89_SC_20_UPPER)
1186 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1187 else
1188 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1189 break;
1190 case RTW89_CHANNEL_WIDTH_80:
1191 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1192 phy_idx);
1193 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1194 phy_idx);
1195 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1196 pri_ch,
1197 phy_idx);
1198 break;
1199 default:
1200 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1201 pri_ch);
1202 }
1203
1204 if (phy_idx == RTW89_PHY_0) {
1205 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1206 if (!rtwdev->dbcc_en)
1207 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1208 } else {
1209 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1210 }
1211 }
1212
rtw8852a_spur_elimination(struct rtw89_dev * rtwdev,u8 central_ch)1213 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1214 {
1215 if (central_ch == 153) {
1216 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1217 0x210);
1218 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1219 0x210);
1220 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1221 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1222 B_P0_NBIIDX_NOTCH_EN, 0x1);
1223 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1224 B_P1_NBIIDX_NOTCH_EN, 0x1);
1225 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1226 0x1);
1227 } else if (central_ch == 151) {
1228 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1229 0x210);
1230 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1231 0x210);
1232 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1233 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1234 B_P0_NBIIDX_NOTCH_EN, 0x1);
1235 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1236 B_P1_NBIIDX_NOTCH_EN, 0x1);
1237 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1238 0x1);
1239 } else if (central_ch == 155) {
1240 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1241 0x2d0);
1242 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1243 0x2d0);
1244 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1245 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1246 B_P0_NBIIDX_NOTCH_EN, 0x1);
1247 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1248 B_P1_NBIIDX_NOTCH_EN, 0x1);
1249 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1250 0x1);
1251 } else {
1252 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1253 B_P0_NBIIDX_NOTCH_EN, 0x0);
1254 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1255 B_P1_NBIIDX_NOTCH_EN, 0x0);
1256 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1257 0x0);
1258 }
1259 }
1260
rtw8852a_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1261 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1262 enum rtw89_phy_idx phy_idx)
1263 {
1264 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1265 phy_idx);
1266 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1267 phy_idx);
1268 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1269 phy_idx);
1270 }
1271
rtw8852a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool en)1272 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1273 enum rtw89_phy_idx phy_idx, bool en)
1274 {
1275 if (en)
1276 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1277 1,
1278 phy_idx);
1279 else
1280 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1281 0,
1282 phy_idx);
1283 }
1284
rtw8852a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1285 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1286 enum rtw89_phy_idx phy_idx)
1287 {
1288 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1289 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1290 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1291 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1292 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1293 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1294 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1295 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1296 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1297 }
1298
rtw8852a_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1299 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1300 enum rtw89_phy_idx phy_idx)
1301 {
1302 u32 addr;
1303
1304 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1305 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1306 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1307 }
1308
rtw8852a_bb_sethw(struct rtw89_dev * rtwdev)1309 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1310 {
1311 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1312 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1313
1314 if (rtwdev->hal.cv <= CHIP_CCV) {
1315 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1316 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1317 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1318 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1319 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1320 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1321 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1322 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1323 }
1324 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1325 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1326 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1327 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1328 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1329 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1330
1331 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1332 }
1333
rtw8852a_bbrst_for_rfk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1334 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1335 enum rtw89_phy_idx phy_idx)
1336 {
1337 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1338 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1339 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1340 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1341 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1342 udelay(1);
1343 }
1344
rtw8852a_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1345 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1346 const struct rtw89_chan *chan,
1347 enum rtw89_phy_idx phy_idx)
1348 {
1349 bool cck_en = chan->channel <= 14;
1350 u8 pri_ch_idx = chan->pri_ch_idx;
1351
1352 if (cck_en)
1353 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1354 chan->primary_channel,
1355 chan->band_width);
1356
1357 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1358 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1359 if (cck_en) {
1360 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1361 } else {
1362 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1363 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1364 }
1365 rtw8852a_spur_elimination(rtwdev, chan->channel);
1366 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1367 chan->primary_channel);
1368 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1369 }
1370
rtw8852a_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1371 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1372 const struct rtw89_chan *chan,
1373 enum rtw89_mac_idx mac_idx,
1374 enum rtw89_phy_idx phy_idx)
1375 {
1376 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1377 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1378 }
1379
rtw8852a_dfs_en(struct rtw89_dev * rtwdev,bool en)1380 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1381 {
1382 if (en)
1383 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1384 else
1385 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1386 }
1387
rtw8852a_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1388 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1389 enum rtw89_rf_path path)
1390 {
1391 static const u32 tssi_trk[2] = {0x5818, 0x7818};
1392 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1393
1394 if (en) {
1395 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1396 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1397 } else {
1398 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1399 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1400 }
1401 }
1402
rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1403 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1404 u8 phy_idx)
1405 {
1406 if (!rtwdev->dbcc_en) {
1407 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1408 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1409 } else {
1410 if (phy_idx == RTW89_PHY_0)
1411 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1412 else
1413 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1414 }
1415 }
1416
rtw8852a_adc_en(struct rtw89_dev * rtwdev,bool en)1417 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1418 {
1419 if (en)
1420 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1421 0x0);
1422 else
1423 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1424 0xf);
1425 }
1426
rtw8852a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1427 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1428 struct rtw89_channel_help_params *p,
1429 const struct rtw89_chan *chan,
1430 enum rtw89_mac_idx mac_idx,
1431 enum rtw89_phy_idx phy_idx)
1432 {
1433 if (enter) {
1434 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1435 RTW89_SCH_TX_SEL_ALL);
1436 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1437 rtw8852a_dfs_en(rtwdev, false);
1438 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1439 rtw8852a_adc_en(rtwdev, false);
1440 fsleep(40);
1441 rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1442 } else {
1443 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1444 rtw8852a_adc_en(rtwdev, true);
1445 rtw8852a_dfs_en(rtwdev, true);
1446 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1447 rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1448 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1449 }
1450 }
1451
rtw8852a_fem_setup(struct rtw89_dev * rtwdev)1452 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1453 {
1454 struct rtw89_efuse *efuse = &rtwdev->efuse;
1455
1456 switch (efuse->rfe_type) {
1457 case 11:
1458 case 12:
1459 case 17:
1460 case 18:
1461 case 51:
1462 case 53:
1463 rtwdev->fem.epa_2g = true;
1464 rtwdev->fem.elna_2g = true;
1465 fallthrough;
1466 case 9:
1467 case 10:
1468 case 15:
1469 case 16:
1470 rtwdev->fem.epa_5g = true;
1471 rtwdev->fem.elna_5g = true;
1472 break;
1473 default:
1474 break;
1475 }
1476 }
1477
rtw8852a_rfk_init(struct rtw89_dev * rtwdev)1478 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1479 {
1480 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1481 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1482
1483 rtw8852a_rck(rtwdev);
1484 rtw8852a_dack(rtwdev, RTW89_CHANCTX_0);
1485 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true, RTW89_CHANCTX_0);
1486 }
1487
rtw8852a_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)1488 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev,
1489 struct rtw89_vif_link *rtwvif_link)
1490 {
1491 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
1492 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1493
1494 rtw89_btc_ntfy_conn_rfk(rtwdev, true);
1495
1496 rtw8852a_rx_dck(rtwdev, phy_idx, true, chanctx_idx);
1497 rtw8852a_iqk(rtwdev, phy_idx, chanctx_idx);
1498 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
1499 rtw8852a_tssi(rtwdev, phy_idx, chanctx_idx);
1500 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
1501 rtw8852a_dpk(rtwdev, phy_idx, chanctx_idx);
1502
1503 rtw89_btc_ntfy_conn_rfk(rtwdev, false);
1504 }
1505
rtw8852a_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)1506 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1507 enum rtw89_phy_idx phy_idx,
1508 const struct rtw89_chan *chan)
1509 {
1510 rtw8852a_tssi_scan(rtwdev, phy_idx, chan);
1511 }
1512
rtw8852a_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)1513 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev,
1514 struct rtw89_vif_link *rtwvif_link,
1515 bool start)
1516 {
1517 rtw8852a_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx);
1518 }
1519
rtw8852a_rfk_track(struct rtw89_dev * rtwdev)1520 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1521 {
1522 rtw8852a_dpk_track(rtwdev);
1523 rtw8852a_tssi_track(rtwdev);
1524 }
1525
rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1526 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1527 enum rtw89_phy_idx phy_idx, s16 ref)
1528 {
1529 s8 ofst_int = 0;
1530 u8 base_cw_0db = 0x27;
1531 u16 tssi_16dbm_cw = 0x12c;
1532 s16 pwr_s10_3 = 0;
1533 s16 rf_pwr_cw = 0;
1534 u16 bb_pwr_cw = 0;
1535 u32 pwr_cw = 0;
1536 u32 tssi_ofst_cw = 0;
1537
1538 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1539 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1540 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1541 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1542 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1543
1544 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1545 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1546 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1547 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1548
1549 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1550 }
1551
1552 static
rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1553 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1554 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1555 {
1556 s8 val_1t = 0;
1557 s8 val_2t = 0;
1558 u32 reg;
1559
1560 if (pw_ofst < -16 || pw_ofst > 15) {
1561 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1562 pw_ofst);
1563 return;
1564 }
1565 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1566 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1567 val_1t = pw_ofst;
1568 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1569 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1570 val_2t = max(val_1t - 3, -16);
1571 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1572 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1573 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1574 val_1t, val_2t);
1575 }
1576
rtw8852a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1577 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1578 enum rtw89_phy_idx phy_idx)
1579 {
1580 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1581 const u32 mask = 0x7FFFFFF;
1582 const u8 ofst_ofdm = 0x4;
1583 const u8 ofst_cck = 0x8;
1584 s16 ref_ofdm = 0;
1585 s16 ref_cck = 0;
1586 u32 val;
1587 u8 i;
1588
1589 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1590
1591 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1592 GENMASK(27, 10), 0x0);
1593
1594 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1595 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1596
1597 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1598 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1599 phy_idx);
1600
1601 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1602 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1603
1604 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1605 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1606 phy_idx);
1607 }
1608
rtw8852a_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1609 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1610 const struct rtw89_chan *chan,
1611 enum rtw89_phy_idx phy_idx)
1612 {
1613 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1614 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1615 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1616 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1617 }
1618
rtw8852a_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1619 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1620 enum rtw89_phy_idx phy_idx)
1621 {
1622 rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1623 }
1624
1625 static int
rtw8852a_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1626 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1627 {
1628 int ret;
1629
1630 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1631 if (ret)
1632 return ret;
1633
1634 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1635 if (ret)
1636 return ret;
1637
1638 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1639 if (ret)
1640 return ret;
1641
1642 return 0;
1643 }
1644
rtw8852a_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1645 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1646 {
1647 u8 i = 0;
1648 u32 addr, val;
1649
1650 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1651 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1652 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1653 rtw89_phy_write32(rtwdev, addr, val);
1654 }
1655 }
1656
rtw8852a_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1657 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1658 struct rtw8852a_bb_pmac_info *tx_info,
1659 enum rtw89_phy_idx idx)
1660 {
1661 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1662 if (tx_info->mode == CONT_TX)
1663 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1664 idx);
1665 else if (tx_info->mode == PKTS_TX)
1666 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1667 idx);
1668 }
1669
rtw8852a_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1670 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1671 struct rtw8852a_bb_pmac_info *tx_info,
1672 enum rtw89_phy_idx idx)
1673 {
1674 enum rtw8852a_pmac_mode mode = tx_info->mode;
1675 u32 pkt_cnt = tx_info->tx_cnt;
1676 u16 period = tx_info->period;
1677
1678 if (mode == CONT_TX && !tx_info->is_cck) {
1679 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1680 idx);
1681 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1682 } else if (mode == PKTS_TX) {
1683 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1684 idx);
1685 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1686 B_PMAC_TX_PRD_MSK, period, idx);
1687 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1688 pkt_cnt, idx);
1689 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1690 }
1691 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1692 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1693 }
1694
rtw8852a_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1695 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1696 struct rtw8852a_bb_pmac_info *tx_info,
1697 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1698 {
1699 if (!tx_info->en_pmac_tx) {
1700 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1701 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1702 if (chan->band_type == RTW89_BAND_2G)
1703 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1704 return;
1705 }
1706 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1707 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1708 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1709 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1710 idx);
1711 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1712 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1713 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1714 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1715 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1716 }
1717
rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1718 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1719 u16 tx_cnt, u16 period, u16 tx_time,
1720 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1721 {
1722 struct rtw8852a_bb_pmac_info tx_info = {0};
1723
1724 tx_info.en_pmac_tx = enable;
1725 tx_info.is_cck = 0;
1726 tx_info.mode = PKTS_TX;
1727 tx_info.tx_cnt = tx_cnt;
1728 tx_info.period = period;
1729 tx_info.tx_time = tx_time;
1730 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan);
1731 }
1732
rtw8852a_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1733 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1734 enum rtw89_phy_idx idx)
1735 {
1736 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1737 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1738 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1739 }
1740
rtw8852a_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1741 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1742 {
1743 u32 rst_mask0 = 0;
1744 u32 rst_mask1 = 0;
1745
1746 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1747 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1748 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1749 if (!rtwdev->dbcc_en) {
1750 if (tx_path == RF_PATH_A) {
1751 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1752 B_TXPATH_SEL_MSK, 1);
1753 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1754 B_TXNSS_MAP_MSK, 0);
1755 } else if (tx_path == RF_PATH_B) {
1756 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1757 B_TXPATH_SEL_MSK, 2);
1758 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1759 B_TXNSS_MAP_MSK, 0);
1760 } else if (tx_path == RF_PATH_AB) {
1761 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1762 B_TXPATH_SEL_MSK, 3);
1763 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1764 B_TXNSS_MAP_MSK, 4);
1765 } else {
1766 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1767 }
1768 } else {
1769 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1770 1);
1771 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1772 RTW89_PHY_1);
1773 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1774 0);
1775 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1776 RTW89_PHY_1);
1777 }
1778 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1779 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1780 if (tx_path == RF_PATH_A) {
1781 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1782 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1783 } else {
1784 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1785 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1786 }
1787 }
1788
rtw8852a_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1789 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1790 enum rtw89_phy_idx idx, u8 mode)
1791 {
1792 if (mode != 0)
1793 return;
1794 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1795 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1796 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1797 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1798 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1799 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1800 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1801 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1802 }
1803
rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1804 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1805 enum rtw89_phy_idx phy_idx)
1806 {
1807 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl :
1808 &rtw8852a_btc_preagc_dis_defs_tbl);
1809 }
1810
rtw8852a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1811 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1812 {
1813 if (rtwdev->is_tssi_mode[rf_path]) {
1814 u32 addr = 0x1c10 + (rf_path << 13);
1815
1816 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1817 }
1818
1819 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1820 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1821 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1822
1823 fsleep(200);
1824
1825 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1826 }
1827
rtw8852a_btc_set_rfe(struct rtw89_dev * rtwdev)1828 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1829 {
1830 struct rtw89_btc_module *md = &rtwdev->btc.mdinfo;
1831
1832 md->rfe_type = rtwdev->efuse.rfe_type;
1833 md->kt_ver = rtwdev->hal.cv;
1834 md->bt_solo = 0;
1835 md->bt0_sw_type = BTC_SWITCH_INTERNAL;
1836
1837 if (md->rfe_type > 0)
1838 md->ant.num = (md->rfe_type % 2 ? 2 : 3);
1839 else
1840 md->ant.num = 2;
1841
1842 md->ant.diversity = 0;
1843 md->ant.isolation = 10;
1844
1845 if (md->ant.num == 3) {
1846 md->ant.type = BTC_ANT_DEDICATED;
1847 md->bt0_pos = BTC_BT_ALONE;
1848 } else {
1849 md->ant.type = BTC_ANT_SHARED;
1850 md->bt0_pos = BTC_BT_BTG;
1851 }
1852 rtwdev->btc.btg_pos = md->ant.btg_pos;
1853 rtwdev->btc.ant_type = md->ant.type;
1854 }
1855
1856 static
rtw8852a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1857 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1858 {
1859 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1860 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1861 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1862 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1863 }
1864
rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1865 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1866 enum rtw89_phy_idx phy_idx)
1867 {
1868 if (en) {
1869 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1870 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1871 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1872 } else {
1873 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1874 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1875 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1876 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1877 }
1878 }
1879
rtw8852a_btc_init_cfg(struct rtw89_dev * rtwdev)1880 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1881 {
1882 struct rtw89_btc *btc = &rtwdev->btc;
1883 const struct rtw89_chip_info *chip = rtwdev->chip;
1884 const struct rtw89_mac_ax_coex coex_params = {
1885 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1886 .direction = RTW89_MAC_AX_COEX_INNER,
1887 };
1888
1889 /* PTA init */
1890 rtw89_mac_coex_init(rtwdev, &coex_params);
1891
1892 /* set WL Tx response = Hi-Pri */
1893 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1894 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1895
1896 /* set rf gnt debug off */
1897 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1898 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1899
1900 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1901 if (btc->ant_type == BTC_ANT_SHARED) {
1902 rtw8852a_set_trx_mask(rtwdev,
1903 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1904 rtw8852a_set_trx_mask(rtwdev,
1905 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1906 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1907 rtw8852a_set_trx_mask(rtwdev,
1908 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1909 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1910 rtw8852a_set_trx_mask(rtwdev,
1911 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1912 rtw8852a_set_trx_mask(rtwdev,
1913 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1914 }
1915
1916 /* set PTA break table */
1917 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1918
1919 /* enable BT counter 0xda40[16,2] = 2b'11 */
1920 rtw89_write32_set(rtwdev,
1921 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1922 }
1923
1924 static
rtw8852a_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1925 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1926 {
1927 u32 bitmap = 0;
1928 u32 reg = 0;
1929
1930 switch (map) {
1931 case BTC_PRI_MASK_TX_RESP:
1932 reg = R_BTC_BT_COEX_MSK_TABLE;
1933 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1934 break;
1935 case BTC_PRI_MASK_BEACON:
1936 reg = R_AX_WL_PRI_MSK;
1937 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1938 break;
1939 default:
1940 return;
1941 }
1942
1943 if (state)
1944 rtw89_write32_set(rtwdev, reg, bitmap);
1945 else
1946 rtw89_write32_clr(rtwdev, reg, bitmap);
1947 }
1948
__btc_ctrl_val_all_time(u32 ctrl)1949 static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1950 {
1951 return FIELD_GET(GENMASK(15, 0), ctrl);
1952 }
1953
__btc_ctrl_rst_all_time(u32 cur)1954 static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1955 {
1956 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1957 }
1958
__btc_ctrl_gen_all_time(u32 cur,u32 val)1959 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1960 {
1961 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1962 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1963
1964 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1965 }
1966
__btc_ctrl_val_gnt_bt(u32 ctrl)1967 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1968 {
1969 return FIELD_GET(GENMASK(31, 16), ctrl);
1970 }
1971
__btc_ctrl_rst_gnt_bt(u32 cur)1972 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1973 {
1974 return cur & ~B_AX_TXAGC_BT_EN;
1975 }
1976
__btc_ctrl_gen_gnt_bt(u32 cur,u32 val)1977 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1978 {
1979 u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1980 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1981
1982 return ov | iv | B_AX_TXAGC_BT_EN;
1983 }
1984
1985 static void
rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)1986 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1987 {
1988 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1989 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1990
1991 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1992 #define __handle(_case) \
1993 do { \
1994 const u32 _reg = __btc_cr_ ## _case; \
1995 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \
1996 u32 _cur, _wrt; \
1997 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1998 "btc ctrl %s: 0x%x\n", #_case, _val); \
1999 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
2000 break; \
2001 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
2002 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \
2003 _wrt = __do_clr(_val) ? \
2004 __btc_ctrl_rst_ ## _case(_cur) : \
2005 __btc_ctrl_gen_ ## _case(_cur, _val); \
2006 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
2007 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
2008 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \
2009 } while (0)
2010
2011 __handle(all_time);
2012 __handle(gnt_bt);
2013
2014 #undef __handle
2015 #undef __do_clr
2016 }
2017
2018 static
rtw8852a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2019 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2020 {
2021 /* +6 for compensate offset */
2022 return clamp_t(s8, val + 6, -100, 0) + 100;
2023 }
2024
2025 static struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8852a_rf_ul_v0[] = {
2026 {255, 0, 0, 7}, /* 0 -> original */
2027 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2028 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2029 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2030 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2031 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2032 {6, 1, 0, 7},
2033 {13, 1, 0, 7},
2034 {13, 1, 0, 7}
2035 };
2036
2037 static struct rtw89_btc_rf_trx_para_v0 rtw89_btc_8852a_rf_dl_v0[] = {
2038 {255, 0, 0, 7}, /* 0 -> original */
2039 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2040 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2041 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2042 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2043 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
2044 {255, 1, 0, 7},
2045 {255, 1, 0, 7},
2046 {255, 1, 0, 7}
2047 };
2048
2049 static const
2050 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2051 static const
2052 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
2053
2054 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
2055 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
2056 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
2057 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
2058 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
2059 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
2060 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
2061 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
2062 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
2063 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
2064 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
2065 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2066 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
2067 };
2068
2069 static
rtw8852a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2070 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2071 {
2072 struct rtw89_btc *btc = &rtwdev->btc;
2073 const struct rtw89_btc_ver *ver = btc->ver;
2074 struct rtw89_btc_cx *cx = &btc->cx;
2075 u32 val;
2076
2077 if (ver->fcxbtcrpt != 1)
2078 return;
2079
2080 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
2081 cx->bt0.bcnt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
2082 cx->bt0.bcnt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
2083
2084 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
2085 cx->bt0.bcnt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
2086 cx->bt0.bcnt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
2087
2088 /* clock-gate off before reset counter*/
2089 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2090 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
2091 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
2092 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
2093 }
2094
2095 static
rtw8852a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2096 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2097 {
2098 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2099 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2100 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
2101
2102 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2103 if (state)
2104 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2105 RFREG_MASK, 0xa2d7c);
2106 else
2107 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2108 RFREG_MASK, 0xa2020);
2109
2110 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2111 }
2112
rtw8852a_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)2113 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2114 {
2115 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2116 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2117 * To improve BT ACI in co-rx
2118 */
2119
2120 switch (level) {
2121 case 0: /* default */
2122 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2123 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2124 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2125 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2126 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2127 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2128 break;
2129 case 1: /* Fix LNA2=5 */
2130 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2131 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2132 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2133 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2134 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2135 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2136 break;
2137 }
2138 }
2139
rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2140 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2141 {
2142 struct rtw89_btc *btc = &rtwdev->btc;
2143
2144 switch (level) {
2145 case 0: /* original */
2146 default:
2147 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2148 btc->dm.wl_lna2 = 0;
2149 break;
2150 case 1: /* for FDD free-run */
2151 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
2152 btc->dm.wl_lna2 = 0;
2153 break;
2154 case 2: /* for BTG Co-Rx*/
2155 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2156 btc->dm.wl_lna2 = 1;
2157 break;
2158 }
2159
2160 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2161 }
2162
rtw8852a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2163 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2164 struct rtw89_rx_phy_ppdu *phy_ppdu,
2165 struct ieee80211_rx_status *status)
2166 {
2167 u16 chan = phy_ppdu->chan_idx;
2168 u8 band;
2169
2170 if (chan == 0)
2171 return;
2172
2173 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
2174 status->freq = ieee80211_channel_to_frequency(chan, band);
2175 status->band = band;
2176 }
2177
rtw8852a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2178 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
2179 struct rtw89_rx_phy_ppdu *phy_ppdu,
2180 struct ieee80211_rx_status *status)
2181 {
2182 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, phy_ppdu->phy_idx);
2183 u8 *rx_power = phy_ppdu->rssi;
2184 u8 path;
2185 u8 raw;
2186
2187 if (!status->signal) {
2188 if (phy_ppdu->to_self && ewma_rssi_read(&bb->bcn_rssi))
2189 raw = ewma_rssi_read(&bb->bcn_rssi);
2190 else
2191 raw = max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]);
2192
2193 status->signal = RTW89_RSSI_RAW_TO_DBM(raw);
2194 }
2195
2196 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2197 status->chains |= BIT(path);
2198 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2199 }
2200 if (phy_ppdu->valid)
2201 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2202 }
2203
2204 #define DECLARE_DIG_TABLE(name) \
2205 static const struct rtw89_phy_dig_gain_cfg name##_table = { \
2206 .table = name, \
2207 .size = ARRAY_SIZE(name) \
2208 }
2209
2210 static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {
2211 {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK},
2212 {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK},
2213 {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK},
2214 {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK},
2215 {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK},
2216 {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK},
2217 {R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK},
2218 };
2219
2220 DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);
2221
2222 static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {
2223 {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK},
2224 {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK},
2225 };
2226
2227 DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);
2228
2229 static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {
2230 {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK},
2231 {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK},
2232 {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK},
2233 {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK},
2234 {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK},
2235 {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK},
2236 {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK},
2237 };
2238
2239 DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);
2240
2241 static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {
2242 {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK},
2243 {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK},
2244 };
2245
2246 DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);
2247
2248 static const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {
2249 .cfg_lna_g = &rtw89_8852a_lna_gain_g_table,
2250 .cfg_tia_g = &rtw89_8852a_tia_gain_g_table,
2251 .cfg_lna_a = &rtw89_8852a_lna_gain_a_table,
2252 .cfg_tia_a = &rtw89_8852a_tia_gain_a_table
2253 };
2254
2255 #ifdef CONFIG_PM
2256 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
2257 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2258 .n_patterns = RTW89_MAX_PATTERN_NUM,
2259 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2260 .pattern_min_len = 1,
2261 };
2262 #endif
2263
2264 static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2265 .enable_bb_rf = rtw89_mac_enable_bb_rf,
2266 .disable_bb_rf = rtw89_mac_disable_bb_rf,
2267 .bb_preinit = NULL,
2268 .bb_postinit = NULL,
2269 .bb_reset = rtw8852a_bb_reset,
2270 .bb_sethw = rtw8852a_bb_sethw,
2271 .read_rf = rtw89_phy_read_rf,
2272 .write_rf = rtw89_phy_write_rf,
2273 .set_channel = rtw8852a_set_channel,
2274 .set_channel_help = rtw8852a_set_channel_help,
2275 .read_efuse = rtw8852a_read_efuse,
2276 .read_phycap = rtw8852a_read_phycap,
2277 .fem_setup = rtw8852a_fem_setup,
2278 .data_setup = NULL,
2279 .rfe_gpio = NULL,
2280 .rfk_hw_init = NULL,
2281 .rfk_init = rtw8852a_rfk_init,
2282 .rfk_init_late = NULL,
2283 .rfk_channel = rtw8852a_rfk_channel,
2284 .rfk_band_changed = rtw8852a_rfk_band_changed,
2285 .rfk_scan = rtw8852a_rfk_scan,
2286 .rfk_track = rtw8852a_rfk_track,
2287 .power_trim = rtw8852a_power_trim,
2288 .set_txpwr = rtw8852a_set_txpwr,
2289 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl,
2290 .init_txpwr_unit = rtw8852a_init_txpwr_unit,
2291 .get_thermal = rtw8852a_get_thermal,
2292 .chan_to_rf18_val = NULL,
2293 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx,
2294 .query_ppdu = rtw8852a_query_ppdu,
2295 .convert_rpl_to_rssi = NULL,
2296 .phy_rpt_to_rssi = NULL,
2297 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx,
2298 .cfg_txrx_path = NULL,
2299 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
2300 .digital_pwr_comp = NULL,
2301 .calc_rx_gain_normal = NULL,
2302 .path_diff_update = NULL,
2303 .pwr_on_func = NULL,
2304 .pwr_off_func = NULL,
2305 .query_rxdesc = rtw89_core_query_rxdesc,
2306 .fill_txdesc = rtw89_core_fill_txdesc,
2307 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2308 .get_ch_dma = {rtw89_core_get_ch_dma,
2309 rtw89_core_get_ch_dma_v2,
2310 NULL,},
2311 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2312 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2313 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2314 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2315 .h2c_dctl_sec_cam = NULL,
2316 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
2317 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
2318 .h2c_ampdu_cmac_tbl = NULL,
2319 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
2320 .h2c_punctured_cmac_tbl = NULL,
2321 .h2c_default_dmac_tbl = NULL,
2322 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2323 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2324 .h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
2325
2326 .btc_set_rfe = rtw8852a_btc_set_rfe,
2327 .btc_init_cfg = rtw8852a_btc_init_cfg,
2328 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
2329 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
2330 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
2331 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
2332 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
2333 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
2334 .btc_set_policy = rtw89_btc_set_policy,
2335 };
2336
2337 const struct rtw89_chip_info rtw8852a_chip_info = {
2338 .chip_id = RTL8852A,
2339 .chip_gen = RTW89_CHIP_AX,
2340 .ops = &rtw8852a_chip_ops,
2341 .mac_def = &rtw89_mac_gen_ax,
2342 .phy_def = &rtw89_phy_gen_ax,
2343 .fw_def = {
2344 .fw_basename = RTW8852A_FW_BASENAME,
2345 .fw_format_max = RTW8852A_FW_FORMAT_MAX,
2346 .fw_b_aid = 0,
2347 },
2348 .try_ce_fw = false,
2349 .bbmcu_nr = 0,
2350 .needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_RTL8852A |
2351 BIT(__RTW89_FW_ELEMENT_ID_INTL_TRANSITION),
2352 .fw_blacklist = NULL,
2353 .fifo_size = 458752,
2354 .small_fifo_size = false,
2355 .dle_scc_rsvd_size = 0,
2356 .max_amsdu_limit = 3500,
2357 .max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2358 .max_eht_mpdu_cap = 0,
2359 .max_tx_agg_num = 128,
2360 .max_rx_agg_num = 64,
2361 .dis_2g_40m_ul_ofdma = true,
2362 .rsvd_ple_ofst = 0x6f800,
2363 .qta_def = {
2364 .hfc_param_ini = {rtw8852a_hfc_param_ini_pcie,
2365 rtw8852a_hfc_param_ini_usb,
2366 rtw8852a_hfc_param_ini_usb,
2367 NULL},
2368 .dle_mem = {rtw8852a_dle_mem_pcie,
2369 rtw8852a_dle_mem_usb,
2370 rtw8852a_dle_mem_usb,
2371 NULL},
2372 },
2373 .wde_qempty_acq_grpnum = 16,
2374 .wde_qempty_mgq_grpsel = 16,
2375 .rf_base_addr = {0xc000, 0xd000},
2376 .thermal_th = {0x32, 0x35},
2377 .pwr_on_seq = pwr_on_seq_8852a,
2378 .pwr_off_seq = pwr_off_seq_8852a,
2379 .bb_table = &rtw89_8852a_phy_bb_table,
2380 .bb_gain_table = NULL,
2381 .rf_table = {&rtw89_8852a_phy_radioa_table,
2382 &rtw89_8852a_phy_radiob_table,},
2383 .nctl_table = &rtw89_8852a_phy_nctl_table,
2384 .nctl_post_table = NULL,
2385 .dflt_parms = &rtw89_8852a_dflt_parms,
2386 .rfe_parms_conf = NULL,
2387 .txpwr_factor_bb = 3,
2388 .txpwr_factor_rf = 2,
2389 .txpwr_factor_mac = 1,
2390 .dig_table = &rtw89_8852a_phy_dig_table,
2391 .dig_regs = &rtw8852a_dig_regs,
2392 .tssi_dbw_table = NULL,
2393 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
2394 .support_link_num = 0,
2395 .support_chanctx_num = 1,
2396 .support_rnr = false,
2397 .support_bands = BIT(NL80211_BAND_2GHZ) |
2398 BIT(NL80211_BAND_5GHZ),
2399 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2400 BIT(NL80211_CHAN_WIDTH_40) |
2401 BIT(NL80211_CHAN_WIDTH_80),
2402 .support_unii4 = false,
2403 .support_ant_gain = false,
2404 .support_tas = false,
2405 .support_sar_by_ant = false,
2406 .support_noise = true,
2407 .support_fw_cmd_ofld = false,
2408 .ul_tb_waveform_ctrl = false,
2409 .ul_tb_pwr_diff = false,
2410 .rx_freq_from_ie = true,
2411 .hw_sec_hdr = false,
2412 .hw_mgmt_tx_encrypt = false,
2413 .hw_tkip_crypto = false,
2414 .hw_mlo_bmc_crypto = false,
2415 .rf_path_num = 2,
2416 .tx_nss = 2,
2417 .rx_nss = 2,
2418 .acam_num = 128,
2419 .bcam_num = 10,
2420 .scam_num = 128,
2421 .bacam_num = 2,
2422 .bacam_dynamic_num = 4,
2423 .bacam_ver = RTW89_BACAM_V0,
2424 .addrcam_ver = 0,
2425 .ppdu_max_usr = 4,
2426 .sec_ctrl_efuse_size = 4,
2427 .physical_efuse_size = 1216,
2428 .logical_efuse_size = 1536,
2429 .limit_efuse_size = 1152,
2430 .dav_phy_efuse_size = 0,
2431 .dav_log_efuse_size = 0,
2432 .efuse_blocks = NULL,
2433 .phycap_addr = 0x580,
2434 .phycap_size = 128,
2435 .para_ver = 0x0,
2436 .wlcx_desired = 0x06000000,
2437 .scbd = 0x1,
2438 .mailbox = 0x1,
2439
2440 .afh_guard_ch = 6,
2441 .fdd_iso_freq = 1000,
2442 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres,
2443 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres,
2444 .rssi_tol = 2,
2445 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2446 .mon_reg = rtw89_btc_8852a_mon_reg,
2447 .rf_para_ulink_v0 = rtw89_btc_8852a_rf_ul_v0,
2448 .rf_para_dlink_v0 = rtw89_btc_8852a_rf_dl_v0,
2449 .rf_para_ulink_num_v0 = ARRAY_SIZE(rtw89_btc_8852a_rf_ul_v0),
2450 .rf_para_dlink_num_v0 = ARRAY_SIZE(rtw89_btc_8852a_rf_dl_v0),
2451 .rf_para_ulink_v9 = NULL,
2452 .rf_para_dlink_v9 = NULL,
2453 .rf_para_ulink_num_v9 = 0,
2454 .rf_para_dlink_num_v9 = 0,
2455 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2456 BIT(RTW89_PS_MODE_CLK_GATED) |
2457 BIT(RTW89_PS_MODE_PWR_GATED),
2458 .low_power_hci_modes = 0,
2459 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2460 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2461 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2462 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2463 .txwd_info_size = sizeof(struct rtw89_txwd_info),
2464 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2465 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2466 .h2c_regs = rtw8852a_h2c_regs,
2467 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2468 .c2h_regs = rtw8852a_c2h_regs,
2469 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2470 .page_regs = &rtw8852a_page_regs,
2471 .wow_reason_reg = rtw8852a_wow_wakeup_regs,
2472 .cfo_src_fd = false,
2473 .cfo_hw_comp = false,
2474 .dcfo_comp = &rtw8852a_dcfo_comp,
2475 .dcfo_comp_sft = 10,
2476 .nhm_report = &rtw8852a_nhm_rpt,
2477 .nhm_th = &rtw8852a_nhm_th,
2478 .imr_info = &rtw8852a_imr_info,
2479 .imr_dmac_table = NULL,
2480 .imr_cmac_table = NULL,
2481 .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
2482 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
2483 .bss_clr_map_reg = R_BSS_CLR_MAP,
2484 .rfkill_init = &rtw8852a_rfkill_regs,
2485 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
2486 .btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
2487 .dma_ch_mask = 0,
2488 .edcca_regs = &rtw8852a_edcca_regs,
2489 .pmac_regs = &rtw8852a_pmac_regs,
2490 #ifdef CONFIG_PM
2491 .wowlan_stub = &rtw_wowlan_stub_8852a,
2492 #endif
2493 .xtal_info = &rtw8852a_xtal_info,
2494 .default_quirks = 0,
2495 .txtime_limit_2ghz = 0,
2496 };
2497 EXPORT_SYMBOL(rtw8852a_chip_info);
2498
2499 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE);
2500 MODULE_AUTHOR("Realtek Corporation");
2501 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2502 MODULE_LICENSE("Dual BSD/GPL");
2503