xref: /linux/drivers/usb/phy/phy-tegra-usb.c (revision 4eee1520ea845a6d6d82e85498d9412419560871)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2010 Google, Inc.
4  * Copyright (C) 2013 NVIDIA Corporation
5  *
6  * Author:
7  *	Erik Gilling <konkers@google.com>
8  *	Benoit Goby <benoit@android.com>
9  *	Venu Byravarasu <vbyravarasu@nvidia.com>
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/export.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/resource.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 
25 #include <linux/regulator/consumer.h>
26 
27 #include <linux/usb/ehci_def.h>
28 #include <linux/usb/of.h>
29 #include <linux/usb/tegra_usb_phy.h>
30 #include <linux/usb/ulpi.h>
31 
32 #define ULPI_VIEWPORT				0x170
33 
34 /* PORTSC PTS/PHCD bits, Tegra20 only */
35 #define TEGRA_USB_PORTSC1			0x184
36 #define TEGRA_USB_PORTSC1_PTS(x)		(((x) & 0x3) << 30)
37 #define TEGRA_USB_PORTSC1_PHCD			BIT(23)
38 
39 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
40 #define TEGRA_USB_HOSTPC1_DEVLC			0x1b4
41 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)		(((x) & 0x7) << 29)
42 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD		BIT(22)
43 
44 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
45 #define TEGRA_PORTSC1_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_OCC)
46 
47 #define USB_SUSP_CTRL				0x400
48 #define   USB_WAKE_ON_RESUME_EN			BIT(2)
49 #define   USB_WAKE_ON_CNNT_EN_DEV		BIT(3)
50 #define   USB_WAKE_ON_DISCON_EN_DEV		BIT(4)
51 #define   USB_SUSP_CLR				BIT(5)
52 #define   USB_PHY_CLK_VALID			BIT(7)
53 #define   UTMIP_RESET				BIT(11)
54 #define   UHSIC_RESET				BIT(11)
55 #define   UTMIP_PHY_ENABLE			BIT(12)
56 #define   ULPI_PHY_ENABLE			BIT(13)
57 #define   USB_SUSP_SET				BIT(14)
58 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)		(((x) & 0x7) << 16)
59 
60 #define USB_PHY_VBUS_SENSORS			0x404
61 #define   B_SESS_VLD_WAKEUP_EN			BIT(14)
62 #define   A_SESS_VLD_WAKEUP_EN			BIT(22)
63 #define   A_VBUS_VLD_WAKEUP_EN			BIT(30)
64 
65 #define USB_PHY_VBUS_WAKEUP_ID			0x408
66 #define   ID_INT_EN				BIT(0)
67 #define   ID_CHG_DET				BIT(1)
68 #define   VBUS_WAKEUP_INT_EN			BIT(8)
69 #define   VBUS_WAKEUP_CHG_DET			BIT(9)
70 #define   VBUS_WAKEUP_STS			BIT(10)
71 #define   VBUS_WAKEUP_WAKEUP_EN			BIT(30)
72 
73 #define USB1_LEGACY_CTRL			0x410
74 #define   USB1_NO_LEGACY_MODE			BIT(0)
75 #define   USB1_VBUS_SENSE_CTL_MASK		(3 << 1)
76 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP	(0 << 1)
77 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
78 						(1 << 1)
79 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD	(2 << 1)
80 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD	(3 << 1)
81 
82 #define ULPI_TIMING_CTRL_0			0x424
83 #define   ULPI_OUTPUT_PINMUX_BYP		BIT(10)
84 #define   ULPI_CLKOUT_PINMUX_BYP		BIT(11)
85 
86 #define ULPI_TIMING_CTRL_1			0x428
87 #define   ULPI_DATA_TRIMMER_LOAD		BIT(0)
88 #define   ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
89 #define   ULPI_STPDIRNXT_TRIMMER_LOAD		BIT(16)
90 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x)		(((x) & 0x7) << 17)
91 #define   ULPI_DIR_TRIMMER_LOAD			BIT(24)
92 #define   ULPI_DIR_TRIMMER_SEL(x)		(((x) & 0x7) << 25)
93 
94 #define UTMIP_PLL_CFG1				0x804
95 #define   UTMIP_XTAL_FREQ_COUNT(x)		(((x) & 0xfff) << 0)
96 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)	(((x) & 0x1f) << 27)
97 
98 #define UTMIP_XCVR_CFG0				0x808
99 #define   UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
100 #define   UTMIP_XCVR_SETUP_MSB(x)		((((x) & 0x70) >> 4) << 22)
101 #define   UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
102 #define   UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
103 #define   UTMIP_FORCE_PD_POWERDOWN		BIT(14)
104 #define   UTMIP_FORCE_PD2_POWERDOWN		BIT(16)
105 #define   UTMIP_FORCE_PDZI_POWERDOWN		BIT(18)
106 #define   UTMIP_XCVR_LSBIAS_SEL			BIT(21)
107 #define   UTMIP_XCVR_HSSLEW(x)			(((x) & 0x3) << 4)
108 #define   UTMIP_XCVR_HSSLEW_MSB(x)		((((x) & 0x1fc) >> 2) << 25)
109 
110 #define UTMIP_BIAS_CFG0				0x80c
111 #define   UTMIP_OTGPD				BIT(11)
112 #define   UTMIP_BIASPD				BIT(10)
113 #define   UTMIP_HSSQUELCH_LEVEL(x)		(((x) & 0x3) << 0)
114 #define   UTMIP_HSDISCON_LEVEL(x)		(((x) & 0x3) << 2)
115 #define   UTMIP_HSDISCON_LEVEL_MSB(x)		((((x) & 0x4) >> 2) << 24)
116 
117 #define UTMIP_HSRX_CFG0				0x810
118 #define   UTMIP_ELASTIC_LIMIT(x)		(((x) & 0x1f) << 10)
119 #define   UTMIP_IDLE_WAIT(x)			(((x) & 0x1f) << 15)
120 
121 #define UTMIP_HSRX_CFG1				0x814
122 #define   UTMIP_HS_SYNC_START_DLY(x)		(((x) & 0x1f) << 1)
123 
124 #define UTMIP_TX_CFG0				0x820
125 #define   UTMIP_FS_PREABMLE_J			BIT(19)
126 #define   UTMIP_HS_DISCON_DISABLE		BIT(8)
127 
128 #define UTMIP_MISC_CFG0				0x824
129 #define   UTMIP_DPDM_OBSERVE			BIT(26)
130 #define   UTMIP_DPDM_OBSERVE_SEL(x)		(((x) & 0xf) << 27)
131 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J		UTMIP_DPDM_OBSERVE_SEL(0xf)
132 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K		UTMIP_DPDM_OBSERVE_SEL(0xe)
133 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1		UTMIP_DPDM_OBSERVE_SEL(0xd)
134 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0		UTMIP_DPDM_OBSERVE_SEL(0xc)
135 #define   UTMIP_SUSPEND_EXIT_ON_EDGE		BIT(22)
136 
137 #define UTMIP_MISC_CFG1				0x828
138 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)		(((x) & 0x1f) << 18)
139 #define   UTMIP_PLLU_STABLE_COUNT(x)		(((x) & 0xfff) << 6)
140 
141 #define UTMIP_DEBOUNCE_CFG0			0x82c
142 #define   UTMIP_BIAS_DEBOUNCE_A(x)		(((x) & 0xffff) << 0)
143 
144 #define UTMIP_BAT_CHRG_CFG0			0x830
145 #define   UTMIP_PD_CHRG				BIT(0)
146 
147 #define UTMIP_SPARE_CFG0			0x834
148 #define   FUSE_SETUP_SEL			BIT(3)
149 
150 #define UTMIP_XCVR_CFG1				0x838
151 #define   UTMIP_FORCE_PDDISC_POWERDOWN		BIT(0)
152 #define   UTMIP_FORCE_PDCHRP_POWERDOWN		BIT(2)
153 #define   UTMIP_FORCE_PDDR_POWERDOWN		BIT(4)
154 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)		(((x) & 0xf) << 18)
155 
156 #define UTMIP_BIAS_CFG1				0x83c
157 #define   UTMIP_BIAS_PDTRK_COUNT(x)		(((x) & 0x1f) << 3)
158 
159 /* For Tegra30 and above only, the address is different in Tegra20 */
160 #define USB_USBMODE				0x1f8
161 #define   USB_USBMODE_MASK			(3 << 0)
162 #define   USB_USBMODE_HOST			(3 << 0)
163 #define   USB_USBMODE_DEVICE			(2 << 0)
164 
165 #define PMC_USB_AO				0xf0
166 #define   VBUS_WAKEUP_PD_P0			BIT(2)
167 #define   ID_PD_P0				BIT(3)
168 
169 static DEFINE_SPINLOCK(utmip_pad_lock);
170 static unsigned int utmip_pad_count;
171 
172 struct tegra_xtal_freq {
173 	unsigned int freq;
174 	u8 enable_delay;
175 	u8 stable_count;
176 	u8 active_delay;
177 	u8 xtal_freq_count;
178 	u16 debounce;
179 };
180 
181 static const struct tegra_xtal_freq tegra_freq_table[] = {
182 	{
183 		.freq = 12000000,
184 		.enable_delay = 0x02,
185 		.stable_count = 0x2F,
186 		.active_delay = 0x04,
187 		.xtal_freq_count = 0x76,
188 		.debounce = 0x7530,
189 	},
190 	{
191 		.freq = 13000000,
192 		.enable_delay = 0x02,
193 		.stable_count = 0x33,
194 		.active_delay = 0x05,
195 		.xtal_freq_count = 0x7F,
196 		.debounce = 0x7EF4,
197 	},
198 	{
199 		.freq = 19200000,
200 		.enable_delay = 0x03,
201 		.stable_count = 0x4B,
202 		.active_delay = 0x06,
203 		.xtal_freq_count = 0xBB,
204 		.debounce = 0xBB80,
205 	},
206 	{
207 		.freq = 26000000,
208 		.enable_delay = 0x04,
209 		.stable_count = 0x66,
210 		.active_delay = 0x09,
211 		.xtal_freq_count = 0xFE,
212 		.debounce = 0xFDE8,
213 	},
214 };
215 
to_tegra_usb_phy(struct usb_phy * u_phy)216 static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
217 {
218 	return container_of(u_phy, struct tegra_usb_phy, u_phy);
219 }
220 
set_pts(struct tegra_usb_phy * phy,u8 pts_val)221 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
222 {
223 	void __iomem *base = phy->regs;
224 	u32 val;
225 
226 	if (phy->soc_config->has_hostpc) {
227 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
228 		val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
229 		val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
230 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
231 	} else {
232 		val = readl_relaxed(base + TEGRA_USB_PORTSC1);
233 		val &= ~TEGRA_PORTSC1_RWC_BITS;
234 		val &= ~TEGRA_USB_PORTSC1_PTS(~0);
235 		val |= TEGRA_USB_PORTSC1_PTS(pts_val);
236 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
237 	}
238 }
239 
set_phcd(struct tegra_usb_phy * phy,bool enable)240 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
241 {
242 	void __iomem *base = phy->regs;
243 	u32 val;
244 
245 	if (phy->soc_config->has_hostpc) {
246 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
247 		if (enable)
248 			val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
249 		else
250 			val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
251 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
252 	} else {
253 		val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
254 		if (enable)
255 			val |= TEGRA_USB_PORTSC1_PHCD;
256 		else
257 			val &= ~TEGRA_USB_PORTSC1_PHCD;
258 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
259 	}
260 }
261 
utmip_pad_open(struct tegra_usb_phy * phy)262 static int utmip_pad_open(struct tegra_usb_phy *phy)
263 {
264 	int ret;
265 
266 	ret = clk_prepare_enable(phy->pad_clk);
267 	if (ret) {
268 		dev_err(phy->u_phy.dev,
269 			"Failed to enable UTMI-pads clock: %d\n", ret);
270 		return ret;
271 	}
272 
273 	spin_lock(&utmip_pad_lock);
274 
275 	ret = reset_control_deassert(phy->pad_rst);
276 	if (ret) {
277 		dev_err(phy->u_phy.dev,
278 			"Failed to initialize UTMI-pads reset: %d\n", ret);
279 		goto unlock;
280 	}
281 
282 	ret = reset_control_assert(phy->pad_rst);
283 	if (ret) {
284 		dev_err(phy->u_phy.dev,
285 			"Failed to assert UTMI-pads reset: %d\n", ret);
286 		goto unlock;
287 	}
288 
289 	udelay(1);
290 
291 	ret = reset_control_deassert(phy->pad_rst);
292 	if (ret)
293 		dev_err(phy->u_phy.dev,
294 			"Failed to deassert UTMI-pads reset: %d\n", ret);
295 unlock:
296 	spin_unlock(&utmip_pad_lock);
297 
298 	clk_disable_unprepare(phy->pad_clk);
299 
300 	return ret;
301 }
302 
utmip_pad_close(struct tegra_usb_phy * phy)303 static int utmip_pad_close(struct tegra_usb_phy *phy)
304 {
305 	int ret;
306 
307 	ret = clk_prepare_enable(phy->pad_clk);
308 	if (ret) {
309 		dev_err(phy->u_phy.dev,
310 			"Failed to enable UTMI-pads clock: %d\n", ret);
311 		return ret;
312 	}
313 
314 	ret = reset_control_assert(phy->pad_rst);
315 	if (ret)
316 		dev_err(phy->u_phy.dev,
317 			"Failed to assert UTMI-pads reset: %d\n", ret);
318 
319 	udelay(1);
320 
321 	clk_disable_unprepare(phy->pad_clk);
322 
323 	return ret;
324 }
325 
utmip_pad_power_on(struct tegra_usb_phy * phy)326 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
327 {
328 	struct tegra_utmip_config *config = phy->config;
329 	void __iomem *base = phy->pad_regs;
330 	u32 val;
331 	int err;
332 
333 	err = clk_prepare_enable(phy->pad_clk);
334 	if (err)
335 		return err;
336 
337 	spin_lock(&utmip_pad_lock);
338 
339 	if (utmip_pad_count++ == 0) {
340 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
341 		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
342 
343 		if (phy->soc_config->requires_extra_tuning_parameters) {
344 			val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
345 				UTMIP_HSDISCON_LEVEL(~0) |
346 				UTMIP_HSDISCON_LEVEL_MSB(~0));
347 
348 			val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
349 			val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
350 			val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
351 		}
352 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
353 	}
354 
355 	if (phy->pad_wakeup) {
356 		phy->pad_wakeup = false;
357 		utmip_pad_count--;
358 	}
359 
360 	spin_unlock(&utmip_pad_lock);
361 
362 	clk_disable_unprepare(phy->pad_clk);
363 
364 	return 0;
365 }
366 
utmip_pad_power_off(struct tegra_usb_phy * phy)367 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
368 {
369 	void __iomem *base = phy->pad_regs;
370 	u32 val;
371 	int ret;
372 
373 	ret = clk_prepare_enable(phy->pad_clk);
374 	if (ret)
375 		return ret;
376 
377 	spin_lock(&utmip_pad_lock);
378 
379 	if (!utmip_pad_count) {
380 		dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
381 		ret = -EINVAL;
382 		goto ulock;
383 	}
384 
385 	/*
386 	 * In accordance to TRM, OTG and Bias pad circuits could be turned off
387 	 * to save power if wake is enabled, but the VBUS-change detection
388 	 * method is board-specific and these circuits may need to be enabled
389 	 * to generate wakeup event, hence we will just keep them both enabled.
390 	 */
391 	if (phy->wakeup_enabled) {
392 		phy->pad_wakeup = true;
393 		utmip_pad_count++;
394 	}
395 
396 	if (--utmip_pad_count == 0) {
397 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
398 		val |= UTMIP_OTGPD | UTMIP_BIASPD;
399 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
400 	}
401 ulock:
402 	spin_unlock(&utmip_pad_lock);
403 
404 	clk_disable_unprepare(phy->pad_clk);
405 
406 	return ret;
407 }
408 
utmi_wait_register(void __iomem * reg,u32 mask,u32 result)409 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
410 {
411 	u32 tmp;
412 
413 	return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
414 					  2000, 6000);
415 }
416 
utmi_phy_clk_disable(struct tegra_usb_phy * phy)417 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
418 {
419 	void __iomem *base = phy->regs;
420 	u32 val;
421 
422 	/*
423 	 * The USB driver may have already initiated the phy clock
424 	 * disable so wait to see if the clock turns off and if not
425 	 * then proceed with gating the clock.
426 	 */
427 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
428 		return;
429 
430 	if (phy->is_legacy_phy) {
431 		val = readl_relaxed(base + USB_SUSP_CTRL);
432 		val |= USB_SUSP_SET;
433 		writel_relaxed(val, base + USB_SUSP_CTRL);
434 
435 		usleep_range(10, 100);
436 
437 		val = readl_relaxed(base + USB_SUSP_CTRL);
438 		val &= ~USB_SUSP_SET;
439 		writel_relaxed(val, base + USB_SUSP_CTRL);
440 	} else {
441 		set_phcd(phy, true);
442 	}
443 
444 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
445 		dev_err(phy->u_phy.dev,
446 			"Timeout waiting for PHY to stabilize on disable\n");
447 }
448 
utmi_phy_clk_enable(struct tegra_usb_phy * phy)449 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
450 {
451 	void __iomem *base = phy->regs;
452 	u32 val;
453 
454 	/*
455 	 * The USB driver may have already initiated the phy clock
456 	 * enable so wait to see if the clock turns on and if not
457 	 * then proceed with ungating the clock.
458 	 */
459 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
460 			       USB_PHY_CLK_VALID) == 0)
461 		return;
462 
463 	if (phy->is_legacy_phy) {
464 		val = readl_relaxed(base + USB_SUSP_CTRL);
465 		val |= USB_SUSP_CLR;
466 		writel_relaxed(val, base + USB_SUSP_CTRL);
467 
468 		usleep_range(10, 100);
469 
470 		val = readl_relaxed(base + USB_SUSP_CTRL);
471 		val &= ~USB_SUSP_CLR;
472 		writel_relaxed(val, base + USB_SUSP_CTRL);
473 	} else {
474 		set_phcd(phy, false);
475 	}
476 
477 	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
478 			       USB_PHY_CLK_VALID))
479 		dev_err(phy->u_phy.dev,
480 			"Timeout waiting for PHY to stabilize on enable\n");
481 }
482 
utmi_phy_power_on(struct tegra_usb_phy * phy)483 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
484 {
485 	struct tegra_utmip_config *config = phy->config;
486 	void __iomem *base = phy->regs;
487 	u32 val;
488 	int err;
489 
490 	val = readl_relaxed(base + USB_SUSP_CTRL);
491 	val |= UTMIP_RESET;
492 	writel_relaxed(val, base + USB_SUSP_CTRL);
493 
494 	if (phy->is_legacy_phy) {
495 		val = readl_relaxed(base + USB1_LEGACY_CTRL);
496 		val |= USB1_NO_LEGACY_MODE;
497 		writel_relaxed(val, base + USB1_LEGACY_CTRL);
498 	}
499 
500 	val = readl_relaxed(base + UTMIP_TX_CFG0);
501 	val |= UTMIP_FS_PREABMLE_J;
502 	writel_relaxed(val, base + UTMIP_TX_CFG0);
503 
504 	val = readl_relaxed(base + UTMIP_HSRX_CFG0);
505 	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
506 	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
507 	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
508 	writel_relaxed(val, base + UTMIP_HSRX_CFG0);
509 
510 	val = readl_relaxed(base + UTMIP_HSRX_CFG1);
511 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
512 	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
513 	writel_relaxed(val, base + UTMIP_HSRX_CFG1);
514 
515 	val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
516 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
517 	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
518 	writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
519 
520 	val = readl_relaxed(base + UTMIP_MISC_CFG0);
521 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
522 	writel_relaxed(val, base + UTMIP_MISC_CFG0);
523 
524 	if (!phy->soc_config->utmi_pll_config_in_car_module) {
525 		val = readl_relaxed(base + UTMIP_MISC_CFG1);
526 		val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
527 			UTMIP_PLLU_STABLE_COUNT(~0));
528 		val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
529 			UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
530 		writel_relaxed(val, base + UTMIP_MISC_CFG1);
531 
532 		val = readl_relaxed(base + UTMIP_PLL_CFG1);
533 		val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
534 			UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
535 		val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
536 			UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
537 		writel_relaxed(val, base + UTMIP_PLL_CFG1);
538 	}
539 
540 	val = readl_relaxed(base + USB_SUSP_CTRL);
541 	val &= ~USB_WAKE_ON_RESUME_EN;
542 	writel_relaxed(val, base + USB_SUSP_CTRL);
543 
544 	if (phy->mode != USB_DR_MODE_HOST) {
545 		val = readl_relaxed(base + USB_SUSP_CTRL);
546 		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
547 		writel_relaxed(val, base + USB_SUSP_CTRL);
548 
549 		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
550 		val &= ~VBUS_WAKEUP_WAKEUP_EN;
551 		val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
552 		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
553 
554 		val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
555 		val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);
556 		val &= ~(B_SESS_VLD_WAKEUP_EN);
557 		writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
558 
559 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
560 		val &= ~UTMIP_PD_CHRG;
561 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
562 	} else {
563 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
564 		val |= UTMIP_PD_CHRG;
565 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
566 	}
567 
568 	err = utmip_pad_power_on(phy);
569 	if (err)
570 		return err;
571 
572 	val = readl_relaxed(base + UTMIP_XCVR_CFG0);
573 	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
574 		 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
575 		 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
576 		 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
577 
578 	if (!config->xcvr_setup_use_fuses) {
579 		val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
580 		val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
581 	}
582 	val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
583 	val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
584 
585 	if (phy->soc_config->requires_extra_tuning_parameters) {
586 		val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
587 		val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
588 		val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
589 	}
590 	writel_relaxed(val, base + UTMIP_XCVR_CFG0);
591 
592 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
593 	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
594 		 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
595 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
596 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);
597 
598 	val = readl_relaxed(base + UTMIP_BIAS_CFG1);
599 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
600 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
601 	writel_relaxed(val, base + UTMIP_BIAS_CFG1);
602 
603 	val = readl_relaxed(base + UTMIP_SPARE_CFG0);
604 	if (config->xcvr_setup_use_fuses)
605 		val |= FUSE_SETUP_SEL;
606 	else
607 		val &= ~FUSE_SETUP_SEL;
608 	writel_relaxed(val, base + UTMIP_SPARE_CFG0);
609 
610 	if (!phy->is_legacy_phy) {
611 		val = readl_relaxed(base + USB_SUSP_CTRL);
612 		val |= UTMIP_PHY_ENABLE;
613 		writel_relaxed(val, base + USB_SUSP_CTRL);
614 	}
615 
616 	val = readl_relaxed(base + USB_SUSP_CTRL);
617 	val &= ~UTMIP_RESET;
618 	writel_relaxed(val, base + USB_SUSP_CTRL);
619 
620 	if (phy->is_legacy_phy) {
621 		val = readl_relaxed(base + USB1_LEGACY_CTRL);
622 		val &= ~USB1_VBUS_SENSE_CTL_MASK;
623 		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
624 		writel_relaxed(val, base + USB1_LEGACY_CTRL);
625 
626 		val = readl_relaxed(base + USB_SUSP_CTRL);
627 		val &= ~USB_SUSP_SET;
628 		writel_relaxed(val, base + USB_SUSP_CTRL);
629 	}
630 
631 	utmi_phy_clk_enable(phy);
632 
633 	if (phy->soc_config->requires_usbmode_setup) {
634 		val = readl_relaxed(base + USB_USBMODE);
635 		val &= ~USB_USBMODE_MASK;
636 		if (phy->mode == USB_DR_MODE_HOST)
637 			val |= USB_USBMODE_HOST;
638 		else
639 			val |= USB_USBMODE_DEVICE;
640 		writel_relaxed(val, base + USB_USBMODE);
641 	}
642 
643 	if (!phy->is_legacy_phy)
644 		set_pts(phy, 0);
645 
646 	return 0;
647 }
648 
utmi_phy_power_off(struct tegra_usb_phy * phy)649 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
650 {
651 	void __iomem *base = phy->regs;
652 	u32 val;
653 
654 	/*
655 	 * Give hardware time to settle down after VBUS disconnection,
656 	 * otherwise PHY will immediately wake up from suspend.
657 	 */
658 	if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST)
659 		readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
660 					   val, !(val & VBUS_WAKEUP_STS),
661 					   5000, 100000);
662 
663 	utmi_phy_clk_disable(phy);
664 
665 	/* PHY won't resume if reset is asserted */
666 	if (!phy->wakeup_enabled) {
667 		val = readl_relaxed(base + USB_SUSP_CTRL);
668 		val |= UTMIP_RESET;
669 		writel_relaxed(val, base + USB_SUSP_CTRL);
670 	}
671 
672 	val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
673 	val |= UTMIP_PD_CHRG;
674 	writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
675 
676 	if (!phy->wakeup_enabled) {
677 		val = readl_relaxed(base + UTMIP_XCVR_CFG0);
678 		val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
679 		       UTMIP_FORCE_PDZI_POWERDOWN;
680 		writel_relaxed(val, base + UTMIP_XCVR_CFG0);
681 	}
682 
683 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
684 	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
685 	       UTMIP_FORCE_PDDR_POWERDOWN;
686 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);
687 
688 	if (phy->wakeup_enabled) {
689 		val = readl_relaxed(base + USB_SUSP_CTRL);
690 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
691 		val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
692 		val |= USB_WAKE_ON_RESUME_EN;
693 		writel_relaxed(val, base + USB_SUSP_CTRL);
694 
695 		/*
696 		 * Ask VBUS sensor to generate wake event once cable is
697 		 * connected.
698 		 */
699 		if (phy->mode != USB_DR_MODE_HOST) {
700 			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
701 			val |= VBUS_WAKEUP_WAKEUP_EN;
702 			val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
703 			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
704 
705 			val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
706 			val |= A_VBUS_VLD_WAKEUP_EN;
707 			writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
708 		}
709 	}
710 
711 	return utmip_pad_power_off(phy);
712 }
713 
ulpi_phy_power_on(struct tegra_usb_phy * phy)714 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
715 {
716 	void __iomem *base = phy->regs;
717 	u32 val;
718 	int err;
719 
720 	gpiod_set_value_cansleep(phy->reset_gpio, 1);
721 
722 	err = clk_prepare_enable(phy->clk);
723 	if (err)
724 		return err;
725 
726 	usleep_range(5000, 6000);
727 
728 	gpiod_set_value_cansleep(phy->reset_gpio, 0);
729 
730 	usleep_range(1000, 2000);
731 
732 	val = readl_relaxed(base + USB_SUSP_CTRL);
733 	val |= UHSIC_RESET;
734 	writel_relaxed(val, base + USB_SUSP_CTRL);
735 
736 	val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
737 	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
738 	writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
739 
740 	val = readl_relaxed(base + USB_SUSP_CTRL);
741 	val |= ULPI_PHY_ENABLE;
742 	writel_relaxed(val, base + USB_SUSP_CTRL);
743 
744 	val = 0;
745 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
746 
747 	val |= ULPI_DATA_TRIMMER_SEL(4);
748 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
749 	val |= ULPI_DIR_TRIMMER_SEL(4);
750 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
751 	usleep_range(10, 100);
752 
753 	val |= ULPI_DATA_TRIMMER_LOAD;
754 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
755 	val |= ULPI_DIR_TRIMMER_LOAD;
756 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
757 
758 	/* Fix VbusInvalid due to floating VBUS */
759 	err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
760 	if (err) {
761 		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
762 		goto disable_clk;
763 	}
764 
765 	err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
766 	if (err) {
767 		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
768 		goto disable_clk;
769 	}
770 
771 	val = readl_relaxed(base + USB_SUSP_CTRL);
772 	val |= USB_SUSP_CLR;
773 	writel_relaxed(val, base + USB_SUSP_CTRL);
774 	usleep_range(100, 1000);
775 
776 	val = readl_relaxed(base + USB_SUSP_CTRL);
777 	val &= ~USB_SUSP_CLR;
778 	writel_relaxed(val, base + USB_SUSP_CTRL);
779 
780 	return 0;
781 
782 disable_clk:
783 	clk_disable_unprepare(phy->clk);
784 
785 	return err;
786 }
787 
ulpi_phy_power_off(struct tegra_usb_phy * phy)788 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
789 {
790 	gpiod_set_value_cansleep(phy->reset_gpio, 1);
791 	usleep_range(5000, 6000);
792 	clk_disable_unprepare(phy->clk);
793 
794 	/*
795 	 * Wakeup currently unimplemented for ULPI, thus PHY needs to be
796 	 * force-resumed.
797 	 */
798 	if (WARN_ON_ONCE(phy->wakeup_enabled)) {
799 		ulpi_phy_power_on(phy);
800 		return -EOPNOTSUPP;
801 	}
802 
803 	return 0;
804 }
805 
tegra_usb_phy_power_on(struct tegra_usb_phy * phy)806 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
807 {
808 	int err;
809 
810 	if (phy->powered_on)
811 		return 0;
812 
813 	if (phy->is_ulpi_phy)
814 		err = ulpi_phy_power_on(phy);
815 	else
816 		err = utmi_phy_power_on(phy);
817 	if (err)
818 		return err;
819 
820 	phy->powered_on = true;
821 
822 	/* Let PHY settle down */
823 	usleep_range(2000, 2500);
824 
825 	return 0;
826 }
827 
tegra_usb_phy_power_off(struct tegra_usb_phy * phy)828 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
829 {
830 	int err;
831 
832 	if (!phy->powered_on)
833 		return 0;
834 
835 	if (phy->is_ulpi_phy)
836 		err = ulpi_phy_power_off(phy);
837 	else
838 		err = utmi_phy_power_off(phy);
839 	if (err)
840 		return err;
841 
842 	phy->powered_on = false;
843 
844 	return 0;
845 }
846 
tegra_usb_phy_shutdown(struct usb_phy * u_phy)847 static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
848 {
849 	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
850 
851 	if (WARN_ON(!phy->freq))
852 		return;
853 
854 	usb_phy_set_wakeup(u_phy, false);
855 	tegra_usb_phy_power_off(phy);
856 
857 	if (!phy->is_ulpi_phy)
858 		utmip_pad_close(phy);
859 
860 	regulator_disable(phy->vbus);
861 	clk_disable_unprepare(phy->pll_u);
862 
863 	phy->freq = NULL;
864 }
865 
tegra_usb_phy_isr(int irq,void * data)866 static irqreturn_t tegra_usb_phy_isr(int irq, void *data)
867 {
868 	u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET;
869 	struct tegra_usb_phy *phy = data;
870 	void __iomem *base = phy->regs;
871 
872 	/*
873 	 * The PHY interrupt also wakes the USB controller driver since
874 	 * interrupt is shared. We don't do anything in the PHY driver,
875 	 * so just clear the interrupt.
876 	 */
877 	val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
878 	writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
879 
880 	return val & int_mask ? IRQ_HANDLED : IRQ_NONE;
881 }
882 
tegra_usb_phy_set_wakeup(struct usb_phy * u_phy,bool enable)883 static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
884 {
885 	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
886 	void __iomem *base = phy->regs;
887 	int ret = 0;
888 	u32 val;
889 
890 	if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST &&
891 	    phy->irq > 0) {
892 		disable_irq(phy->irq);
893 
894 		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
895 		val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN);
896 		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
897 
898 		enable_irq(phy->irq);
899 
900 		free_irq(phy->irq, phy);
901 
902 		phy->wakeup_enabled = false;
903 	}
904 
905 	if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) {
906 		ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED,
907 				  dev_name(phy->u_phy.dev), phy);
908 		if (!ret) {
909 			disable_irq(phy->irq);
910 
911 			/*
912 			 * USB clock will be resumed once wake event will be
913 			 * generated.  The ID-change event requires to have
914 			 * interrupts enabled, otherwise it won't be generated.
915 			 */
916 			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
917 			val |= ID_INT_EN | VBUS_WAKEUP_INT_EN;
918 			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
919 
920 			enable_irq(phy->irq);
921 		} else {
922 			dev_err(phy->u_phy.dev,
923 				"Failed to request interrupt: %d", ret);
924 			enable = false;
925 		}
926 	}
927 
928 	phy->wakeup_enabled = enable;
929 
930 	return ret;
931 }
932 
tegra_usb_phy_set_suspend(struct usb_phy * u_phy,int suspend)933 static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
934 {
935 	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
936 	int ret;
937 
938 	if (WARN_ON(!phy->freq))
939 		return -EINVAL;
940 
941 	/*
942 	 * PHY is sharing IRQ with the CI driver, hence here we either
943 	 * disable interrupt for both PHY and CI or for CI only.  The
944 	 * interrupt needs to be disabled while hardware is reprogrammed
945 	 * because interrupt touches the programmed registers, and thus,
946 	 * there could be a race condition.
947 	 */
948 	if (phy->irq > 0)
949 		disable_irq(phy->irq);
950 
951 	if (suspend)
952 		ret = tegra_usb_phy_power_off(phy);
953 	else
954 		ret = tegra_usb_phy_power_on(phy);
955 
956 	if (phy->irq > 0)
957 		enable_irq(phy->irq);
958 
959 	return ret;
960 }
961 
tegra_usb_phy_configure_pmc(struct tegra_usb_phy * phy)962 static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy)
963 {
964 	int err, val = 0;
965 
966 	/* older device-trees don't have PMC regmap */
967 	if (!phy->pmc_regmap)
968 		return 0;
969 
970 	/*
971 	 * Tegra20 has a different layout of PMC USB register bits and AO is
972 	 * enabled by default after system reset on Tegra20, so assume nothing
973 	 * to do on Tegra20.
974 	 */
975 	if (!phy->soc_config->requires_pmc_ao_power_up)
976 		return 0;
977 
978 	/* enable VBUS wake-up detector */
979 	if (phy->mode != USB_DR_MODE_HOST)
980 		val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4;
981 
982 	/* enable ID-pin ACC detector for OTG mode switching */
983 	if (phy->mode == USB_DR_MODE_OTG)
984 		val |= ID_PD_P0 << phy->instance * 4;
985 
986 	/* disable detectors to reset them */
987 	err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);
988 	if (err) {
989 		dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err);
990 		return err;
991 	}
992 
993 	usleep_range(10, 100);
994 
995 	/* enable detectors */
996 	err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val);
997 	if (err) {
998 		dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err);
999 		return err;
1000 	}
1001 
1002 	/* detectors starts to work after 10ms */
1003 	usleep_range(10000, 15000);
1004 
1005 	return 0;
1006 }
1007 
tegra_usb_phy_init(struct usb_phy * u_phy)1008 static int tegra_usb_phy_init(struct usb_phy *u_phy)
1009 {
1010 	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1011 	unsigned long parent_rate;
1012 	unsigned int i;
1013 	int err;
1014 
1015 	if (WARN_ON(phy->freq))
1016 		return 0;
1017 
1018 	err = clk_prepare_enable(phy->pll_u);
1019 	if (err)
1020 		return err;
1021 
1022 	parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
1023 	for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
1024 		if (tegra_freq_table[i].freq == parent_rate) {
1025 			phy->freq = &tegra_freq_table[i];
1026 			break;
1027 		}
1028 	}
1029 	if (!phy->freq) {
1030 		dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
1031 			parent_rate);
1032 		err = -EINVAL;
1033 		goto disable_clk;
1034 	}
1035 
1036 	err = regulator_enable(phy->vbus);
1037 	if (err) {
1038 		dev_err(phy->u_phy.dev,
1039 			"Failed to enable USB VBUS regulator: %d\n", err);
1040 		goto disable_clk;
1041 	}
1042 
1043 	if (!phy->is_ulpi_phy) {
1044 		err = utmip_pad_open(phy);
1045 		if (err)
1046 			goto disable_vbus;
1047 	}
1048 
1049 	err = tegra_usb_phy_configure_pmc(phy);
1050 	if (err)
1051 		goto close_phy;
1052 
1053 	err = tegra_usb_phy_power_on(phy);
1054 	if (err)
1055 		goto close_phy;
1056 
1057 	return 0;
1058 
1059 close_phy:
1060 	if (!phy->is_ulpi_phy)
1061 		utmip_pad_close(phy);
1062 
1063 disable_vbus:
1064 	regulator_disable(phy->vbus);
1065 
1066 disable_clk:
1067 	clk_disable_unprepare(phy->pll_u);
1068 
1069 	phy->freq = NULL;
1070 
1071 	return err;
1072 }
1073 
read_utmi_param(struct platform_device * pdev,const char * param,u8 * dest)1074 static int read_utmi_param(struct platform_device *pdev, const char *param,
1075 			   u8 *dest)
1076 {
1077 	u32 value;
1078 	int err;
1079 
1080 	err = of_property_read_u32(pdev->dev.of_node, param, &value);
1081 	if (err)
1082 		dev_err(&pdev->dev,
1083 			"Failed to read USB UTMI parameter %s: %d\n",
1084 			param, err);
1085 	else
1086 		*dest = value;
1087 
1088 	return err;
1089 }
1090 
utmi_phy_probe(struct tegra_usb_phy * tegra_phy,struct platform_device * pdev)1091 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
1092 			  struct platform_device *pdev)
1093 {
1094 	struct tegra_utmip_config *config;
1095 	struct resource *res;
1096 	int err;
1097 
1098 	tegra_phy->is_ulpi_phy = false;
1099 
1100 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1101 	if (!res) {
1102 		dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
1103 		return  -ENXIO;
1104 	}
1105 
1106 	/*
1107 	 * Note that UTMI pad registers are shared by all PHYs, therefore
1108 	 * devm_platform_ioremap_resource() can't be used here.
1109 	 */
1110 	tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
1111 					   resource_size(res));
1112 	if (!tegra_phy->pad_regs) {
1113 		dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
1114 		return -ENOMEM;
1115 	}
1116 
1117 	tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
1118 					 GFP_KERNEL);
1119 	if (!tegra_phy->config)
1120 		return -ENOMEM;
1121 
1122 	config = tegra_phy->config;
1123 
1124 	err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
1125 			      &config->hssync_start_delay);
1126 	if (err)
1127 		return err;
1128 
1129 	err = read_utmi_param(pdev, "nvidia,elastic-limit",
1130 			      &config->elastic_limit);
1131 	if (err)
1132 		return err;
1133 
1134 	err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1135 			      &config->idle_wait_delay);
1136 	if (err)
1137 		return err;
1138 
1139 	err = read_utmi_param(pdev, "nvidia,term-range-adj",
1140 			      &config->term_range_adj);
1141 	if (err)
1142 		return err;
1143 
1144 	err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1145 			      &config->xcvr_lsfslew);
1146 	if (err)
1147 		return err;
1148 
1149 	err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1150 			      &config->xcvr_lsrslew);
1151 	if (err)
1152 		return err;
1153 
1154 	if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1155 		err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1156 				      &config->xcvr_hsslew);
1157 		if (err)
1158 			return err;
1159 
1160 		err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1161 				      &config->hssquelch_level);
1162 		if (err)
1163 			return err;
1164 
1165 		err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1166 				      &config->hsdiscon_level);
1167 		if (err)
1168 			return err;
1169 	}
1170 
1171 	config->xcvr_setup_use_fuses = of_property_read_bool(
1172 		pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1173 
1174 	if (!config->xcvr_setup_use_fuses) {
1175 		err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1176 				      &config->xcvr_setup);
1177 		if (err)
1178 			return err;
1179 	}
1180 
1181 	return 0;
1182 }
1183 
tegra_usb_phy_put_pmc_device(void * dev)1184 static void tegra_usb_phy_put_pmc_device(void *dev)
1185 {
1186 	put_device(dev);
1187 }
1188 
tegra_usb_phy_parse_pmc(struct device * dev,struct tegra_usb_phy * phy)1189 static int tegra_usb_phy_parse_pmc(struct device *dev,
1190 				   struct tegra_usb_phy *phy)
1191 {
1192 	struct platform_device *pmc_pdev;
1193 	struct of_phandle_args args;
1194 	int err;
1195 
1196 	err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc",
1197 					       1, 0, &args);
1198 	if (err) {
1199 		if (err != -ENOENT)
1200 			return err;
1201 
1202 		dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n");
1203 		return 0;
1204 	}
1205 
1206 	pmc_pdev = of_find_device_by_node(args.np);
1207 	of_node_put(args.np);
1208 	if (!pmc_pdev)
1209 		return -ENODEV;
1210 
1211 	err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device,
1212 				       &pmc_pdev->dev);
1213 	if (err)
1214 		return err;
1215 
1216 	if (!platform_get_drvdata(pmc_pdev))
1217 		return -EPROBE_DEFER;
1218 
1219 	phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk");
1220 	if (!phy->pmc_regmap)
1221 		return -EINVAL;
1222 
1223 	phy->instance = args.args[0];
1224 
1225 	return 0;
1226 }
1227 
1228 static const struct tegra_phy_soc_config tegra20_soc_config = {
1229 	.utmi_pll_config_in_car_module = false,
1230 	.has_hostpc = false,
1231 	.requires_usbmode_setup = false,
1232 	.requires_extra_tuning_parameters = false,
1233 	.requires_pmc_ao_power_up = false,
1234 };
1235 
1236 static const struct tegra_phy_soc_config tegra30_soc_config = {
1237 	.utmi_pll_config_in_car_module = true,
1238 	.has_hostpc = true,
1239 	.requires_usbmode_setup = true,
1240 	.requires_extra_tuning_parameters = true,
1241 	.requires_pmc_ao_power_up = true,
1242 };
1243 
1244 static const struct of_device_id tegra_usb_phy_id_table[] = {
1245 	{ .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1246 	{ .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1247 	{ },
1248 };
1249 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1250 
tegra_usb_phy_probe(struct platform_device * pdev)1251 static int tegra_usb_phy_probe(struct platform_device *pdev)
1252 {
1253 	struct device_node *np = pdev->dev.of_node;
1254 	struct tegra_usb_phy *tegra_phy;
1255 	enum usb_phy_interface phy_type;
1256 	struct reset_control *reset;
1257 	struct gpio_desc *gpiod;
1258 	struct resource *res;
1259 	struct usb_phy *phy;
1260 	int err;
1261 
1262 	tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1263 	if (!tegra_phy)
1264 		return -ENOMEM;
1265 
1266 	tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1267 	tegra_phy->irq = platform_get_irq_optional(pdev, 0);
1268 
1269 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1270 	if (!res) {
1271 		dev_err(&pdev->dev, "Failed to get I/O memory\n");
1272 		return  -ENXIO;
1273 	}
1274 
1275 	/*
1276 	 * Note that PHY and USB controller are using shared registers,
1277 	 * therefore devm_platform_ioremap_resource() can't be used here.
1278 	 */
1279 	tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1280 				       resource_size(res));
1281 	if (!tegra_phy->regs) {
1282 		dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1283 		return -ENOMEM;
1284 	}
1285 
1286 	tegra_phy->is_legacy_phy =
1287 		of_property_read_bool(np, "nvidia,has-legacy-mode");
1288 
1289 	if (of_property_present(np, "dr_mode"))
1290 		tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1291 	else
1292 		tegra_phy->mode = USB_DR_MODE_HOST;
1293 
1294 	if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1295 		dev_err(&pdev->dev, "dr_mode is invalid\n");
1296 		return -EINVAL;
1297 	}
1298 
1299 	/* On some boards, the VBUS regulator doesn't need to be controlled */
1300 	tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1301 	if (IS_ERR(tegra_phy->vbus))
1302 		return PTR_ERR(tegra_phy->vbus);
1303 
1304 	tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1305 	err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1306 	if (err) {
1307 		dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1308 		return err;
1309 	}
1310 
1311 	err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy);
1312 	if (err) {
1313 		dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n");
1314 		return err;
1315 	}
1316 
1317 	phy_type = of_usb_get_phy_mode(np);
1318 	switch (phy_type) {
1319 	case USBPHY_INTERFACE_MODE_UTMI:
1320 		err = utmi_phy_probe(tegra_phy, pdev);
1321 		if (err)
1322 			return err;
1323 
1324 		tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1325 		err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1326 		if (err) {
1327 			dev_err(&pdev->dev,
1328 				"Failed to get UTMIP pad clock: %d\n", err);
1329 			return err;
1330 		}
1331 
1332 		reset = devm_reset_control_get_optional_shared(&pdev->dev,
1333 							       "utmi-pads");
1334 		err = PTR_ERR_OR_ZERO(reset);
1335 		if (err) {
1336 			dev_err(&pdev->dev,
1337 				"Failed to get UTMI-pads reset: %d\n", err);
1338 			return err;
1339 		}
1340 		tegra_phy->pad_rst = reset;
1341 		break;
1342 
1343 	case USBPHY_INTERFACE_MODE_ULPI:
1344 		tegra_phy->is_ulpi_phy = true;
1345 
1346 		tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1347 		err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1348 		if (err) {
1349 			dev_err(&pdev->dev,
1350 				"Failed to get ULPI clock: %d\n", err);
1351 			return err;
1352 		}
1353 
1354 		gpiod = devm_gpiod_get(&pdev->dev, "nvidia,phy-reset",
1355 				       GPIOD_OUT_HIGH);
1356 		err = PTR_ERR_OR_ZERO(gpiod);
1357 		if (err) {
1358 			dev_err(&pdev->dev,
1359 				"Request failed for reset GPIO: %d\n", err);
1360 			return err;
1361 		}
1362 
1363 		err = gpiod_set_consumer_name(gpiod, "ulpi_phy_reset_b");
1364 		if (err) {
1365 			dev_err(&pdev->dev,
1366 				"Failed to set up reset GPIO name: %d\n", err);
1367 			return err;
1368 		}
1369 
1370 		tegra_phy->reset_gpio = gpiod;
1371 
1372 		phy = devm_otg_ulpi_create(&pdev->dev,
1373 					   &ulpi_viewport_access_ops, 0);
1374 		if (!phy) {
1375 			dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1376 			return -ENOMEM;
1377 		}
1378 
1379 		tegra_phy->ulpi = phy;
1380 		tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1381 		break;
1382 
1383 	default:
1384 		dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1385 			phy_type);
1386 		return -EINVAL;
1387 	}
1388 
1389 	tegra_phy->u_phy.dev = &pdev->dev;
1390 	tegra_phy->u_phy.init = tegra_usb_phy_init;
1391 	tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1392 	tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
1393 	tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1394 
1395 	platform_set_drvdata(pdev, tegra_phy);
1396 
1397 	return usb_add_phy_dev(&tegra_phy->u_phy);
1398 }
1399 
tegra_usb_phy_remove(struct platform_device * pdev)1400 static void tegra_usb_phy_remove(struct platform_device *pdev)
1401 {
1402 	struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1403 
1404 	usb_remove_phy(&tegra_phy->u_phy);
1405 }
1406 
1407 static struct platform_driver tegra_usb_phy_driver = {
1408 	.probe		= tegra_usb_phy_probe,
1409 	.remove		= tegra_usb_phy_remove,
1410 	.driver		= {
1411 		.name	= "tegra-phy",
1412 		.of_match_table = tegra_usb_phy_id_table,
1413 	},
1414 };
1415 module_platform_driver(tegra_usb_phy_driver);
1416 
1417 MODULE_DESCRIPTION("Tegra USB PHY driver");
1418 MODULE_LICENSE("GPL v2");
1419