/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 283 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); getAddSubImmOpValue() local 600 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); getImm8OptLsl() local 627 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); getMoveVecShifterOpValue() local [all...] |
H A D | AArch64InstPrinter.cpp | 1264 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); printArithExtend() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMatInt.cpp | 511 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 1253 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local 1275 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local 1622 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local 1637 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local 4671 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local 4734 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
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H A D | AArch64ISelDAGToDAG.cpp | 678 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local 940 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local 993 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local 1225 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
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H A D | AArch64InstrInfo.cpp | 940 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local 967 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local 975 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
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H A D | AArch64TargetTransformInfo.cpp | 374 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMParallelDSP.cpp | 783 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelper.cpp | 1892 auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) { in matchShiftOfShiftedLogic() 2009 unsigned &ShiftVal) { in matchCombineMulToShl() 2021 unsigned &ShiftVal) { in applyCombineMulToShl() 2303 unsigned &ShiftVal) { in matchCombineShiftToUnmerge() 2327 const unsigned &ShiftVal) { in applyCombineShiftToUnmerge()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 2315 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local 2336 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
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H A D | AMDGPUISelLowering.cpp | 5219 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
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H A D | SIISelLowering.cpp | 12150 auto ShiftVal = 32 * (DWordOffset % (ScalarTySize / 32)); in getDWordFromOffset() local 12177 auto ShiftVal = 32 * DWordOffset; in getDWordFromOffset() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1572 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, StVal, in LowerUnalignedStoreParam() local 3377 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, RetVal, in LowerUnalignedStoreRet() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstCombineIntrinsic.cpp | 390 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
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H A D | X86TargetTransformInfo.cpp | 5642 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
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H A D | X86ISelLowering.cpp | 6170 uint64_t ShiftVal = N.getConstantOperandVal(1); in getFauxShuffleMask() local 6770 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); in getVShift() local 18124 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT() local 18136 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT() local 30568 auto *ShiftVal = dyn_cast<ConstantInt>(I->getOperand(0)); in FindSingleBitChange() local 37698 const APInt &ShiftVal = Op.getConstantOperandAPInt(1); in ComputeNumSignBitsForTargetNode() local 37709 APInt ShiftVal = Op.getConstantOperandAPInt(1); in ComputeNumSignBitsForTargetNode() local 48711 unsigned ShiftVal = N->getConstantOperandVal(1); in combineVectorShiftImm() local 49442 unsigned ShiftVal = SplatVal.countr_one(); in combineAndMaskToShift() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 7006 const APInt ShiftVal = ValAndVeg->Value; in isWorthFoldingIntoAddrMode() local 7579 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local 7670 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 15326 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 15367 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 15450 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 15479 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 15509 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local 15530 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 409 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
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H A D | InstCombineCompares.cpp | 2277 const APInt *ShiftVal; in foldICmpShlConstant() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 2400 auto ShiftVal = Op.getOperand(1); in LowerShift() local
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/freebsd/contrib/llvm-project/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 1612 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in upgradeX86ALIGNIntrinsics() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 2738 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() 2916 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 5347 unsigned ShiftVal = 0; in Select() local
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