1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Wrapper driver for SERDES used in J721E 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-ti.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/gpio.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/mux/consumer.h> 20 #include <linux/of_address.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/reset-controller.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 #define REF_CLK_156_25MHZ 156250000 31 32 /* SCM offsets */ 33 #define SERDES_SUP_CTRL 0x4400 34 35 /* SERDES offsets */ 36 #define WIZ_SERDES_CTRL 0x404 37 #define WIZ_SERDES_TOP_CTRL 0x408 38 #define WIZ_SERDES_RST 0x40c 39 #define WIZ_SERDES_TYPEC 0x410 40 #define WIZ_LANECTL(n) (0x480 + (0x40 * (n))) 41 #define WIZ_LANEDIV(n) (0x484 + (0x40 * (n))) 42 43 #define WIZ_MAX_INPUT_CLOCKS 4 44 /* To include mux clocks, divider clocks and gate clocks */ 45 #define WIZ_MAX_OUTPUT_CLOCKS 32 46 47 #define WIZ_MAX_LANES 4 48 #define WIZ_MUX_NUM_CLOCKS 3 49 #define WIZ_DIV_NUM_CLOCKS_16G 2 50 #define WIZ_DIV_NUM_CLOCKS_10G 1 51 52 #define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30) 53 54 enum wiz_lane_standard_mode { 55 LANE_MODE_GEN1, 56 LANE_MODE_GEN2, 57 LANE_MODE_GEN3, 58 LANE_MODE_GEN4, 59 }; 60 61 /* 62 * List of master lanes used for lane swapping 63 */ 64 enum wiz_typec_master_lane { 65 LANE0 = 0, 66 LANE2 = 2, 67 }; 68 69 enum wiz_refclk_mux_sel { 70 PLL0_REFCLK, 71 PLL1_REFCLK, 72 REFCLK_DIG, 73 }; 74 75 enum wiz_refclk_div_sel { 76 CMN_REFCLK_DIG_DIV, 77 CMN_REFCLK1_DIG_DIV, 78 }; 79 80 enum wiz_clock_input { 81 WIZ_CORE_REFCLK, 82 WIZ_EXT_REFCLK, 83 WIZ_CORE_REFCLK1, 84 WIZ_EXT_REFCLK1, 85 }; 86 87 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31); 88 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31); 89 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 90 static const struct reg_field pll1_refclk_mux_sel = 91 REG_FIELD(WIZ_SERDES_RST, 29, 29); 92 static const struct reg_field pll1_refclk_mux_sel_2 = 93 REG_FIELD(WIZ_SERDES_RST, 22, 23); 94 static const struct reg_field pll0_refclk_mux_sel = 95 REG_FIELD(WIZ_SERDES_RST, 28, 28); 96 static const struct reg_field pll0_refclk_mux_sel_2 = 97 REG_FIELD(WIZ_SERDES_RST, 28, 29); 98 static const struct reg_field refclk_dig_sel_16g = 99 REG_FIELD(WIZ_SERDES_RST, 24, 25); 100 static const struct reg_field refclk_dig_sel_10g = 101 REG_FIELD(WIZ_SERDES_RST, 24, 24); 102 static const struct reg_field pma_cmn_refclk_int_mode = 103 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 104 static const struct reg_field pma_cmn_refclk1_int_mode = 105 REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); 106 static const struct reg_field pma_cmn_refclk_mode = 107 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 108 static const struct reg_field pma_cmn_refclk_dig_div = 109 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27); 110 static const struct reg_field pma_cmn_refclk1_dig_div = 111 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25); 112 113 static const struct reg_field sup_pll0_refclk_mux_sel = 114 REG_FIELD(SERDES_SUP_CTRL, 0, 1); 115 static const struct reg_field sup_pll1_refclk_mux_sel = 116 REG_FIELD(SERDES_SUP_CTRL, 2, 3); 117 static const struct reg_field sup_pma_cmn_refclk1_int_mode = 118 REG_FIELD(SERDES_SUP_CTRL, 4, 5); 119 static const struct reg_field sup_refclk_dig_sel_10g = 120 REG_FIELD(SERDES_SUP_CTRL, 6, 7); 121 static const struct reg_field sup_legacy_clk_override = 122 REG_FIELD(SERDES_SUP_CTRL, 8, 8); 123 124 static const char * const output_clk_names[] = { 125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk", 126 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk", 127 [TI_WIZ_REFCLK_DIG] = "refclk-dig", 128 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk", 129 }; 130 131 static const struct reg_field p_enable[WIZ_MAX_LANES] = { 132 REG_FIELD(WIZ_LANECTL(0), 30, 31), 133 REG_FIELD(WIZ_LANECTL(1), 30, 31), 134 REG_FIELD(WIZ_LANECTL(2), 30, 31), 135 REG_FIELD(WIZ_LANECTL(3), 30, 31), 136 }; 137 138 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 }; 139 140 static const struct reg_field p_align[WIZ_MAX_LANES] = { 141 REG_FIELD(WIZ_LANECTL(0), 29, 29), 142 REG_FIELD(WIZ_LANECTL(1), 29, 29), 143 REG_FIELD(WIZ_LANECTL(2), 29, 29), 144 REG_FIELD(WIZ_LANECTL(3), 29, 29), 145 }; 146 147 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = { 148 REG_FIELD(WIZ_LANECTL(0), 28, 28), 149 REG_FIELD(WIZ_LANECTL(1), 28, 28), 150 REG_FIELD(WIZ_LANECTL(2), 28, 28), 151 REG_FIELD(WIZ_LANECTL(3), 28, 28), 152 }; 153 154 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = { 155 REG_FIELD(WIZ_LANECTL(0), 24, 25), 156 REG_FIELD(WIZ_LANECTL(1), 24, 25), 157 REG_FIELD(WIZ_LANECTL(2), 24, 25), 158 REG_FIELD(WIZ_LANECTL(3), 24, 25), 159 }; 160 161 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = { 162 REG_FIELD(WIZ_LANECTL(0), 22, 23), 163 REG_FIELD(WIZ_LANECTL(1), 22, 23), 164 REG_FIELD(WIZ_LANECTL(2), 22, 23), 165 REG_FIELD(WIZ_LANECTL(3), 22, 23), 166 }; 167 168 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = { 169 REG_FIELD(WIZ_LANECTL(0), 20, 21), 170 REG_FIELD(WIZ_LANECTL(1), 20, 21), 171 REG_FIELD(WIZ_LANECTL(2), 20, 21), 172 REG_FIELD(WIZ_LANECTL(3), 20, 21), 173 }; 174 175 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = { 176 REG_FIELD(WIZ_LANECTL(0), 6, 7), 177 REG_FIELD(WIZ_LANECTL(1), 6, 7), 178 REG_FIELD(WIZ_LANECTL(2), 6, 7), 179 REG_FIELD(WIZ_LANECTL(3), 6, 7), 180 }; 181 182 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = { 183 REG_FIELD(WIZ_LANECTL(0), 18, 19), 184 REG_FIELD(WIZ_LANECTL(1), 18, 19), 185 REG_FIELD(WIZ_LANECTL(2), 18, 19), 186 REG_FIELD(WIZ_LANECTL(3), 18, 19), 187 }; 188 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = { 189 REG_FIELD(WIZ_LANEDIV(0), 16, 22), 190 REG_FIELD(WIZ_LANEDIV(1), 16, 22), 191 REG_FIELD(WIZ_LANEDIV(2), 16, 22), 192 REG_FIELD(WIZ_LANEDIV(3), 16, 22), 193 }; 194 195 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = { 196 REG_FIELD(WIZ_LANEDIV(0), 0, 8), 197 REG_FIELD(WIZ_LANEDIV(1), 0, 8), 198 REG_FIELD(WIZ_LANEDIV(2), 0, 8), 199 REG_FIELD(WIZ_LANEDIV(3), 0, 8), 200 }; 201 202 static const struct reg_field typec_ln10_swap = 203 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30); 204 205 static const struct reg_field typec_ln23_swap = 206 REG_FIELD(WIZ_SERDES_TYPEC, 31, 31); 207 208 struct wiz_clk_mux { 209 struct clk_hw hw; 210 struct regmap_field *field; 211 const u32 *table; 212 struct clk_init_data clk_data; 213 }; 214 215 #define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) 216 217 struct wiz_clk_divider { 218 struct clk_hw hw; 219 struct regmap_field *field; 220 const struct clk_div_table *table; 221 struct clk_init_data clk_data; 222 }; 223 224 #define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) 225 226 struct wiz_clk_mux_sel { 227 u32 table[WIZ_MAX_INPUT_CLOCKS]; 228 const char *node_name; 229 u32 num_parents; 230 u32 parents[WIZ_MAX_INPUT_CLOCKS]; 231 }; 232 233 struct wiz_clk_div_sel { 234 const struct clk_div_table *table; 235 const char *node_name; 236 }; 237 238 struct wiz_phy_en_refclk { 239 struct clk_hw hw; 240 struct regmap_field *phy_en_refclk; 241 struct clk_init_data clk_data; 242 }; 243 244 #define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw) 245 246 static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = { 247 { 248 /* 249 * Mux value to be configured for each of the input clocks 250 * in the order populated in device tree 251 */ 252 .table = { 1, 0 }, 253 .node_name = "pll0-refclk", 254 }, 255 { 256 .table = { 1, 0 }, 257 .node_name = "pll1-refclk", 258 }, 259 { 260 .table = { 1, 3, 0, 2 }, 261 .node_name = "refclk-dig", 262 }, 263 }; 264 265 static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = { 266 { 267 /* 268 * Mux value to be configured for each of the input clocks 269 * in the order populated in device tree 270 */ 271 .num_parents = 2, 272 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 273 .table = { 1, 0 }, 274 .node_name = "pll0-refclk", 275 }, 276 { 277 .num_parents = 2, 278 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 279 .table = { 1, 0 }, 280 .node_name = "pll1-refclk", 281 }, 282 { 283 .num_parents = 2, 284 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK }, 285 .table = { 1, 0 }, 286 .node_name = "refclk-dig", 287 }, 288 }; 289 290 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = { 291 { 292 .num_parents = 3, 293 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 294 .table = { 2, 3, 0 }, 295 .node_name = "pll0-refclk", 296 }, 297 { 298 .num_parents = 3, 299 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 300 .table = { 2, 3, 0 }, 301 .node_name = "pll1-refclk", 302 }, 303 { 304 .num_parents = 3, 305 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK }, 306 .table = { 2, 3, 0 }, 307 .node_name = "refclk-dig", 308 }, 309 }; 310 311 static const struct clk_div_table clk_div_table[] = { 312 { .val = 0, .div = 1, }, 313 { .val = 1, .div = 2, }, 314 { .val = 2, .div = 4, }, 315 { .val = 3, .div = 8, }, 316 { /* sentinel */ }, 317 }; 318 319 static const struct wiz_clk_div_sel clk_div_sel[] = { 320 { 321 .table = clk_div_table, 322 .node_name = "cmn-refclk-dig-div", 323 }, 324 { 325 .table = clk_div_table, 326 .node_name = "cmn-refclk1-dig-div", 327 }, 328 }; 329 330 enum wiz_type { 331 J721E_WIZ_16G, 332 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 333 AM64_WIZ_10G, 334 J722S_WIZ_10G, 335 J7200_WIZ_10G, /* J7200 SR2.0 */ 336 J784S4_WIZ_10G, 337 J721S2_WIZ_10G, 338 }; 339 340 struct wiz_data { 341 enum wiz_type type; 342 const struct reg_field *pll0_refclk_mux_sel; 343 const struct reg_field *pll1_refclk_mux_sel; 344 const struct reg_field *refclk_dig_sel; 345 const struct reg_field *pma_cmn_refclk1_dig_div; 346 const struct reg_field *pma_cmn_refclk1_int_mode; 347 const struct wiz_clk_mux_sel *clk_mux_sel; 348 unsigned int clk_div_sel_num; 349 }; 350 351 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ 352 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 353 354 struct wiz { 355 struct regmap *regmap; 356 struct regmap *scm_regmap; 357 enum wiz_type type; 358 const struct wiz_clk_mux_sel *clk_mux_sel; 359 const struct wiz_clk_div_sel *clk_div_sel; 360 unsigned int clk_div_sel_num; 361 struct regmap_field *por_en; 362 struct regmap_field *phy_reset_n; 363 struct regmap_field *phy_en_refclk; 364 struct regmap_field *p_enable[WIZ_MAX_LANES]; 365 struct regmap_field *p_align[WIZ_MAX_LANES]; 366 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES]; 367 struct regmap_field *p_standard_mode[WIZ_MAX_LANES]; 368 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES]; 369 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES]; 370 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES]; 371 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES]; 372 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES]; 373 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES]; 374 struct regmap_field *pma_cmn_refclk_int_mode; 375 struct regmap_field *pma_cmn_refclk1_int_mode; 376 struct regmap_field *pma_cmn_refclk_mode; 377 struct regmap_field *pma_cmn_refclk_dig_div; 378 struct regmap_field *pma_cmn_refclk1_dig_div; 379 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS]; 380 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G]; 381 struct regmap_field *typec_ln10_swap; 382 struct regmap_field *typec_ln23_swap; 383 struct regmap_field *sup_legacy_clk_override; 384 385 struct device *dev; 386 u32 num_lanes; 387 struct platform_device *serdes_pdev; 388 struct reset_controller_dev wiz_phy_reset_dev; 389 struct gpio_desc *gpio_typec_dir; 390 int typec_dir_delay; 391 u32 lane_phy_type[WIZ_MAX_LANES]; 392 u32 master_lane_num[WIZ_MAX_LANES]; 393 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; 394 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS]; 395 struct clk_onecell_data clk_data; 396 const struct wiz_data *data; 397 int mux_sel_status[WIZ_MUX_NUM_CLOCKS]; 398 }; 399 400 static int wiz_reset(struct wiz *wiz) 401 { 402 int ret; 403 404 ret = regmap_field_write(wiz->por_en, 0x1); 405 if (ret) 406 return ret; 407 408 mdelay(1); 409 410 ret = regmap_field_write(wiz->por_en, 0x0); 411 if (ret) 412 return ret; 413 414 return 0; 415 } 416 417 static int wiz_p_mac_div_sel(struct wiz *wiz) 418 { 419 u32 num_lanes = wiz->num_lanes; 420 int ret; 421 int i; 422 423 for (i = 0; i < num_lanes; i++) { 424 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII || 425 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII || 426 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 427 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1); 428 if (ret) 429 return ret; 430 431 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2); 432 if (ret) 433 return ret; 434 } 435 } 436 437 return 0; 438 } 439 440 static int wiz_mode_select(struct wiz *wiz) 441 { 442 u32 num_lanes = wiz->num_lanes; 443 enum wiz_lane_standard_mode mode; 444 int ret; 445 int i; 446 447 for (i = 0; i < num_lanes; i++) { 448 if (wiz->lane_phy_type[i] == PHY_TYPE_DP) { 449 mode = LANE_MODE_GEN1; 450 } else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) { 451 mode = LANE_MODE_GEN2; 452 } else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) { 453 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3); 454 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3); 455 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2); 456 mode = LANE_MODE_GEN2; 457 } else { 458 continue; 459 } 460 461 ret = regmap_field_write(wiz->p_standard_mode[i], mode); 462 if (ret) 463 return ret; 464 } 465 466 return 0; 467 } 468 469 static int wiz_init_raw_interface(struct wiz *wiz, bool enable) 470 { 471 u32 num_lanes = wiz->num_lanes; 472 int i; 473 int ret; 474 475 for (i = 0; i < num_lanes; i++) { 476 ret = regmap_field_write(wiz->p_align[i], enable); 477 if (ret) 478 return ret; 479 480 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); 481 if (ret) 482 return ret; 483 } 484 485 return 0; 486 } 487 488 static int wiz_init(struct wiz *wiz) 489 { 490 struct device *dev = wiz->dev; 491 int ret; 492 493 ret = wiz_reset(wiz); 494 if (ret) { 495 dev_err(dev, "WIZ reset failed\n"); 496 return ret; 497 } 498 499 ret = wiz_mode_select(wiz); 500 if (ret) { 501 dev_err(dev, "WIZ mode select failed\n"); 502 return ret; 503 } 504 505 ret = wiz_p_mac_div_sel(wiz); 506 if (ret) { 507 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n"); 508 return ret; 509 } 510 511 ret = wiz_init_raw_interface(wiz, true); 512 if (ret) { 513 dev_err(dev, "WIZ interface initialization failed\n"); 514 return ret; 515 } 516 517 return 0; 518 } 519 520 static int wiz_regfield_init(struct wiz *wiz) 521 { 522 struct regmap *regmap = wiz->regmap; 523 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */ 524 int num_lanes = wiz->num_lanes; 525 struct device *dev = wiz->dev; 526 const struct wiz_data *data = wiz->data; 527 int i; 528 529 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); 530 if (IS_ERR(wiz->por_en)) { 531 dev_err(dev, "POR_EN reg field init failed\n"); 532 return PTR_ERR(wiz->por_en); 533 } 534 535 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, 536 phy_reset_n); 537 if (IS_ERR(wiz->phy_reset_n)) { 538 dev_err(dev, "PHY_RESET_N reg field init failed\n"); 539 return PTR_ERR(wiz->phy_reset_n); 540 } 541 542 wiz->pma_cmn_refclk_int_mode = 543 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); 544 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) { 545 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n"); 546 return PTR_ERR(wiz->pma_cmn_refclk_int_mode); 547 } 548 549 wiz->pma_cmn_refclk_mode = 550 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); 551 if (IS_ERR(wiz->pma_cmn_refclk_mode)) { 552 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n"); 553 return PTR_ERR(wiz->pma_cmn_refclk_mode); 554 } 555 556 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] = 557 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div); 558 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) { 559 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n"); 560 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]); 561 } 562 563 if (data->pma_cmn_refclk1_dig_div) { 564 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] = 565 devm_regmap_field_alloc(dev, regmap, 566 *data->pma_cmn_refclk1_dig_div); 567 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) { 568 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n"); 569 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]); 570 } 571 } 572 573 if (wiz->scm_regmap) { 574 scm_regmap = wiz->scm_regmap; 575 wiz->sup_legacy_clk_override = 576 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override); 577 if (IS_ERR(wiz->sup_legacy_clk_override)) { 578 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n"); 579 return PTR_ERR(wiz->sup_legacy_clk_override); 580 } 581 } 582 583 wiz->mux_sel_field[PLL0_REFCLK] = 584 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel); 585 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { 586 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n"); 587 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); 588 } 589 590 wiz->mux_sel_field[PLL1_REFCLK] = 591 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel); 592 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { 593 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n"); 594 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); 595 } 596 597 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap, 598 *data->refclk_dig_sel); 599 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) { 600 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n"); 601 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]); 602 } 603 604 if (data->pma_cmn_refclk1_int_mode) { 605 wiz->pma_cmn_refclk1_int_mode = 606 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode); 607 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) { 608 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n"); 609 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode); 610 } 611 } 612 613 for (i = 0; i < num_lanes; i++) { 614 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, 615 p_enable[i]); 616 if (IS_ERR(wiz->p_enable[i])) { 617 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 618 return PTR_ERR(wiz->p_enable[i]); 619 } 620 621 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, 622 p_align[i]); 623 if (IS_ERR(wiz->p_align[i])) { 624 dev_err(dev, "P%d_ALIGN reg field init failed\n", i); 625 return PTR_ERR(wiz->p_align[i]); 626 } 627 628 wiz->p_raw_auto_start[i] = 629 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); 630 if (IS_ERR(wiz->p_raw_auto_start[i])) { 631 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n", 632 i); 633 return PTR_ERR(wiz->p_raw_auto_start[i]); 634 } 635 636 wiz->p_standard_mode[i] = 637 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); 638 if (IS_ERR(wiz->p_standard_mode[i])) { 639 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n", 640 i); 641 return PTR_ERR(wiz->p_standard_mode[i]); 642 } 643 644 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]); 645 if (IS_ERR(wiz->p0_fullrt_div[i])) { 646 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i); 647 return PTR_ERR(wiz->p0_fullrt_div[i]); 648 } 649 650 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]); 651 if (IS_ERR(wiz->p0_mac_src_sel[i])) { 652 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i); 653 return PTR_ERR(wiz->p0_mac_src_sel[i]); 654 } 655 656 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]); 657 if (IS_ERR(wiz->p0_rxfclk_sel[i])) { 658 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i); 659 return PTR_ERR(wiz->p0_rxfclk_sel[i]); 660 } 661 662 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]); 663 if (IS_ERR(wiz->p0_refclk_sel[i])) { 664 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i); 665 return PTR_ERR(wiz->p0_refclk_sel[i]); 666 } 667 668 wiz->p_mac_div_sel0[i] = 669 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]); 670 if (IS_ERR(wiz->p_mac_div_sel0[i])) { 671 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n", 672 i); 673 return PTR_ERR(wiz->p_mac_div_sel0[i]); 674 } 675 676 wiz->p_mac_div_sel1[i] = 677 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]); 678 if (IS_ERR(wiz->p_mac_div_sel1[i])) { 679 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n", 680 i); 681 return PTR_ERR(wiz->p_mac_div_sel1[i]); 682 } 683 } 684 685 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap, 686 typec_ln10_swap); 687 if (IS_ERR(wiz->typec_ln10_swap)) { 688 dev_err(dev, "LN10_SWAP reg field init failed\n"); 689 return PTR_ERR(wiz->typec_ln10_swap); 690 } 691 692 wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap, 693 typec_ln23_swap); 694 if (IS_ERR(wiz->typec_ln23_swap)) { 695 dev_err(dev, "LN23_SWAP reg field init failed\n"); 696 return PTR_ERR(wiz->typec_ln23_swap); 697 } 698 699 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk); 700 if (IS_ERR(wiz->phy_en_refclk)) { 701 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n"); 702 return PTR_ERR(wiz->phy_en_refclk); 703 } 704 705 return 0; 706 } 707 708 static int wiz_phy_en_refclk_enable(struct clk_hw *hw) 709 { 710 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 711 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 712 713 regmap_field_write(phy_en_refclk, 1); 714 715 return 0; 716 } 717 718 static void wiz_phy_en_refclk_disable(struct clk_hw *hw) 719 { 720 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 721 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 722 723 regmap_field_write(phy_en_refclk, 0); 724 } 725 726 static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw) 727 { 728 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw); 729 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk; 730 int val; 731 732 regmap_field_read(phy_en_refclk, &val); 733 734 return !!val; 735 } 736 737 static const struct clk_ops wiz_phy_en_refclk_ops = { 738 .enable = wiz_phy_en_refclk_enable, 739 .disable = wiz_phy_en_refclk_disable, 740 .is_enabled = wiz_phy_en_refclk_is_enabled, 741 }; 742 743 static int wiz_phy_en_refclk_register(struct wiz *wiz) 744 { 745 struct wiz_phy_en_refclk *wiz_phy_en_refclk; 746 struct device *dev = wiz->dev; 747 struct clk_init_data *init; 748 struct clk *clk; 749 char *clk_name; 750 unsigned int sz; 751 752 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL); 753 if (!wiz_phy_en_refclk) 754 return -ENOMEM; 755 756 init = &wiz_phy_en_refclk->clk_data; 757 758 init->ops = &wiz_phy_en_refclk_ops; 759 init->flags = 0; 760 761 sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2; 762 763 clk_name = kzalloc(sz, GFP_KERNEL); 764 if (!clk_name) 765 return -ENOMEM; 766 767 snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]); 768 init->name = clk_name; 769 770 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk; 771 wiz_phy_en_refclk->hw.init = init; 772 773 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw); 774 775 kfree(clk_name); 776 777 if (IS_ERR(clk)) 778 return PTR_ERR(clk); 779 780 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk; 781 782 return 0; 783 } 784 785 static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) 786 { 787 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 788 struct regmap_field *field = mux->field; 789 unsigned int val; 790 791 regmap_field_read(field, &val); 792 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val); 793 } 794 795 static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) 796 { 797 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); 798 struct regmap_field *field = mux->field; 799 int val; 800 801 val = mux->table[index]; 802 return regmap_field_write(field, val); 803 } 804 805 static const struct clk_ops wiz_clk_mux_ops = { 806 .determine_rate = __clk_mux_determine_rate, 807 .set_parent = wiz_clk_mux_set_parent, 808 .get_parent = wiz_clk_mux_get_parent, 809 }; 810 811 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, 812 const struct wiz_clk_mux_sel *mux_sel, int clk_index) 813 { 814 struct device *dev = wiz->dev; 815 struct clk_init_data *init; 816 const char **parent_names; 817 unsigned int num_parents; 818 struct wiz_clk_mux *mux; 819 char clk_name[100]; 820 struct clk *clk; 821 int ret = 0, i; 822 823 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 824 if (!mux) 825 return -ENOMEM; 826 827 num_parents = mux_sel->num_parents; 828 829 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); 830 if (!parent_names) 831 return -ENOMEM; 832 833 for (i = 0; i < num_parents; i++) { 834 clk = wiz->input_clks[mux_sel->parents[i]]; 835 if (IS_ERR_OR_NULL(clk)) { 836 dev_err(dev, "Failed to get parent clk for %s\n", 837 output_clk_names[clk_index]); 838 ret = -EINVAL; 839 goto err; 840 } 841 parent_names[i] = __clk_get_name(clk); 842 } 843 844 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]); 845 846 init = &mux->clk_data; 847 848 init->ops = &wiz_clk_mux_ops; 849 init->flags = CLK_SET_RATE_NO_REPARENT; 850 init->parent_names = parent_names; 851 init->num_parents = num_parents; 852 init->name = clk_name; 853 854 mux->field = field; 855 mux->table = mux_sel->table; 856 mux->hw.init = init; 857 858 clk = devm_clk_register(dev, &mux->hw); 859 if (IS_ERR(clk)) { 860 ret = PTR_ERR(clk); 861 goto err; 862 } 863 864 wiz->output_clks[clk_index] = clk; 865 866 err: 867 kfree(parent_names); 868 869 return ret; 870 } 871 872 static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node, 873 struct regmap_field *field, const u32 *table) 874 { 875 struct device *dev = wiz->dev; 876 struct clk_init_data *init; 877 const char **parent_names; 878 unsigned int num_parents; 879 struct wiz_clk_mux *mux; 880 char clk_name[100]; 881 struct clk *clk; 882 int ret; 883 884 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 885 if (!mux) 886 return -ENOMEM; 887 888 num_parents = of_clk_get_parent_count(node); 889 if (num_parents < 2) { 890 dev_err(dev, "SERDES clock must have parents\n"); 891 return -EINVAL; 892 } 893 894 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), 895 GFP_KERNEL); 896 if (!parent_names) 897 return -ENOMEM; 898 899 of_clk_parent_fill(node, parent_names, num_parents); 900 901 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 902 node->name); 903 904 init = &mux->clk_data; 905 906 init->ops = &wiz_clk_mux_ops; 907 init->flags = CLK_SET_RATE_NO_REPARENT; 908 init->parent_names = parent_names; 909 init->num_parents = num_parents; 910 init->name = clk_name; 911 912 mux->field = field; 913 mux->table = table; 914 mux->hw.init = init; 915 916 clk = devm_clk_register(dev, &mux->hw); 917 if (IS_ERR(clk)) 918 return PTR_ERR(clk); 919 920 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 921 if (ret) 922 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 923 924 return ret; 925 } 926 927 static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, 928 unsigned long parent_rate) 929 { 930 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 931 struct regmap_field *field = div->field; 932 int val; 933 934 regmap_field_read(field, &val); 935 936 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); 937 } 938 939 static int wiz_clk_div_determine_rate(struct clk_hw *hw, 940 struct clk_rate_request *req) 941 { 942 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 943 944 return divider_determine_rate(hw, req, div->table, 2, 0x0); 945 } 946 947 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 948 unsigned long parent_rate) 949 { 950 struct wiz_clk_divider *div = to_wiz_clk_div(hw); 951 struct regmap_field *field = div->field; 952 int val; 953 954 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); 955 if (val < 0) 956 return val; 957 958 return regmap_field_write(field, val); 959 } 960 961 static const struct clk_ops wiz_clk_div_ops = { 962 .recalc_rate = wiz_clk_div_recalc_rate, 963 .determine_rate = wiz_clk_div_determine_rate, 964 .set_rate = wiz_clk_div_set_rate, 965 }; 966 967 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, 968 struct regmap_field *field, 969 const struct clk_div_table *table) 970 { 971 struct device *dev = wiz->dev; 972 struct wiz_clk_divider *div; 973 struct clk_init_data *init; 974 const char **parent_names; 975 char clk_name[100]; 976 struct clk *clk; 977 int ret; 978 979 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 980 if (!div) 981 return -ENOMEM; 982 983 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 984 node->name); 985 986 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 987 if (!parent_names) 988 return -ENOMEM; 989 990 of_clk_parent_fill(node, parent_names, 1); 991 992 init = &div->clk_data; 993 994 init->ops = &wiz_clk_div_ops; 995 init->flags = 0; 996 init->parent_names = parent_names; 997 init->num_parents = 1; 998 init->name = clk_name; 999 1000 div->field = field; 1001 div->table = table; 1002 div->hw.init = init; 1003 1004 clk = devm_clk_register(dev, &div->hw); 1005 if (IS_ERR(clk)) 1006 return PTR_ERR(clk); 1007 1008 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); 1009 if (ret) 1010 dev_err(dev, "Failed to add clock provider: %s\n", clk_name); 1011 1012 return ret; 1013 } 1014 1015 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) 1016 { 1017 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1018 struct device *dev = wiz->dev; 1019 struct device_node *clk_node; 1020 int i; 1021 1022 switch (wiz->type) { 1023 case AM64_WIZ_10G: 1024 case J722S_WIZ_10G: 1025 case J7200_WIZ_10G: 1026 case J784S4_WIZ_10G: 1027 case J721S2_WIZ_10G: 1028 of_clk_del_provider(dev->of_node); 1029 return; 1030 default: 1031 break; 1032 } 1033 1034 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1035 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); 1036 of_clk_del_provider(clk_node); 1037 of_node_put(clk_node); 1038 } 1039 1040 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1041 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name); 1042 of_clk_del_provider(clk_node); 1043 of_node_put(clk_node); 1044 } 1045 1046 of_clk_del_provider(wiz->dev->of_node); 1047 } 1048 1049 static int wiz_clock_register(struct wiz *wiz) 1050 { 1051 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1052 struct device *dev = wiz->dev; 1053 struct device_node *node = dev->of_node; 1054 int clk_index; 1055 int ret; 1056 int i; 1057 1058 clk_index = TI_WIZ_PLL0_REFCLK; 1059 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) { 1060 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index); 1061 if (ret) { 1062 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]); 1063 return ret; 1064 } 1065 } 1066 1067 ret = wiz_phy_en_refclk_register(wiz); 1068 if (ret) { 1069 dev_err(dev, "Failed to add phy-en-refclk\n"); 1070 return ret; 1071 } 1072 1073 wiz->clk_data.clks = wiz->output_clks; 1074 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS; 1075 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data); 1076 if (ret) 1077 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 1078 1079 return ret; 1080 } 1081 1082 static void wiz_clock_init(struct wiz *wiz) 1083 { 1084 unsigned long rate; 1085 1086 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]); 1087 if (rate >= REF_CLK_100MHZ) 1088 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1089 else 1090 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); 1091 1092 switch (wiz->type) { 1093 case AM64_WIZ_10G: 1094 case J722S_WIZ_10G: 1095 case J7200_WIZ_10G: 1096 switch (rate) { 1097 case REF_CLK_100MHZ: 1098 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2); 1099 break; 1100 case REF_CLK_156_25MHZ: 1101 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3); 1102 break; 1103 default: 1104 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0); 1105 break; 1106 } 1107 break; 1108 default: 1109 break; 1110 } 1111 1112 if (wiz->input_clks[WIZ_CORE_REFCLK1]) { 1113 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]); 1114 if (rate >= REF_CLK_100MHZ) 1115 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1116 else 1117 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1118 } 1119 1120 rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]); 1121 if (rate >= REF_CLK_100MHZ) 1122 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1123 else 1124 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1125 } 1126 1127 static int wiz_clock_probe(struct wiz *wiz, struct device_node *node) 1128 { 1129 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1130 struct device *dev = wiz->dev; 1131 struct device_node *clk_node; 1132 const char *node_name; 1133 struct clk *clk; 1134 int ret; 1135 int i; 1136 1137 clk = devm_clk_get(dev, "core_ref_clk"); 1138 if (IS_ERR(clk)) 1139 return dev_err_probe(dev, PTR_ERR(clk), 1140 "core_ref_clk clock not found\n"); 1141 1142 wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1143 1144 if (wiz->data->pma_cmn_refclk1_int_mode) { 1145 clk = devm_clk_get(dev, "core_ref1_clk"); 1146 if (IS_ERR(clk)) 1147 return dev_err_probe(dev, PTR_ERR(clk), 1148 "core_ref1_clk clock not found\n"); 1149 1150 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1151 } 1152 1153 clk = devm_clk_get(dev, "ext_ref_clk"); 1154 if (IS_ERR(clk)) 1155 return dev_err_probe(dev, PTR_ERR(clk), 1156 "ext_ref_clk clock not found\n"); 1157 1158 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1159 1160 wiz_clock_init(wiz); 1161 1162 switch (wiz->type) { 1163 case AM64_WIZ_10G: 1164 case J722S_WIZ_10G: 1165 case J7200_WIZ_10G: 1166 case J784S4_WIZ_10G: 1167 case J721S2_WIZ_10G: 1168 ret = wiz_clock_register(wiz); 1169 if (ret) 1170 return dev_err_probe(dev, ret, "Failed to register wiz clocks\n"); 1171 1172 return 0; 1173 default: 1174 break; 1175 } 1176 1177 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) { 1178 node_name = clk_mux_sel[i].node_name; 1179 clk_node = of_get_child_by_name(node, node_name); 1180 if (!clk_node) { 1181 ret = dev_err_probe(dev, -EINVAL, "Unable to get %s node\n", node_name); 1182 goto err; 1183 } 1184 1185 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i], 1186 clk_mux_sel[i].table); 1187 of_node_put(clk_node); 1188 if (ret) { 1189 dev_err_probe(dev, ret, "Failed to register %s clock\n", 1190 node_name); 1191 goto err; 1192 } 1193 1194 } 1195 1196 for (i = 0; i < wiz->clk_div_sel_num; i++) { 1197 node_name = clk_div_sel[i].node_name; 1198 clk_node = of_get_child_by_name(node, node_name); 1199 if (!clk_node) { 1200 ret = dev_err_probe(dev, -EINVAL, "Unable to get %s node\n", node_name); 1201 goto err; 1202 } 1203 1204 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i], 1205 clk_div_sel[i].table); 1206 of_node_put(clk_node); 1207 if (ret) { 1208 dev_err_probe(dev, ret, "Failed to register %s clock\n", 1209 node_name); 1210 goto err; 1211 } 1212 } 1213 1214 return 0; 1215 err: 1216 wiz_clock_cleanup(wiz, node); 1217 1218 return ret; 1219 } 1220 1221 static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, 1222 unsigned long id) 1223 { 1224 struct device *dev = rcdev->dev; 1225 struct wiz *wiz = dev_get_drvdata(dev); 1226 int ret = 0; 1227 1228 if (id == 0) { 1229 ret = regmap_field_write(wiz->phy_reset_n, false); 1230 return ret; 1231 } 1232 1233 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE); 1234 return ret; 1235 } 1236 1237 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane) 1238 { 1239 switch (wiz->type) { 1240 case AM64_WIZ_10G: 1241 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1242 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1243 break; 1244 1245 case J721E_WIZ_16G: 1246 case J721E_WIZ_10G: 1247 case J7200_WIZ_10G: 1248 case J721S2_WIZ_10G: 1249 case J784S4_WIZ_10G: 1250 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1251 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1252 break; 1253 1254 case J722S_WIZ_10G: 1255 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE) 1256 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); 1257 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1258 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1259 break; 1260 1261 default: 1262 return 0; 1263 } 1264 return 0; 1265 } 1266 1267 static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, 1268 unsigned long id) 1269 { 1270 struct device *dev = rcdev->dev; 1271 struct wiz *wiz = dev_get_drvdata(dev); 1272 int ret; 1273 1274 if (id == 0) { 1275 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */ 1276 if (wiz->gpio_typec_dir) { 1277 if (wiz->typec_dir_delay) 1278 msleep_interruptible(wiz->typec_dir_delay); 1279 1280 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir)) 1281 regmap_field_write(wiz->typec_ln10_swap, 1); 1282 else 1283 regmap_field_write(wiz->typec_ln10_swap, 0); 1284 } else { 1285 /* if no typec-dir gpio is specified and PHY type is USB3 1286 * with master lane number is '0' or '2', then set LN10 or 1287 * LN23 SWAP bit to '1' respectively. 1288 */ 1289 u32 num_lanes = wiz->num_lanes; 1290 int i; 1291 1292 for (i = 0; i < num_lanes; i++) { 1293 if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) { 1294 switch (wiz->master_lane_num[i]) { 1295 case LANE0: 1296 regmap_field_write(wiz->typec_ln10_swap, 1); 1297 break; 1298 case LANE2: 1299 regmap_field_write(wiz->typec_ln23_swap, 1); 1300 break; 1301 default: 1302 break; 1303 } 1304 } 1305 } 1306 } 1307 } 1308 1309 if (id == 0) { 1310 ret = regmap_field_write(wiz->phy_reset_n, true); 1311 return ret; 1312 } 1313 1314 ret = wiz_phy_fullrt_div(wiz, id - 1); 1315 if (ret) 1316 return ret; 1317 1318 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) 1319 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); 1320 else 1321 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); 1322 1323 return ret; 1324 } 1325 1326 static const struct reset_control_ops wiz_phy_reset_ops = { 1327 .assert = wiz_phy_reset_assert, 1328 .deassert = wiz_phy_reset_deassert, 1329 }; 1330 1331 static const struct regmap_config wiz_regmap_config = { 1332 .reg_bits = 32, 1333 .val_bits = 32, 1334 .reg_stride = 4, 1335 }; 1336 1337 static struct wiz_data j721e_16g_data = { 1338 .type = J721E_WIZ_16G, 1339 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1340 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1341 .refclk_dig_sel = &refclk_dig_sel_16g, 1342 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div, 1343 .clk_mux_sel = clk_mux_sel_16g, 1344 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G, 1345 }; 1346 1347 static struct wiz_data j721e_10g_data = { 1348 .type = J721E_WIZ_10G, 1349 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1350 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1351 .refclk_dig_sel = &refclk_dig_sel_10g, 1352 .clk_mux_sel = clk_mux_sel_10g, 1353 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1354 }; 1355 1356 static struct wiz_data am64_10g_data = { 1357 .type = AM64_WIZ_10G, 1358 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1359 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1360 .refclk_dig_sel = &refclk_dig_sel_10g, 1361 .clk_mux_sel = clk_mux_sel_10g, 1362 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1363 }; 1364 1365 static struct wiz_data j722s_10g_data = { 1366 .type = J722S_WIZ_10G, 1367 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1368 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1369 .refclk_dig_sel = &refclk_dig_sel_10g, 1370 .clk_mux_sel = clk_mux_sel_10g, 1371 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1372 }; 1373 1374 static struct wiz_data j7200_pg2_10g_data = { 1375 .type = J7200_WIZ_10G, 1376 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel, 1377 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel, 1378 .refclk_dig_sel = &sup_refclk_dig_sel_10g, 1379 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode, 1380 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1381 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1382 }; 1383 1384 static struct wiz_data j784s4_10g_data = { 1385 .type = J784S4_WIZ_10G, 1386 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, 1387 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, 1388 .refclk_dig_sel = &refclk_dig_sel_16g, 1389 .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, 1390 .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1391 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1392 }; 1393 1394 static struct wiz_data j721s2_10g_data = { 1395 .type = J721S2_WIZ_10G, 1396 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1397 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1398 .refclk_dig_sel = &refclk_dig_sel_10g, 1399 .clk_mux_sel = clk_mux_sel_10g, 1400 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1401 }; 1402 1403 static const struct of_device_id wiz_id_table[] = { 1404 { 1405 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, 1406 }, 1407 { 1408 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data, 1409 }, 1410 { 1411 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data, 1412 }, 1413 { 1414 .compatible = "ti,j722s-wiz-10g", .data = &j722s_10g_data, 1415 }, 1416 { 1417 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1418 }, 1419 { 1420 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, 1421 }, 1422 { 1423 .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data, 1424 }, 1425 {} 1426 }; 1427 MODULE_DEVICE_TABLE(of, wiz_id_table); 1428 1429 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz) 1430 { 1431 struct device_node *serdes; 1432 1433 serdes = of_get_child_by_name(dev->of_node, "serdes"); 1434 if (!serdes) { 1435 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__); 1436 return -EINVAL; 1437 } 1438 1439 for_each_child_of_node_scoped(serdes, subnode) { 1440 u32 reg, num_lanes = 1, phy_type = PHY_NONE; 1441 int ret, i; 1442 1443 if (!(of_node_name_eq(subnode, "phy") || 1444 of_node_name_eq(subnode, "link"))) 1445 continue; 1446 1447 ret = of_property_read_u32(subnode, "reg", ®); 1448 if (ret) { 1449 dev_err(dev, 1450 "%s: Reading \"reg\" from \"%s\" failed: %d\n", 1451 __func__, subnode->name, ret); 1452 of_node_put(serdes); 1453 return ret; 1454 } 1455 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes); 1456 of_property_read_u32(subnode, "cdns,phy-type", &phy_type); 1457 1458 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__, 1459 reg, reg + num_lanes - 1, phy_type); 1460 1461 for (i = reg; i < reg + num_lanes; i++) { 1462 wiz->master_lane_num[i] = reg; 1463 wiz->lane_phy_type[i] = phy_type; 1464 } 1465 } 1466 1467 of_node_put(serdes); 1468 return 0; 1469 } 1470 1471 static int wiz_probe(struct platform_device *pdev) 1472 { 1473 struct reset_controller_dev *phy_reset_dev; 1474 struct device *dev = &pdev->dev; 1475 struct device_node *node = dev->of_node; 1476 struct platform_device *serdes_pdev; 1477 bool already_configured = false; 1478 struct device_node *child_node; 1479 struct regmap *regmap; 1480 struct resource res; 1481 void __iomem *base; 1482 struct wiz *wiz; 1483 int ret, val, i; 1484 u32 num_lanes; 1485 const struct wiz_data *data; 1486 1487 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL); 1488 if (!wiz) 1489 return -ENOMEM; 1490 1491 data = of_device_get_match_data(dev); 1492 if (!data) { 1493 dev_err(dev, "NULL device data\n"); 1494 return -EINVAL; 1495 } 1496 1497 wiz->data = data; 1498 wiz->type = data->type; 1499 1500 child_node = of_get_child_by_name(node, "serdes"); 1501 if (!child_node) { 1502 dev_err(dev, "Failed to get SERDES child DT node\n"); 1503 return -ENODEV; 1504 } 1505 1506 ret = of_address_to_resource(child_node, 0, &res); 1507 if (ret) { 1508 dev_err(dev, "Failed to get memory resource\n"); 1509 goto err_addr_to_resource; 1510 } 1511 1512 base = devm_ioremap(dev, res.start, resource_size(&res)); 1513 if (!base) { 1514 ret = -ENOMEM; 1515 goto err_addr_to_resource; 1516 } 1517 1518 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); 1519 if (IS_ERR(regmap)) { 1520 dev_err(dev, "Failed to initialize regmap\n"); 1521 ret = PTR_ERR(regmap); 1522 goto err_addr_to_resource; 1523 } 1524 1525 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm"); 1526 if (IS_ERR(wiz->scm_regmap)) { 1527 if (wiz->type == J7200_WIZ_10G) { 1528 dev_err(dev, "Couldn't get ti,scm regmap\n"); 1529 ret = -ENODEV; 1530 goto err_addr_to_resource; 1531 } 1532 1533 wiz->scm_regmap = NULL; 1534 } 1535 1536 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 1537 if (ret) { 1538 dev_err(dev, "Failed to read num-lanes property\n"); 1539 goto err_addr_to_resource; 1540 } 1541 1542 if (num_lanes > WIZ_MAX_LANES) { 1543 dev_err(dev, "Cannot support %d lanes\n", num_lanes); 1544 ret = -ENODEV; 1545 goto err_addr_to_resource; 1546 } 1547 1548 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir", 1549 GPIOD_IN); 1550 if (IS_ERR(wiz->gpio_typec_dir)) { 1551 ret = PTR_ERR(wiz->gpio_typec_dir); 1552 if (ret != -EPROBE_DEFER) 1553 dev_err(dev, "Failed to request typec-dir gpio: %d\n", 1554 ret); 1555 goto err_addr_to_resource; 1556 } 1557 1558 if (wiz->gpio_typec_dir) { 1559 ret = of_property_read_u32(node, "typec-dir-debounce-ms", 1560 &wiz->typec_dir_delay); 1561 if (ret && ret != -EINVAL) { 1562 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1563 goto err_addr_to_resource; 1564 } 1565 1566 /* use min. debounce from Type-C spec if not provided in DT */ 1567 if (ret == -EINVAL) 1568 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN; 1569 1570 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1571 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1572 ret = -EINVAL; 1573 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1574 goto err_addr_to_resource; 1575 } 1576 } 1577 1578 ret = wiz_get_lane_phy_types(dev, wiz); 1579 if (ret) 1580 goto err_addr_to_resource; 1581 1582 wiz->dev = dev; 1583 wiz->regmap = regmap; 1584 wiz->num_lanes = num_lanes; 1585 wiz->clk_mux_sel = data->clk_mux_sel; 1586 wiz->clk_div_sel = clk_div_sel; 1587 wiz->clk_div_sel_num = data->clk_div_sel_num; 1588 1589 platform_set_drvdata(pdev, wiz); 1590 1591 ret = wiz_regfield_init(wiz); 1592 if (ret) { 1593 dev_err(dev, "Failed to initialize regfields\n"); 1594 goto err_addr_to_resource; 1595 } 1596 1597 /* Enable supplemental Control override if available */ 1598 if (wiz->scm_regmap) 1599 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1600 1601 phy_reset_dev = &wiz->wiz_phy_reset_dev; 1602 phy_reset_dev->dev = dev; 1603 phy_reset_dev->ops = &wiz_phy_reset_ops; 1604 phy_reset_dev->owner = THIS_MODULE; 1605 phy_reset_dev->of_node = node; 1606 /* Reset for each of the lane and one for the entire SERDES */ 1607 phy_reset_dev->nr_resets = num_lanes + 1; 1608 1609 ret = devm_reset_controller_register(dev, phy_reset_dev); 1610 if (ret < 0) { 1611 dev_warn(dev, "Failed to register reset controller\n"); 1612 goto err_addr_to_resource; 1613 } 1614 1615 pm_runtime_enable(dev); 1616 ret = pm_runtime_get_sync(dev); 1617 if (ret < 0) { 1618 dev_err(dev, "pm_runtime_get_sync failed\n"); 1619 goto err_get_sync; 1620 } 1621 1622 ret = wiz_clock_probe(wiz, node); 1623 if (ret < 0) { 1624 dev_warn(dev, "Failed to initialize clocks\n"); 1625 goto err_get_sync; 1626 } 1627 1628 for (i = 0; i < wiz->num_lanes; i++) { 1629 regmap_field_read(wiz->p_enable[i], &val); 1630 if (val & (P_ENABLE | P_ENABLE_FORCE)) { 1631 already_configured = true; 1632 break; 1633 } 1634 } 1635 1636 if (!already_configured) { 1637 ret = wiz_init(wiz); 1638 if (ret) { 1639 dev_err(dev, "WIZ initialization failed\n"); 1640 goto err_wiz_init; 1641 } 1642 } 1643 1644 serdes_pdev = of_platform_device_create(child_node, NULL, dev); 1645 if (!serdes_pdev) { 1646 dev_WARN(dev, "Unable to create SERDES platform device\n"); 1647 ret = -ENOMEM; 1648 goto err_wiz_init; 1649 } 1650 wiz->serdes_pdev = serdes_pdev; 1651 1652 of_node_put(child_node); 1653 return 0; 1654 1655 err_wiz_init: 1656 wiz_clock_cleanup(wiz, node); 1657 1658 err_get_sync: 1659 pm_runtime_put(dev); 1660 pm_runtime_disable(dev); 1661 1662 err_addr_to_resource: 1663 of_node_put(child_node); 1664 1665 return ret; 1666 } 1667 1668 static void wiz_remove(struct platform_device *pdev) 1669 { 1670 struct device *dev = &pdev->dev; 1671 struct device_node *node = dev->of_node; 1672 struct platform_device *serdes_pdev; 1673 struct wiz *wiz; 1674 1675 wiz = dev_get_drvdata(dev); 1676 serdes_pdev = wiz->serdes_pdev; 1677 1678 of_platform_device_destroy(&serdes_pdev->dev, NULL); 1679 wiz_clock_cleanup(wiz, node); 1680 pm_runtime_put(dev); 1681 pm_runtime_disable(dev); 1682 } 1683 1684 static int wiz_suspend_noirq(struct device *dev) 1685 { 1686 struct wiz *wiz = dev_get_drvdata(dev); 1687 int i; 1688 1689 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) 1690 regmap_field_read(wiz->mux_sel_field[i], &wiz->mux_sel_status[i]); 1691 1692 return 0; 1693 } 1694 1695 static int wiz_resume_noirq(struct device *dev) 1696 { 1697 struct device_node *node = dev->of_node; 1698 struct wiz *wiz = dev_get_drvdata(dev); 1699 int ret, i; 1700 1701 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) 1702 regmap_field_write(wiz->mux_sel_field[i], wiz->mux_sel_status[i]); 1703 1704 /* Enable supplemental Control override if available */ 1705 if (wiz->sup_legacy_clk_override) 1706 regmap_field_write(wiz->sup_legacy_clk_override, 1); 1707 1708 wiz_clock_init(wiz); 1709 1710 ret = wiz_init(wiz); 1711 if (ret) { 1712 dev_err(dev, "WIZ initialization failed\n"); 1713 goto err_wiz_init; 1714 } 1715 1716 return 0; 1717 1718 err_wiz_init: 1719 wiz_clock_cleanup(wiz, node); 1720 1721 return ret; 1722 } 1723 1724 static DEFINE_NOIRQ_DEV_PM_OPS(wiz_pm_ops, wiz_suspend_noirq, wiz_resume_noirq); 1725 1726 static struct platform_driver wiz_driver = { 1727 .probe = wiz_probe, 1728 .remove = wiz_remove, 1729 .driver = { 1730 .name = "wiz", 1731 .of_match_table = wiz_id_table, 1732 .pm = pm_sleep_ptr(&wiz_pm_ops), 1733 }, 1734 }; 1735 module_platform_driver(wiz_driver); 1736 1737 MODULE_AUTHOR("Texas Instruments Inc."); 1738 MODULE_DESCRIPTION("TI J721E WIZ driver"); 1739 MODULE_LICENSE("GPL v2"); 1740