1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Volume Management Device driver
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #include <linux/device.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip/irq-msi-lib.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/msi.h>
14 #include <linux/pci.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
17 #include <linux/srcu.h>
18 #include <linux/rculist.h>
19 #include <linux/rcupdate.h>
20
21 #include <xen/xen.h>
22
23 #include <asm/irqdomain.h>
24
25 #define VMD_CFGBAR 0
26 #define VMD_MEMBAR1 2
27 #define VMD_MEMBAR2 4
28
29 #define PCI_REG_VMCAP 0x40
30 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
31 #define PCI_REG_VMCONFIG 0x44
32 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
33 #define VMCONFIG_MSI_REMAP 0x2
34 #define PCI_REG_VMLOCK 0x70
35 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
36
37 #define MB2_SHADOW_OFFSET 0x2000
38 #define MB2_SHADOW_SIZE 16
39
40 enum vmd_features {
41 /*
42 * Device may contain registers which hint the physical location of the
43 * membars, in order to allow proper address translation during
44 * resource assignment to enable guest virtualization
45 */
46 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0),
47
48 /*
49 * Device may provide root port configuration information which limits
50 * bus numbering
51 */
52 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1),
53
54 /*
55 * Device contains physical location shadow registers in
56 * vendor-specific capability space
57 */
58 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2),
59
60 /*
61 * Device may use MSI-X vector 0 for software triggering and will not
62 * be used for MSI remapping
63 */
64 VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3),
65
66 /*
67 * Device can bypass remapping MSI-X transactions into its MSI-X table,
68 * avoiding the requirement of a VMD MSI domain for child device
69 * interrupt handling.
70 */
71 VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4),
72
73 /*
74 * Enable ASPM on the PCIE root ports and set the default LTR of the
75 * storage devices on platforms where these values are not configured by
76 * BIOS. This is needed for laptops, which require these settings for
77 * proper power management of the SoC.
78 */
79 VMD_FEAT_BIOS_PM_QUIRK = (1 << 5),
80 };
81
82 #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */
83
84 #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \
85 VMD_FEAT_HAS_BUS_RESTRICTIONS | \
86 VMD_FEAT_OFFSET_FIRST_VECTOR | \
87 VMD_FEAT_BIOS_PM_QUIRK)
88
89 static DEFINE_IDA(vmd_instance_ida);
90
91 /*
92 * Lock for manipulating VMD IRQ lists.
93 */
94 static DEFINE_RAW_SPINLOCK(list_lock);
95
96 /**
97 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector
98 * @node: list item for parent traversal.
99 * @irq: back pointer to parent.
100 * @enabled: true if driver enabled IRQ
101 * @virq: the virtual IRQ value provided to the requesting driver.
102 *
103 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
104 * a VMD IRQ using this structure.
105 */
106 struct vmd_irq {
107 struct list_head node;
108 struct vmd_irq_list *irq;
109 bool enabled;
110 unsigned int virq;
111 };
112
113 /**
114 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
115 * @irq_list: the list of irq's the VMD one demuxes to.
116 * @srcu: SRCU struct for local synchronization.
117 * @count: number of child IRQs assigned to this vector; used to track
118 * sharing.
119 * @virq: The underlying VMD Linux interrupt number
120 */
121 struct vmd_irq_list {
122 struct list_head irq_list;
123 struct srcu_struct srcu;
124 unsigned int count;
125 unsigned int virq;
126 };
127
128 struct vmd_dev {
129 struct pci_dev *dev;
130
131 raw_spinlock_t cfg_lock;
132 void __iomem *cfgbar;
133
134 int msix_count;
135 struct vmd_irq_list *irqs;
136
137 struct pci_sysdata sysdata;
138 struct resource resources[3];
139 struct irq_domain *irq_domain;
140 struct pci_bus *bus;
141 u8 busn_start;
142 u8 first_vec;
143 char *name;
144 int instance;
145 };
146
vmd_from_bus(struct pci_bus * bus)147 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
148 {
149 return container_of(bus->sysdata, struct vmd_dev, sysdata);
150 }
151
index_from_irqs(struct vmd_dev * vmd,struct vmd_irq_list * irqs)152 static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
153 struct vmd_irq_list *irqs)
154 {
155 return irqs - vmd->irqs;
156 }
157
158 /*
159 * Drivers managing a device in a VMD domain allocate their own IRQs as before,
160 * but the MSI entry for the hardware it's driving will be programmed with a
161 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
162 * domain into one of its own, and the VMD driver de-muxes these for the
163 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
164 * and irq_chip to set this up.
165 */
vmd_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)166 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
167 {
168 struct vmd_irq *vmdirq = data->chip_data;
169 struct vmd_irq_list *irq = vmdirq->irq;
170 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
171
172 memset(msg, 0, sizeof(*msg));
173 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
174 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
175 msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irq);
176 }
177
vmd_irq_enable(struct irq_data * data)178 static void vmd_irq_enable(struct irq_data *data)
179 {
180 struct vmd_irq *vmdirq = data->chip_data;
181
182 scoped_guard(raw_spinlock_irqsave, &list_lock) {
183 WARN_ON(vmdirq->enabled);
184 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
185 vmdirq->enabled = true;
186 }
187 }
188
vmd_pci_msi_enable(struct irq_data * data)189 static void vmd_pci_msi_enable(struct irq_data *data)
190 {
191 vmd_irq_enable(data->parent_data);
192 data->chip->irq_unmask(data);
193 }
194
vmd_irq_disable(struct irq_data * data)195 static void vmd_irq_disable(struct irq_data *data)
196 {
197 struct vmd_irq *vmdirq = data->chip_data;
198
199 scoped_guard(raw_spinlock_irqsave, &list_lock) {
200 if (vmdirq->enabled) {
201 list_del_rcu(&vmdirq->node);
202 vmdirq->enabled = false;
203 }
204 }
205 }
206
vmd_pci_msi_disable(struct irq_data * data)207 static void vmd_pci_msi_disable(struct irq_data *data)
208 {
209 data->chip->irq_mask(data);
210 vmd_irq_disable(data->parent_data);
211 }
212
213 static struct irq_chip vmd_msi_controller = {
214 .name = "VMD-MSI",
215 .irq_compose_msi_msg = vmd_compose_msi_msg,
216 };
217
218 /*
219 * XXX: We can be even smarter selecting the best IRQ once we solve the
220 * affinity problem.
221 */
vmd_next_irq(struct vmd_dev * vmd,struct msi_desc * desc)222 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
223 {
224 int i, best;
225
226 if (vmd->msix_count == 1 + vmd->first_vec)
227 return &vmd->irqs[vmd->first_vec];
228
229 /*
230 * White list for fast-interrupt handlers. All others will share the
231 * "slow" interrupt vector.
232 */
233 switch (msi_desc_to_pci_dev(desc)->class) {
234 case PCI_CLASS_STORAGE_EXPRESS:
235 break;
236 default:
237 return &vmd->irqs[vmd->first_vec];
238 }
239
240 scoped_guard(raw_spinlock_irq, &list_lock) {
241 best = vmd->first_vec + 1;
242 for (i = best; i < vmd->msix_count; i++)
243 if (vmd->irqs[i].count < vmd->irqs[best].count)
244 best = i;
245 vmd->irqs[best].count++;
246 }
247
248 return &vmd->irqs[best];
249 }
250
251 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq,
252 unsigned int nr_irqs);
253
vmd_msi_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)254 static int vmd_msi_alloc(struct irq_domain *domain, unsigned int virq,
255 unsigned int nr_irqs, void *arg)
256 {
257 struct msi_desc *desc = ((msi_alloc_info_t *)arg)->desc;
258 struct vmd_dev *vmd = domain->host_data;
259 struct vmd_irq *vmdirq;
260
261 for (int i = 0; i < nr_irqs; ++i) {
262 vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
263 if (!vmdirq) {
264 vmd_msi_free(domain, virq, i);
265 return -ENOMEM;
266 }
267
268 INIT_LIST_HEAD(&vmdirq->node);
269 vmdirq->irq = vmd_next_irq(vmd, desc);
270 vmdirq->virq = virq + i;
271
272 irq_domain_set_info(domain, virq + i, vmdirq->irq->virq,
273 &vmd_msi_controller, vmdirq,
274 handle_untracked_irq, vmd, NULL);
275 }
276
277 return 0;
278 }
279
vmd_msi_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)280 static void vmd_msi_free(struct irq_domain *domain, unsigned int virq,
281 unsigned int nr_irqs)
282 {
283 struct irq_data *irq_data;
284 struct vmd_irq *vmdirq;
285
286 for (int i = 0; i < nr_irqs; ++i) {
287 irq_data = irq_domain_get_irq_data(domain, virq + i);
288 vmdirq = irq_data->chip_data;
289
290 synchronize_srcu(&vmdirq->irq->srcu);
291
292 /* XXX: Potential optimization to rebalance */
293 scoped_guard(raw_spinlock_irq, &list_lock)
294 vmdirq->irq->count--;
295
296 kfree(vmdirq);
297 }
298 }
299
300 static const struct irq_domain_ops vmd_msi_domain_ops = {
301 .alloc = vmd_msi_alloc,
302 .free = vmd_msi_free,
303 };
304
vmd_init_dev_msi_info(struct device * dev,struct irq_domain * domain,struct irq_domain * real_parent,struct msi_domain_info * info)305 static bool vmd_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
306 struct irq_domain *real_parent,
307 struct msi_domain_info *info)
308 {
309 if (WARN_ON_ONCE(info->bus_token != DOMAIN_BUS_PCI_DEVICE_MSIX))
310 return false;
311
312 if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info))
313 return false;
314
315 info->chip->irq_enable = vmd_pci_msi_enable;
316 info->chip->irq_disable = vmd_pci_msi_disable;
317 return true;
318 }
319
320 #define VMD_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX)
321 #define VMD_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_NO_AFFINITY)
322
323 static const struct msi_parent_ops vmd_msi_parent_ops = {
324 .supported_flags = VMD_MSI_FLAGS_SUPPORTED,
325 .required_flags = VMD_MSI_FLAGS_REQUIRED,
326 .bus_select_token = DOMAIN_BUS_VMD_MSI,
327 .bus_select_mask = MATCH_PCI_MSI,
328 .prefix = "VMD-",
329 .init_dev_msi_info = vmd_init_dev_msi_info,
330 };
331
vmd_create_irq_domain(struct vmd_dev * vmd)332 static int vmd_create_irq_domain(struct vmd_dev *vmd)
333 {
334 struct irq_domain_info info = {
335 .size = vmd->msix_count,
336 .ops = &vmd_msi_domain_ops,
337 .host_data = vmd,
338 };
339
340 info.fwnode = irq_domain_alloc_named_id_fwnode("VMD-MSI",
341 vmd->sysdata.domain);
342 if (!info.fwnode)
343 return -ENODEV;
344
345 vmd->irq_domain = msi_create_parent_irq_domain(&info,
346 &vmd_msi_parent_ops);
347 if (!vmd->irq_domain) {
348 irq_domain_free_fwnode(info.fwnode);
349 return -ENODEV;
350 }
351
352 return 0;
353 }
354
vmd_set_msi_remapping(struct vmd_dev * vmd,bool enable)355 static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable)
356 {
357 u16 reg;
358
359 pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, ®);
360 reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) :
361 (reg | VMCONFIG_MSI_REMAP);
362 pci_write_config_word(vmd->dev, PCI_REG_VMCONFIG, reg);
363 }
364
vmd_remove_irq_domain(struct vmd_dev * vmd)365 static void vmd_remove_irq_domain(struct vmd_dev *vmd)
366 {
367 /*
368 * Some production BIOS won't enable remapping between soft reboots.
369 * Ensure remapping is restored before unloading the driver.
370 */
371 if (!vmd->msix_count)
372 vmd_set_msi_remapping(vmd, true);
373
374 if (vmd->irq_domain) {
375 struct fwnode_handle *fn = vmd->irq_domain->fwnode;
376
377 irq_domain_remove(vmd->irq_domain);
378 irq_domain_free_fwnode(fn);
379 }
380 }
381
vmd_cfg_addr(struct vmd_dev * vmd,struct pci_bus * bus,unsigned int devfn,int reg,int len)382 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
383 unsigned int devfn, int reg, int len)
384 {
385 unsigned int busnr_ecam = bus->number - vmd->busn_start;
386 u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg);
387
388 if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR]))
389 return NULL;
390
391 return vmd->cfgbar + offset;
392 }
393
394 /*
395 * CPU may deadlock if config space is not serialized on some versions of this
396 * hardware, so all config space access is done under a spinlock.
397 */
vmd_pci_read(struct pci_bus * bus,unsigned int devfn,int reg,int len,u32 * value)398 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
399 int len, u32 *value)
400 {
401 struct vmd_dev *vmd = vmd_from_bus(bus);
402 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
403
404 if (!addr)
405 return -EFAULT;
406
407 guard(raw_spinlock_irqsave)(&vmd->cfg_lock);
408 switch (len) {
409 case 1:
410 *value = readb(addr);
411 return 0;
412 case 2:
413 *value = readw(addr);
414 return 0;
415 case 4:
416 *value = readl(addr);
417 return 0;
418 default:
419 return -EINVAL;
420 }
421 }
422
423 /*
424 * VMD h/w converts non-posted config writes to posted memory writes. The
425 * read-back in this function forces the completion so it returns only after
426 * the config space was written, as expected.
427 */
vmd_pci_write(struct pci_bus * bus,unsigned int devfn,int reg,int len,u32 value)428 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
429 int len, u32 value)
430 {
431 struct vmd_dev *vmd = vmd_from_bus(bus);
432 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
433
434 if (!addr)
435 return -EFAULT;
436
437 guard(raw_spinlock_irqsave)(&vmd->cfg_lock);
438 switch (len) {
439 case 1:
440 writeb(value, addr);
441 readb(addr);
442 return 0;
443 case 2:
444 writew(value, addr);
445 readw(addr);
446 return 0;
447 case 4:
448 writel(value, addr);
449 readl(addr);
450 return 0;
451 default:
452 return -EINVAL;
453 }
454 }
455
456 static struct pci_ops vmd_ops = {
457 .read = vmd_pci_read,
458 .write = vmd_pci_write,
459 };
460
461 #ifdef CONFIG_ACPI
vmd_acpi_find_companion(struct pci_dev * pci_dev)462 static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev)
463 {
464 struct pci_host_bridge *bridge;
465 u32 busnr, addr;
466
467 if (pci_dev->bus->ops != &vmd_ops)
468 return NULL;
469
470 bridge = pci_find_host_bridge(pci_dev->bus);
471 busnr = pci_dev->bus->number - bridge->bus->number;
472 /*
473 * The address computation below is only applicable to relative bus
474 * numbers below 32.
475 */
476 if (busnr > 31)
477 return NULL;
478
479 addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU;
480
481 dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n",
482 addr);
483
484 return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), addr,
485 false);
486 }
487
488 static bool hook_installed;
489
vmd_acpi_begin(void)490 static void vmd_acpi_begin(void)
491 {
492 if (pci_acpi_set_companion_lookup_hook(vmd_acpi_find_companion))
493 return;
494
495 hook_installed = true;
496 }
497
vmd_acpi_end(void)498 static void vmd_acpi_end(void)
499 {
500 if (!hook_installed)
501 return;
502
503 pci_acpi_clear_companion_lookup_hook();
504 hook_installed = false;
505 }
506 #else
vmd_acpi_begin(void)507 static inline void vmd_acpi_begin(void) { }
vmd_acpi_end(void)508 static inline void vmd_acpi_end(void) { }
509 #endif /* CONFIG_ACPI */
510
vmd_domain_reset(struct vmd_dev * vmd)511 static void vmd_domain_reset(struct vmd_dev *vmd)
512 {
513 u16 bus, max_buses = resource_size(&vmd->resources[0]);
514 u8 dev, functions, fn, hdr_type;
515 char __iomem *base;
516
517 for (bus = 0; bus < max_buses; bus++) {
518 for (dev = 0; dev < 32; dev++) {
519 base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus,
520 PCI_DEVFN(dev, 0), 0);
521
522 hdr_type = readb(base + PCI_HEADER_TYPE);
523
524 functions = (hdr_type & PCI_HEADER_TYPE_MFD) ? 8 : 1;
525 for (fn = 0; fn < functions; fn++) {
526 base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus,
527 PCI_DEVFN(dev, fn), 0);
528
529 hdr_type = readb(base + PCI_HEADER_TYPE) &
530 PCI_HEADER_TYPE_MASK;
531
532 if (hdr_type != PCI_HEADER_TYPE_BRIDGE ||
533 (readw(base + PCI_CLASS_DEVICE) !=
534 PCI_CLASS_BRIDGE_PCI))
535 continue;
536
537 /*
538 * Temporarily disable the I/O range before updating
539 * PCI_IO_BASE.
540 */
541 writel(0x0000ffff, base + PCI_IO_BASE_UPPER16);
542 /* Update lower 16 bits of I/O base/limit */
543 writew(0x00f0, base + PCI_IO_BASE);
544 /* Update upper 16 bits of I/O base/limit */
545 writel(0, base + PCI_IO_BASE_UPPER16);
546
547 /* MMIO Base/Limit */
548 writel(0x0000fff0, base + PCI_MEMORY_BASE);
549
550 /* Prefetchable MMIO Base/Limit */
551 writel(0, base + PCI_PREF_LIMIT_UPPER32);
552 writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE);
553 writel(0xffffffff, base + PCI_PREF_BASE_UPPER32);
554 }
555 }
556 }
557 }
558
vmd_attach_resources(struct vmd_dev * vmd)559 static void vmd_attach_resources(struct vmd_dev *vmd)
560 {
561 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
562 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
563 }
564
vmd_detach_resources(struct vmd_dev * vmd)565 static void vmd_detach_resources(struct vmd_dev *vmd)
566 {
567 vmd->dev->resource[VMD_MEMBAR1].child = NULL;
568 vmd->dev->resource[VMD_MEMBAR2].child = NULL;
569 }
570
571 /*
572 * VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
573 * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
574 * 16 bits are the PCI Segment Group (domain) number. Other bits are
575 * currently reserved.
576 */
vmd_find_free_domain(void)577 static int vmd_find_free_domain(void)
578 {
579 int domain = 0xffff;
580 struct pci_bus *bus = NULL;
581
582 while ((bus = pci_find_next_bus(bus)) != NULL)
583 domain = max_t(int, domain, pci_domain_nr(bus));
584 return domain + 1;
585 }
586
vmd_get_phys_offsets(struct vmd_dev * vmd,bool native_hint,resource_size_t * offset1,resource_size_t * offset2)587 static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
588 resource_size_t *offset1,
589 resource_size_t *offset2)
590 {
591 struct pci_dev *dev = vmd->dev;
592 u64 phys1, phys2;
593
594 if (native_hint) {
595 u32 vmlock;
596 int ret;
597
598 ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock);
599 if (ret || PCI_POSSIBLE_ERROR(vmlock))
600 return -ENODEV;
601
602 if (MB2_SHADOW_EN(vmlock)) {
603 void __iomem *membar2;
604
605 membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
606 if (!membar2)
607 return -ENOMEM;
608 phys1 = readq(membar2 + MB2_SHADOW_OFFSET);
609 phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8);
610 pci_iounmap(dev, membar2);
611 } else
612 return 0;
613 } else {
614 /* Hypervisor-Emulated Vendor-Specific Capability */
615 int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
616 u32 reg, regu;
617
618 pci_read_config_dword(dev, pos + 4, ®);
619
620 /* "SHDW" */
621 if (pos && reg == 0x53484457) {
622 pci_read_config_dword(dev, pos + 8, ®);
623 pci_read_config_dword(dev, pos + 12, ®u);
624 phys1 = (u64) regu << 32 | reg;
625
626 pci_read_config_dword(dev, pos + 16, ®);
627 pci_read_config_dword(dev, pos + 20, ®u);
628 phys2 = (u64) regu << 32 | reg;
629 } else
630 return 0;
631 }
632
633 *offset1 = dev->resource[VMD_MEMBAR1].start -
634 (phys1 & PCI_BASE_ADDRESS_MEM_MASK);
635 *offset2 = dev->resource[VMD_MEMBAR2].start -
636 (phys2 & PCI_BASE_ADDRESS_MEM_MASK);
637
638 return 0;
639 }
640
vmd_get_bus_number_start(struct vmd_dev * vmd)641 static int vmd_get_bus_number_start(struct vmd_dev *vmd)
642 {
643 struct pci_dev *dev = vmd->dev;
644 u16 reg;
645
646 pci_read_config_word(dev, PCI_REG_VMCAP, ®);
647 if (BUS_RESTRICT_CAP(reg)) {
648 pci_read_config_word(dev, PCI_REG_VMCONFIG, ®);
649
650 switch (BUS_RESTRICT_CFG(reg)) {
651 case 0:
652 vmd->busn_start = 0;
653 break;
654 case 1:
655 vmd->busn_start = 128;
656 break;
657 case 2:
658 vmd->busn_start = 224;
659 break;
660 default:
661 pci_err(dev, "Unknown Bus Offset Setting (%d)\n",
662 BUS_RESTRICT_CFG(reg));
663 return -ENODEV;
664 }
665 }
666
667 return 0;
668 }
669
vmd_irq(int irq,void * data)670 static irqreturn_t vmd_irq(int irq, void *data)
671 {
672 struct vmd_irq_list *irqs = data;
673 struct vmd_irq *vmdirq;
674 int idx;
675
676 idx = srcu_read_lock(&irqs->srcu);
677 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
678 generic_handle_irq(vmdirq->virq);
679 srcu_read_unlock(&irqs->srcu, idx);
680
681 return IRQ_HANDLED;
682 }
683
vmd_alloc_irqs(struct vmd_dev * vmd)684 static int vmd_alloc_irqs(struct vmd_dev *vmd)
685 {
686 struct pci_dev *dev = vmd->dev;
687 int i, err;
688
689 vmd->msix_count = pci_msix_vec_count(dev);
690 if (vmd->msix_count < 0)
691 return -ENODEV;
692
693 vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1,
694 vmd->msix_count, PCI_IRQ_MSIX);
695 if (vmd->msix_count < 0)
696 return vmd->msix_count;
697
698 vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
699 GFP_KERNEL);
700 if (!vmd->irqs)
701 return -ENOMEM;
702
703 for (i = 0; i < vmd->msix_count; i++) {
704 err = init_srcu_struct(&vmd->irqs[i].srcu);
705 if (err)
706 return err;
707
708 INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
709 vmd->irqs[i].virq = pci_irq_vector(dev, i);
710 err = devm_request_irq(&dev->dev, vmd->irqs[i].virq,
711 vmd_irq, IRQF_NO_THREAD,
712 vmd->name, &vmd->irqs[i]);
713 if (err)
714 return err;
715 }
716
717 return 0;
718 }
719
720 /*
721 * Since VMD is an aperture to regular PCIe root ports, only allow it to
722 * control features that the OS is allowed to control on the physical PCI bus.
723 */
vmd_copy_host_bridge_flags(struct pci_host_bridge * root_bridge,struct pci_host_bridge * vmd_bridge)724 static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge,
725 struct pci_host_bridge *vmd_bridge)
726 {
727 vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug;
728 vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug;
729 vmd_bridge->native_aer = root_bridge->native_aer;
730 vmd_bridge->native_pme = root_bridge->native_pme;
731 vmd_bridge->native_ltr = root_bridge->native_ltr;
732 vmd_bridge->native_dpc = root_bridge->native_dpc;
733 }
734
735 /*
736 * Enable ASPM and LTR settings on devices that aren't configured by BIOS.
737 */
vmd_pm_enable_quirk(struct pci_dev * pdev,void * userdata)738 static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata)
739 {
740 unsigned long features = *(unsigned long *)userdata;
741 u16 ltr = VMD_BIOS_PM_QUIRK_LTR;
742 u32 ltr_reg;
743 int pos;
744
745 if (!(features & VMD_FEAT_BIOS_PM_QUIRK))
746 return 0;
747
748 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR);
749 if (!pos)
750 goto out_state_change;
751
752 /*
753 * Skip if the max snoop LTR is non-zero, indicating BIOS has set it
754 * so the LTR quirk is not needed.
755 */
756 pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg);
757 if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK)))
758 goto out_state_change;
759
760 /*
761 * Set the default values to the maximum required by the platform to
762 * allow the deepest power management savings. Write as a DWORD where
763 * the lower word is the max snoop latency and the upper word is the
764 * max non-snoop latency.
765 */
766 ltr_reg = (ltr << 16) | ltr;
767 pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg);
768 pci_info(pdev, "VMD: Default LTR value set by driver\n");
769
770 out_state_change:
771 /*
772 * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
773 * PCIe r6.0, sec 5.5.4.
774 */
775 pci_set_power_state_locked(pdev, PCI_D0);
776 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
777 return 0;
778 }
779
vmd_enable_domain(struct vmd_dev * vmd,unsigned long features)780 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
781 {
782 struct pci_sysdata *sd = &vmd->sysdata;
783 struct resource *res;
784 u32 upper_bits;
785 unsigned long flags;
786 LIST_HEAD(resources);
787 resource_size_t offset[2] = {0};
788 resource_size_t membar2_offset = 0x2000;
789 struct pci_bus *child;
790 struct pci_dev *dev;
791 int ret;
792
793 /*
794 * Shadow registers may exist in certain VMD device ids which allow
795 * guests to correctly assign host physical addresses to the root ports
796 * and child devices. These registers will either return the host value
797 * or 0, depending on an enable bit in the VMD device.
798 */
799 if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
800 membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
801 ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]);
802 if (ret)
803 return ret;
804 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) {
805 ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]);
806 if (ret)
807 return ret;
808 }
809
810 /*
811 * Certain VMD devices may have a root port configuration option which
812 * limits the bus range to between 0-127, 128-255, or 224-255
813 */
814 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
815 ret = vmd_get_bus_number_start(vmd);
816 if (ret)
817 return ret;
818 }
819
820 res = &vmd->dev->resource[VMD_CFGBAR];
821 vmd->resources[0] = (struct resource) {
822 .name = "VMD CFGBAR",
823 .start = vmd->busn_start,
824 .end = vmd->busn_start + (resource_size(res) >> 20) - 1,
825 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
826 };
827
828 /*
829 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
830 * put 32-bit resources in the window.
831 *
832 * There's no hardware reason why a 64-bit window *couldn't*
833 * contain a 32-bit resource, but pbus_size_mem() computes the
834 * bridge window size assuming a 64-bit window will contain no
835 * 32-bit resources. __pci_assign_resource() enforces that
836 * artificial restriction to make sure everything will fit.
837 *
838 * The only way we could use a 64-bit non-prefetchable MEMBAR is
839 * if its address is <4GB so that we can convert it to a 32-bit
840 * resource. To be visible to the host OS, all VMD endpoints must
841 * be initially configured by platform BIOS, which includes setting
842 * up these resources. We can assume the device is configured
843 * according to the platform needs.
844 */
845 res = &vmd->dev->resource[VMD_MEMBAR1];
846 upper_bits = upper_32_bits(res->end);
847 flags = res->flags & ~IORESOURCE_SIZEALIGN;
848 if (!upper_bits)
849 flags &= ~IORESOURCE_MEM_64;
850 vmd->resources[1] = (struct resource) {
851 .name = "VMD MEMBAR1",
852 .start = res->start,
853 .end = res->end,
854 .flags = flags,
855 .parent = res,
856 };
857
858 res = &vmd->dev->resource[VMD_MEMBAR2];
859 upper_bits = upper_32_bits(res->end);
860 flags = res->flags & ~IORESOURCE_SIZEALIGN;
861 if (!upper_bits)
862 flags &= ~IORESOURCE_MEM_64;
863 vmd->resources[2] = (struct resource) {
864 .name = "VMD MEMBAR2",
865 .start = res->start + membar2_offset,
866 .end = res->end,
867 .flags = flags,
868 .parent = res,
869 };
870
871 sd->vmd_dev = vmd->dev;
872 sd->domain = vmd_find_free_domain();
873 if (sd->domain < 0)
874 return sd->domain;
875
876 sd->node = pcibus_to_node(vmd->dev->bus);
877
878 /*
879 * Currently MSI remapping must be enabled in guest passthrough mode
880 * due to some missing interrupt remapping plumbing. This is probably
881 * acceptable because the guest is usually CPU-limited and MSI
882 * remapping doesn't become a performance bottleneck.
883 */
884 if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) ||
885 offset[0] || offset[1]) {
886 ret = vmd_alloc_irqs(vmd);
887 if (ret)
888 return ret;
889
890 vmd_set_msi_remapping(vmd, true);
891
892 ret = vmd_create_irq_domain(vmd);
893 if (ret)
894 return ret;
895 } else {
896 vmd_set_msi_remapping(vmd, false);
897 }
898
899 pci_add_resource(&resources, &vmd->resources[0]);
900 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
901 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
902
903 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
904 &vmd_ops, sd, &resources);
905 if (!vmd->bus) {
906 pci_free_resource_list(&resources);
907 vmd_remove_irq_domain(vmd);
908 return -ENODEV;
909 }
910
911 vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus),
912 to_pci_host_bridge(vmd->bus->bridge));
913
914 vmd_attach_resources(vmd);
915 if (vmd->irq_domain)
916 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
917 else
918 dev_set_msi_domain(&vmd->bus->dev,
919 dev_get_msi_domain(&vmd->dev->dev));
920
921 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
922 "domain"), "Can't create symlink to domain\n");
923
924 vmd_acpi_begin();
925
926 pci_scan_child_bus(vmd->bus);
927 vmd_domain_reset(vmd);
928
929 /* When Intel VMD is enabled, the OS does not discover the Root Ports
930 * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies
931 * a reset to the parent of the PCI device supplied as argument. This
932 * is why we pass a child device, so the reset can be triggered at
933 * the Intel bridge level and propagated to all the children in the
934 * hierarchy.
935 */
936 list_for_each_entry(child, &vmd->bus->children, node) {
937 if (!list_empty(&child->devices)) {
938 dev = list_first_entry(&child->devices,
939 struct pci_dev, bus_list);
940 ret = pci_reset_bus(dev);
941 if (ret)
942 pci_warn(dev, "can't reset device: %d\n", ret);
943
944 break;
945 }
946 }
947
948 pci_assign_unassigned_bus_resources(vmd->bus);
949
950 pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features);
951
952 /*
953 * VMD root buses are virtual and don't return true on pci_is_pcie()
954 * and will fail pcie_bus_configure_settings() early. It can instead be
955 * run on each of the real root ports.
956 */
957 list_for_each_entry(child, &vmd->bus->children, node)
958 pcie_bus_configure_settings(child);
959
960 pci_bus_add_devices(vmd->bus);
961
962 vmd_acpi_end();
963 return 0;
964 }
965
vmd_probe(struct pci_dev * dev,const struct pci_device_id * id)966 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
967 {
968 unsigned long features = (unsigned long) id->driver_data;
969 struct vmd_dev *vmd;
970 int err;
971
972 if (xen_domain()) {
973 /*
974 * Xen doesn't have knowledge about devices in the VMD bus
975 * because the config space of devices behind the VMD bridge is
976 * not known to Xen, and hence Xen cannot discover or configure
977 * them in any way.
978 *
979 * Bypass of MSI remapping won't work in that case as direct
980 * write by Linux to the MSI entries won't result in functional
981 * interrupts, as Xen is the entity that manages the host
982 * interrupt controller and must configure interrupts. However
983 * multiplexing of interrupts by the VMD bridge will work under
984 * Xen, so force the usage of that mode which must always be
985 * supported by VMD bridges.
986 */
987 features &= ~VMD_FEAT_CAN_BYPASS_MSI_REMAP;
988 }
989
990 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
991 return -ENOMEM;
992
993 vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
994 if (!vmd)
995 return -ENOMEM;
996
997 vmd->dev = dev;
998 vmd->instance = ida_alloc(&vmd_instance_ida, GFP_KERNEL);
999 if (vmd->instance < 0)
1000 return vmd->instance;
1001
1002 vmd->name = devm_kasprintf(&dev->dev, GFP_KERNEL, "vmd%d",
1003 vmd->instance);
1004 if (!vmd->name) {
1005 err = -ENOMEM;
1006 goto out_release_instance;
1007 }
1008
1009 err = pcim_enable_device(dev);
1010 if (err < 0)
1011 goto out_release_instance;
1012
1013 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
1014 if (!vmd->cfgbar) {
1015 err = -ENOMEM;
1016 goto out_release_instance;
1017 }
1018
1019 pci_set_master(dev);
1020 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
1021 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) {
1022 err = -ENODEV;
1023 goto out_release_instance;
1024 }
1025
1026 if (features & VMD_FEAT_OFFSET_FIRST_VECTOR)
1027 vmd->first_vec = 1;
1028
1029 raw_spin_lock_init(&vmd->cfg_lock);
1030 pci_set_drvdata(dev, vmd);
1031 err = vmd_enable_domain(vmd, features);
1032 if (err)
1033 goto out_release_instance;
1034
1035 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
1036 vmd->sysdata.domain);
1037 return 0;
1038
1039 out_release_instance:
1040 ida_free(&vmd_instance_ida, vmd->instance);
1041 return err;
1042 }
1043
vmd_cleanup_srcu(struct vmd_dev * vmd)1044 static void vmd_cleanup_srcu(struct vmd_dev *vmd)
1045 {
1046 int i;
1047
1048 for (i = 0; i < vmd->msix_count; i++)
1049 cleanup_srcu_struct(&vmd->irqs[i].srcu);
1050 }
1051
vmd_remove(struct pci_dev * dev)1052 static void vmd_remove(struct pci_dev *dev)
1053 {
1054 struct vmd_dev *vmd = pci_get_drvdata(dev);
1055
1056 pci_stop_root_bus(vmd->bus);
1057 sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
1058 pci_remove_root_bus(vmd->bus);
1059 vmd_cleanup_srcu(vmd);
1060 vmd_detach_resources(vmd);
1061 vmd_remove_irq_domain(vmd);
1062 ida_free(&vmd_instance_ida, vmd->instance);
1063 }
1064
vmd_shutdown(struct pci_dev * dev)1065 static void vmd_shutdown(struct pci_dev *dev)
1066 {
1067 struct vmd_dev *vmd = pci_get_drvdata(dev);
1068
1069 vmd_remove_irq_domain(vmd);
1070 }
1071
1072 #ifdef CONFIG_PM_SLEEP
vmd_suspend(struct device * dev)1073 static int vmd_suspend(struct device *dev)
1074 {
1075 struct pci_dev *pdev = to_pci_dev(dev);
1076 struct vmd_dev *vmd = pci_get_drvdata(pdev);
1077 int i;
1078
1079 for (i = 0; i < vmd->msix_count; i++)
1080 devm_free_irq(dev, vmd->irqs[i].virq, &vmd->irqs[i]);
1081
1082 return 0;
1083 }
1084
vmd_resume(struct device * dev)1085 static int vmd_resume(struct device *dev)
1086 {
1087 struct pci_dev *pdev = to_pci_dev(dev);
1088 struct vmd_dev *vmd = pci_get_drvdata(pdev);
1089 int err, i;
1090
1091 vmd_set_msi_remapping(vmd, !!vmd->irq_domain);
1092
1093 for (i = 0; i < vmd->msix_count; i++) {
1094 err = devm_request_irq(dev, vmd->irqs[i].virq,
1095 vmd_irq, IRQF_NO_THREAD,
1096 vmd->name, &vmd->irqs[i]);
1097 if (err)
1098 return err;
1099 }
1100
1101 return 0;
1102 }
1103 #endif
1104 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
1105
1106 static const struct pci_device_id vmd_ids[] = {
1107 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
1108 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
1109 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
1110 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
1111 VMD_FEAT_HAS_BUS_RESTRICTIONS |
1112 VMD_FEAT_CAN_BYPASS_MSI_REMAP,},
1113 {PCI_VDEVICE(INTEL, 0x467f),
1114 .driver_data = VMD_FEATS_CLIENT,},
1115 {PCI_VDEVICE(INTEL, 0x4c3d),
1116 .driver_data = VMD_FEATS_CLIENT,},
1117 {PCI_VDEVICE(INTEL, 0xa77f),
1118 .driver_data = VMD_FEATS_CLIENT,},
1119 {PCI_VDEVICE(INTEL, 0x7d0b),
1120 .driver_data = VMD_FEATS_CLIENT,},
1121 {PCI_VDEVICE(INTEL, 0xad0b),
1122 .driver_data = VMD_FEATS_CLIENT,},
1123 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
1124 .driver_data = VMD_FEATS_CLIENT,},
1125 {PCI_VDEVICE(INTEL, 0xb60b),
1126 .driver_data = VMD_FEATS_CLIENT,},
1127 {PCI_VDEVICE(INTEL, 0xb06f),
1128 .driver_data = VMD_FEATS_CLIENT,},
1129 {PCI_VDEVICE(INTEL, 0xb07f),
1130 .driver_data = VMD_FEATS_CLIENT,},
1131 {0,}
1132 };
1133 MODULE_DEVICE_TABLE(pci, vmd_ids);
1134
1135 static struct pci_driver vmd_drv = {
1136 .name = "vmd",
1137 .id_table = vmd_ids,
1138 .probe = vmd_probe,
1139 .remove = vmd_remove,
1140 .shutdown = vmd_shutdown,
1141 .driver = {
1142 .pm = &vmd_dev_pm_ops,
1143 },
1144 };
1145 module_pci_driver(vmd_drv);
1146
1147 MODULE_AUTHOR("Intel Corporation");
1148 MODULE_DESCRIPTION("Volume Management Device driver");
1149 MODULE_LICENSE("GPL v2");
1150 MODULE_VERSION("0.6");
1151