1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/serial.h> 7 #include <linux/serial_reg.h> 8 #include <linux/slab.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/console.h> 12 #include <linux/serial_core.h> 13 #include <linux/tty.h> 14 #include <linux/tty_flip.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/dmi.h> 18 #include <linux/nmi.h> 19 #include <linux/delay.h> 20 #include <linux/of.h> 21 22 #include <linux/debugfs.h> 23 #include <linux/dmaengine.h> 24 #include <linux/pch_dma.h> 25 26 enum { 27 PCH_UART_HANDLED_RX_INT_SHIFT, 28 PCH_UART_HANDLED_TX_INT_SHIFT, 29 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 30 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 31 PCH_UART_HANDLED_MS_INT_SHIFT, 32 PCH_UART_HANDLED_LS_INT_SHIFT, 33 }; 34 35 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 36 37 /* Set the max number of UART port 38 * Intel EG20T PCH: 4 port 39 * LAPIS Semiconductor ML7213 IOH: 3 port 40 * LAPIS Semiconductor ML7223 IOH: 2 port 41 */ 42 #define PCH_UART_NR 4 43 44 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 45 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 46 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 47 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 48 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 49 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 50 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 51 52 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 53 54 #define PCH_UART_RBR 0x00 55 #define PCH_UART_THR 0x00 56 57 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 58 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 59 #define PCH_UART_IER_ERBFI 0x00000001 60 #define PCH_UART_IER_ETBEI 0x00000002 61 #define PCH_UART_IER_ELSI 0x00000004 62 #define PCH_UART_IER_EDSSI 0x00000008 63 64 #define PCH_UART_IIR_IP 0x00000001 65 #define PCH_UART_IIR_IID 0x00000006 66 #define PCH_UART_IIR_MSI 0x00000000 67 #define PCH_UART_IIR_TRI 0x00000002 68 #define PCH_UART_IIR_RRI 0x00000004 69 #define PCH_UART_IIR_REI 0x00000006 70 #define PCH_UART_IIR_TOI 0x00000008 71 #define PCH_UART_IIR_FIFO256 0x00000020 72 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 73 #define PCH_UART_IIR_FE 0x000000C0 74 75 #define PCH_UART_FCR_FIFOE 0x00000001 76 #define PCH_UART_FCR_RFR 0x00000002 77 #define PCH_UART_FCR_TFR 0x00000004 78 #define PCH_UART_FCR_DMS 0x00000008 79 #define PCH_UART_FCR_FIFO256 0x00000020 80 #define PCH_UART_FCR_RFTL 0x000000C0 81 82 #define PCH_UART_FCR_RFTL1 0x00000000 83 #define PCH_UART_FCR_RFTL64 0x00000040 84 #define PCH_UART_FCR_RFTL128 0x00000080 85 #define PCH_UART_FCR_RFTL224 0x000000C0 86 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 87 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 88 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 89 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 90 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 91 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 92 #define PCH_UART_FCR_RFTL_SHIFT 6 93 94 #define PCH_UART_LCR_WLS 0x00000003 95 #define PCH_UART_LCR_STB 0x00000004 96 #define PCH_UART_LCR_PEN 0x00000008 97 #define PCH_UART_LCR_EPS 0x00000010 98 #define PCH_UART_LCR_SP 0x00000020 99 #define PCH_UART_LCR_SB 0x00000040 100 #define PCH_UART_LCR_DLAB 0x00000080 101 #define PCH_UART_LCR_NP 0x00000000 102 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 103 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 104 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 105 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 106 PCH_UART_LCR_SP) 107 108 #define PCH_UART_LCR_5BIT 0x00000000 109 #define PCH_UART_LCR_6BIT 0x00000001 110 #define PCH_UART_LCR_7BIT 0x00000002 111 #define PCH_UART_LCR_8BIT 0x00000003 112 113 #define PCH_UART_MCR_DTR 0x00000001 114 #define PCH_UART_MCR_RTS 0x00000002 115 #define PCH_UART_MCR_OUT 0x0000000C 116 #define PCH_UART_MCR_LOOP 0x00000010 117 #define PCH_UART_MCR_AFE 0x00000020 118 119 #define PCH_UART_LSR_DR 0x00000001 120 #define PCH_UART_LSR_ERR (1<<7) 121 122 #define PCH_UART_MSR_DCTS 0x00000001 123 #define PCH_UART_MSR_DDSR 0x00000002 124 #define PCH_UART_MSR_TERI 0x00000004 125 #define PCH_UART_MSR_DDCD 0x00000008 126 #define PCH_UART_MSR_CTS 0x00000010 127 #define PCH_UART_MSR_DSR 0x00000020 128 #define PCH_UART_MSR_RI 0x00000040 129 #define PCH_UART_MSR_DCD 0x00000080 130 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 131 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 132 133 #define PCH_UART_DLL 0x00 134 #define PCH_UART_DLM 0x01 135 136 #define PCH_UART_BRCSR 0x0E 137 138 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 139 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 140 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 141 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 142 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 143 144 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 145 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 146 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 147 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 148 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 149 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 150 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 151 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 152 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 153 #define PCH_UART_HAL_STB1 0 154 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 155 156 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 157 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 158 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 159 PCH_UART_HAL_CLR_RX_FIFO) 160 161 #define PCH_UART_HAL_DMA_MODE0 0 162 #define PCH_UART_HAL_FIFO_DIS 0 163 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 164 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 165 PCH_UART_FCR_FIFO256) 166 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 167 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 168 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 169 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 170 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 171 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 172 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 173 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 174 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 175 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 176 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 177 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 178 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 179 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 180 181 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 182 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 183 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 184 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 185 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 186 187 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 188 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 189 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 190 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 191 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 192 193 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 194 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 195 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 196 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 197 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 198 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 199 200 struct pch_uart_buffer { 201 unsigned char *buf; 202 int size; 203 }; 204 205 struct eg20t_port { 206 struct uart_port port; 207 int port_type; 208 void __iomem *membase; 209 resource_size_t mapbase; 210 unsigned int iobase; 211 struct pci_dev *pdev; 212 int fifo_size; 213 unsigned int uartclk; 214 int start_tx; 215 int start_rx; 216 int tx_empty; 217 int trigger; 218 int trigger_level; 219 struct pch_uart_buffer rxbuf; 220 unsigned int dmsr; 221 unsigned int fcr; 222 unsigned int mcr; 223 unsigned int use_dma; 224 struct dma_async_tx_descriptor *desc_tx; 225 struct dma_async_tx_descriptor *desc_rx; 226 struct pch_dma_slave param_tx; 227 struct pch_dma_slave param_rx; 228 struct dma_chan *chan_tx; 229 struct dma_chan *chan_rx; 230 struct scatterlist *sg_tx_p; 231 int nent; 232 int orig_nent; 233 struct scatterlist sg_rx; 234 int tx_dma_use; 235 void *rx_buf_virt; 236 dma_addr_t rx_buf_dma; 237 238 #define IRQ_NAME_SIZE 17 239 char irq_name[IRQ_NAME_SIZE]; 240 }; 241 242 /** 243 * struct pch_uart_driver_data - private data structure for UART-DMA 244 * @port_type: The type of UART port 245 * @line_no: UART port line number (0, 1, 2...) 246 */ 247 struct pch_uart_driver_data { 248 int port_type; 249 int line_no; 250 }; 251 252 enum pch_uart_num_t { 253 pch_et20t_uart0 = 0, 254 pch_et20t_uart1, 255 pch_et20t_uart2, 256 pch_et20t_uart3, 257 pch_ml7213_uart0, 258 pch_ml7213_uart1, 259 pch_ml7213_uart2, 260 pch_ml7223_uart0, 261 pch_ml7223_uart1, 262 pch_ml7831_uart0, 263 pch_ml7831_uart1, 264 }; 265 266 static struct pch_uart_driver_data drv_dat[] = { 267 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 268 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 269 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 270 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 271 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 272 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 273 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 274 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 275 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 276 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 277 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 278 }; 279 280 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 281 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 282 #endif 283 static unsigned int default_baud = 9600; 284 static unsigned int user_uartclk = 0; 285 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 286 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 287 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 288 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 289 290 #define PCH_REGS_BUFSIZE 1024 291 292 293 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 294 size_t count, loff_t *ppos) 295 { 296 struct eg20t_port *priv = file->private_data; 297 char *buf; 298 u32 len = 0; 299 ssize_t ret; 300 unsigned char lcr; 301 302 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 303 if (!buf) 304 return 0; 305 306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 307 "PCH EG20T port[%d] regs:\n", priv->port.line); 308 309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 310 "=================================\n"); 311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 324 "BRCSR: \t0x%02x\n", 325 ioread8(priv->membase + PCH_UART_BRCSR)); 326 327 lcr = ioread8(priv->membase + UART_LCR); 328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 331 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 333 iowrite8(lcr, priv->membase + UART_LCR); 334 335 if (len > PCH_REGS_BUFSIZE) 336 len = PCH_REGS_BUFSIZE; 337 338 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 339 kfree(buf); 340 return ret; 341 } 342 343 static const struct file_operations port_regs_ops = { 344 .owner = THIS_MODULE, 345 .open = simple_open, 346 .read = port_show_regs, 347 .llseek = default_llseek, 348 }; 349 350 static const struct dmi_system_id pch_uart_dmi_table[] = { 351 { 352 .ident = "CM-iTC", 353 { 354 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 355 }, 356 (void *)CMITC_UARTCLK, 357 }, 358 { 359 .ident = "FRI2", 360 { 361 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 362 }, 363 (void *)FRI2_64_UARTCLK, 364 }, 365 { 366 .ident = "Fish River Island II", 367 { 368 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 369 }, 370 (void *)FRI2_48_UARTCLK, 371 }, 372 { 373 .ident = "COMe-mTT", 374 { 375 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 376 }, 377 (void *)NTC1_UARTCLK, 378 }, 379 { 380 .ident = "nanoETXexpress-TT", 381 { 382 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 383 }, 384 (void *)NTC1_UARTCLK, 385 }, 386 { 387 .ident = "MinnowBoard", 388 { 389 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 390 }, 391 (void *)MINNOW_UARTCLK, 392 }, 393 { } 394 }; 395 396 /* Return UART clock, checking for board specific clocks. */ 397 static unsigned int pch_uart_get_uartclk(void) 398 { 399 const struct dmi_system_id *d; 400 401 if (user_uartclk) 402 return user_uartclk; 403 404 d = dmi_first_match(pch_uart_dmi_table); 405 if (d) 406 return (unsigned long)d->driver_data; 407 408 return DEFAULT_UARTCLK; 409 } 410 411 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 412 unsigned int flag) 413 { 414 u8 ier = ioread8(priv->membase + UART_IER); 415 ier |= flag & PCH_UART_IER_MASK; 416 iowrite8(ier, priv->membase + UART_IER); 417 } 418 419 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 420 unsigned int flag) 421 { 422 u8 ier = ioread8(priv->membase + UART_IER); 423 ier &= ~(flag & PCH_UART_IER_MASK); 424 iowrite8(ier, priv->membase + UART_IER); 425 } 426 427 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 428 unsigned int parity, unsigned int bits, 429 unsigned int stb) 430 { 431 unsigned int dll, dlm, lcr; 432 int div; 433 434 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 435 if (div < 0 || USHRT_MAX <= div) { 436 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 437 return -EINVAL; 438 } 439 440 dll = (unsigned int)div & 0x00FFU; 441 dlm = ((unsigned int)div >> 8) & 0x00FFU; 442 443 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 444 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 445 return -EINVAL; 446 } 447 448 if (bits & ~PCH_UART_LCR_WLS) { 449 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 450 return -EINVAL; 451 } 452 453 if (stb & ~PCH_UART_LCR_STB) { 454 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 455 return -EINVAL; 456 } 457 458 lcr = parity; 459 lcr |= bits; 460 lcr |= stb; 461 462 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 463 __func__, baud, div, lcr, jiffies); 464 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 465 iowrite8(dll, priv->membase + PCH_UART_DLL); 466 iowrite8(dlm, priv->membase + PCH_UART_DLM); 467 iowrite8(lcr, priv->membase + UART_LCR); 468 469 return 0; 470 } 471 472 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 473 unsigned int flag) 474 { 475 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 476 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 477 __func__, flag); 478 return -EINVAL; 479 } 480 481 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 482 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 483 priv->membase + UART_FCR); 484 iowrite8(priv->fcr, priv->membase + UART_FCR); 485 486 return 0; 487 } 488 489 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 490 unsigned int dmamode, 491 unsigned int fifo_size, unsigned int trigger) 492 { 493 u8 fcr; 494 495 if (dmamode & ~PCH_UART_FCR_DMS) { 496 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 497 __func__, dmamode); 498 return -EINVAL; 499 } 500 501 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 502 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 503 __func__, fifo_size); 504 return -EINVAL; 505 } 506 507 if (trigger & ~PCH_UART_FCR_RFTL) { 508 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 509 __func__, trigger); 510 return -EINVAL; 511 } 512 513 switch (priv->fifo_size) { 514 case 256: 515 priv->trigger_level = 516 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 517 break; 518 case 64: 519 priv->trigger_level = 520 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 521 break; 522 case 16: 523 priv->trigger_level = 524 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 525 break; 526 default: 527 priv->trigger_level = 528 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 529 break; 530 } 531 fcr = 532 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 533 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 534 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 535 priv->membase + UART_FCR); 536 iowrite8(fcr, priv->membase + UART_FCR); 537 priv->fcr = fcr; 538 539 return 0; 540 } 541 542 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 543 { 544 unsigned int msr = ioread8(priv->membase + UART_MSR); 545 priv->dmsr = msr & PCH_UART_MSR_DELTA; 546 return (u8)msr; 547 } 548 549 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 550 int rx_size) 551 { 552 int i; 553 u8 rbr, lsr; 554 struct uart_port *port = &priv->port; 555 556 lsr = ioread8(priv->membase + UART_LSR); 557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 558 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 559 lsr = ioread8(priv->membase + UART_LSR)) { 560 rbr = ioread8(priv->membase + PCH_UART_RBR); 561 562 if (lsr & UART_LSR_BI) { 563 port->icount.brk++; 564 if (uart_handle_break(port)) 565 continue; 566 } 567 if (uart_prepare_sysrq_char(port, rbr)) 568 continue; 569 570 buf[i++] = rbr; 571 } 572 return i; 573 } 574 575 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 576 { 577 return ioread8(priv->membase + UART_IIR) &\ 578 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 579 } 580 581 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 582 { 583 return ioread8(priv->membase + UART_LSR); 584 } 585 586 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 587 { 588 unsigned int lcr; 589 590 lcr = ioread8(priv->membase + UART_LCR); 591 if (on) 592 lcr |= PCH_UART_LCR_SB; 593 else 594 lcr &= ~PCH_UART_LCR_SB; 595 596 iowrite8(lcr, priv->membase + UART_LCR); 597 } 598 599 static void push_rx(struct eg20t_port *priv, const unsigned char *buf, 600 int size) 601 { 602 struct uart_port *port = &priv->port; 603 struct tty_port *tport = &port->state->port; 604 605 tty_insert_flip_string(tport, buf, size); 606 tty_flip_buffer_push(tport); 607 } 608 609 static int dma_push_rx(struct eg20t_port *priv, int size) 610 { 611 int room; 612 struct uart_port *port = &priv->port; 613 struct tty_port *tport = &port->state->port; 614 615 room = tty_buffer_request_room(tport, size); 616 617 if (room < size) 618 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 619 size - room); 620 if (!room) 621 return 0; 622 623 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 624 625 port->icount.rx += room; 626 627 return room; 628 } 629 630 static void pch_free_dma(struct uart_port *port) 631 { 632 struct eg20t_port *priv; 633 priv = container_of(port, struct eg20t_port, port); 634 635 if (priv->chan_tx) { 636 dma_release_channel(priv->chan_tx); 637 priv->chan_tx = NULL; 638 } 639 if (priv->chan_rx) { 640 dma_release_channel(priv->chan_rx); 641 priv->chan_rx = NULL; 642 } 643 644 if (priv->rx_buf_dma) { 645 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 646 priv->rx_buf_dma); 647 priv->rx_buf_virt = NULL; 648 priv->rx_buf_dma = 0; 649 } 650 651 return; 652 } 653 654 static bool filter(struct dma_chan *chan, void *slave) 655 { 656 struct pch_dma_slave *param = slave; 657 658 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 659 chan->device->dev)) { 660 chan->private = param; 661 return true; 662 } else { 663 return false; 664 } 665 } 666 667 static void pch_request_dma(struct uart_port *port) 668 { 669 dma_cap_mask_t mask; 670 struct dma_chan *chan; 671 struct pci_dev *dma_dev; 672 struct pch_dma_slave *param; 673 struct eg20t_port *priv = 674 container_of(port, struct eg20t_port, port); 675 dma_cap_zero(mask); 676 dma_cap_set(DMA_SLAVE, mask); 677 678 /* Get DMA's dev information */ 679 dma_dev = pci_get_slot(priv->pdev->bus, 680 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 681 682 /* Set Tx DMA */ 683 param = &priv->param_tx; 684 param->dma_dev = &dma_dev->dev; 685 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 686 687 param->tx_reg = port->mapbase + UART_TX; 688 chan = dma_request_channel(mask, filter, param); 689 if (!chan) { 690 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 691 __func__); 692 goto err_pci_get; 693 } 694 priv->chan_tx = chan; 695 696 /* Set Rx DMA */ 697 param = &priv->param_rx; 698 param->dma_dev = &dma_dev->dev; 699 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 700 701 param->rx_reg = port->mapbase + UART_RX; 702 chan = dma_request_channel(mask, filter, param); 703 if (!chan) { 704 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 705 __func__); 706 goto err_req_tx; 707 } 708 709 /* Get Consistent memory for DMA */ 710 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 711 &priv->rx_buf_dma, GFP_KERNEL); 712 if (!priv->rx_buf_virt) 713 goto err_req_rx; 714 priv->chan_rx = chan; 715 716 pci_dev_put(dma_dev); 717 return; 718 719 err_req_rx: 720 dma_release_channel(chan); 721 err_req_tx: 722 dma_release_channel(priv->chan_tx); 723 priv->chan_tx = NULL; 724 err_pci_get: 725 pci_dev_put(dma_dev); 726 } 727 728 static void pch_dma_rx_complete(void *arg) 729 { 730 struct eg20t_port *priv = arg; 731 struct uart_port *port = &priv->port; 732 int count; 733 734 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 735 count = dma_push_rx(priv, priv->trigger_level); 736 if (count) 737 tty_flip_buffer_push(&port->state->port); 738 async_tx_ack(priv->desc_rx); 739 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 740 PCH_UART_HAL_RX_ERR_INT); 741 } 742 743 static void pch_dma_tx_complete(void *arg) 744 { 745 struct eg20t_port *priv = arg; 746 struct uart_port *port = &priv->port; 747 struct scatterlist *sg = priv->sg_tx_p; 748 int i; 749 750 for (i = 0; i < priv->nent; i++, sg++) 751 uart_xmit_advance(port, sg_dma_len(sg)); 752 753 async_tx_ack(priv->desc_tx); 754 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE); 755 priv->tx_dma_use = 0; 756 priv->nent = 0; 757 priv->orig_nent = 0; 758 kfree(priv->sg_tx_p); 759 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 760 } 761 762 static int handle_rx_to(struct eg20t_port *priv) 763 { 764 struct pch_uart_buffer *buf; 765 int rx_size; 766 767 if (!priv->start_rx) { 768 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 769 PCH_UART_HAL_RX_ERR_INT); 770 return 0; 771 } 772 buf = &priv->rxbuf; 773 do { 774 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 775 push_rx(priv, buf->buf, rx_size); 776 } while (rx_size == buf->size); 777 778 return PCH_UART_HANDLED_RX_INT; 779 } 780 781 static int dma_handle_rx(struct eg20t_port *priv) 782 { 783 struct uart_port *port = &priv->port; 784 struct dma_async_tx_descriptor *desc; 785 struct scatterlist *sg; 786 787 priv = container_of(port, struct eg20t_port, port); 788 sg = &priv->sg_rx; 789 790 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 791 792 sg_dma_len(sg) = priv->trigger_level; 793 794 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 795 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 796 797 sg_dma_address(sg) = priv->rx_buf_dma; 798 799 desc = dmaengine_prep_slave_sg(priv->chan_rx, 800 sg, 1, DMA_DEV_TO_MEM, 801 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 802 803 if (!desc) 804 return 0; 805 806 priv->desc_rx = desc; 807 desc->callback = pch_dma_rx_complete; 808 desc->callback_param = priv; 809 desc->tx_submit(desc); 810 dma_async_issue_pending(priv->chan_rx); 811 812 return PCH_UART_HANDLED_RX_INT; 813 } 814 815 static unsigned int handle_tx(struct eg20t_port *priv) 816 { 817 struct uart_port *port = &priv->port; 818 unsigned char ch; 819 int fifo_size; 820 int tx_empty; 821 822 if (!priv->start_tx) { 823 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 824 __func__, jiffies); 825 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 826 priv->tx_empty = 1; 827 return 0; 828 } 829 830 fifo_size = max(priv->fifo_size, 1); 831 tx_empty = 1; 832 if (port->x_char) { 833 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 834 port->icount.tx++; 835 port->x_char = 0; 836 tx_empty = 0; 837 fifo_size--; 838 } 839 840 while (!uart_tx_stopped(port) && fifo_size && 841 uart_fifo_get(port, &ch)) { 842 iowrite8(ch, priv->membase + PCH_UART_THR); 843 fifo_size--; 844 tx_empty = 0; 845 } 846 847 priv->tx_empty = tx_empty; 848 849 if (tx_empty) { 850 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 851 uart_write_wakeup(port); 852 } 853 854 return PCH_UART_HANDLED_TX_INT; 855 } 856 857 static unsigned int dma_handle_tx(struct eg20t_port *priv) 858 { 859 struct uart_port *port = &priv->port; 860 struct tty_port *tport = &port->state->port; 861 struct scatterlist *sg; 862 int nent; 863 int fifo_size; 864 struct dma_async_tx_descriptor *desc; 865 unsigned int bytes, tail; 866 int num; 867 int i; 868 int size; 869 int rem; 870 871 if (!priv->start_tx) { 872 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 873 __func__, jiffies); 874 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 875 priv->tx_empty = 1; 876 return 0; 877 } 878 879 if (priv->tx_dma_use) { 880 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 881 __func__, jiffies); 882 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 883 priv->tx_empty = 1; 884 return 0; 885 } 886 887 fifo_size = max(priv->fifo_size, 1); 888 889 if (port->x_char) { 890 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 891 port->icount.tx++; 892 port->x_char = 0; 893 fifo_size--; 894 } 895 896 bytes = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); 897 if (!bytes) { 898 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 899 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 900 uart_write_wakeup(port); 901 return 0; 902 } 903 904 if (bytes > fifo_size) { 905 num = bytes / fifo_size + 1; 906 size = fifo_size; 907 rem = bytes % fifo_size; 908 } else { 909 num = 1; 910 size = bytes; 911 rem = bytes; 912 } 913 914 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 915 __func__, num, size, rem); 916 917 priv->tx_dma_use = 1; 918 919 priv->sg_tx_p = kmalloc_objs(struct scatterlist, num, GFP_ATOMIC); 920 if (!priv->sg_tx_p) { 921 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 922 return 0; 923 } 924 925 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 926 sg = priv->sg_tx_p; 927 928 for (i = 0; i < num; i++, sg++) { 929 if (i == (num - 1)) 930 sg_set_page(sg, virt_to_page(tport->xmit_buf), 931 rem, fifo_size * i); 932 else 933 sg_set_page(sg, virt_to_page(tport->xmit_buf), 934 size, fifo_size * i); 935 } 936 937 sg = priv->sg_tx_p; 938 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 939 if (!nent) { 940 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 941 return 0; 942 } 943 priv->orig_nent = num; 944 priv->nent = nent; 945 946 for (i = 0; i < nent; i++, sg++) { 947 sg->offset = tail + fifo_size * i; 948 sg_dma_address(sg) = (sg_dma_address(sg) & 949 ~(UART_XMIT_SIZE - 1)) + sg->offset; 950 if (i == (nent - 1)) 951 sg_dma_len(sg) = rem; 952 else 953 sg_dma_len(sg) = size; 954 } 955 956 desc = dmaengine_prep_slave_sg(priv->chan_tx, 957 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 958 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 959 if (!desc) { 960 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 961 __func__); 962 return 0; 963 } 964 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, num, DMA_TO_DEVICE); 965 priv->desc_tx = desc; 966 desc->callback = pch_dma_tx_complete; 967 desc->callback_param = priv; 968 969 desc->tx_submit(desc); 970 971 dma_async_issue_pending(priv->chan_tx); 972 973 return PCH_UART_HANDLED_TX_INT; 974 } 975 976 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 977 { 978 struct uart_port *port = &priv->port; 979 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 980 char *error_msg[5] = {}; 981 int i = 0; 982 983 if (lsr & PCH_UART_LSR_ERR) 984 error_msg[i++] = "Error data in FIFO\n"; 985 986 if (lsr & UART_LSR_FE) { 987 port->icount.frame++; 988 error_msg[i++] = " Framing Error\n"; 989 } 990 991 if (lsr & UART_LSR_PE) { 992 port->icount.parity++; 993 error_msg[i++] = " Parity Error\n"; 994 } 995 996 if (lsr & UART_LSR_OE) { 997 port->icount.overrun++; 998 error_msg[i++] = " Overrun Error\n"; 999 } 1000 1001 if (tty == NULL) { 1002 for (i = 0; error_msg[i] != NULL; i++) 1003 dev_err(&priv->pdev->dev, error_msg[i]); 1004 } else { 1005 tty_kref_put(tty); 1006 } 1007 } 1008 1009 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1010 { 1011 struct eg20t_port *priv = dev_id; 1012 unsigned int handled; 1013 u8 lsr; 1014 int ret = 0; 1015 unsigned char iid; 1016 int next = 1; 1017 u8 msr; 1018 1019 uart_port_lock(&priv->port); 1020 handled = 0; 1021 while (next) { 1022 iid = pch_uart_hal_get_iid(priv); 1023 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1024 break; 1025 switch (iid) { 1026 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1027 lsr = pch_uart_hal_get_line_status(priv); 1028 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1029 UART_LSR_PE | UART_LSR_OE)) { 1030 pch_uart_err_ir(priv, lsr); 1031 ret = PCH_UART_HANDLED_RX_ERR_INT; 1032 } else { 1033 ret = PCH_UART_HANDLED_LS_INT; 1034 } 1035 break; 1036 case PCH_UART_IID_RDR: /* Received Data Ready */ 1037 if (priv->use_dma) { 1038 pch_uart_hal_disable_interrupt(priv, 1039 PCH_UART_HAL_RX_INT | 1040 PCH_UART_HAL_RX_ERR_INT); 1041 ret = dma_handle_rx(priv); 1042 if (!ret) 1043 pch_uart_hal_enable_interrupt(priv, 1044 PCH_UART_HAL_RX_INT | 1045 PCH_UART_HAL_RX_ERR_INT); 1046 } else { 1047 ret = handle_rx_to(priv); 1048 } 1049 break; 1050 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1051 (FIFO Timeout) */ 1052 ret = handle_rx_to(priv); 1053 break; 1054 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1055 Empty */ 1056 if (priv->use_dma) 1057 ret = dma_handle_tx(priv); 1058 else 1059 ret = handle_tx(priv); 1060 break; 1061 case PCH_UART_IID_MS: /* Modem Status */ 1062 msr = pch_uart_hal_get_modem(priv); 1063 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1064 means final interrupt */ 1065 if ((msr & UART_MSR_ANY_DELTA) == 0) 1066 break; 1067 ret |= PCH_UART_HANDLED_MS_INT; 1068 break; 1069 default: /* Never junp to this label */ 1070 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1071 iid, jiffies); 1072 ret = -1; 1073 next = 0; 1074 break; 1075 } 1076 handled |= (unsigned int)ret; 1077 } 1078 1079 uart_unlock_and_check_sysrq(&priv->port); 1080 return IRQ_RETVAL(handled); 1081 } 1082 1083 /* This function tests whether the transmitter fifo and shifter for the port 1084 described by 'port' is empty. */ 1085 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1086 { 1087 struct eg20t_port *priv; 1088 1089 priv = container_of(port, struct eg20t_port, port); 1090 if (priv->tx_empty) 1091 return TIOCSER_TEMT; 1092 else 1093 return 0; 1094 } 1095 1096 /* Returns the current state of modem control inputs. */ 1097 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1098 { 1099 struct eg20t_port *priv; 1100 u8 modem; 1101 unsigned int ret = 0; 1102 1103 priv = container_of(port, struct eg20t_port, port); 1104 modem = pch_uart_hal_get_modem(priv); 1105 1106 if (modem & UART_MSR_DCD) 1107 ret |= TIOCM_CAR; 1108 1109 if (modem & UART_MSR_RI) 1110 ret |= TIOCM_RNG; 1111 1112 if (modem & UART_MSR_DSR) 1113 ret |= TIOCM_DSR; 1114 1115 if (modem & UART_MSR_CTS) 1116 ret |= TIOCM_CTS; 1117 1118 return ret; 1119 } 1120 1121 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1122 { 1123 u32 mcr = 0; 1124 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1125 1126 if (mctrl & TIOCM_DTR) 1127 mcr |= UART_MCR_DTR; 1128 if (mctrl & TIOCM_RTS) 1129 mcr |= UART_MCR_RTS; 1130 if (mctrl & TIOCM_LOOP) 1131 mcr |= UART_MCR_LOOP; 1132 1133 if (priv->mcr & UART_MCR_AFE) 1134 mcr |= UART_MCR_AFE; 1135 1136 if (mctrl) 1137 iowrite8(mcr, priv->membase + UART_MCR); 1138 } 1139 1140 static void pch_uart_stop_tx(struct uart_port *port) 1141 { 1142 struct eg20t_port *priv; 1143 priv = container_of(port, struct eg20t_port, port); 1144 priv->start_tx = 0; 1145 priv->tx_dma_use = 0; 1146 } 1147 1148 static void pch_uart_start_tx(struct uart_port *port) 1149 { 1150 struct eg20t_port *priv; 1151 1152 priv = container_of(port, struct eg20t_port, port); 1153 1154 if (priv->use_dma) { 1155 if (priv->tx_dma_use) { 1156 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1157 __func__); 1158 return; 1159 } 1160 } 1161 1162 priv->start_tx = 1; 1163 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1164 } 1165 1166 static void pch_uart_stop_rx(struct uart_port *port) 1167 { 1168 struct eg20t_port *priv; 1169 priv = container_of(port, struct eg20t_port, port); 1170 priv->start_rx = 0; 1171 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1172 PCH_UART_HAL_RX_ERR_INT); 1173 } 1174 1175 /* Enable the modem status interrupts. */ 1176 static void pch_uart_enable_ms(struct uart_port *port) 1177 { 1178 struct eg20t_port *priv; 1179 priv = container_of(port, struct eg20t_port, port); 1180 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1181 } 1182 1183 /* Control the transmission of a break signal. */ 1184 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1185 { 1186 struct eg20t_port *priv; 1187 unsigned long flags; 1188 1189 priv = container_of(port, struct eg20t_port, port); 1190 uart_port_lock_irqsave(&priv->port, &flags); 1191 pch_uart_hal_set_break(priv, ctl); 1192 uart_port_unlock_irqrestore(&priv->port, flags); 1193 } 1194 1195 /* Grab any interrupt resources and initialise any low level driver state. */ 1196 static int pch_uart_startup(struct uart_port *port) 1197 { 1198 struct eg20t_port *priv; 1199 int ret; 1200 int fifo_size; 1201 int trigger_level; 1202 1203 priv = container_of(port, struct eg20t_port, port); 1204 priv->tx_empty = 1; 1205 1206 if (port->uartclk) 1207 priv->uartclk = port->uartclk; 1208 else 1209 port->uartclk = priv->uartclk; 1210 1211 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1212 ret = pch_uart_hal_set_line(priv, default_baud, 1213 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1214 PCH_UART_HAL_STB1); 1215 if (ret) 1216 return ret; 1217 1218 switch (priv->fifo_size) { 1219 case 256: 1220 fifo_size = PCH_UART_HAL_FIFO256; 1221 break; 1222 case 64: 1223 fifo_size = PCH_UART_HAL_FIFO64; 1224 break; 1225 case 16: 1226 fifo_size = PCH_UART_HAL_FIFO16; 1227 break; 1228 case 1: 1229 default: 1230 fifo_size = PCH_UART_HAL_FIFO_DIS; 1231 break; 1232 } 1233 1234 switch (priv->trigger) { 1235 case PCH_UART_HAL_TRIGGER1: 1236 trigger_level = 1; 1237 break; 1238 case PCH_UART_HAL_TRIGGER_L: 1239 trigger_level = priv->fifo_size / 4; 1240 break; 1241 case PCH_UART_HAL_TRIGGER_M: 1242 trigger_level = priv->fifo_size / 2; 1243 break; 1244 case PCH_UART_HAL_TRIGGER_H: 1245 default: 1246 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1247 break; 1248 } 1249 1250 priv->trigger_level = trigger_level; 1251 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1252 fifo_size, priv->trigger); 1253 if (ret < 0) 1254 return ret; 1255 1256 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1257 priv->irq_name, priv); 1258 if (ret < 0) 1259 return ret; 1260 1261 if (priv->use_dma) 1262 pch_request_dma(port); 1263 1264 priv->start_rx = 1; 1265 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1266 PCH_UART_HAL_RX_ERR_INT); 1267 uart_update_timeout(port, CS8, default_baud); 1268 1269 return 0; 1270 } 1271 1272 static void pch_uart_shutdown(struct uart_port *port) 1273 { 1274 struct eg20t_port *priv; 1275 int ret; 1276 1277 priv = container_of(port, struct eg20t_port, port); 1278 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1279 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1280 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1281 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1282 if (ret) 1283 dev_err(priv->port.dev, 1284 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1285 1286 pch_free_dma(port); 1287 1288 free_irq(priv->port.irq, priv); 1289 } 1290 1291 /* Change the port parameters, including word length, parity, stop 1292 *bits. Update read_status_mask and ignore_status_mask to indicate 1293 *the types of events we are interested in receiving. */ 1294 static void pch_uart_set_termios(struct uart_port *port, 1295 struct ktermios *termios, 1296 const struct ktermios *old) 1297 { 1298 int rtn; 1299 unsigned int baud, parity, bits, stb; 1300 struct eg20t_port *priv; 1301 unsigned long flags; 1302 1303 priv = container_of(port, struct eg20t_port, port); 1304 switch (termios->c_cflag & CSIZE) { 1305 case CS5: 1306 bits = PCH_UART_HAL_5BIT; 1307 break; 1308 case CS6: 1309 bits = PCH_UART_HAL_6BIT; 1310 break; 1311 case CS7: 1312 bits = PCH_UART_HAL_7BIT; 1313 break; 1314 default: /* CS8 */ 1315 bits = PCH_UART_HAL_8BIT; 1316 break; 1317 } 1318 if (termios->c_cflag & CSTOPB) 1319 stb = PCH_UART_HAL_STB2; 1320 else 1321 stb = PCH_UART_HAL_STB1; 1322 1323 if (termios->c_cflag & PARENB) { 1324 if (termios->c_cflag & PARODD) 1325 parity = PCH_UART_HAL_PARITY_ODD; 1326 else 1327 parity = PCH_UART_HAL_PARITY_EVEN; 1328 1329 } else 1330 parity = PCH_UART_HAL_PARITY_NONE; 1331 1332 /* Only UART0 has auto hardware flow function */ 1333 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1334 priv->mcr |= UART_MCR_AFE; 1335 else 1336 priv->mcr &= ~UART_MCR_AFE; 1337 1338 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1339 1340 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1341 1342 uart_port_lock_irqsave(port, &flags); 1343 1344 uart_update_timeout(port, termios->c_cflag, baud); 1345 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1346 if (rtn) 1347 goto out; 1348 1349 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1350 /* Don't rewrite B0 */ 1351 if (tty_termios_baud_rate(termios)) 1352 tty_termios_encode_baud_rate(termios, baud, baud); 1353 1354 out: 1355 uart_port_unlock_irqrestore(port, flags); 1356 } 1357 1358 static const char *pch_uart_type(struct uart_port *port) 1359 { 1360 return KBUILD_MODNAME; 1361 } 1362 1363 static void pch_uart_release_port(struct uart_port *port) 1364 { 1365 struct eg20t_port *priv; 1366 1367 priv = container_of(port, struct eg20t_port, port); 1368 pci_iounmap(priv->pdev, priv->membase); 1369 pci_release_regions(priv->pdev); 1370 } 1371 1372 static int pch_uart_request_port(struct uart_port *port) 1373 { 1374 struct eg20t_port *priv; 1375 int ret; 1376 void __iomem *membase; 1377 1378 priv = container_of(port, struct eg20t_port, port); 1379 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1380 if (ret < 0) 1381 return -EBUSY; 1382 1383 membase = pci_iomap(priv->pdev, 1, 0); 1384 if (!membase) { 1385 pci_release_regions(priv->pdev); 1386 return -EBUSY; 1387 } 1388 priv->membase = port->membase = membase; 1389 1390 return 0; 1391 } 1392 1393 static void pch_uart_config_port(struct uart_port *port, int type) 1394 { 1395 struct eg20t_port *priv; 1396 1397 priv = container_of(port, struct eg20t_port, port); 1398 if (type & UART_CONFIG_TYPE) { 1399 port->type = priv->port_type; 1400 pch_uart_request_port(port); 1401 } 1402 } 1403 1404 static int pch_uart_verify_port(struct uart_port *port, 1405 struct serial_struct *serinfo) 1406 { 1407 struct eg20t_port *priv; 1408 1409 priv = container_of(port, struct eg20t_port, port); 1410 if (serinfo->flags & UPF_LOW_LATENCY) { 1411 dev_info(priv->port.dev, 1412 "PCH UART : Use PIO Mode (without DMA)\n"); 1413 priv->use_dma = 0; 1414 serinfo->flags &= ~UPF_LOW_LATENCY; 1415 } else { 1416 #ifndef CONFIG_PCH_DMA 1417 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1418 __func__); 1419 return -EOPNOTSUPP; 1420 #endif 1421 if (!priv->use_dma) { 1422 pch_request_dma(port); 1423 if (priv->chan_rx) 1424 priv->use_dma = 1; 1425 } 1426 dev_info(priv->port.dev, "PCH UART: %s\n", 1427 priv->use_dma ? 1428 "Use DMA Mode" : "No DMA"); 1429 } 1430 1431 return 0; 1432 } 1433 1434 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1435 /* 1436 * Wait for transmitter & holding register to empty 1437 */ 1438 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1439 { 1440 unsigned int status, tmout = 10000; 1441 1442 /* Wait up to 10ms for the character(s) to be sent. */ 1443 for (;;) { 1444 status = ioread8(up->membase + UART_LSR); 1445 1446 if ((status & bits) == bits) 1447 break; 1448 if (--tmout == 0) 1449 break; 1450 udelay(1); 1451 } 1452 1453 /* Wait up to 1s for flow control if necessary */ 1454 if (up->port.flags & UPF_CONS_FLOW) { 1455 unsigned int tmout; 1456 for (tmout = 1000000; tmout; tmout--) { 1457 unsigned int msr = ioread8(up->membase + UART_MSR); 1458 if (msr & UART_MSR_CTS) 1459 break; 1460 udelay(1); 1461 touch_nmi_watchdog(); 1462 } 1463 } 1464 } 1465 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1466 1467 #ifdef CONFIG_CONSOLE_POLL 1468 /* 1469 * Console polling routines for communicate via uart while 1470 * in an interrupt or debug context. 1471 */ 1472 static int pch_uart_get_poll_char(struct uart_port *port) 1473 { 1474 struct eg20t_port *priv = 1475 container_of(port, struct eg20t_port, port); 1476 u8 lsr = ioread8(priv->membase + UART_LSR); 1477 1478 if (!(lsr & UART_LSR_DR)) 1479 return NO_POLL_CHAR; 1480 1481 return ioread8(priv->membase + PCH_UART_RBR); 1482 } 1483 1484 1485 static void pch_uart_put_poll_char(struct uart_port *port, 1486 unsigned char c) 1487 { 1488 unsigned int ier; 1489 struct eg20t_port *priv = 1490 container_of(port, struct eg20t_port, port); 1491 1492 /* 1493 * First save the IER then disable the interrupts 1494 */ 1495 ier = ioread8(priv->membase + UART_IER); 1496 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1497 1498 wait_for_xmitr(priv, UART_LSR_THRE); 1499 /* 1500 * Send the character out. 1501 */ 1502 iowrite8(c, priv->membase + PCH_UART_THR); 1503 1504 /* 1505 * Finally, wait for transmitter to become empty 1506 * and restore the IER 1507 */ 1508 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1509 iowrite8(ier, priv->membase + UART_IER); 1510 } 1511 #endif /* CONFIG_CONSOLE_POLL */ 1512 1513 static const struct uart_ops pch_uart_ops = { 1514 .tx_empty = pch_uart_tx_empty, 1515 .set_mctrl = pch_uart_set_mctrl, 1516 .get_mctrl = pch_uart_get_mctrl, 1517 .stop_tx = pch_uart_stop_tx, 1518 .start_tx = pch_uart_start_tx, 1519 .stop_rx = pch_uart_stop_rx, 1520 .enable_ms = pch_uart_enable_ms, 1521 .break_ctl = pch_uart_break_ctl, 1522 .startup = pch_uart_startup, 1523 .shutdown = pch_uart_shutdown, 1524 .set_termios = pch_uart_set_termios, 1525 .type = pch_uart_type, 1526 .release_port = pch_uart_release_port, 1527 .request_port = pch_uart_request_port, 1528 .config_port = pch_uart_config_port, 1529 .verify_port = pch_uart_verify_port, 1530 #ifdef CONFIG_CONSOLE_POLL 1531 .poll_get_char = pch_uart_get_poll_char, 1532 .poll_put_char = pch_uart_put_poll_char, 1533 #endif 1534 }; 1535 1536 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1537 1538 static void pch_console_putchar(struct uart_port *port, unsigned char ch) 1539 { 1540 struct eg20t_port *priv = 1541 container_of(port, struct eg20t_port, port); 1542 1543 wait_for_xmitr(priv, UART_LSR_THRE); 1544 iowrite8(ch, priv->membase + PCH_UART_THR); 1545 } 1546 1547 /* 1548 * Print a string to the serial port trying not to disturb 1549 * any possible real use of the port... 1550 * 1551 * The console_lock must be held when we get here. 1552 */ 1553 static void 1554 pch_console_write(struct console *co, const char *s, unsigned int count) 1555 { 1556 struct eg20t_port *priv; 1557 unsigned long flags; 1558 int locked = 1; 1559 u8 ier; 1560 1561 priv = pch_uart_ports[co->index]; 1562 1563 touch_nmi_watchdog(); 1564 1565 if (oops_in_progress) 1566 locked = uart_port_trylock_irqsave(&priv->port, &flags); 1567 else 1568 uart_port_lock_irqsave(&priv->port, &flags); 1569 1570 /* 1571 * First save the IER then disable the interrupts 1572 */ 1573 ier = ioread8(priv->membase + UART_IER); 1574 1575 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1576 1577 uart_console_write(&priv->port, s, count, pch_console_putchar); 1578 1579 /* 1580 * Finally, wait for transmitter to become empty 1581 * and restore the IER 1582 */ 1583 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1584 iowrite8(ier, priv->membase + UART_IER); 1585 1586 if (locked) 1587 uart_port_unlock_irqrestore(&priv->port, flags); 1588 } 1589 1590 static int __init pch_console_setup(struct console *co, char *options) 1591 { 1592 struct uart_port *port; 1593 int baud = default_baud; 1594 int bits = 8; 1595 int parity = 'n'; 1596 int flow = 'n'; 1597 1598 /* 1599 * Check whether an invalid uart number has been specified, and 1600 * if so, search for the first available port that does have 1601 * console support. 1602 */ 1603 if (co->index >= PCH_UART_NR) 1604 co->index = 0; 1605 port = &pch_uart_ports[co->index]->port; 1606 1607 if (!port || (!port->iobase && !port->membase)) 1608 return -ENODEV; 1609 1610 port->uartclk = pch_uart_get_uartclk(); 1611 1612 if (options) 1613 uart_parse_options(options, &baud, &parity, &bits, &flow); 1614 1615 return uart_set_options(port, co, baud, parity, bits, flow); 1616 } 1617 1618 static struct uart_driver pch_uart_driver; 1619 1620 static struct console pch_console = { 1621 .name = PCH_UART_DRIVER_DEVICE, 1622 .write = pch_console_write, 1623 .device = uart_console_device, 1624 .setup = pch_console_setup, 1625 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1626 .index = -1, 1627 .data = &pch_uart_driver, 1628 }; 1629 1630 #define PCH_CONSOLE (&pch_console) 1631 #else 1632 #define PCH_CONSOLE NULL 1633 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1634 1635 static struct uart_driver pch_uart_driver = { 1636 .owner = THIS_MODULE, 1637 .driver_name = KBUILD_MODNAME, 1638 .dev_name = PCH_UART_DRIVER_DEVICE, 1639 .major = 0, 1640 .minor = 0, 1641 .nr = PCH_UART_NR, 1642 .cons = PCH_CONSOLE, 1643 }; 1644 1645 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1646 const struct pci_device_id *id) 1647 { 1648 struct eg20t_port *priv; 1649 int ret; 1650 unsigned int iobase; 1651 unsigned int mapbase; 1652 unsigned char *rxbuf; 1653 int fifosize; 1654 int port_type; 1655 struct pch_uart_driver_data *board; 1656 char name[32]; 1657 1658 board = &drv_dat[id->driver_data]; 1659 port_type = board->port_type; 1660 1661 priv = kzalloc_obj(struct eg20t_port); 1662 if (priv == NULL) 1663 goto init_port_alloc_err; 1664 1665 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1666 if (!rxbuf) 1667 goto init_port_free_txbuf; 1668 1669 switch (port_type) { 1670 case PORT_PCH_8LINE: 1671 fifosize = 256; /* EG20T/ML7213: UART0 */ 1672 break; 1673 case PORT_PCH_2LINE: 1674 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1675 break; 1676 default: 1677 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1678 goto init_port_hal_free; 1679 } 1680 1681 pci_enable_msi(pdev); 1682 pci_set_master(pdev); 1683 1684 iobase = pci_resource_start(pdev, 0); 1685 mapbase = pci_resource_start(pdev, 1); 1686 priv->mapbase = mapbase; 1687 priv->iobase = iobase; 1688 priv->pdev = pdev; 1689 priv->tx_empty = 1; 1690 priv->rxbuf.buf = rxbuf; 1691 priv->rxbuf.size = PAGE_SIZE; 1692 1693 priv->fifo_size = fifosize; 1694 priv->uartclk = pch_uart_get_uartclk(); 1695 priv->port_type = port_type; 1696 priv->port.dev = &pdev->dev; 1697 priv->port.iobase = iobase; 1698 priv->port.membase = NULL; 1699 priv->port.mapbase = mapbase; 1700 priv->port.irq = pdev->irq; 1701 priv->port.iotype = UPIO_PORT; 1702 priv->port.ops = &pch_uart_ops; 1703 priv->port.flags = UPF_BOOT_AUTOCONF; 1704 priv->port.fifosize = fifosize; 1705 priv->port.line = board->line_no; 1706 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); 1707 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1708 1709 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1710 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1711 priv->port.line); 1712 1713 pci_set_drvdata(pdev, priv); 1714 priv->trigger_level = 1; 1715 priv->fcr = 0; 1716 1717 if (pdev->dev.of_node) 1718 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1719 , &user_uartclk); 1720 1721 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1722 pch_uart_ports[board->line_no] = priv; 1723 #endif 1724 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1725 if (ret < 0) 1726 goto init_port_hal_free; 1727 1728 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1729 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv, 1730 &port_regs_ops); 1731 1732 return priv; 1733 1734 init_port_hal_free: 1735 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1736 pch_uart_ports[board->line_no] = NULL; 1737 #endif 1738 free_page((unsigned long)rxbuf); 1739 init_port_free_txbuf: 1740 kfree(priv); 1741 init_port_alloc_err: 1742 1743 return NULL; 1744 } 1745 1746 static void pch_uart_exit_port(struct eg20t_port *priv) 1747 { 1748 char name[32]; 1749 1750 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1751 debugfs_lookup_and_remove(name, NULL); 1752 uart_remove_one_port(&pch_uart_driver, &priv->port); 1753 free_page((unsigned long)priv->rxbuf.buf); 1754 } 1755 1756 static void pch_uart_pci_remove(struct pci_dev *pdev) 1757 { 1758 struct eg20t_port *priv = pci_get_drvdata(pdev); 1759 1760 pci_disable_msi(pdev); 1761 1762 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1763 pch_uart_ports[priv->port.line] = NULL; 1764 #endif 1765 pch_uart_exit_port(priv); 1766 pci_disable_device(pdev); 1767 kfree(priv); 1768 return; 1769 } 1770 1771 static int __maybe_unused pch_uart_pci_suspend(struct device *dev) 1772 { 1773 struct eg20t_port *priv = dev_get_drvdata(dev); 1774 1775 uart_suspend_port(&pch_uart_driver, &priv->port); 1776 1777 return 0; 1778 } 1779 1780 static int __maybe_unused pch_uart_pci_resume(struct device *dev) 1781 { 1782 struct eg20t_port *priv = dev_get_drvdata(dev); 1783 1784 uart_resume_port(&pch_uart_driver, &priv->port); 1785 1786 return 0; 1787 } 1788 1789 static const struct pci_device_id pch_uart_pci_id[] = { 1790 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1791 .driver_data = pch_et20t_uart0}, 1792 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1793 .driver_data = pch_et20t_uart1}, 1794 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1795 .driver_data = pch_et20t_uart2}, 1796 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1797 .driver_data = pch_et20t_uart3}, 1798 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1799 .driver_data = pch_ml7213_uart0}, 1800 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1801 .driver_data = pch_ml7213_uart1}, 1802 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1803 .driver_data = pch_ml7213_uart2}, 1804 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1805 .driver_data = pch_ml7223_uart0}, 1806 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1807 .driver_data = pch_ml7223_uart1}, 1808 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1809 .driver_data = pch_ml7831_uart0}, 1810 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1811 .driver_data = pch_ml7831_uart1}, 1812 {0,}, 1813 }; 1814 1815 static int pch_uart_pci_probe(struct pci_dev *pdev, 1816 const struct pci_device_id *id) 1817 { 1818 int ret; 1819 struct eg20t_port *priv; 1820 1821 ret = pci_enable_device(pdev); 1822 if (ret < 0) 1823 goto probe_error; 1824 1825 priv = pch_uart_init_port(pdev, id); 1826 if (!priv) { 1827 ret = -EBUSY; 1828 goto probe_disable_device; 1829 } 1830 pci_set_drvdata(pdev, priv); 1831 1832 return ret; 1833 1834 probe_disable_device: 1835 pci_disable_msi(pdev); 1836 pci_disable_device(pdev); 1837 probe_error: 1838 return ret; 1839 } 1840 1841 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops, 1842 pch_uart_pci_suspend, 1843 pch_uart_pci_resume); 1844 1845 static struct pci_driver pch_uart_pci_driver = { 1846 .name = "pch_uart", 1847 .id_table = pch_uart_pci_id, 1848 .probe = pch_uart_pci_probe, 1849 .remove = pch_uart_pci_remove, 1850 .driver.pm = &pch_uart_pci_pm_ops, 1851 }; 1852 1853 static int __init pch_uart_module_init(void) 1854 { 1855 int ret; 1856 1857 /* register as UART driver */ 1858 ret = uart_register_driver(&pch_uart_driver); 1859 if (ret < 0) 1860 return ret; 1861 1862 /* register as PCI driver */ 1863 ret = pci_register_driver(&pch_uart_pci_driver); 1864 if (ret < 0) 1865 uart_unregister_driver(&pch_uart_driver); 1866 1867 return ret; 1868 } 1869 module_init(pch_uart_module_init); 1870 1871 static void __exit pch_uart_module_exit(void) 1872 { 1873 pci_unregister_driver(&pch_uart_pci_driver); 1874 uart_unregister_driver(&pch_uart_driver); 1875 } 1876 module_exit(pch_uart_module_exit); 1877 1878 MODULE_LICENSE("GPL v2"); 1879 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1880 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 1881 1882 module_param(default_baud, uint, S_IRUGO); 1883 MODULE_PARM_DESC(default_baud, 1884 "Default BAUD for initial driver state and console (default 9600)"); 1885 module_param(user_uartclk, uint, S_IRUGO); 1886 MODULE_PARM_DESC(user_uartclk, 1887 "Override UART default or board specific UART clock"); 1888