1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 bool have_cap_arm_mte;
19
20 enum ftr_type {
21 FTR_EXACT, /* Use a predefined safe value */
22 FTR_LOWER_SAFE, /* Smaller value is safe */
23 FTR_HIGHER_SAFE, /* Bigger value is safe */
24 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
25 FTR_END, /* Mark the last ftr bits */
26 };
27
28 #define FTR_SIGNED true /* Value should be treated as signed */
29 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
30
31 struct reg_ftr_bits {
32 char *name;
33 bool sign;
34 enum ftr_type type;
35 uint8_t shift;
36 uint64_t mask;
37 /*
38 * For FTR_EXACT, safe_val is used as the exact safe value.
39 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
40 */
41 int64_t safe_val;
42 };
43
44 struct test_feature_reg {
45 uint32_t reg;
46 const struct reg_ftr_bits *ftr_bits;
47 };
48
49 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
50 { \
51 .name = #NAME, \
52 .sign = SIGNED, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .mask = MASK, \
56 .safe_val = SAFE_VAL, \
57 }
58
59 #define REG_FTR_BITS(type, reg, field, safe_val) \
60 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
61 reg##_##field##_MASK, safe_val)
62
63 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
64 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
65 reg##_##field##_MASK, safe_val)
66
67 #define REG_FTR_END \
68 { \
69 .type = FTR_END, \
70 }
71
72 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
75 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
76 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
77 REG_FTR_END,
78 };
79
80 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
81 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
82 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
83 REG_FTR_END,
84 };
85
86 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
100 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
101 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
102 REG_FTR_END,
103 };
104
105 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
116 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
117 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
118 REG_FTR_END,
119 };
120
121 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
123 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
124 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
125 REG_FTR_END,
126 };
127
128 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
131 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
133 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1),
136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1),
137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1),
138 REG_FTR_END,
139 };
140
141 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0),
143 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
144 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
145 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
146 REG_FTR_END,
147 };
148
149 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
152 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1),
153 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1),
154 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1),
155 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
156 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
159 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
160 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
162 REG_FTR_END,
163 };
164
165 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
169 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
174 REG_FTR_END,
175 };
176
177 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
188 REG_FTR_END,
189 };
190
191 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = {
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0),
195 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0),
196 REG_FTR_END,
197 };
198
199 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
202 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
203 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
204 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
205 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
206 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
209 REG_FTR_END,
210 };
211
212 #define TEST_REG(id, table) \
213 { \
214 .reg = id, \
215 .ftr_bits = &((table)[0]), \
216 }
217
218 static struct test_feature_reg test_regs[] = {
219 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
220 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
221 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
222 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
223 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
224 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
225 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
226 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
227 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
228 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
229 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1),
230 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
231 };
232
233 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
234
guest_code(void)235 static void guest_code(void)
236 {
237 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
238 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
239 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
240 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
241 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
242 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
243 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
244 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
245 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
246 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
247 GUEST_REG_SYNC(SYS_CTR_EL0);
248 GUEST_REG_SYNC(SYS_MIDR_EL1);
249 GUEST_REG_SYNC(SYS_REVIDR_EL1);
250 GUEST_REG_SYNC(SYS_AIDR_EL1);
251
252 GUEST_DONE();
253 }
254
255 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)256 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
257 {
258 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
259
260 if (ftr_bits->sign == FTR_UNSIGNED) {
261 switch (ftr_bits->type) {
262 case FTR_EXACT:
263 ftr = ftr_bits->safe_val;
264 break;
265 case FTR_LOWER_SAFE:
266 if (ftr > ftr_bits->safe_val)
267 ftr--;
268 break;
269 case FTR_HIGHER_SAFE:
270 if (ftr < ftr_max)
271 ftr++;
272 break;
273 case FTR_HIGHER_OR_ZERO_SAFE:
274 if (ftr == ftr_max)
275 ftr = 0;
276 else if (ftr != 0)
277 ftr++;
278 break;
279 default:
280 break;
281 }
282 } else if (ftr != ftr_max) {
283 switch (ftr_bits->type) {
284 case FTR_EXACT:
285 ftr = ftr_bits->safe_val;
286 break;
287 case FTR_LOWER_SAFE:
288 if (ftr > ftr_bits->safe_val)
289 ftr--;
290 break;
291 case FTR_HIGHER_SAFE:
292 if (ftr < ftr_max - 1)
293 ftr++;
294 break;
295 case FTR_HIGHER_OR_ZERO_SAFE:
296 if (ftr != 0 && ftr != ftr_max - 1)
297 ftr++;
298 break;
299 default:
300 break;
301 }
302 }
303
304 return ftr;
305 }
306
307 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)308 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
309 {
310 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
311
312 if (ftr_bits->sign == FTR_UNSIGNED) {
313 switch (ftr_bits->type) {
314 case FTR_EXACT:
315 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
316 break;
317 case FTR_LOWER_SAFE:
318 ftr++;
319 break;
320 case FTR_HIGHER_SAFE:
321 ftr--;
322 break;
323 case FTR_HIGHER_OR_ZERO_SAFE:
324 if (ftr == 0)
325 ftr = ftr_max;
326 else
327 ftr--;
328 break;
329 default:
330 break;
331 }
332 } else if (ftr != ftr_max) {
333 switch (ftr_bits->type) {
334 case FTR_EXACT:
335 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
336 break;
337 case FTR_LOWER_SAFE:
338 ftr++;
339 break;
340 case FTR_HIGHER_SAFE:
341 ftr--;
342 break;
343 case FTR_HIGHER_OR_ZERO_SAFE:
344 if (ftr == 0)
345 ftr = ftr_max - 1;
346 else
347 ftr--;
348 break;
349 default:
350 break;
351 }
352 } else {
353 ftr = 0;
354 }
355
356 return ftr;
357 }
358
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)359 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
360 const struct reg_ftr_bits *ftr_bits)
361 {
362 uint8_t shift = ftr_bits->shift;
363 uint64_t mask = ftr_bits->mask;
364 uint64_t val, new_val, ftr;
365
366 val = vcpu_get_reg(vcpu, reg);
367 ftr = (val & mask) >> shift;
368
369 ftr = get_safe_value(ftr_bits, ftr);
370
371 ftr <<= shift;
372 val &= ~mask;
373 val |= ftr;
374
375 vcpu_set_reg(vcpu, reg, val);
376 new_val = vcpu_get_reg(vcpu, reg);
377 TEST_ASSERT_EQ(new_val, val);
378
379 return new_val;
380 }
381
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)382 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
383 const struct reg_ftr_bits *ftr_bits)
384 {
385 uint8_t shift = ftr_bits->shift;
386 uint64_t mask = ftr_bits->mask;
387 uint64_t val, old_val, ftr;
388 int r;
389
390 val = vcpu_get_reg(vcpu, reg);
391 ftr = (val & mask) >> shift;
392
393 ftr = get_invalid_value(ftr_bits, ftr);
394
395 old_val = val;
396 ftr <<= shift;
397 val &= ~mask;
398 val |= ftr;
399
400 r = __vcpu_set_reg(vcpu, reg, val);
401 TEST_ASSERT(r < 0 && errno == EINVAL,
402 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
403
404 val = vcpu_get_reg(vcpu, reg);
405 TEST_ASSERT_EQ(val, old_val);
406 }
407
408 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
409
410 #define encoding_to_range_idx(encoding) \
411 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
412 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
413 sys_reg_Op2(encoding))
414
415
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)416 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
417 {
418 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
419 struct reg_mask_range range = {
420 .addr = (__u64)masks,
421 };
422 int ret;
423
424 /* KVM should return error when reserved field is not zero */
425 range.reserved[0] = 1;
426 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
427 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
428
429 /* Get writable masks for feature ID registers */
430 memset(range.reserved, 0, sizeof(range.reserved));
431 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
432
433 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
434 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
435 uint32_t reg_id = test_regs[i].reg;
436 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
437 int idx;
438
439 /* Get the index to masks array for the idreg */
440 idx = encoding_to_range_idx(reg_id);
441
442 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
443 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
444 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
445 ksft_test_result_skip("%s on AARCH64 only system\n",
446 ftr_bits[j].name);
447 continue;
448 }
449
450 /* Make sure the feature field is writable */
451 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
452
453 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
454
455 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
456 &ftr_bits[j]);
457
458 ksft_test_result_pass("%s\n", ftr_bits[j].name);
459 }
460 }
461 }
462
463 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)464 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
465 {
466 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
467 struct reg_mask_range range = {
468 .addr = (__u64)masks,
469 };
470 uint64_t val;
471 int idx, err;
472
473 /*
474 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
475 * check that if it can be set to 1, (i.e. it is supported by the
476 * hardware), that it can't be set to other values.
477 */
478
479 /* Get writable masks for feature ID registers */
480 memset(range.reserved, 0, sizeof(range.reserved));
481 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
482
483 /* Writeable? Nothing to test! */
484 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
485 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
486 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
487 return;
488 }
489
490 /* Get the id register value */
491 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
492
493 /* Try to set MPAM=0. This should always be possible. */
494 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
495 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
496 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
497 if (err)
498 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
499 else
500 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
501
502 /* Try to set MPAM=1 */
503 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
504 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
505 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
506 if (err)
507 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
508 else
509 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
510
511 /* Try to set MPAM=2 */
512 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
513 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
514 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
515 if (err)
516 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
517 else
518 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
519
520 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
521 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
522 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
523 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
524 return;
525 }
526
527 /* Get the id register value */
528 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
529
530 /* Try to set MPAM_frac=0. This should always be possible. */
531 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
532 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
533 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
534 if (err)
535 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
536 else
537 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
538
539 /* Try to set MPAM_frac=1 */
540 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
541 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
542 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
543 if (err)
544 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
545 else
546 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
547
548 /* Try to set MPAM_frac=2 */
549 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
550 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
551 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
552 if (err)
553 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
554 else
555 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
556 }
557
558 #define MTE_IDREG_TEST 1
test_user_set_mte_reg(struct kvm_vcpu * vcpu)559 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
560 {
561 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
562 struct reg_mask_range range = {
563 .addr = (__u64)masks,
564 };
565 uint64_t val;
566 uint64_t mte;
567 uint64_t mte_frac;
568 int idx, err;
569
570 if (!have_cap_arm_mte) {
571 ksft_test_result_skip("MTE capability not supported, nothing to test\n");
572 return;
573 }
574
575 /* Get writable masks for feature ID registers */
576 memset(range.reserved, 0, sizeof(range.reserved));
577 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
578
579 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
580 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) {
581 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n");
582 return;
583 }
584
585 /*
586 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2)
587 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported
588 * and MTE_frac == 0 indicates it is supported.
589 *
590 * As MTE_frac was previously unconditionally read as 0, check
591 * that the set to 0 succeeds but does not change MTE_frac
592 * from unsupported (0xF) to supported (0).
593 *
594 */
595 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
596
597 mte = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), val);
598 mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
599 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 ||
600 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) {
601 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n");
602 return;
603 }
604
605 /* Try to set MTE_frac=0. */
606 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
607 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0);
608 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
609 if (err) {
610 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n");
611 return;
612 }
613
614 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
615 mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
616 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI)
617 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n");
618 else
619 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n");
620 }
621
test_guest_reg_read(struct kvm_vcpu * vcpu)622 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
623 {
624 bool done = false;
625 struct ucall uc;
626
627 while (!done) {
628 vcpu_run(vcpu);
629
630 switch (get_ucall(vcpu, &uc)) {
631 case UCALL_ABORT:
632 REPORT_GUEST_ASSERT(uc);
633 break;
634 case UCALL_SYNC:
635 /* Make sure the written values are seen by guest */
636 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
637 uc.args[3]);
638 break;
639 case UCALL_DONE:
640 done = true;
641 break;
642 default:
643 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
644 }
645 }
646 }
647
648 /* Politely lifted from arch/arm64/include/asm/cache.h */
649 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
650 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
651 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
652 #define CLIDR_CTYPE(clidr, level) \
653 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
654
test_clidr(struct kvm_vcpu * vcpu)655 static void test_clidr(struct kvm_vcpu *vcpu)
656 {
657 uint64_t clidr;
658 int level;
659
660 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
661
662 /* find the first empty level in the cache hierarchy */
663 for (level = 1; level < 7; level++) {
664 if (!CLIDR_CTYPE(clidr, level))
665 break;
666 }
667
668 /*
669 * If you have a mind-boggling 7 levels of cache, congratulations, you
670 * get to fix this.
671 */
672 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
673
674 /* stick in a unified cache level */
675 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
676
677 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
678 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
679 }
680
test_ctr(struct kvm_vcpu * vcpu)681 static void test_ctr(struct kvm_vcpu *vcpu)
682 {
683 u64 ctr;
684
685 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
686 ctr &= ~CTR_EL0_DIC_MASK;
687 if (ctr & CTR_EL0_IminLine_MASK)
688 ctr--;
689
690 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
691 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
692 }
693
test_id_reg(struct kvm_vcpu * vcpu,u32 id)694 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id)
695 {
696 u64 val;
697
698 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
699 val++;
700 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val);
701 test_reg_vals[encoding_to_range_idx(id)] = val;
702 }
703
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)704 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
705 {
706 test_clidr(vcpu);
707 test_ctr(vcpu);
708
709 test_id_reg(vcpu, SYS_MPIDR_EL1);
710 ksft_test_result_pass("%s\n", __func__);
711 }
712
test_vcpu_non_ftr_id_regs(struct kvm_vcpu * vcpu)713 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
714 {
715 test_id_reg(vcpu, SYS_MIDR_EL1);
716 test_id_reg(vcpu, SYS_REVIDR_EL1);
717 test_id_reg(vcpu, SYS_AIDR_EL1);
718
719 ksft_test_result_pass("%s\n", __func__);
720 }
721
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)722 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
723 {
724 size_t idx = encoding_to_range_idx(encoding);
725 uint64_t observed;
726
727 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
728 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
729 }
730
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)731 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
732 {
733 /*
734 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
735 * architectural reset of the vCPU.
736 */
737 aarch64_vcpu_setup(vcpu, NULL);
738
739 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
740 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
741
742 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
743 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
744 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
745 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1);
746 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1);
747 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1);
748
749 ksft_test_result_pass("%s\n", __func__);
750 }
751
kvm_arch_vm_post_create(struct kvm_vm * vm)752 void kvm_arch_vm_post_create(struct kvm_vm *vm)
753 {
754 if (vm_check_cap(vm, KVM_CAP_ARM_MTE)) {
755 vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0);
756 have_cap_arm_mte = true;
757 }
758 }
759
main(void)760 int main(void)
761 {
762 struct kvm_vcpu *vcpu;
763 struct kvm_vm *vm;
764 bool aarch64_only;
765 uint64_t val, el0;
766 int test_cnt;
767
768 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
769 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS));
770
771 vm = vm_create(1);
772 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0);
773 vcpu = vm_vcpu_add(vm, 0, guest_code);
774
775 /* Check for AARCH64 only system */
776 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
777 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
778 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
779
780 ksft_print_header();
781
782 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
783 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
784 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
785 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
786 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
787 ARRAY_SIZE(ftr_id_aa64mmfr3_el1) + ARRAY_SIZE(ftr_id_aa64zfr0_el1) -
788 ARRAY_SIZE(test_regs) + 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST;
789
790 ksft_set_plan(test_cnt);
791
792 test_vm_ftr_id_regs(vcpu, aarch64_only);
793 test_vcpu_ftr_id_regs(vcpu);
794 test_vcpu_non_ftr_id_regs(vcpu);
795 test_user_set_mpam_reg(vcpu);
796 test_user_set_mte_reg(vcpu);
797
798 test_guest_reg_read(vcpu);
799
800 test_reset_preserves_id_regs(vcpu);
801
802 kvm_vm_free(vm);
803
804 ksft_finished();
805 }
806