xref: /linux/drivers/gpu/drm/amd/display/dc/dc_types.h (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef DC_TYPES_H_
26 #define DC_TYPES_H_
27 
28 /* AND EdidUtility only needs a portion
29  * of this file, including the rest only
30  * causes additional issues.
31  */
32 #include "os_types.h"
33 #include "fixed31_32.h"
34 #include "irq_types.h"
35 #include "dc_ddc_types.h"
36 #include "dc_dp_types.h"
37 #include "dc_hdmi_types.h"
38 #include "dc_hw_types.h"
39 #include "dal_types.h"
40 #include "grph_object_defs.h"
41 #include "grph_object_ctrl_defs.h"
42 
43 #include "dm_cp_psp.h"
44 
45 /* forward declarations */
46 struct dc_plane_state;
47 struct dc_stream_state;
48 struct dc_link;
49 struct dc_sink;
50 struct dal;
51 struct dc_dmub_srv;
52 
53 /********************************
54  * Environment definitions
55  ********************************/
56 enum dce_environment {
57 	DCE_ENV_PRODUCTION_DRV = 0,
58 	/* Emulation on FPGA, in "Maximus" System.
59 	 * This environment enforces that *only* DC registers accessed.
60 	 * (access to non-DC registers will hang FPGA) */
61 	DCE_ENV_FPGA_MAXIMUS,
62 	/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
63 	 * requirements of Diagnostics team. */
64 	DCE_ENV_DIAG,
65 	/*
66 	 * Guest VM system, DC HW may exist but is not virtualized and
67 	 * should not be used.  SW support for VDI only.
68 	 */
69 	DCE_ENV_VIRTUAL_HW
70 };
71 
72 struct dc_perf_trace {
73 	unsigned long read_count;
74 	unsigned long write_count;
75 	unsigned long last_entry_read;
76 	unsigned long last_entry_write;
77 };
78 
79 #define NUM_PIXEL_FORMATS 10
80 
81 enum tiling_mode {
82 	TILING_MODE_INVALID,
83 	TILING_MODE_LINEAR,
84 	TILING_MODE_TILED,
85 	TILING_MODE_COUNT
86 };
87 
88 enum view_3d_format {
89 	VIEW_3D_FORMAT_NONE = 0,
90 	VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
91 	VIEW_3D_FORMAT_SIDE_BY_SIDE,
92 	VIEW_3D_FORMAT_TOP_AND_BOTTOM,
93 	VIEW_3D_FORMAT_COUNT,
94 	VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
95 };
96 
97 enum plane_stereo_format {
98 	PLANE_STEREO_FORMAT_NONE = 0,
99 	PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
100 	PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
101 	PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
102 	PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
103 	PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
104 	PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
105 };
106 
107 /* TODO: Find way to calculate number of bits
108  *  Please increase if pixel_format enum increases
109  * num  from  PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
110  */
111 
112 enum dc_edid_connector_type {
113 	DC_EDID_CONNECTOR_UNKNOWN = 0,
114 	DC_EDID_CONNECTOR_ANALOG = 1,
115 	DC_EDID_CONNECTOR_DIGITAL = 10,
116 	DC_EDID_CONNECTOR_DVI = 11,
117 	DC_EDID_CONNECTOR_HDMIA = 12,
118 	DC_EDID_CONNECTOR_MDDI = 14,
119 	DC_EDID_CONNECTOR_DISPLAYPORT = 15
120 };
121 
122 enum dc_edid_status {
123 	EDID_OK,
124 	EDID_BAD_INPUT,
125 	EDID_NO_RESPONSE,
126 	EDID_BAD_CHECKSUM,
127 	EDID_THE_SAME,
128 	EDID_FALL_BACK,
129 	EDID_PARTIAL_VALID,
130 };
131 
132 enum act_return_status {
133 	ACT_SUCCESS,
134 	ACT_LINK_LOST,
135 	ACT_FAILED
136 };
137 
138 /* audio capability from EDID*/
139 struct dc_cea_audio_mode {
140 	uint8_t format_code; /* ucData[0] [6:3]*/
141 	uint8_t channel_count; /* ucData[0] [2:0]*/
142 	uint8_t sample_rate; /* ucData[1]*/
143 	union {
144 		uint8_t sample_size; /* for LPCM*/
145 		/*  for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
146 		uint8_t max_bit_rate;
147 		uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
148 	};
149 };
150 
151 struct dc_edid {
152 	uint32_t length;
153 	uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
154 };
155 
156 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
157  * is used. In this case we assume speaker location are: front left, front
158  * right and front center. */
159 #define DEFAULT_SPEAKER_LOCATION 5
160 
161 #define DC_MAX_AUDIO_DESC_COUNT 16
162 
163 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
164 
165 struct dc_panel_patch {
166 	unsigned int dppowerup_delay;
167 	unsigned int extra_t12_ms;
168 	unsigned int extra_delay_backlight_off;
169 	unsigned int extra_t7_ms;
170 	unsigned int skip_scdc_overwrite;
171 	unsigned int delay_ignore_msa;
172 	unsigned int disable_fec;
173 	unsigned int extra_t3_ms;
174 	unsigned int max_dsc_target_bpp_limit;
175 	unsigned int embedded_tiled_slave;
176 	unsigned int disable_fams;
177 	unsigned int skip_avmute;
178 	unsigned int mst_start_top_delay;
179 	unsigned int remove_sink_ext_caps;
180 	unsigned int disable_colorimetry;
181 	uint8_t blankstream_before_otg_off;
182 	bool oled_optimize_display_on;
183 	unsigned int force_mst_blocked_discovery;
184 };
185 
186 struct dc_edid_caps {
187 	/* sink identification */
188 	uint16_t manufacturer_id;
189 	uint16_t product_id;
190 	uint32_t serial_number;
191 	uint8_t manufacture_week;
192 	uint8_t manufacture_year;
193 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
194 
195 	/* audio caps */
196 	uint8_t speaker_flags;
197 	uint32_t audio_mode_count;
198 	struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
199 	uint32_t audio_latency;
200 	uint32_t video_latency;
201 
202 	uint8_t qs_bit;
203 	uint8_t qy_bit;
204 
205 	uint32_t max_tmds_clk_mhz;
206 
207 	/*HDMI 2.0 caps*/
208 	bool lte_340mcsc_scramble;
209 
210 	bool edid_hdmi;
211 	bool hdr_supported;
212 
213 	struct dc_panel_patch panel_patch;
214 };
215 
216 struct dc_mode_flags {
217 	/* note: part of refresh rate flag*/
218 	uint32_t INTERLACE :1;
219 	/* native display timing*/
220 	uint32_t NATIVE :1;
221 	/* preferred is the recommended mode, one per display */
222 	uint32_t PREFERRED :1;
223 	/* true if this mode should use reduced blanking timings
224 	 *_not_ related to the Reduced Blanking adjustment*/
225 	uint32_t REDUCED_BLANKING :1;
226 	/* note: part of refreshrate flag*/
227 	uint32_t VIDEO_OPTIMIZED_RATE :1;
228 	/* should be reported to upper layers as mode_flags*/
229 	uint32_t PACKED_PIXEL_FORMAT :1;
230 	/*< preferred view*/
231 	uint32_t PREFERRED_VIEW :1;
232 	/* this timing should be used only in tiled mode*/
233 	uint32_t TILED_MODE :1;
234 	uint32_t DSE_MODE :1;
235 	/* Refresh rate divider when Miracast sink is using a
236 	 different rate than the output display device
237 	 Must be zero for wired displays and non-zero for
238 	 Miracast displays*/
239 	uint32_t MIRACAST_REFRESH_DIVIDER;
240 };
241 
242 
243 enum dc_timing_source {
244 	TIMING_SOURCE_UNDEFINED,
245 
246 	/* explicitly specifed by user, most important*/
247 	TIMING_SOURCE_USER_FORCED,
248 	TIMING_SOURCE_USER_OVERRIDE,
249 	TIMING_SOURCE_CUSTOM,
250 	TIMING_SOURCE_EXPLICIT,
251 
252 	/* explicitly specified by the display device, more important*/
253 	TIMING_SOURCE_EDID_CEA_SVD_3D,
254 	TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
255 	TIMING_SOURCE_EDID_CEA_SVD_420,
256 	TIMING_SOURCE_EDID_DETAILED,
257 	TIMING_SOURCE_EDID_ESTABLISHED,
258 	TIMING_SOURCE_EDID_STANDARD,
259 	TIMING_SOURCE_EDID_CEA_SVD,
260 	TIMING_SOURCE_EDID_CVT_3BYTE,
261 	TIMING_SOURCE_EDID_4BYTE,
262 	TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB,
263 	TIMING_SOURCE_EDID_CEA_RID,
264 	TIMING_SOURCE_VBIOS,
265 	TIMING_SOURCE_CV,
266 	TIMING_SOURCE_TV,
267 	TIMING_SOURCE_HDMI_VIC,
268 
269 	/* implicitly specified by display device, still safe but less important*/
270 	TIMING_SOURCE_DEFAULT,
271 
272 	/* only used for custom base modes */
273 	TIMING_SOURCE_CUSTOM_BASE,
274 
275 	/* these timing might not work, least important*/
276 	TIMING_SOURCE_RANGELIMIT,
277 	TIMING_SOURCE_OS_FORCED,
278 	TIMING_SOURCE_IMPLICIT,
279 
280 	/* only used by default mode list*/
281 	TIMING_SOURCE_BASICMODE,
282 
283 	TIMING_SOURCE_COUNT
284 };
285 
286 
287 struct stereo_3d_features {
288 	bool supported			;
289 	bool allTimings			;
290 	bool cloneMode			;
291 	bool scaling			;
292 	bool singleFrameSWPacked;
293 };
294 
295 enum dc_timing_support_method {
296 	TIMING_SUPPORT_METHOD_UNDEFINED,
297 	TIMING_SUPPORT_METHOD_EXPLICIT,
298 	TIMING_SUPPORT_METHOD_IMPLICIT,
299 	TIMING_SUPPORT_METHOD_NATIVE
300 };
301 
302 struct dc_mode_info {
303 	uint32_t pixel_width;
304 	uint32_t pixel_height;
305 	uint32_t field_rate;
306 	/* Vertical refresh rate for progressive modes.
307 	* Field rate for interlaced modes.*/
308 
309 	enum dc_timing_standard timing_standard;
310 	enum dc_timing_source timing_source;
311 	struct dc_mode_flags flags;
312 };
313 
314 enum dc_power_state {
315 	DC_POWER_STATE_ON = 1,
316 	DC_POWER_STATE_STANDBY,
317 	DC_POWER_STATE_SUSPEND,
318 	DC_POWER_STATE_OFF
319 };
320 
321 /* DC PowerStates */
322 enum dc_video_power_state {
323 	DC_VIDEO_POWER_UNSPECIFIED = 0,
324 	DC_VIDEO_POWER_ON = 1,
325 	DC_VIDEO_POWER_STANDBY,
326 	DC_VIDEO_POWER_SUSPEND,
327 	DC_VIDEO_POWER_OFF,
328 	DC_VIDEO_POWER_HIBERNATE,
329 	DC_VIDEO_POWER_SHUTDOWN,
330 	DC_VIDEO_POWER_ULPS,	/* BACO or Ultra-Light-Power-State */
331 	DC_VIDEO_POWER_AFTER_RESET,
332 	DC_VIDEO_POWER_MAXIMUM
333 };
334 
335 enum dc_acpi_cm_power_state {
336 	DC_ACPI_CM_POWER_STATE_D0 = 1,
337 	DC_ACPI_CM_POWER_STATE_D1 = 2,
338 	DC_ACPI_CM_POWER_STATE_D2 = 4,
339 	DC_ACPI_CM_POWER_STATE_D3 = 8
340 };
341 
342 enum dc_connection_type {
343 	dc_connection_none,
344 	dc_connection_single,
345 	dc_connection_mst_branch,
346 	dc_connection_sst_branch
347 };
348 
349 struct dc_csc_adjustments {
350 	struct fixed31_32 contrast;
351 	struct fixed31_32 saturation;
352 	struct fixed31_32 brightness;
353 	struct fixed31_32 hue;
354 };
355 
356 /* Scaling format */
357 enum scaling_transformation {
358 	SCALING_TRANSFORMATION_UNINITIALIZED,
359 	SCALING_TRANSFORMATION_IDENTITY = 0x0001,
360 	SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
361 	SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
362 	SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
363 	SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
364 	SCALING_TRANSFORMATION_INVALID = 0x80000000,
365 
366 	/* Flag the first and last */
367 	SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
368 	SCALING_TRANSFORMATION_END =
369 		SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
370 };
371 
372 enum display_content_type {
373 	DISPLAY_CONTENT_TYPE_NO_DATA = 0,
374 	DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
375 	DISPLAY_CONTENT_TYPE_PHOTO = 2,
376 	DISPLAY_CONTENT_TYPE_CINEMA = 4,
377 	DISPLAY_CONTENT_TYPE_GAME = 8
378 };
379 
380 enum cm_gamut_adjust_type {
381 	CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
382 	CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
383 	CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */
384 };
385 
386 struct cm_grph_csc_adjustment {
387 	struct fixed31_32 temperature_matrix[12];
388 	enum cm_gamut_adjust_type gamut_adjust_type;
389 	enum cm_gamut_coef_format gamut_coef_format;
390 };
391 
392 /* writeback */
393 struct dwb_stereo_params {
394 	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
395 	enum dwb_stereo_type		stereo_type;		/* indicates stereo format */
396 	bool				stereo_polarity;	/* indicates left eye or right eye comes first in stereo mode */
397 	enum dwb_stereo_eye_select	stereo_eye_select;	/* indicate which eye should be captured */
398 };
399 
400 struct dc_dwb_cnv_params {
401 	unsigned int		src_width;	/* input active width */
402 	unsigned int		src_height;	/* input active height (half-active height in interlaced mode) */
403 	unsigned int		crop_width;	/* cropped window width at cnv output */
404 	bool			crop_en;	/* window cropping enable in cnv */
405 	unsigned int		crop_height;	/* cropped window height at cnv output */
406 	unsigned int		crop_x;		/* cropped window start x value at cnv output */
407 	unsigned int		crop_y;		/* cropped window start y value at cnv output */
408 	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */
409 	enum dwb_out_format	fc_out_format;	/* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
410 	enum dwb_out_denorm	out_denorm_mode;/* dwb output denormalization mode */
411 	unsigned int		out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
412 	unsigned int		out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
413 };
414 
415 struct dc_dwb_params {
416 	unsigned int			dwbscl_black_color; /* must be in FP1.5.10 */
417 	unsigned int			hdr_mult;	/* must be in FP1.6.12 */
418 	struct cm_grph_csc_adjustment	csc_params;
419 	struct dwb_stereo_params	stereo_params;
420 	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */
421 	unsigned int			dest_width;	/* Destination width */
422 	unsigned int			dest_height;	/* Destination height */
423 	enum dwb_scaler_mode		out_format;	/* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */
424 	enum dwb_output_depth		output_depth;	/* output pixel depth - 8bpc or 10bpc */
425 	enum dwb_capture_rate		capture_rate;	/* controls the frame capture rate */
426 	struct scaling_taps 		scaler_taps;	/* Scaling taps */
427 	enum dwb_subsample_position	subsample_position;
428 	const struct dc_transfer_func *out_transfer_func;
429 };
430 
431 /* audio*/
432 
433 union audio_sample_rates {
434 	struct sample_rates {
435 		uint8_t RATE_32:1;
436 		uint8_t RATE_44_1:1;
437 		uint8_t RATE_48:1;
438 		uint8_t RATE_88_2:1;
439 		uint8_t RATE_96:1;
440 		uint8_t RATE_176_4:1;
441 		uint8_t RATE_192:1;
442 	} rate;
443 
444 	uint8_t all;
445 };
446 
447 struct audio_speaker_flags {
448 	uint32_t FL_FR:1;
449 	uint32_t LFE:1;
450 	uint32_t FC:1;
451 	uint32_t RL_RR:1;
452 	uint32_t RC:1;
453 	uint32_t FLC_FRC:1;
454 	uint32_t RLC_RRC:1;
455 	uint32_t SUPPORT_AI:1;
456 };
457 
458 struct audio_speaker_info {
459 	uint32_t ALLSPEAKERS:7;
460 	uint32_t SUPPORT_AI:1;
461 };
462 
463 
464 struct audio_info_flags {
465 
466 	union {
467 
468 		struct audio_speaker_flags speaker_flags;
469 		struct audio_speaker_info   info;
470 
471 		uint8_t all;
472 	};
473 };
474 
475 enum audio_format_code {
476 	AUDIO_FORMAT_CODE_FIRST = 1,
477 	AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
478 
479 	AUDIO_FORMAT_CODE_AC3,
480 	/*Layers 1 & 2 */
481 	AUDIO_FORMAT_CODE_MPEG1,
482 	/*MPEG1 Layer 3 */
483 	AUDIO_FORMAT_CODE_MP3,
484 	/*multichannel */
485 	AUDIO_FORMAT_CODE_MPEG2,
486 	AUDIO_FORMAT_CODE_AAC,
487 	AUDIO_FORMAT_CODE_DTS,
488 	AUDIO_FORMAT_CODE_ATRAC,
489 	AUDIO_FORMAT_CODE_1BITAUDIO,
490 	AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
491 	AUDIO_FORMAT_CODE_DTS_HD,
492 	AUDIO_FORMAT_CODE_MAT_MLP,
493 	AUDIO_FORMAT_CODE_DST,
494 	AUDIO_FORMAT_CODE_WMAPRO,
495 	AUDIO_FORMAT_CODE_LAST,
496 	AUDIO_FORMAT_CODE_COUNT =
497 		AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
498 };
499 
500 struct audio_mode {
501 	 /* ucData[0] [6:3] */
502 	enum audio_format_code format_code;
503 	/* ucData[0] [2:0] */
504 	uint8_t channel_count;
505 	/* ucData[1] */
506 	union audio_sample_rates sample_rates;
507 	union {
508 		/* for LPCM */
509 		uint8_t sample_size;
510 		/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
511 		uint8_t max_bit_rate;
512 		/* for Audio Formats 9-15 */
513 		uint8_t vendor_specific;
514 	};
515 };
516 
517 struct audio_info {
518 	struct audio_info_flags flags;
519 	uint32_t video_latency;
520 	uint32_t audio_latency;
521 	uint32_t display_index;
522 	uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
523 	uint32_t manufacture_id;
524 	uint32_t product_id;
525 	/* PortID used for ContainerID when defined */
526 	uint32_t port_id[2];
527 	uint32_t mode_count;
528 	/* this field must be last in this struct */
529 	struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
530 };
531 struct audio_check {
532 	unsigned int audio_packet_type;
533 	unsigned int max_audiosample_rate;
534 	unsigned int acat;
535 };
536 enum dc_infoframe_type {
537 	DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
538 	DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
539 	DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
540 	DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
541 	DC_DP_INFOFRAME_TYPE_PPS = 0x10,
542 };
543 
544 struct dc_info_packet {
545 	bool valid;
546 	uint8_t hb0;
547 	uint8_t hb1;
548 	uint8_t hb2;
549 	uint8_t hb3;
550 	uint8_t sb[32];
551 };
552 
553 struct dc_info_packet_128 {
554 	bool valid;
555 	uint8_t hb0;
556 	uint8_t hb1;
557 	uint8_t hb2;
558 	uint8_t hb3;
559 	uint8_t sb[128];
560 };
561 
562 #define DC_PLANE_UPDATE_TIMES_MAX 10
563 
564 struct dc_plane_flip_time {
565 	unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
566 	unsigned int index;
567 	unsigned int prev_update_time_in_us;
568 };
569 
570 enum dc_psr_state {
571 	PSR_STATE0 = 0x0,
572 	PSR_STATE1,
573 	PSR_STATE1a,
574 	PSR_STATE2,
575 	PSR_STATE2a,
576 	PSR_STATE2b,
577 	PSR_STATE3,
578 	PSR_STATE3Init,
579 	PSR_STATE4,
580 	PSR_STATE4a,
581 	PSR_STATE4b,
582 	PSR_STATE4c,
583 	PSR_STATE4d,
584 	PSR_STATE4_FULL_FRAME,
585 	PSR_STATE4a_FULL_FRAME,
586 	PSR_STATE4b_FULL_FRAME,
587 	PSR_STATE4c_FULL_FRAME,
588 	PSR_STATE4_FULL_FRAME_POWERUP,
589 	PSR_STATE4_FULL_FRAME_HW_LOCK,
590 	PSR_STATE5,
591 	PSR_STATE5a,
592 	PSR_STATE5b,
593 	PSR_STATE5c,
594 	PSR_STATE_HWLOCK_MGR,
595 	PSR_STATE_POLLVUPDATE,
596 	PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME,
597 	PSR_STATE_INVALID = 0xFF
598 };
599 
600 struct psr_config {
601 	unsigned char psr_version;
602 	unsigned int psr_rfb_setup_time;
603 	bool psr_exit_link_training_required;
604 	bool psr_frame_capture_indication_req;
605 	unsigned int psr_sdp_transmit_line_num_deadline;
606 	bool allow_smu_optimizations;
607 	bool allow_multi_disp_optimizations;
608 	/* Panel self refresh 2 selective update granularity required */
609 	bool su_granularity_required;
610 	/* psr2 selective update y granularity capability */
611 	uint8_t su_y_granularity;
612 	unsigned int line_time_in_us;
613 	uint8_t rate_control_caps;
614 	uint16_t dsc_slice_height;
615 };
616 
617 union dmcu_psr_level {
618 	struct {
619 		unsigned int SKIP_CRC:1;
620 		unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
621 		unsigned int SKIP_PHY_POWER_DOWN:1;
622 		unsigned int SKIP_AUX_ACK_CHECK:1;
623 		unsigned int SKIP_CRTC_DISABLE:1;
624 		unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
625 		unsigned int SKIP_SMU_NOTIFICATION:1;
626 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
627 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
628 		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
629 		unsigned int DISABLE_ALPM:1;
630 		unsigned int ALPM_DEFAULT_PD_MODE:1;
631 		unsigned int RESERVED:20;
632 	} bits;
633 	unsigned int u32all;
634 };
635 
636 enum physical_phy_id {
637 	PHYLD_0,
638 	PHYLD_1,
639 	PHYLD_2,
640 	PHYLD_3,
641 	PHYLD_4,
642 	PHYLD_5,
643 	PHYLD_6,
644 	PHYLD_7,
645 	PHYLD_8,
646 	PHYLD_9,
647 	PHYLD_COUNT,
648 	PHYLD_UNKNOWN = (-1L)
649 };
650 
651 enum phy_type {
652 	PHY_TYPE_UNKNOWN  = 1,
653 	PHY_TYPE_PCIE_PHY = 2,
654 	PHY_TYPE_UNIPHY = 3,
655 };
656 
657 struct psr_context {
658 	/* ddc line */
659 	enum channel_id channel;
660 	/* Transmitter id */
661 	enum transmitter transmitterId;
662 	/* Engine Id is used for Dig Be source select */
663 	enum engine_id engineId;
664 	/* Controller Id used for Dig Fe source select */
665 	enum controller_id controllerId;
666 	/* Pcie or Uniphy */
667 	enum phy_type phyType;
668 	/* Physical PHY Id used by SMU interpretation */
669 	enum physical_phy_id smuPhyId;
670 	/* Vertical total pixels from crtc timing.
671 	 * This is used for static screen detection.
672 	 * ie. If we want to detect half a frame,
673 	 * we use this to determine the hyst lines.
674 	 */
675 	unsigned int crtcTimingVerticalTotal;
676 	/* PSR supported from panel capabilities and
677 	 * current display configuration
678 	 */
679 	bool psrSupportedDisplayConfig;
680 	/* Whether fast link training is supported by the panel */
681 	bool psrExitLinkTrainingRequired;
682 	/* If RFB setup time is greater than the total VBLANK time,
683 	 * it is not possible for the sink to capture the video frame
684 	 * in the same frame the SDP is sent. In this case,
685 	 * the frame capture indication bit should be set and an extra
686 	 * static frame should be transmitted to the sink.
687 	 */
688 	bool psrFrameCaptureIndicationReq;
689 	/* Set the last possible line SDP may be transmitted without violating
690 	 * the RFB setup time or entering the active video frame.
691 	 */
692 	unsigned int sdpTransmitLineNumDeadline;
693 	/* The VSync rate in Hz used to calculate the
694 	 * step size for smooth brightness feature
695 	 */
696 	unsigned int vsync_rate_hz;
697 	unsigned int skipPsrWaitForPllLock;
698 	unsigned int numberOfControllers;
699 	/* Unused, for future use. To indicate that first changed frame from
700 	 * state3 shouldn't result in psr_inactive, but rather to perform
701 	 * an automatic single frame rfb_update.
702 	 */
703 	bool rfb_update_auto_en;
704 	/* Number of frame before entering static screen */
705 	unsigned int timehyst_frames;
706 	/* Partial frames before entering static screen */
707 	unsigned int hyst_lines;
708 	/* # of repeated AUX transaction attempts to make before
709 	 * indicating failure to the driver
710 	 */
711 	unsigned int aux_repeats;
712 	/* Controls hw blocks to power down during PSR active state */
713 	union dmcu_psr_level psr_level;
714 	/* Controls additional delay after remote frame capture before
715 	 * continuing powerd own
716 	 */
717 	unsigned int frame_delay;
718 	bool allow_smu_optimizations;
719 	bool allow_multi_disp_optimizations;
720 	/* Panel self refresh 2 selective update granularity required */
721 	bool su_granularity_required;
722 	/* psr2 selective update y granularity capability */
723 	uint8_t su_y_granularity;
724 	unsigned int line_time_in_us;
725 	uint8_t rate_control_caps;
726 	uint16_t dsc_slice_height;
727 };
728 
729 struct colorspace_transform {
730 	struct fixed31_32 matrix[12];
731 	bool enable_remap;
732 };
733 
734 enum i2c_mot_mode {
735 	I2C_MOT_UNDEF,
736 	I2C_MOT_TRUE,
737 	I2C_MOT_FALSE
738 };
739 
740 struct AsicStateEx {
741 	unsigned int memoryClock;
742 	unsigned int displayClock;
743 	unsigned int engineClock;
744 	unsigned int maxSupportedDppClock;
745 	unsigned int dppClock;
746 	unsigned int socClock;
747 	unsigned int dcfClockDeepSleep;
748 	unsigned int fClock;
749 	unsigned int phyClock;
750 };
751 
752 
753 enum dc_clock_type {
754 	DC_CLOCK_TYPE_DISPCLK = 0,
755 	DC_CLOCK_TYPE_DPPCLK        = 1,
756 };
757 
758 struct dc_clock_config {
759 	uint32_t max_clock_khz;
760 	uint32_t min_clock_khz;
761 	uint32_t bw_requirequired_clock_khz;
762 	uint32_t current_clock_khz;/*current clock in use*/
763 };
764 
765 struct hw_asic_id {
766 	uint32_t chip_id;
767 	uint32_t chip_family;
768 	uint32_t pci_revision_id;
769 	uint32_t hw_internal_rev;
770 	uint32_t vram_type;
771 	uint32_t vram_width;
772 	uint32_t feature_flags;
773 	uint32_t fake_paths_num;
774 	void *atombios_base_address;
775 };
776 
777 struct dc_context {
778 	struct dc *dc;
779 
780 	void *driver_context; /* e.g. amdgpu_device */
781 	struct dal_logger *logger;
782 	struct dc_perf_trace *perf_trace;
783 	void *cgs_device;
784 
785 	enum dce_environment dce_environment;
786 	struct hw_asic_id asic_id;
787 
788 	/* todo: below should probably move to dc.  to facilitate removal
789 	 * of AS we will store these here
790 	 */
791 	enum dce_version dce_version;
792 	struct dc_bios *dc_bios;
793 	bool created_bios;
794 	struct gpio_service *gpio_service;
795 	uint32_t dc_sink_id_count;
796 	uint32_t dc_stream_id_count;
797 	uint32_t dc_edp_id_count;
798 	uint64_t fbc_gpu_addr;
799 	struct dc_dmub_srv *dmub_srv;
800 	struct cp_psp cp_psp;
801 	uint32_t *dcn_reg_offsets;
802 	uint32_t *nbio_reg_offsets;
803 	uint32_t *clk_reg_offsets;
804 };
805 
806 /* DSC DPCD capabilities */
807 union dsc_slice_caps1 {
808 	struct {
809 		uint8_t NUM_SLICES_1 : 1;
810 		uint8_t NUM_SLICES_2 : 1;
811 		uint8_t RESERVED : 1;
812 		uint8_t NUM_SLICES_4 : 1;
813 		uint8_t NUM_SLICES_6 : 1;
814 		uint8_t NUM_SLICES_8 : 1;
815 		uint8_t NUM_SLICES_10 : 1;
816 		uint8_t NUM_SLICES_12 : 1;
817 	} bits;
818 	uint8_t raw;
819 };
820 
821 union dsc_slice_caps2 {
822 	struct {
823 		uint8_t NUM_SLICES_16 : 1;
824 		uint8_t NUM_SLICES_20 : 1;
825 		uint8_t NUM_SLICES_24 : 1;
826 		uint8_t RESERVED : 5;
827 	} bits;
828 	uint8_t raw;
829 };
830 
831 union dsc_color_formats {
832 	struct {
833 		uint8_t RGB : 1;
834 		uint8_t YCBCR_444 : 1;
835 		uint8_t YCBCR_SIMPLE_422 : 1;
836 		uint8_t YCBCR_NATIVE_422 : 1;
837 		uint8_t YCBCR_NATIVE_420 : 1;
838 		uint8_t RESERVED : 3;
839 	} bits;
840 	uint8_t raw;
841 };
842 
843 union dsc_color_depth {
844 	struct {
845 		uint8_t RESERVED1 : 1;
846 		uint8_t COLOR_DEPTH_8_BPC : 1;
847 		uint8_t COLOR_DEPTH_10_BPC : 1;
848 		uint8_t COLOR_DEPTH_12_BPC : 1;
849 		uint8_t RESERVED2 : 3;
850 	} bits;
851 	uint8_t raw;
852 };
853 
854 struct dsc_dec_dpcd_caps {
855 	bool is_dsc_supported;
856 	uint8_t dsc_version;
857 	int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
858 	union dsc_slice_caps1 slice_caps1;
859 	union dsc_slice_caps2 slice_caps2;
860 	int32_t lb_bit_depth;
861 	bool is_block_pred_supported;
862 	int32_t edp_max_bits_per_pixel; /* Valid only in eDP */
863 	union dsc_color_formats color_formats;
864 	union dsc_color_depth color_depth;
865 	int32_t throughput_mode_0_mps; /* In MPs */
866 	int32_t throughput_mode_1_mps; /* In MPs */
867 	int32_t max_slice_width;
868 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
869 
870 	/* Extended DSC caps */
871 	uint32_t branch_overall_throughput_0_mps; /* In MPs */
872 	uint32_t branch_overall_throughput_1_mps; /* In MPs */
873 	uint32_t branch_max_line_width;
874 	bool is_dp; /* Decoded format */
875 };
876 
877 struct hblank_expansion_dpcd_caps {
878 	bool expansion_supported;
879 	bool reduction_supported;
880 	bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/
881 	bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/
882 	uint32_t buffer_size; /* Add 1 to value and multiply by 32 */
883 };
884 
885 struct dc_golden_table {
886 	uint16_t dc_golden_table_ver;
887 	uint32_t aux_dphy_rx_control0_val;
888 	uint32_t aux_dphy_tx_control_val;
889 	uint32_t aux_dphy_rx_control1_val;
890 	uint32_t dc_gpio_aux_ctrl_0_val;
891 	uint32_t dc_gpio_aux_ctrl_1_val;
892 	uint32_t dc_gpio_aux_ctrl_2_val;
893 	uint32_t dc_gpio_aux_ctrl_3_val;
894 	uint32_t dc_gpio_aux_ctrl_4_val;
895 	uint32_t dc_gpio_aux_ctrl_5_val;
896 };
897 
898 enum dc_gpu_mem_alloc_type {
899 	DC_MEM_ALLOC_TYPE_GART,
900 	DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
901 	DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
902 	DC_MEM_ALLOC_TYPE_AGP
903 };
904 
905 enum dc_link_encoding_format {
906 	DC_LINK_ENCODING_UNSPECIFIED = 0,
907 	DC_LINK_ENCODING_DP_8b_10b,
908 	DC_LINK_ENCODING_DP_128b_132b,
909 	DC_LINK_ENCODING_HDMI_TMDS,
910 	DC_LINK_ENCODING_HDMI_FRL
911 };
912 
913 enum dc_psr_version {
914 	DC_PSR_VERSION_1			= 0,
915 	DC_PSR_VERSION_SU_1			= 1,
916 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,
917 };
918 
919 /* Possible values of display_endpoint_id.endpoint */
920 enum display_endpoint_type {
921 	DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */
922 	DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */
923 	DISPLAY_ENDPOINT_UNKNOWN = -1
924 };
925 
926 /* Extends graphics_object_id with an additional member 'ep_type' for
927  * distinguishing between physical endpoints (with entries in BIOS connector table) and
928  * logical endpoints.
929  */
930 struct display_endpoint_id {
931 	struct graphics_object_id link_id;
932 	enum display_endpoint_type ep_type;
933 };
934 
935 enum backlight_control_type {
936 	BACKLIGHT_CONTROL_PWM = 0,
937 	BACKLIGHT_CONTROL_VESA_AUX = 1,
938 	BACKLIGHT_CONTROL_AMD_AUX = 2,
939 };
940 
941 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
942 #define MAX_CRC_WINDOW_NUM	2
943 
944 struct otg_phy_mux {
945 	uint8_t phy_output_num;
946 	uint8_t otg_output_num;
947 };
948 
949 struct crc_window {
950 	struct rect rect;
951 	bool enable;
952 };
953 #endif
954 
955 enum dc_detect_reason {
956 	DETECT_REASON_BOOT,
957 	DETECT_REASON_RESUMEFROMS3S4,
958 	DETECT_REASON_HPD,
959 	DETECT_REASON_HPDRX,
960 	DETECT_REASON_FALLBACK,
961 	DETECT_REASON_RETRAIN,
962 	DETECT_REASON_TDR,
963 };
964 
965 struct dc_link_status {
966 	bool link_active;
967 	struct dpcd_caps *dpcd_caps;
968 };
969 
970 union hdcp_rx_caps {
971 	struct {
972 		uint8_t version;
973 		uint8_t reserved;
974 		struct {
975 			uint8_t repeater	: 1;
976 			uint8_t hdcp_capable	: 1;
977 			uint8_t reserved	: 6;
978 		} byte0;
979 	} fields;
980 	uint8_t raw[3];
981 };
982 
983 union hdcp_bcaps {
984 	struct {
985 		uint8_t HDCP_CAPABLE:1;
986 		uint8_t REPEATER:1;
987 		uint8_t RESERVED:6;
988 	} bits;
989 	uint8_t raw;
990 };
991 
992 struct hdcp_caps {
993 	union hdcp_rx_caps rx_caps;
994 	union hdcp_bcaps bcaps;
995 };
996 
997 /* DP MST stream allocation (payload bandwidth number) */
998 struct link_mst_stream_allocation {
999 	/* DIG front */
1000 	const struct stream_encoder *stream_enc;
1001 	/* HPO DP Stream Encoder */
1002 	const struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
1003 	/* associate DRM payload table with DC stream encoder */
1004 	uint8_t vcp_id;
1005 	/* number of slots required for the DP stream in transport packet */
1006 	uint8_t slot_count;
1007 };
1008 
1009 #define MAX_CONTROLLER_NUM 6
1010 
1011 /* DP MST stream allocation table */
1012 struct link_mst_stream_allocation_table {
1013 	/* number of DP video streams */
1014 	int stream_count;
1015 	/* array of stream allocations */
1016 	struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
1017 };
1018 
1019 /* PSR feature flags */
1020 struct psr_settings {
1021 	bool psr_feature_enabled;		// PSR is supported by sink
1022 	bool psr_allow_active;			// PSR is currently active
1023 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
1024 	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
1025 	unsigned long long psr_dirty_rects_change_timestamp_ns;	// for delay of enabling PSR-SU
1026 
1027 	/* These parameters are calculated in Driver,
1028 	 * based on display timing and Sink capabilities.
1029 	 * If VBLANK region is too small and Sink takes a long time
1030 	 * to set up RFB, it may take an extra frame to enter PSR state.
1031 	 */
1032 	bool psr_frame_capture_indication_req;
1033 	unsigned int psr_sdp_transmit_line_num_deadline;
1034 	uint8_t force_ffu_mode;
1035 	unsigned int psr_power_opt;
1036 };
1037 
1038 enum replay_coasting_vtotal_type {
1039 	PR_COASTING_TYPE_NOM = 0,
1040 	PR_COASTING_TYPE_STATIC,
1041 	PR_COASTING_TYPE_FULL_SCREEN_VIDEO,
1042 	PR_COASTING_TYPE_TEST_HARNESS,
1043 	PR_COASTING_TYPE_NUM,
1044 };
1045 
1046 enum replay_link_off_frame_count_level {
1047 	PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0,
1048 	PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2,
1049 	PR_LINK_OFF_FRAME_COUNT_BEST = 0x6,
1050 };
1051 
1052 /*
1053  * This is general Interface for Replay to
1054  * set an 32 bit variable to dmub
1055  * The Message_type indicates which variable
1056  * passed to DMUB.
1057  */
1058 enum replay_FW_Message_type {
1059 	Replay_Msg_Not_Support = -1,
1060 	Replay_Set_Timing_Sync_Supported,
1061 	Replay_Set_Residency_Frameupdate_Timer,
1062 	Replay_Set_Pseudo_VTotal,
1063 	Replay_Disabled_Adaptive_Sync_SDP,
1064 	Replay_Set_General_Cmd,
1065 };
1066 
1067 union replay_error_status {
1068 	struct {
1069 		unsigned int STATE_TRANSITION_ERROR     :1;
1070 		unsigned int LINK_CRC_ERROR             :1;
1071 		unsigned int DESYNC_ERROR               :1;
1072 		unsigned int RESERVED_3                 :1;
1073 		unsigned int LOW_RR_INCORRECT_VTOTAL    :1;
1074 		unsigned int NO_DOUBLED_RR              :1;
1075 		unsigned int RESERVED_6_7               :2;
1076 	} bits;
1077 	unsigned char raw;
1078 };
1079 
1080 union replay_low_refresh_rate_enable_options {
1081 	struct {
1082 	//BIT[0-3]: Replay Low Hz Support control
1083 		unsigned int ENABLE_LOW_RR_SUPPORT          :1;
1084 		unsigned int RESERVED_1_3                   :3;
1085 	//BIT[4-15]: Replay Low Hz Enable Scenarios
1086 		unsigned int ENABLE_STATIC_SCREEN           :1;
1087 		unsigned int ENABLE_FULL_SCREEN_VIDEO       :1;
1088 		unsigned int ENABLE_GENERAL_UI              :1;
1089 		unsigned int RESERVED_7_15                  :9;
1090 	//BIT[16-31]: Replay Low Hz Enable Check
1091 		unsigned int ENABLE_STATIC_FLICKER_CHECK    :1;
1092 		unsigned int RESERVED_17_31                 :15;
1093 	} bits;
1094 	unsigned int raw;
1095 };
1096 
1097 struct replay_config {
1098 	/* Replay feature is supported */
1099 	bool replay_supported;
1100 	/* Replay caps support DPCD & EDID caps*/
1101 	bool replay_cap_support;
1102 	/* Power opt flags that are supported */
1103 	unsigned int replay_power_opt_supported;
1104 	/* SMU optimization is supported */
1105 	bool replay_smu_opt_supported;
1106 	/* Replay enablement option */
1107 	unsigned int replay_enable_option;
1108 	/* Replay debug flags */
1109 	uint32_t debug_flags;
1110 	/* Replay sync is supported */
1111 	bool replay_timing_sync_supported;
1112 	/* Replay Disable desync error check. */
1113 	bool force_disable_desync_error_check;
1114 	/* Replay Received Desync Error HPD. */
1115 	bool received_desync_error_hpd;
1116 	/* Replay feature is supported long vblank */
1117 	bool replay_support_fast_resync_in_ultra_sleep_mode;
1118 	/* Replay error status */
1119 	union replay_error_status replay_error_status;
1120 	/* Replay Low Hz enable Options */
1121 	union replay_low_refresh_rate_enable_options low_rr_enable_options;
1122 	/* Replay coasting vtotal is within low refresh rate range. */
1123 	bool low_rr_activated;
1124 };
1125 
1126 /* Replay feature flags*/
1127 struct replay_settings {
1128 	/* Replay configuration */
1129 	struct replay_config config;
1130 	/* Replay feature is ready for activating */
1131 	bool replay_feature_enabled;
1132 	/* Replay is currently active */
1133 	bool replay_allow_active;
1134 	/* Replay is currently active */
1135 	bool replay_allow_long_vblank;
1136 	/* Power opt flags that are activated currently */
1137 	unsigned int replay_power_opt_active;
1138 	/* SMU optimization is enabled */
1139 	bool replay_smu_opt_enable;
1140 	/* Current Coasting vtotal */
1141 	uint32_t coasting_vtotal;
1142 	/* Coasting vtotal table */
1143 	uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM];
1144 	/* Defer Update Coasting vtotal table */
1145 	uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM];
1146 	/* Maximum link off frame count */
1147 	uint32_t link_off_frame_count;
1148 	/* Replay pseudo vtotal for low refresh rate*/
1149 	uint16_t low_rr_full_screen_video_pseudo_vtotal;
1150 	/* Replay last pseudo vtotal set to DMUB */
1151 	uint16_t last_pseudo_vtotal;
1152 	/* Replay desync error */
1153 	uint32_t replay_desync_error_fail_count;
1154 };
1155 
1156 /* To split out "global" and "per-panel" config settings.
1157  * Add a struct dc_panel_config under dc_link
1158  */
1159 struct dc_panel_config {
1160 	/* extra panel power sequence parameters */
1161 	struct pps {
1162 		unsigned int extra_t3_ms;
1163 		unsigned int extra_t7_ms;
1164 		unsigned int extra_delay_backlight_off;
1165 		unsigned int extra_post_t7_ms;
1166 		unsigned int extra_pre_t11_ms;
1167 		unsigned int extra_t12_ms;
1168 		unsigned int extra_post_OUI_ms;
1169 	} pps;
1170 	/* nit brightness */
1171 	struct nits_brightness {
1172 		unsigned int peak; /* nits */
1173 		unsigned int max_avg; /* nits */
1174 		unsigned int min; /* 1/10000 nits */
1175 		unsigned int max_nonboost_brightness_millinits;
1176 		unsigned int min_brightness_millinits;
1177 	} nits_brightness;
1178 	/* PSR */
1179 	struct psr {
1180 		bool disable_psr;
1181 		bool disallow_psrsu;
1182 		bool disallow_replay;
1183 		bool rc_disable;
1184 		bool rc_allow_static_screen;
1185 		bool rc_allow_fullscreen_VPB;
1186 		unsigned int replay_enable_option;
1187 	} psr;
1188 	/* ABM */
1189 	struct varib {
1190 		unsigned int varibright_feature_enable;
1191 		unsigned int def_varibright_level;
1192 		unsigned int abm_config_setting;
1193 	} varib;
1194 	/* edp DSC */
1195 	struct dsc {
1196 		bool disable_dsc_edp;
1197 		unsigned int force_dsc_edp_policy;
1198 	} dsc;
1199 	/* eDP ILR */
1200 	struct ilr {
1201 		bool optimize_edp_link_rate; /* eDP ILR */
1202 	} ilr;
1203 };
1204 
1205 #define MAX_SINKS_PER_LINK 4
1206 
1207 /*
1208  *  USB4 DPIA BW ALLOCATION STRUCTS
1209  */
1210 struct dc_dpia_bw_alloc {
1211 	int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks
1212 	int link_verified_bw;  // The Verified BW that link can allocated and use that has been verified already
1213 	int link_max_bw;       // The Max BW that link can require/support
1214 	int allocated_bw;      // The Actual Allocated BW for this DPIA
1215 	int estimated_bw;      // The estimated available BW for this DPIA
1216 	int bw_granularity;    // BW Granularity
1217 	int dp_overhead;       // DP overhead in dp tunneling
1218 	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx & Dpia & CM
1219 	bool response_ready;   // Response ready from the CM side
1220 	uint8_t nrd_max_lane_count; // Non-reduced max lane count
1221 	uint8_t nrd_max_link_rate; // Non-reduced max link rate
1222 };
1223 
1224 enum dc_hpd_enable_select {
1225 	HPD_EN_FOR_ALL_EDP = 0,
1226 	HPD_EN_FOR_PRIMARY_EDP_ONLY,
1227 	HPD_EN_FOR_SECONDARY_EDP_ONLY,
1228 };
1229 
1230 enum dc_cm2_shaper_3dlut_setting {
1231 	DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL,
1232 	DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER,
1233 	/* Bypassing Shaper will always bypass 3DLUT */
1234 	DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT
1235 };
1236 
1237 enum dc_cm2_gpu_mem_layout {
1238 	DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB,
1239 	DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR,
1240 	DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR
1241 };
1242 
1243 enum dc_cm2_gpu_mem_pixel_component_order {
1244 	DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,
1245 };
1246 
1247 enum dc_cm2_gpu_mem_format {
1248 	DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB,
1249 	DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB,
1250 	DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10
1251 };
1252 
1253 struct dc_cm2_gpu_mem_format_parameters {
1254 	enum dc_cm2_gpu_mem_format format;
1255 	union {
1256 		struct {
1257 			/* bias & scale for float only */
1258 			uint16_t bias;
1259 			uint16_t scale;
1260 		} float_params;
1261 	};
1262 };
1263 
1264 enum dc_cm2_gpu_mem_size {
1265 	DC_CM2_GPU_MEM_SIZE_171717,
1266 	DC_CM2_GPU_MEM_SIZE_TRANSFORMED
1267 };
1268 
1269 struct dc_cm2_gpu_mem_parameters {
1270 	struct dc_plane_address addr;
1271 	enum dc_cm2_gpu_mem_layout layout;
1272 	struct dc_cm2_gpu_mem_format_parameters format_params;
1273 	enum dc_cm2_gpu_mem_pixel_component_order component_order;
1274 	enum dc_cm2_gpu_mem_size  size;
1275 };
1276 
1277 enum dc_cm2_transfer_func_source {
1278 	DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM,
1279 	DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM
1280 };
1281 
1282 struct dc_cm2_component_settings {
1283 	enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting;
1284 	bool lut1d_enable;
1285 };
1286 
1287 /*
1288  * All pointers in this struct must remain valid for as long as the 3DLUTs are used
1289  */
1290 struct dc_cm2_func_luts {
1291 	const struct dc_transfer_func *shaper;
1292 	struct {
1293 		enum dc_cm2_transfer_func_source lut3d_src;
1294 		union {
1295 			const struct dc_3dlut *lut3d_func;
1296 			struct dc_cm2_gpu_mem_parameters gpu_mem_params;
1297 		};
1298 	} lut3d_data;
1299 	const struct dc_transfer_func *lut1d_func;
1300 };
1301 
1302 struct dc_cm2_parameters {
1303 	struct dc_cm2_component_settings component_settings;
1304 	struct dc_cm2_func_luts cm2_luts;
1305 };
1306 
1307 enum mall_stream_type {
1308 	SUBVP_NONE, // subvp not in use
1309 	SUBVP_MAIN, // subvp in use, this stream is main stream
1310 	SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
1311 };
1312 
1313 enum dc_power_source_type {
1314 	DC_POWER_SOURCE_AC, // wall power
1315 	DC_POWER_SOURCE_DC, // battery power
1316 };
1317 
1318 struct dc_state_create_params {
1319 	enum dc_power_source_type power_source;
1320 };
1321 
1322 struct dc_commit_streams_params {
1323 	struct dc_stream_state **streams;
1324 	uint8_t stream_count;
1325 	enum dc_power_source_type power_source;
1326 };
1327 
1328 struct set_backlight_level_params {
1329 	/* backlight in pwm */
1330 	uint32_t backlight_pwm_u16_16;
1331 	/* brightness ramping */
1332 	uint32_t frame_ramp;
1333 	/* backlight control type
1334 	 * 0: PWM backlight control
1335 	 * 1: VESA AUX backlight control
1336 	 * 2: AMD AUX backlight control
1337 	 */
1338 	enum backlight_control_type control_type;
1339 	/* backlight in millinits */
1340 	uint32_t backlight_millinits;
1341 	/* transition time in ms */
1342 	uint32_t transition_time_in_ms;
1343 	/* minimum luminance in nits */
1344 	uint32_t min_luminance;
1345 	/* maximum luminance in nits */
1346 	uint32_t max_luminance;
1347 	/* minimum backlight in pwm */
1348 	uint32_t min_backlight_pwm;
1349 	/* maximum backlight in pwm */
1350 	uint32_t max_backlight_pwm;
1351 	/* AUX HW instance */
1352 	uint8_t aux_inst;
1353 };
1354 
1355 #endif /* DC_TYPES_H_ */
1356