1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2025 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_AX210_UCODE_API_MAX 89 14 15 /* Lowest firmware API version supported */ 16 #define IWL_AX210_UCODE_API_MIN 89 17 18 /* Memory offsets and lengths */ 19 #define IWL_AX210_SMEM_OFFSET 0x400000 20 #define IWL_AX210_SMEM_LEN 0xD0000 21 22 static const struct iwl_family_base_params iwl_ax210_base = { 23 .num_of_queues = 512, 24 .max_tfd_queue_size = 65536, 25 .shadow_ram_support = true, 26 .led_compensation = 57, 27 .wd_timeout = IWL_LONG_WD_TIMEOUT, 28 .max_event_log_size = 512, 29 .shadow_reg_enable = true, 30 .pcie_l1_allowed = true, 31 .smem_offset = IWL_AX210_SMEM_OFFSET, 32 .smem_len = IWL_AX210_SMEM_LEN, 33 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 34 .apmg_not_supported = true, 35 .mac_addr_from_csr = 0x380, 36 .min_umac_error_event_table = 0x400000, 37 .d3_debug_data_base_addr = 0x401000, 38 .d3_debug_data_length = 60 * 1024, 39 .mon_smem_regs = { 40 .write_ptr = { 41 .addr = LDBG_M2S_BUF_WPTR, 42 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 43 }, 44 .cycle_cnt = { 45 .addr = LDBG_M2S_BUF_WRAP_CNT, 46 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 47 }, 48 }, 49 .min_txq_size = 128, 50 .gp2_reg_addr = 0xd02c68, 51 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, 52 .mon_dram_regs = { 53 .write_ptr = { 54 .addr = DBGC_CUR_DBGBUF_STATUS, 55 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 56 }, 57 .cycle_cnt = { 58 .addr = DBGC_DBGBUF_WRAP_AROUND, 59 .mask = 0xffffffff, 60 }, 61 .cur_frag = { 62 .addr = DBGC_CUR_DBGBUF_STATUS, 63 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 64 }, 65 }, 66 .ucode_api_min = IWL_AX210_UCODE_API_MIN, 67 .ucode_api_max = IWL_AX210_UCODE_API_MAX, 68 }; 69 70 const struct iwl_mac_cfg iwl_ty_mac_cfg = { 71 .mq_rx_supported = true, 72 .gen2 = true, 73 .device_family = IWL_DEVICE_FAMILY_AX210, 74 .base = &iwl_ax210_base, 75 .umac_prph_offset = 0x300000, 76 /* TODO: the following values need to be checked */ 77 .xtal_latency = 500, 78 }; 79 80 const struct iwl_mac_cfg iwl_so_mac_cfg = { 81 .mq_rx_supported = true, 82 .gen2 = true, 83 .device_family = IWL_DEVICE_FAMILY_AX210, 84 .base = &iwl_ax210_base, 85 .umac_prph_offset = 0x300000, 86 .integrated = true, 87 /* TODO: the following values need to be checked */ 88 .xtal_latency = 500, 89 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 90 }; 91 92 const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg = { 93 .mq_rx_supported = true, 94 .gen2 = true, 95 .device_family = IWL_DEVICE_FAMILY_AX210, 96 .base = &iwl_ax210_base, 97 .umac_prph_offset = 0x300000, 98 .integrated = true, 99 .low_latency_xtal = true, 100 .xtal_latency = 12000, 101 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 102 }; 103 104 const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg = { 105 .mq_rx_supported = true, 106 .gen2 = true, 107 .device_family = IWL_DEVICE_FAMILY_AX210, 108 .base = &iwl_ax210_base, 109 .umac_prph_offset = 0x300000, 110 .integrated = true, 111 .low_latency_xtal = true, 112 .xtal_latency = 12000, 113 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 114 .imr_enabled = true, 115 }; 116 117 const struct iwl_mac_cfg iwl_ma_mac_cfg = { 118 .device_family = IWL_DEVICE_FAMILY_AX210, 119 .base = &iwl_ax210_base, 120 .mq_rx_supported = true, 121 .gen2 = true, 122 .integrated = true, 123 .umac_prph_offset = 0x300000 124 }; 125