1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-tegra/gpio.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Erik Gilling <konkers@google.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/module.h> 21 #include <linux/irqdomain.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 #include <linux/property.h> 26 #include <linux/seq_file.h> 27 28 #define GPIO_BANK(x) ((x) >> 5) 29 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 30 #define GPIO_BIT(x) ((x) & 0x7) 31 32 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ 33 GPIO_PORT(x) * 4) 34 35 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) 36 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) 37 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) 38 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) 39 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) 40 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) 41 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) 42 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) 43 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) 44 45 46 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) 47 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) 48 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) 49 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) 50 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) 51 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) 52 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) 53 54 #define GPIO_INT_LVL_MASK 0x010101 55 #define GPIO_INT_LVL_EDGE_RISING 0x000101 56 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 57 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 58 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 59 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 60 61 struct tegra_gpio_info; 62 63 struct tegra_gpio_bank { 64 unsigned int bank; 65 66 /* 67 * IRQ-core code uses raw locking, and thus, nested locking also 68 * should be raw in order not to trip spinlock debug warnings. 69 */ 70 raw_spinlock_t lvl_lock[4]; 71 72 /* Lock for updating debounce count register */ 73 spinlock_t dbc_lock[4]; 74 75 #ifdef CONFIG_PM_SLEEP 76 u32 cnf[4]; 77 u32 out[4]; 78 u32 oe[4]; 79 u32 int_enb[4]; 80 u32 int_lvl[4]; 81 u32 wake_enb[4]; 82 u32 dbc_enb[4]; 83 #endif 84 u32 dbc_cnt[4]; 85 }; 86 87 struct tegra_gpio_soc_config { 88 bool debounce_supported; 89 u32 bank_stride; 90 u32 upper_offset; 91 }; 92 93 struct tegra_gpio_info { 94 struct device *dev; 95 void __iomem *regs; 96 struct tegra_gpio_bank *bank_info; 97 const struct tegra_gpio_soc_config *soc; 98 struct gpio_chip gc; 99 u32 bank_count; 100 unsigned int *irqs; 101 }; 102 103 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, 104 u32 val, u32 reg) 105 { 106 writel_relaxed(val, tgi->regs + reg); 107 } 108 109 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) 110 { 111 return readl_relaxed(tgi->regs + reg); 112 } 113 114 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, 115 unsigned int bit) 116 { 117 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 118 } 119 120 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, 121 unsigned int gpio, u32 value) 122 { 123 u32 val; 124 125 val = 0x100 << GPIO_BIT(gpio); 126 if (value) 127 val |= 1 << GPIO_BIT(gpio); 128 tegra_gpio_writel(tgi, val, reg); 129 } 130 131 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) 132 { 133 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); 134 } 135 136 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) 137 { 138 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); 139 } 140 141 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 142 { 143 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 144 145 pinctrl_gpio_free(chip, offset); 146 tegra_gpio_disable(tgi, offset); 147 } 148 149 static int tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, 150 int value) 151 { 152 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 153 154 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); 155 156 return 0; 157 } 158 159 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) 160 { 161 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 162 unsigned int bval = BIT(GPIO_BIT(offset)); 163 164 /* If gpio is in output mode then read from the out value */ 165 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) 166 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); 167 168 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); 169 } 170 171 static int tegra_gpio_direction_input(struct gpio_chip *chip, 172 unsigned int offset) 173 { 174 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 175 176 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); 177 tegra_gpio_enable(tgi, offset); 178 179 return 0; 180 } 181 182 static int tegra_gpio_direction_output(struct gpio_chip *chip, 183 unsigned int offset, 184 int value) 185 { 186 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 187 188 tegra_gpio_set(chip, offset, value); 189 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); 190 tegra_gpio_enable(tgi, offset); 191 192 return 0; 193 } 194 195 static int tegra_gpio_get_direction(struct gpio_chip *chip, 196 unsigned int offset) 197 { 198 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 199 u32 pin_mask = BIT(GPIO_BIT(offset)); 200 u32 cnf, oe; 201 202 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); 203 if (!(cnf & pin_mask)) 204 return -EINVAL; 205 206 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); 207 208 if (oe & pin_mask) 209 return GPIO_LINE_DIRECTION_OUT; 210 211 return GPIO_LINE_DIRECTION_IN; 212 } 213 214 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 215 unsigned int debounce) 216 { 217 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 218 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; 219 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); 220 unsigned long flags; 221 unsigned int port; 222 223 if (!debounce_ms) { 224 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), 225 offset, 0); 226 return 0; 227 } 228 229 debounce_ms = min(debounce_ms, 255U); 230 port = GPIO_PORT(offset); 231 232 /* There is only one debounce count register per port and hence 233 * set the maximum of current and requested debounce time. 234 */ 235 spin_lock_irqsave(&bank->dbc_lock[port], flags); 236 if (bank->dbc_cnt[port] < debounce_ms) { 237 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); 238 bank->dbc_cnt[port] = debounce_ms; 239 } 240 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); 241 242 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); 243 244 return 0; 245 } 246 247 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 248 unsigned long config) 249 { 250 u32 debounce; 251 252 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 253 return -ENOTSUPP; 254 255 debounce = pinconf_to_config_argument(config); 256 return tegra_gpio_set_debounce(chip, offset, debounce); 257 } 258 259 static void tegra_gpio_irq_ack(struct irq_data *d) 260 { 261 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 262 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 263 unsigned int gpio = d->hwirq; 264 265 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); 266 } 267 268 static void tegra_gpio_irq_mask(struct irq_data *d) 269 { 270 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 271 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 272 unsigned int gpio = d->hwirq; 273 274 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); 275 gpiochip_disable_irq(chip, gpio); 276 } 277 278 static void tegra_gpio_irq_unmask(struct irq_data *d) 279 { 280 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 281 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 282 unsigned int gpio = d->hwirq; 283 284 gpiochip_enable_irq(chip, gpio); 285 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); 286 } 287 288 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 289 { 290 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; 291 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 292 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 293 struct tegra_gpio_bank *bank; 294 unsigned long flags; 295 int ret; 296 u32 val; 297 298 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; 299 300 switch (type & IRQ_TYPE_SENSE_MASK) { 301 case IRQ_TYPE_EDGE_RISING: 302 lvl_type = GPIO_INT_LVL_EDGE_RISING; 303 break; 304 305 case IRQ_TYPE_EDGE_FALLING: 306 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 307 break; 308 309 case IRQ_TYPE_EDGE_BOTH: 310 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 311 break; 312 313 case IRQ_TYPE_LEVEL_HIGH: 314 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 315 break; 316 317 case IRQ_TYPE_LEVEL_LOW: 318 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 319 break; 320 321 default: 322 return -EINVAL; 323 } 324 325 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); 326 327 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 328 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 329 val |= lvl_type << GPIO_BIT(gpio); 330 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); 331 332 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 333 334 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); 335 tegra_gpio_enable(tgi, gpio); 336 337 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); 338 if (ret) { 339 dev_err(tgi->dev, 340 "unable to lock Tegra GPIO %u as IRQ\n", gpio); 341 tegra_gpio_disable(tgi, gpio); 342 return ret; 343 } 344 345 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 346 irq_set_handler_locked(d, handle_level_irq); 347 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 348 irq_set_handler_locked(d, handle_edge_irq); 349 350 if (d->parent_data) 351 ret = irq_chip_set_type_parent(d, type); 352 353 return ret; 354 } 355 356 static void tegra_gpio_irq_shutdown(struct irq_data *d) 357 { 358 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 359 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 360 unsigned int gpio = d->hwirq; 361 362 tegra_gpio_irq_mask(d); 363 gpiochip_unlock_as_irq(&tgi->gc, gpio); 364 } 365 366 static void tegra_gpio_irq_handler(struct irq_desc *desc) 367 { 368 struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc); 369 struct irq_chip *chip = irq_desc_get_chip(desc); 370 struct irq_domain *domain = tgi->gc.irq.domain; 371 unsigned int irq = irq_desc_get_irq(desc); 372 struct tegra_gpio_bank *bank = NULL; 373 unsigned int port, pin, gpio, i; 374 bool unmasked = false; 375 unsigned long sta; 376 u32 lvl; 377 378 for (i = 0; i < tgi->bank_count; i++) { 379 if (tgi->irqs[i] == irq) { 380 bank = &tgi->bank_info[i]; 381 break; 382 } 383 } 384 385 if (WARN_ON(bank == NULL)) 386 return; 387 388 chained_irq_enter(chip, desc); 389 390 for (port = 0; port < 4; port++) { 391 gpio = tegra_gpio_compose(bank->bank, port, 0); 392 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & 393 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); 394 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); 395 396 for_each_set_bit(pin, &sta, 8) { 397 int ret; 398 399 tegra_gpio_writel(tgi, 1 << pin, 400 GPIO_INT_CLR(tgi, gpio)); 401 402 /* if gpio is edge triggered, clear condition 403 * before executing the handler so that we don't 404 * miss edges 405 */ 406 if (!unmasked && lvl & (0x100 << pin)) { 407 unmasked = true; 408 chained_irq_exit(chip, desc); 409 } 410 411 ret = generic_handle_domain_irq(domain, gpio + pin); 412 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin); 413 } 414 } 415 416 if (!unmasked) 417 chained_irq_exit(chip, desc); 418 } 419 420 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 421 unsigned int hwirq, 422 unsigned int type, 423 unsigned int *parent_hwirq, 424 unsigned int *parent_type) 425 { 426 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 427 *parent_type = type; 428 429 return 0; 430 } 431 432 static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip, 433 union gpio_irq_fwspec *gfwspec, 434 unsigned int parent_hwirq, 435 unsigned int parent_type) 436 { 437 struct irq_fwspec *fwspec = &gfwspec->fwspec; 438 439 fwspec->fwnode = chip->irq.parent_domain->fwnode; 440 fwspec->param_count = 3; 441 fwspec->param[0] = 0; 442 fwspec->param[1] = parent_hwirq; 443 fwspec->param[2] = parent_type; 444 445 return 0; 446 } 447 448 #ifdef CONFIG_PM_SLEEP 449 static int tegra_gpio_resume(struct device *dev) 450 { 451 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 452 unsigned int b, p; 453 454 for (b = 0; b < tgi->bank_count; b++) { 455 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 456 457 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 458 unsigned int gpio = (b << 5) | (p << 3); 459 460 tegra_gpio_writel(tgi, bank->cnf[p], 461 GPIO_CNF(tgi, gpio)); 462 463 if (tgi->soc->debounce_supported) { 464 tegra_gpio_writel(tgi, bank->dbc_cnt[p], 465 GPIO_DBC_CNT(tgi, gpio)); 466 tegra_gpio_writel(tgi, bank->dbc_enb[p], 467 GPIO_MSK_DBC_EN(tgi, gpio)); 468 } 469 470 tegra_gpio_writel(tgi, bank->out[p], 471 GPIO_OUT(tgi, gpio)); 472 tegra_gpio_writel(tgi, bank->oe[p], 473 GPIO_OE(tgi, gpio)); 474 tegra_gpio_writel(tgi, bank->int_lvl[p], 475 GPIO_INT_LVL(tgi, gpio)); 476 tegra_gpio_writel(tgi, bank->int_enb[p], 477 GPIO_INT_ENB(tgi, gpio)); 478 } 479 } 480 481 return 0; 482 } 483 484 static int tegra_gpio_suspend(struct device *dev) 485 { 486 struct tegra_gpio_info *tgi = dev_get_drvdata(dev); 487 unsigned int b, p; 488 489 for (b = 0; b < tgi->bank_count; b++) { 490 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; 491 492 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 493 unsigned int gpio = (b << 5) | (p << 3); 494 495 bank->cnf[p] = tegra_gpio_readl(tgi, 496 GPIO_CNF(tgi, gpio)); 497 bank->out[p] = tegra_gpio_readl(tgi, 498 GPIO_OUT(tgi, gpio)); 499 bank->oe[p] = tegra_gpio_readl(tgi, 500 GPIO_OE(tgi, gpio)); 501 if (tgi->soc->debounce_supported) { 502 bank->dbc_enb[p] = tegra_gpio_readl(tgi, 503 GPIO_MSK_DBC_EN(tgi, gpio)); 504 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | 505 bank->dbc_enb[p]; 506 } 507 508 bank->int_enb[p] = tegra_gpio_readl(tgi, 509 GPIO_INT_ENB(tgi, gpio)); 510 bank->int_lvl[p] = tegra_gpio_readl(tgi, 511 GPIO_INT_LVL(tgi, gpio)); 512 513 /* Enable gpio irq for wake up source */ 514 tegra_gpio_writel(tgi, bank->wake_enb[p], 515 GPIO_INT_ENB(tgi, gpio)); 516 } 517 } 518 519 return 0; 520 } 521 522 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 523 { 524 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 525 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 526 struct tegra_gpio_bank *bank; 527 unsigned int gpio = d->hwirq; 528 u32 port, bit, mask; 529 int err; 530 531 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; 532 533 port = GPIO_PORT(gpio); 534 bit = GPIO_BIT(gpio); 535 mask = BIT(bit); 536 537 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable); 538 if (err) 539 return err; 540 541 if (d->parent_data) { 542 err = irq_chip_set_wake_parent(d, enable); 543 if (err) { 544 irq_set_irq_wake(tgi->irqs[bank->bank], !enable); 545 return err; 546 } 547 } 548 549 if (enable) 550 bank->wake_enb[port] |= mask; 551 else 552 bank->wake_enb[port] &= ~mask; 553 554 return 0; 555 } 556 #endif 557 558 static int tegra_gpio_irq_set_affinity(struct irq_data *data, 559 const struct cpumask *dest, 560 bool force) 561 { 562 if (data->parent_data) 563 return irq_chip_set_affinity_parent(data, dest, force); 564 565 return -EINVAL; 566 } 567 568 static int tegra_gpio_irq_request_resources(struct irq_data *d) 569 { 570 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 571 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 572 573 tegra_gpio_enable(tgi, d->hwirq); 574 575 return gpiochip_reqres_irq(chip, d->hwirq); 576 } 577 578 static void tegra_gpio_irq_release_resources(struct irq_data *d) 579 { 580 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 581 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 582 583 gpiochip_relres_irq(chip, d->hwirq); 584 tegra_gpio_disable(tgi, d->hwirq); 585 } 586 587 static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s) 588 { 589 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 590 591 seq_puts(s, dev_name(chip->parent)); 592 } 593 594 static const struct irq_chip tegra_gpio_irq_chip = { 595 .irq_shutdown = tegra_gpio_irq_shutdown, 596 .irq_ack = tegra_gpio_irq_ack, 597 .irq_mask = tegra_gpio_irq_mask, 598 .irq_unmask = tegra_gpio_irq_unmask, 599 .irq_set_type = tegra_gpio_irq_set_type, 600 #ifdef CONFIG_PM_SLEEP 601 .irq_set_wake = tegra_gpio_irq_set_wake, 602 #endif 603 .irq_print_chip = tegra_gpio_irq_print_chip, 604 .irq_request_resources = tegra_gpio_irq_request_resources, 605 .irq_release_resources = tegra_gpio_irq_release_resources, 606 .flags = IRQCHIP_IMMUTABLE, 607 }; 608 609 static const struct irq_chip tegra210_gpio_irq_chip = { 610 .irq_shutdown = tegra_gpio_irq_shutdown, 611 .irq_ack = tegra_gpio_irq_ack, 612 .irq_mask = tegra_gpio_irq_mask, 613 .irq_unmask = tegra_gpio_irq_unmask, 614 .irq_set_affinity = tegra_gpio_irq_set_affinity, 615 .irq_set_type = tegra_gpio_irq_set_type, 616 #ifdef CONFIG_PM_SLEEP 617 .irq_set_wake = tegra_gpio_irq_set_wake, 618 #endif 619 .irq_print_chip = tegra_gpio_irq_print_chip, 620 .irq_request_resources = tegra_gpio_irq_request_resources, 621 .irq_release_resources = tegra_gpio_irq_release_resources, 622 .flags = IRQCHIP_IMMUTABLE, 623 }; 624 625 #ifdef CONFIG_DEBUG_FS 626 627 #include <linux/debugfs.h> 628 629 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) 630 { 631 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private); 632 unsigned int i, j; 633 634 for (i = 0; i < tgi->bank_count; i++) { 635 for (j = 0; j < 4; j++) { 636 unsigned int gpio = tegra_gpio_compose(i, j, 0); 637 638 seq_printf(s, 639 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", 640 i, j, 641 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), 642 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), 643 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), 644 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), 645 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), 646 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), 647 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); 648 } 649 } 650 return 0; 651 } 652 653 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 654 { 655 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL, 656 tegra_dbg_gpio_show); 657 } 658 659 #else 660 661 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) 662 { 663 } 664 665 #endif 666 667 static const struct dev_pm_ops tegra_gpio_pm_ops = { 668 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 669 }; 670 671 static const struct of_device_id tegra_pmc_of_match[] = { 672 { .compatible = "nvidia,tegra210-pmc", }, 673 { /* sentinel */ }, 674 }; 675 676 static int tegra_gpio_probe(struct platform_device *pdev) 677 { 678 struct tegra_gpio_bank *bank; 679 struct tegra_gpio_info *tgi; 680 struct gpio_irq_chip *irq; 681 struct device_node *np; 682 unsigned int i, j; 683 int ret; 684 685 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); 686 if (!tgi) 687 return -ENOMEM; 688 689 tgi->soc = of_device_get_match_data(&pdev->dev); 690 tgi->dev = &pdev->dev; 691 692 ret = platform_irq_count(pdev); 693 if (ret < 0) 694 return ret; 695 696 tgi->bank_count = ret; 697 698 if (!tgi->bank_count) { 699 dev_err(&pdev->dev, "Missing IRQ resource\n"); 700 return -ENODEV; 701 } 702 703 tgi->gc.label = "tegra-gpio"; 704 tgi->gc.request = pinctrl_gpio_request; 705 tgi->gc.free = tegra_gpio_free; 706 tgi->gc.direction_input = tegra_gpio_direction_input; 707 tgi->gc.get = tegra_gpio_get; 708 tgi->gc.direction_output = tegra_gpio_direction_output; 709 tgi->gc.set = tegra_gpio_set; 710 tgi->gc.get_direction = tegra_gpio_get_direction; 711 tgi->gc.base = 0; 712 tgi->gc.ngpio = tgi->bank_count * 32; 713 tgi->gc.parent = &pdev->dev; 714 715 platform_set_drvdata(pdev, tgi); 716 717 if (tgi->soc->debounce_supported) 718 tgi->gc.set_config = tegra_gpio_set_config; 719 720 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, 721 sizeof(*tgi->bank_info), GFP_KERNEL); 722 if (!tgi->bank_info) 723 return -ENOMEM; 724 725 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count, 726 sizeof(*tgi->irqs), GFP_KERNEL); 727 if (!tgi->irqs) 728 return -ENOMEM; 729 730 for (i = 0; i < tgi->bank_count; i++) { 731 ret = platform_get_irq(pdev, i); 732 if (ret < 0) 733 return ret; 734 735 bank = &tgi->bank_info[i]; 736 bank->bank = i; 737 738 tgi->irqs[i] = ret; 739 740 for (j = 0; j < 4; j++) { 741 raw_spin_lock_init(&bank->lvl_lock[j]); 742 spin_lock_init(&bank->dbc_lock[j]); 743 } 744 } 745 746 irq = &tgi->gc.irq; 747 irq->fwnode = dev_fwnode(&pdev->dev); 748 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq; 749 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec; 750 irq->handler = handle_simple_irq; 751 irq->default_type = IRQ_TYPE_NONE; 752 irq->parent_handler = tegra_gpio_irq_handler; 753 irq->parent_handler_data = tgi; 754 irq->num_parents = tgi->bank_count; 755 irq->parents = tgi->irqs; 756 757 np = of_find_matching_node(NULL, tegra_pmc_of_match); 758 if (np) { 759 irq->parent_domain = irq_find_host(np); 760 of_node_put(np); 761 762 if (!irq->parent_domain) 763 return -EPROBE_DEFER; 764 765 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip); 766 } else { 767 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip); 768 } 769 770 tgi->regs = devm_platform_ioremap_resource(pdev, 0); 771 if (IS_ERR(tgi->regs)) 772 return PTR_ERR(tgi->regs); 773 774 for (i = 0; i < tgi->bank_count; i++) { 775 for (j = 0; j < 4; j++) { 776 int gpio = tegra_gpio_compose(i, j, 0); 777 778 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); 779 } 780 } 781 782 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); 783 if (ret < 0) 784 return ret; 785 786 tegra_gpio_debuginit(tgi); 787 788 return 0; 789 } 790 791 static const struct tegra_gpio_soc_config tegra20_gpio_config = { 792 .bank_stride = 0x80, 793 .upper_offset = 0x800, 794 }; 795 796 static const struct tegra_gpio_soc_config tegra30_gpio_config = { 797 .bank_stride = 0x100, 798 .upper_offset = 0x80, 799 }; 800 801 static const struct tegra_gpio_soc_config tegra210_gpio_config = { 802 .debounce_supported = true, 803 .bank_stride = 0x100, 804 .upper_offset = 0x80, 805 }; 806 807 static const struct of_device_id tegra_gpio_of_match[] = { 808 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, 809 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 810 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 811 { }, 812 }; 813 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match); 814 815 static struct platform_driver tegra_gpio_driver = { 816 .driver = { 817 .name = "tegra-gpio", 818 .pm = &tegra_gpio_pm_ops, 819 .of_match_table = tegra_gpio_of_match, 820 }, 821 .probe = tegra_gpio_probe, 822 }; 823 module_platform_driver(tegra_gpio_driver); 824 825 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver"); 826 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 827 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 828 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 829 MODULE_AUTHOR("Erik Gilling <konkers@google.com>"); 830 MODULE_LICENSE("GPL v2"); 831