1 // SPDX-License-Identifier: GPL-2.0
2 // CAN bus driver for Bosch M_CAN controller
3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
4 // Dong Aisheng <aisheng.dong@nxp.com>
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6
7 /* Bosch M_CAN user manual can be obtained from:
8 * https://github.com/linux-can/can-doc/tree/master/m_can
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/can/dev.h>
13 #include <linux/ethtool.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26
27 #include "m_can.h"
28
29 /* registers definition */
30 enum m_can_reg {
31 M_CAN_CREL = 0x0,
32 M_CAN_ENDN = 0x4,
33 M_CAN_CUST = 0x8,
34 M_CAN_DBTP = 0xc,
35 M_CAN_TEST = 0x10,
36 M_CAN_RWD = 0x14,
37 M_CAN_CCCR = 0x18,
38 M_CAN_NBTP = 0x1c,
39 M_CAN_TSCC = 0x20,
40 M_CAN_TSCV = 0x24,
41 M_CAN_TOCC = 0x28,
42 M_CAN_TOCV = 0x2c,
43 M_CAN_ECR = 0x40,
44 M_CAN_PSR = 0x44,
45 /* TDCR Register only available for version >=3.1.x */
46 M_CAN_TDCR = 0x48,
47 M_CAN_IR = 0x50,
48 M_CAN_IE = 0x54,
49 M_CAN_ILS = 0x58,
50 M_CAN_ILE = 0x5c,
51 M_CAN_GFC = 0x80,
52 M_CAN_SIDFC = 0x84,
53 M_CAN_XIDFC = 0x88,
54 M_CAN_XIDAM = 0x90,
55 M_CAN_HPMS = 0x94,
56 M_CAN_NDAT1 = 0x98,
57 M_CAN_NDAT2 = 0x9c,
58 M_CAN_RXF0C = 0xa0,
59 M_CAN_RXF0S = 0xa4,
60 M_CAN_RXF0A = 0xa8,
61 M_CAN_RXBC = 0xac,
62 M_CAN_RXF1C = 0xb0,
63 M_CAN_RXF1S = 0xb4,
64 M_CAN_RXF1A = 0xb8,
65 M_CAN_RXESC = 0xbc,
66 M_CAN_TXBC = 0xc0,
67 M_CAN_TXFQS = 0xc4,
68 M_CAN_TXESC = 0xc8,
69 M_CAN_TXBRP = 0xcc,
70 M_CAN_TXBAR = 0xd0,
71 M_CAN_TXBCR = 0xd4,
72 M_CAN_TXBTO = 0xd8,
73 M_CAN_TXBCF = 0xdc,
74 M_CAN_TXBTIE = 0xe0,
75 M_CAN_TXBCIE = 0xe4,
76 M_CAN_TXEFC = 0xf0,
77 M_CAN_TXEFS = 0xf4,
78 M_CAN_TXEFA = 0xf8,
79 };
80
81 /* message ram configuration data length */
82 #define MRAM_CFG_LEN 8
83
84 /* Core Release Register (CREL) */
85 #define CREL_REL_MASK GENMASK(31, 28)
86 #define CREL_STEP_MASK GENMASK(27, 24)
87 #define CREL_SUBSTEP_MASK GENMASK(23, 20)
88
89 /* Data Bit Timing & Prescaler Register (DBTP) */
90 #define DBTP_TDC BIT(23)
91 #define DBTP_DBRP_MASK GENMASK(20, 16)
92 #define DBTP_DTSEG1_MASK GENMASK(12, 8)
93 #define DBTP_DTSEG2_MASK GENMASK(7, 4)
94 #define DBTP_DSJW_MASK GENMASK(3, 0)
95
96 /* Transmitter Delay Compensation Register (TDCR) */
97 #define TDCR_TDCO_MASK GENMASK(14, 8)
98 #define TDCR_TDCF_MASK GENMASK(6, 0)
99
100 /* Test Register (TEST) */
101 #define TEST_LBCK BIT(4)
102
103 /* CC Control Register (CCCR) */
104 #define CCCR_TXP BIT(14)
105 #define CCCR_TEST BIT(7)
106 #define CCCR_DAR BIT(6)
107 #define CCCR_MON BIT(5)
108 #define CCCR_CSR BIT(4)
109 #define CCCR_CSA BIT(3)
110 #define CCCR_ASM BIT(2)
111 #define CCCR_CCE BIT(1)
112 #define CCCR_INIT BIT(0)
113 /* for version 3.0.x */
114 #define CCCR_CMR_MASK GENMASK(11, 10)
115 #define CCCR_CMR_CANFD 0x1
116 #define CCCR_CMR_CANFD_BRS 0x2
117 #define CCCR_CMR_CAN 0x3
118 #define CCCR_CME_MASK GENMASK(9, 8)
119 #define CCCR_CME_CAN 0
120 #define CCCR_CME_CANFD 0x1
121 #define CCCR_CME_CANFD_BRS 0x2
122 /* for version >=3.1.x */
123 #define CCCR_EFBI BIT(13)
124 #define CCCR_PXHD BIT(12)
125 #define CCCR_BRSE BIT(9)
126 #define CCCR_FDOE BIT(8)
127 /* for version >=3.2.x */
128 #define CCCR_NISO BIT(15)
129 /* for version >=3.3.x */
130 #define CCCR_WMM BIT(11)
131 #define CCCR_UTSU BIT(10)
132
133 /* Nominal Bit Timing & Prescaler Register (NBTP) */
134 #define NBTP_NSJW_MASK GENMASK(31, 25)
135 #define NBTP_NBRP_MASK GENMASK(24, 16)
136 #define NBTP_NTSEG1_MASK GENMASK(15, 8)
137 #define NBTP_NTSEG2_MASK GENMASK(6, 0)
138
139 /* Timestamp Counter Configuration Register (TSCC) */
140 #define TSCC_TCP_MASK GENMASK(19, 16)
141 #define TSCC_TSS_MASK GENMASK(1, 0)
142 #define TSCC_TSS_DISABLE 0x0
143 #define TSCC_TSS_INTERNAL 0x1
144 #define TSCC_TSS_EXTERNAL 0x2
145
146 /* Timestamp Counter Value Register (TSCV) */
147 #define TSCV_TSC_MASK GENMASK(15, 0)
148
149 /* Error Counter Register (ECR) */
150 #define ECR_RP BIT(15)
151 #define ECR_REC_MASK GENMASK(14, 8)
152 #define ECR_TEC_MASK GENMASK(7, 0)
153
154 /* Protocol Status Register (PSR) */
155 #define PSR_BO BIT(7)
156 #define PSR_EW BIT(6)
157 #define PSR_EP BIT(5)
158 #define PSR_LEC_MASK GENMASK(2, 0)
159 #define PSR_DLEC_MASK GENMASK(10, 8)
160
161 /* Interrupt Register (IR) */
162 #define IR_ALL_INT 0xffffffff
163
164 /* Renamed bits for versions > 3.1.x */
165 #define IR_ARA BIT(29)
166 #define IR_PED BIT(28)
167 #define IR_PEA BIT(27)
168
169 /* Bits for version 3.0.x */
170 #define IR_STE BIT(31)
171 #define IR_FOE BIT(30)
172 #define IR_ACKE BIT(29)
173 #define IR_BE BIT(28)
174 #define IR_CRCE BIT(27)
175 #define IR_WDI BIT(26)
176 #define IR_BO BIT(25)
177 #define IR_EW BIT(24)
178 #define IR_EP BIT(23)
179 #define IR_ELO BIT(22)
180 #define IR_BEU BIT(21)
181 #define IR_BEC BIT(20)
182 #define IR_DRX BIT(19)
183 #define IR_TOO BIT(18)
184 #define IR_MRAF BIT(17)
185 #define IR_TSW BIT(16)
186 #define IR_TEFL BIT(15)
187 #define IR_TEFF BIT(14)
188 #define IR_TEFW BIT(13)
189 #define IR_TEFN BIT(12)
190 #define IR_TFE BIT(11)
191 #define IR_TCF BIT(10)
192 #define IR_TC BIT(9)
193 #define IR_HPM BIT(8)
194 #define IR_RF1L BIT(7)
195 #define IR_RF1F BIT(6)
196 #define IR_RF1W BIT(5)
197 #define IR_RF1N BIT(4)
198 #define IR_RF0L BIT(3)
199 #define IR_RF0F BIT(2)
200 #define IR_RF0W BIT(1)
201 #define IR_RF0N BIT(0)
202 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
203
204 /* Interrupts for version 3.0.x */
205 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
206 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \
207 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
208 IR_RF0L)
209 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
210
211 /* Interrupts for version >= 3.1.x */
212 #define IR_ERR_LEC_31X (IR_PED | IR_PEA)
213 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \
214 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
215 IR_RF0L)
216 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
217
218 /* Interrupt Line Select (ILS) */
219 #define ILS_ALL_INT0 0x0
220 #define ILS_ALL_INT1 0xFFFFFFFF
221
222 /* Interrupt Line Enable (ILE) */
223 #define ILE_EINT1 BIT(1)
224 #define ILE_EINT0 BIT(0)
225
226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
227 #define RXFC_FWM_MASK GENMASK(30, 24)
228 #define RXFC_FS_MASK GENMASK(22, 16)
229
230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
231 #define RXFS_RFL BIT(25)
232 #define RXFS_FF BIT(24)
233 #define RXFS_FPI_MASK GENMASK(21, 16)
234 #define RXFS_FGI_MASK GENMASK(13, 8)
235 #define RXFS_FFL_MASK GENMASK(6, 0)
236
237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
238 #define RXESC_RBDS_MASK GENMASK(10, 8)
239 #define RXESC_F1DS_MASK GENMASK(6, 4)
240 #define RXESC_F0DS_MASK GENMASK(2, 0)
241 #define RXESC_64B 0x7
242
243 /* Tx Buffer Configuration (TXBC) */
244 #define TXBC_TFQS_MASK GENMASK(29, 24)
245 #define TXBC_NDTB_MASK GENMASK(21, 16)
246
247 /* Tx FIFO/Queue Status (TXFQS) */
248 #define TXFQS_TFQF BIT(21)
249 #define TXFQS_TFQPI_MASK GENMASK(20, 16)
250 #define TXFQS_TFGI_MASK GENMASK(12, 8)
251 #define TXFQS_TFFL_MASK GENMASK(5, 0)
252
253 /* Tx Buffer Element Size Configuration (TXESC) */
254 #define TXESC_TBDS_MASK GENMASK(2, 0)
255 #define TXESC_TBDS_64B 0x7
256
257 /* Tx Event FIFO Configuration (TXEFC) */
258 #define TXEFC_EFWM_MASK GENMASK(29, 24)
259 #define TXEFC_EFS_MASK GENMASK(21, 16)
260
261 /* Tx Event FIFO Status (TXEFS) */
262 #define TXEFS_TEFL BIT(25)
263 #define TXEFS_EFF BIT(24)
264 #define TXEFS_EFGI_MASK GENMASK(12, 8)
265 #define TXEFS_EFFL_MASK GENMASK(5, 0)
266
267 /* Tx Event FIFO Acknowledge (TXEFA) */
268 #define TXEFA_EFAI_MASK GENMASK(4, 0)
269
270 /* Message RAM Configuration (in bytes) */
271 #define SIDF_ELEMENT_SIZE 4
272 #define XIDF_ELEMENT_SIZE 8
273 #define RXF0_ELEMENT_SIZE 72
274 #define RXF1_ELEMENT_SIZE 72
275 #define RXB_ELEMENT_SIZE 72
276 #define TXE_ELEMENT_SIZE 8
277 #define TXB_ELEMENT_SIZE 72
278
279 /* Message RAM Elements */
280 #define M_CAN_FIFO_ID 0x0
281 #define M_CAN_FIFO_DLC 0x4
282 #define M_CAN_FIFO_DATA 0x8
283
284 /* Rx Buffer Element */
285 /* R0 */
286 #define RX_BUF_ESI BIT(31)
287 #define RX_BUF_XTD BIT(30)
288 #define RX_BUF_RTR BIT(29)
289 /* R1 */
290 #define RX_BUF_ANMF BIT(31)
291 #define RX_BUF_FDF BIT(21)
292 #define RX_BUF_BRS BIT(20)
293 #define RX_BUF_RXTS_MASK GENMASK(15, 0)
294
295 /* Tx Buffer Element */
296 /* T0 */
297 #define TX_BUF_ESI BIT(31)
298 #define TX_BUF_XTD BIT(30)
299 #define TX_BUF_RTR BIT(29)
300 /* T1 */
301 #define TX_BUF_EFC BIT(23)
302 #define TX_BUF_FDF BIT(21)
303 #define TX_BUF_BRS BIT(20)
304 #define TX_BUF_MM_MASK GENMASK(31, 24)
305 #define TX_BUF_DLC_MASK GENMASK(19, 16)
306
307 /* Tx event FIFO Element */
308 /* E1 */
309 #define TX_EVENT_MM_MASK GENMASK(31, 24)
310 #define TX_EVENT_TXTS_MASK GENMASK(15, 0)
311
312 /* Hrtimer polling interval */
313 #define HRTIMER_POLL_INTERVAL_MS 1
314
315 /* The ID and DLC registers are adjacent in M_CAN FIFO memory,
316 * and we can save a (potentially slow) bus round trip by combining
317 * reads and writes to them.
318 */
319 struct id_and_dlc {
320 u32 id;
321 u32 dlc;
322 };
323
324 struct m_can_fifo_element {
325 u32 id;
326 u32 dlc;
327 u8 data[CANFD_MAX_DLEN];
328 };
329
m_can_read(struct m_can_classdev * cdev,enum m_can_reg reg)330 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
331 {
332 return cdev->ops->read_reg(cdev, reg);
333 }
334
m_can_write(struct m_can_classdev * cdev,enum m_can_reg reg,u32 val)335 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
336 u32 val)
337 {
338 cdev->ops->write_reg(cdev, reg, val);
339 }
340
341 static int
m_can_fifo_read(struct m_can_classdev * cdev,u32 fgi,unsigned int offset,void * val,size_t val_count)342 m_can_fifo_read(struct m_can_classdev *cdev,
343 u32 fgi, unsigned int offset, void *val, size_t val_count)
344 {
345 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
346 offset;
347
348 if (val_count == 0)
349 return 0;
350
351 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
352 }
353
354 static int
m_can_fifo_write(struct m_can_classdev * cdev,u32 fpi,unsigned int offset,const void * val,size_t val_count)355 m_can_fifo_write(struct m_can_classdev *cdev,
356 u32 fpi, unsigned int offset, const void *val, size_t val_count)
357 {
358 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
359 offset;
360
361 if (val_count == 0)
362 return 0;
363
364 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
365 }
366
m_can_fifo_write_no_off(struct m_can_classdev * cdev,u32 fpi,u32 val)367 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
368 u32 fpi, u32 val)
369 {
370 return cdev->ops->write_fifo(cdev, fpi, &val, 1);
371 }
372
373 static int
m_can_txe_fifo_read(struct m_can_classdev * cdev,u32 fgi,u32 offset,u32 * val)374 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
375 {
376 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
377 offset;
378
379 return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
380 }
381
m_can_cccr_update_bits(struct m_can_classdev * cdev,u32 mask,u32 val)382 static int m_can_cccr_update_bits(struct m_can_classdev *cdev, u32 mask, u32 val)
383 {
384 u32 val_before = m_can_read(cdev, M_CAN_CCCR);
385 u32 val_after = (val_before & ~mask) | val;
386 size_t tries = 10;
387
388 if (!(mask & CCCR_INIT) && !(val_before & CCCR_INIT)) {
389 dev_err(cdev->dev,
390 "refusing to configure device when in normal mode\n");
391 return -EBUSY;
392 }
393
394 /* The chip should be in standby mode when changing the CCCR register,
395 * and some chips set the CSR and CSA bits when in standby. Furthermore,
396 * the CSR and CSA bits should be written as zeros, even when they read
397 * ones.
398 */
399 val_after &= ~(CCCR_CSR | CCCR_CSA);
400
401 while (tries--) {
402 u32 val_read;
403
404 /* Write the desired value in each try, as setting some bits in
405 * the CCCR register require other bits to be set first. E.g.
406 * setting the NISO bit requires setting the CCE bit first.
407 */
408 m_can_write(cdev, M_CAN_CCCR, val_after);
409
410 val_read = m_can_read(cdev, M_CAN_CCCR) & ~(CCCR_CSR | CCCR_CSA);
411
412 if (val_read == val_after)
413 return 0;
414
415 usleep_range(1, 5);
416 }
417
418 return -ETIMEDOUT;
419 }
420
m_can_config_enable(struct m_can_classdev * cdev)421 static int m_can_config_enable(struct m_can_classdev *cdev)
422 {
423 int err;
424
425 /* CCCR_INIT must be set in order to set CCCR_CCE, but access to
426 * configuration registers should only be enabled when in standby mode,
427 * where CCCR_INIT is always set.
428 */
429 err = m_can_cccr_update_bits(cdev, CCCR_CCE, CCCR_CCE);
430 if (err)
431 netdev_err(cdev->net, "failed to enable configuration mode\n");
432
433 return err;
434 }
435
m_can_config_disable(struct m_can_classdev * cdev)436 static int m_can_config_disable(struct m_can_classdev *cdev)
437 {
438 int err;
439
440 /* Only clear CCCR_CCE, since CCCR_INIT cannot be cleared while in
441 * standby mode
442 */
443 err = m_can_cccr_update_bits(cdev, CCCR_CCE, 0);
444 if (err)
445 netdev_err(cdev->net, "failed to disable configuration registers\n");
446
447 return err;
448 }
449
m_can_interrupt_enable(struct m_can_classdev * cdev,u32 interrupts)450 static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts)
451 {
452 if (cdev->active_interrupts == interrupts)
453 return;
454 cdev->ops->write_reg(cdev, M_CAN_IE, interrupts);
455 cdev->active_interrupts = interrupts;
456 }
457
m_can_coalescing_disable(struct m_can_classdev * cdev)458 static void m_can_coalescing_disable(struct m_can_classdev *cdev)
459 {
460 u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN;
461
462 if (!cdev->net->irq)
463 return;
464
465 hrtimer_cancel(&cdev->hrtimer);
466 m_can_interrupt_enable(cdev, new_interrupts);
467 }
468
m_can_enable_all_interrupts(struct m_can_classdev * cdev)469 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
470 {
471 if (!cdev->net->irq) {
472 dev_dbg(cdev->dev, "Start hrtimer\n");
473 hrtimer_start(&cdev->hrtimer,
474 ms_to_ktime(HRTIMER_POLL_INTERVAL_MS),
475 HRTIMER_MODE_REL_PINNED);
476 }
477
478 /* Only interrupt line 0 is used in this driver */
479 m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
480 }
481
m_can_disable_all_interrupts(struct m_can_classdev * cdev)482 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
483 {
484 m_can_coalescing_disable(cdev);
485 m_can_write(cdev, M_CAN_ILE, 0x0);
486
487 if (!cdev->net->irq) {
488 dev_dbg(cdev->dev, "Stop hrtimer\n");
489 hrtimer_try_to_cancel(&cdev->hrtimer);
490 }
491 }
492
493 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit
494 * width.
495 */
m_can_get_timestamp(struct m_can_classdev * cdev)496 static u32 m_can_get_timestamp(struct m_can_classdev *cdev)
497 {
498 u32 tscv;
499 u32 tsc;
500
501 tscv = m_can_read(cdev, M_CAN_TSCV);
502 tsc = FIELD_GET(TSCV_TSC_MASK, tscv);
503
504 return (tsc << 16);
505 }
506
m_can_clean(struct net_device * net)507 static void m_can_clean(struct net_device *net)
508 {
509 struct m_can_classdev *cdev = netdev_priv(net);
510 unsigned long irqflags;
511
512 if (cdev->tx_ops) {
513 for (int i = 0; i != cdev->tx_fifo_size; ++i) {
514 if (!cdev->tx_ops[i].skb)
515 continue;
516
517 net->stats.tx_errors++;
518 cdev->tx_ops[i].skb = NULL;
519 }
520 }
521
522 for (int i = 0; i != cdev->can.echo_skb_max; ++i)
523 can_free_echo_skb(cdev->net, i, NULL);
524
525 netdev_reset_queue(cdev->net);
526
527 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
528 cdev->tx_fifo_in_flight = 0;
529 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
530 }
531
532 /* For peripherals, pass skb to rx-offload, which will push skb from
533 * napi. For non-peripherals, RX is done in napi already, so push
534 * directly. timestamp is used to ensure good skb ordering in
535 * rx-offload and is ignored for non-peripherals.
536 */
m_can_receive_skb(struct m_can_classdev * cdev,struct sk_buff * skb,u32 timestamp)537 static void m_can_receive_skb(struct m_can_classdev *cdev,
538 struct sk_buff *skb,
539 u32 timestamp)
540 {
541 if (cdev->is_peripheral) {
542 struct net_device_stats *stats = &cdev->net->stats;
543 int err;
544
545 err = can_rx_offload_queue_timestamp(&cdev->offload, skb,
546 timestamp);
547 if (err)
548 stats->rx_fifo_errors++;
549 } else {
550 netif_receive_skb(skb);
551 }
552 }
553
m_can_read_fifo(struct net_device * dev,u32 fgi)554 static int m_can_read_fifo(struct net_device *dev, u32 fgi)
555 {
556 struct net_device_stats *stats = &dev->stats;
557 struct m_can_classdev *cdev = netdev_priv(dev);
558 struct canfd_frame *cf;
559 struct sk_buff *skb;
560 struct id_and_dlc fifo_header;
561 u32 timestamp = 0;
562 int err;
563
564 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2);
565 if (err)
566 goto out_fail;
567
568 if (fifo_header.dlc & RX_BUF_FDF)
569 skb = alloc_canfd_skb(dev, &cf);
570 else
571 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
572 if (!skb) {
573 stats->rx_dropped++;
574 return 0;
575 }
576
577 if (fifo_header.dlc & RX_BUF_FDF)
578 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F);
579 else
580 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F);
581
582 if (fifo_header.id & RX_BUF_XTD)
583 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG;
584 else
585 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK;
586
587 if (fifo_header.id & RX_BUF_ESI) {
588 cf->flags |= CANFD_ESI;
589 netdev_dbg(dev, "ESI Error\n");
590 }
591
592 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) {
593 cf->can_id |= CAN_RTR_FLAG;
594 } else {
595 if (fifo_header.dlc & RX_BUF_BRS)
596 cf->flags |= CANFD_BRS;
597
598 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA,
599 cf->data, DIV_ROUND_UP(cf->len, 4));
600 if (err)
601 goto out_free_skb;
602
603 stats->rx_bytes += cf->len;
604 }
605 stats->rx_packets++;
606
607 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16;
608
609 m_can_receive_skb(cdev, skb, timestamp);
610
611 return 0;
612
613 out_free_skb:
614 kfree_skb(skb);
615 out_fail:
616 netdev_err(dev, "FIFO read returned %d\n", err);
617 return err;
618 }
619
m_can_do_rx_poll(struct net_device * dev,int quota)620 static int m_can_do_rx_poll(struct net_device *dev, int quota)
621 {
622 struct m_can_classdev *cdev = netdev_priv(dev);
623 u32 pkts = 0;
624 u32 rxfs;
625 u32 rx_count;
626 u32 fgi;
627 int ack_fgi = -1;
628 int i;
629 int err = 0;
630
631 rxfs = m_can_read(cdev, M_CAN_RXF0S);
632 if (!(rxfs & RXFS_FFL_MASK)) {
633 netdev_dbg(dev, "no messages in fifo0\n");
634 return 0;
635 }
636
637 rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs);
638 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
639
640 for (i = 0; i < rx_count && quota > 0; ++i) {
641 err = m_can_read_fifo(dev, fgi);
642 if (err)
643 break;
644
645 quota--;
646 pkts++;
647 ack_fgi = fgi;
648 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi);
649 }
650
651 if (ack_fgi != -1)
652 m_can_write(cdev, M_CAN_RXF0A, ack_fgi);
653
654 if (err)
655 return err;
656
657 return pkts;
658 }
659
m_can_handle_lost_msg(struct net_device * dev)660 static int m_can_handle_lost_msg(struct net_device *dev)
661 {
662 struct m_can_classdev *cdev = netdev_priv(dev);
663 struct net_device_stats *stats = &dev->stats;
664 struct sk_buff *skb;
665 struct can_frame *frame;
666 u32 timestamp = 0;
667
668 netdev_dbg(dev, "msg lost in rxf0\n");
669
670 stats->rx_errors++;
671 stats->rx_over_errors++;
672
673 skb = alloc_can_err_skb(dev, &frame);
674 if (unlikely(!skb))
675 return 0;
676
677 frame->can_id |= CAN_ERR_CRTL;
678 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
679
680 if (cdev->is_peripheral)
681 timestamp = m_can_get_timestamp(cdev);
682
683 m_can_receive_skb(cdev, skb, timestamp);
684
685 return 1;
686 }
687
m_can_handle_lec_err(struct net_device * dev,enum m_can_lec_type lec_type)688 static int m_can_handle_lec_err(struct net_device *dev,
689 enum m_can_lec_type lec_type)
690 {
691 struct m_can_classdev *cdev = netdev_priv(dev);
692 struct net_device_stats *stats = &dev->stats;
693 struct can_frame *cf;
694 struct sk_buff *skb;
695 u32 timestamp = 0;
696
697 cdev->can.can_stats.bus_error++;
698
699 /* propagate the error condition to the CAN stack */
700 skb = alloc_can_err_skb(dev, &cf);
701
702 /* check for 'last error code' which tells us the
703 * type of the last error to occur on the CAN bus
704 */
705 if (likely(skb))
706 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
707
708 switch (lec_type) {
709 case LEC_STUFF_ERROR:
710 netdev_dbg(dev, "stuff error\n");
711 stats->rx_errors++;
712 if (likely(skb))
713 cf->data[2] |= CAN_ERR_PROT_STUFF;
714 break;
715 case LEC_FORM_ERROR:
716 netdev_dbg(dev, "form error\n");
717 stats->rx_errors++;
718 if (likely(skb))
719 cf->data[2] |= CAN_ERR_PROT_FORM;
720 break;
721 case LEC_ACK_ERROR:
722 netdev_dbg(dev, "ack error\n");
723 stats->tx_errors++;
724 if (likely(skb))
725 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
726 break;
727 case LEC_BIT1_ERROR:
728 netdev_dbg(dev, "bit1 error\n");
729 stats->tx_errors++;
730 if (likely(skb))
731 cf->data[2] |= CAN_ERR_PROT_BIT1;
732 break;
733 case LEC_BIT0_ERROR:
734 netdev_dbg(dev, "bit0 error\n");
735 stats->tx_errors++;
736 if (likely(skb))
737 cf->data[2] |= CAN_ERR_PROT_BIT0;
738 break;
739 case LEC_CRC_ERROR:
740 netdev_dbg(dev, "CRC error\n");
741 stats->rx_errors++;
742 if (likely(skb))
743 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
744 break;
745 default:
746 break;
747 }
748
749 if (unlikely(!skb))
750 return 0;
751
752 if (cdev->is_peripheral)
753 timestamp = m_can_get_timestamp(cdev);
754
755 m_can_receive_skb(cdev, skb, timestamp);
756
757 return 1;
758 }
759
__m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)760 static int __m_can_get_berr_counter(const struct net_device *dev,
761 struct can_berr_counter *bec)
762 {
763 struct m_can_classdev *cdev = netdev_priv(dev);
764 unsigned int ecr;
765
766 ecr = m_can_read(cdev, M_CAN_ECR);
767 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
768 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
769
770 return 0;
771 }
772
m_can_clk_start(struct m_can_classdev * cdev)773 static int m_can_clk_start(struct m_can_classdev *cdev)
774 {
775 if (cdev->pm_clock_support == 0)
776 return 0;
777
778 return pm_runtime_resume_and_get(cdev->dev);
779 }
780
m_can_clk_stop(struct m_can_classdev * cdev)781 static void m_can_clk_stop(struct m_can_classdev *cdev)
782 {
783 if (cdev->pm_clock_support)
784 pm_runtime_put_sync(cdev->dev);
785 }
786
m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)787 static int m_can_get_berr_counter(const struct net_device *dev,
788 struct can_berr_counter *bec)
789 {
790 struct m_can_classdev *cdev = netdev_priv(dev);
791 int err;
792
793 err = m_can_clk_start(cdev);
794 if (err)
795 return err;
796
797 __m_can_get_berr_counter(dev, bec);
798
799 m_can_clk_stop(cdev);
800
801 return 0;
802 }
803
m_can_handle_state_change(struct net_device * dev,enum can_state new_state)804 static int m_can_handle_state_change(struct net_device *dev,
805 enum can_state new_state)
806 {
807 struct m_can_classdev *cdev = netdev_priv(dev);
808 struct can_frame *cf;
809 struct sk_buff *skb;
810 struct can_berr_counter bec;
811 unsigned int ecr;
812 u32 timestamp = 0;
813
814 switch (new_state) {
815 case CAN_STATE_ERROR_ACTIVE:
816 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
817 break;
818 case CAN_STATE_ERROR_WARNING:
819 /* error warning state */
820 cdev->can.can_stats.error_warning++;
821 cdev->can.state = CAN_STATE_ERROR_WARNING;
822 break;
823 case CAN_STATE_ERROR_PASSIVE:
824 /* error passive state */
825 cdev->can.can_stats.error_passive++;
826 cdev->can.state = CAN_STATE_ERROR_PASSIVE;
827 break;
828 case CAN_STATE_BUS_OFF:
829 /* bus-off state */
830 cdev->can.state = CAN_STATE_BUS_OFF;
831 m_can_disable_all_interrupts(cdev);
832 cdev->can.can_stats.bus_off++;
833 can_bus_off(dev);
834 break;
835 default:
836 break;
837 }
838
839 /* propagate the error condition to the CAN stack */
840 skb = alloc_can_err_skb(dev, &cf);
841 if (unlikely(!skb))
842 return 0;
843
844 __m_can_get_berr_counter(dev, &bec);
845
846 switch (new_state) {
847 case CAN_STATE_ERROR_ACTIVE:
848 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
849 cf->data[1] = CAN_ERR_CRTL_ACTIVE;
850 cf->data[6] = bec.txerr;
851 cf->data[7] = bec.rxerr;
852 break;
853 case CAN_STATE_ERROR_WARNING:
854 /* error warning state */
855 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
856 cf->data[1] = (bec.txerr > bec.rxerr) ?
857 CAN_ERR_CRTL_TX_WARNING :
858 CAN_ERR_CRTL_RX_WARNING;
859 cf->data[6] = bec.txerr;
860 cf->data[7] = bec.rxerr;
861 break;
862 case CAN_STATE_ERROR_PASSIVE:
863 /* error passive state */
864 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
865 ecr = m_can_read(cdev, M_CAN_ECR);
866 if (ecr & ECR_RP)
867 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
868 if (bec.txerr > 127)
869 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
870 cf->data[6] = bec.txerr;
871 cf->data[7] = bec.rxerr;
872 break;
873 case CAN_STATE_BUS_OFF:
874 /* bus-off state */
875 cf->can_id |= CAN_ERR_BUSOFF;
876 break;
877 default:
878 break;
879 }
880
881 if (cdev->is_peripheral)
882 timestamp = m_can_get_timestamp(cdev);
883
884 m_can_receive_skb(cdev, skb, timestamp);
885
886 return 1;
887 }
888
889 static enum can_state
m_can_state_get_by_psr(struct m_can_classdev * cdev)890 m_can_state_get_by_psr(struct m_can_classdev *cdev)
891 {
892 u32 reg_psr;
893
894 reg_psr = m_can_read(cdev, M_CAN_PSR);
895
896 if (reg_psr & PSR_BO)
897 return CAN_STATE_BUS_OFF;
898 if (reg_psr & PSR_EP)
899 return CAN_STATE_ERROR_PASSIVE;
900 if (reg_psr & PSR_EW)
901 return CAN_STATE_ERROR_WARNING;
902
903 return CAN_STATE_ERROR_ACTIVE;
904 }
905
m_can_handle_state_errors(struct net_device * dev)906 static int m_can_handle_state_errors(struct net_device *dev)
907 {
908 struct m_can_classdev *cdev = netdev_priv(dev);
909 enum can_state new_state;
910
911 new_state = m_can_state_get_by_psr(cdev);
912 if (new_state == cdev->can.state)
913 return 0;
914
915 return m_can_handle_state_change(dev, new_state);
916 }
917
m_can_handle_other_err(struct net_device * dev,u32 irqstatus)918 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
919 {
920 if (irqstatus & IR_WDI)
921 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
922 if (irqstatus & IR_BEU)
923 netdev_err(dev, "Bit Error Uncorrected\n");
924 if (irqstatus & IR_BEC)
925 netdev_err(dev, "Bit Error Corrected\n");
926 if (irqstatus & IR_TOO)
927 netdev_err(dev, "Timeout reached\n");
928 if (irqstatus & IR_MRAF)
929 netdev_err(dev, "Message RAM access failure occurred\n");
930 }
931
is_lec_err(u8 lec)932 static inline bool is_lec_err(u8 lec)
933 {
934 return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE;
935 }
936
m_can_is_protocol_err(u32 irqstatus)937 static inline bool m_can_is_protocol_err(u32 irqstatus)
938 {
939 return irqstatus & IR_ERR_LEC_31X;
940 }
941
m_can_handle_protocol_error(struct net_device * dev,u32 irqstatus)942 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
943 {
944 struct net_device_stats *stats = &dev->stats;
945 struct m_can_classdev *cdev = netdev_priv(dev);
946 struct can_frame *cf;
947 struct sk_buff *skb;
948 u32 timestamp = 0;
949
950 /* propagate the error condition to the CAN stack */
951 skb = alloc_can_err_skb(dev, &cf);
952
953 /* update tx error stats since there is protocol error */
954 stats->tx_errors++;
955
956 /* update arbitration lost status */
957 if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
958 netdev_dbg(dev, "Protocol error in Arbitration fail\n");
959 cdev->can.can_stats.arbitration_lost++;
960 if (skb) {
961 cf->can_id |= CAN_ERR_LOSTARB;
962 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
963 }
964 }
965
966 if (unlikely(!skb)) {
967 netdev_dbg(dev, "allocation of skb failed\n");
968 return 0;
969 }
970
971 if (cdev->is_peripheral)
972 timestamp = m_can_get_timestamp(cdev);
973
974 m_can_receive_skb(cdev, skb, timestamp);
975
976 return 1;
977 }
978
m_can_handle_bus_errors(struct net_device * dev,u32 irqstatus,u32 psr)979 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
980 u32 psr)
981 {
982 struct m_can_classdev *cdev = netdev_priv(dev);
983 int work_done = 0;
984
985 if (irqstatus & IR_RF0L)
986 work_done += m_can_handle_lost_msg(dev);
987
988 /* handle lec errors on the bus */
989 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
990 u8 lec = FIELD_GET(PSR_LEC_MASK, psr);
991 u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr);
992
993 if (is_lec_err(lec)) {
994 netdev_dbg(dev, "Arbitration phase error detected\n");
995 work_done += m_can_handle_lec_err(dev, lec);
996 }
997
998 if (is_lec_err(dlec)) {
999 netdev_dbg(dev, "Data phase error detected\n");
1000 work_done += m_can_handle_lec_err(dev, dlec);
1001 }
1002 }
1003
1004 /* handle protocol errors in arbitration phase */
1005 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
1006 m_can_is_protocol_err(irqstatus))
1007 work_done += m_can_handle_protocol_error(dev, irqstatus);
1008
1009 /* other unproccessed error interrupts */
1010 m_can_handle_other_err(dev, irqstatus);
1011
1012 return work_done;
1013 }
1014
m_can_rx_handler(struct net_device * dev,int quota,u32 irqstatus)1015 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus)
1016 {
1017 struct m_can_classdev *cdev = netdev_priv(dev);
1018 int rx_work_or_err;
1019 int work_done = 0;
1020
1021 if (!irqstatus)
1022 goto end;
1023
1024 /* Errata workaround for issue "Needless activation of MRAF irq"
1025 * During frame reception while the MCAN is in Error Passive state
1026 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
1027 * it may happen that MCAN_IR.MRAF is set although there was no
1028 * Message RAM access failure.
1029 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
1030 * The Message RAM Access Failure interrupt routine needs to check
1031 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
1032 * In this case, reset MCAN_IR.MRAF. No further action is required.
1033 */
1034 if (cdev->version <= 31 && irqstatus & IR_MRAF &&
1035 m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
1036 struct can_berr_counter bec;
1037
1038 __m_can_get_berr_counter(dev, &bec);
1039 if (bec.rxerr == 127) {
1040 m_can_write(cdev, M_CAN_IR, IR_MRAF);
1041 irqstatus &= ~IR_MRAF;
1042 }
1043 }
1044
1045 if (irqstatus & IR_ERR_STATE)
1046 work_done += m_can_handle_state_errors(dev);
1047
1048 if (irqstatus & IR_ERR_BUS_30X)
1049 work_done += m_can_handle_bus_errors(dev, irqstatus,
1050 m_can_read(cdev, M_CAN_PSR));
1051
1052 if (irqstatus & IR_RF0N) {
1053 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done));
1054 if (rx_work_or_err < 0)
1055 return rx_work_or_err;
1056
1057 work_done += rx_work_or_err;
1058 }
1059 end:
1060 return work_done;
1061 }
1062
m_can_poll(struct napi_struct * napi,int quota)1063 static int m_can_poll(struct napi_struct *napi, int quota)
1064 {
1065 struct net_device *dev = napi->dev;
1066 struct m_can_classdev *cdev = netdev_priv(dev);
1067 int work_done;
1068 u32 irqstatus;
1069
1070 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
1071
1072 work_done = m_can_rx_handler(dev, quota, irqstatus);
1073
1074 /* Don't re-enable interrupts if the driver had a fatal error
1075 * (e.g., FIFO read failure).
1076 */
1077 if (work_done >= 0 && work_done < quota) {
1078 napi_complete_done(napi, work_done);
1079 m_can_enable_all_interrupts(cdev);
1080 }
1081
1082 return work_done;
1083 }
1084
1085 /* Echo tx skb and update net stats. Peripherals use rx-offload for
1086 * echo. timestamp is used for peripherals to ensure correct ordering
1087 * by rx-offload, and is ignored for non-peripherals.
1088 */
m_can_tx_update_stats(struct m_can_classdev * cdev,unsigned int msg_mark,u32 timestamp)1089 static unsigned int m_can_tx_update_stats(struct m_can_classdev *cdev,
1090 unsigned int msg_mark, u32 timestamp)
1091 {
1092 struct net_device *dev = cdev->net;
1093 struct net_device_stats *stats = &dev->stats;
1094 unsigned int frame_len;
1095
1096 if (cdev->is_peripheral)
1097 stats->tx_bytes +=
1098 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload,
1099 msg_mark,
1100 timestamp,
1101 &frame_len);
1102 else
1103 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, &frame_len);
1104
1105 stats->tx_packets++;
1106
1107 return frame_len;
1108 }
1109
m_can_finish_tx(struct m_can_classdev * cdev,int transmitted,unsigned int transmitted_frame_len)1110 static void m_can_finish_tx(struct m_can_classdev *cdev, int transmitted,
1111 unsigned int transmitted_frame_len)
1112 {
1113 unsigned long irqflags;
1114
1115 netdev_completed_queue(cdev->net, transmitted, transmitted_frame_len);
1116
1117 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1118 if (cdev->tx_fifo_in_flight >= cdev->tx_fifo_size && transmitted > 0)
1119 netif_wake_queue(cdev->net);
1120 cdev->tx_fifo_in_flight -= transmitted;
1121 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1122 }
1123
m_can_start_tx(struct m_can_classdev * cdev)1124 static netdev_tx_t m_can_start_tx(struct m_can_classdev *cdev)
1125 {
1126 unsigned long irqflags;
1127 int tx_fifo_in_flight;
1128
1129 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1130 tx_fifo_in_flight = cdev->tx_fifo_in_flight + 1;
1131 if (tx_fifo_in_flight >= cdev->tx_fifo_size) {
1132 netif_stop_queue(cdev->net);
1133 if (tx_fifo_in_flight > cdev->tx_fifo_size) {
1134 netdev_err_once(cdev->net, "hard_xmit called while TX FIFO full\n");
1135 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1136 return NETDEV_TX_BUSY;
1137 }
1138 }
1139 cdev->tx_fifo_in_flight = tx_fifo_in_flight;
1140 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1141
1142 return NETDEV_TX_OK;
1143 }
1144
m_can_echo_tx_event(struct net_device * dev)1145 static int m_can_echo_tx_event(struct net_device *dev)
1146 {
1147 u32 txe_count = 0;
1148 u32 m_can_txefs;
1149 u32 fgi = 0;
1150 int ack_fgi = -1;
1151 int i = 0;
1152 int err = 0;
1153 unsigned int msg_mark;
1154 int processed = 0;
1155 unsigned int processed_frame_len = 0;
1156
1157 struct m_can_classdev *cdev = netdev_priv(dev);
1158
1159 /* read tx event fifo status */
1160 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
1161
1162 /* Get Tx Event fifo element count */
1163 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
1164 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs);
1165
1166 /* Get and process all sent elements */
1167 for (i = 0; i < txe_count; i++) {
1168 u32 txe, timestamp = 0;
1169
1170 /* get message marker, timestamp */
1171 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe);
1172 if (err) {
1173 netdev_err(dev, "TXE FIFO read returned %d\n", err);
1174 break;
1175 }
1176
1177 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
1178 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16;
1179
1180 ack_fgi = fgi;
1181 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi);
1182
1183 /* update stats */
1184 processed_frame_len += m_can_tx_update_stats(cdev, msg_mark,
1185 timestamp);
1186
1187 ++processed;
1188 }
1189
1190 if (ack_fgi != -1)
1191 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
1192 ack_fgi));
1193
1194 m_can_finish_tx(cdev, processed, processed_frame_len);
1195
1196 return err;
1197 }
1198
m_can_coalescing_update(struct m_can_classdev * cdev,u32 ir)1199 static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir)
1200 {
1201 u32 new_interrupts = cdev->active_interrupts;
1202 bool enable_rx_timer = false;
1203 bool enable_tx_timer = false;
1204
1205 if (!cdev->net->irq)
1206 return;
1207
1208 if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) {
1209 enable_rx_timer = true;
1210 new_interrupts &= ~IR_RF0N;
1211 }
1212 if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) {
1213 enable_tx_timer = true;
1214 new_interrupts &= ~IR_TEFN;
1215 }
1216 if (!enable_rx_timer && !hrtimer_active(&cdev->hrtimer))
1217 new_interrupts |= IR_RF0N;
1218 if (!enable_tx_timer && !hrtimer_active(&cdev->hrtimer))
1219 new_interrupts |= IR_TEFN;
1220
1221 m_can_interrupt_enable(cdev, new_interrupts);
1222 if (enable_rx_timer | enable_tx_timer)
1223 hrtimer_start(&cdev->hrtimer, cdev->irq_timer_wait,
1224 HRTIMER_MODE_REL);
1225 }
1226
1227 /* This interrupt handler is called either from the interrupt thread or a
1228 * hrtimer. This has implications like cancelling a timer won't be possible
1229 * blocking.
1230 */
m_can_interrupt_handler(struct m_can_classdev * cdev)1231 static int m_can_interrupt_handler(struct m_can_classdev *cdev)
1232 {
1233 struct net_device *dev = cdev->net;
1234 u32 ir = 0, ir_read;
1235 int ret;
1236
1237 if (pm_runtime_suspended(cdev->dev))
1238 return IRQ_NONE;
1239
1240 /* The m_can controller signals its interrupt status as a level, but
1241 * depending in the integration the CPU may interpret the signal as
1242 * edge-triggered (for example with m_can_pci). For these
1243 * edge-triggered integrations, we must observe that IR is 0 at least
1244 * once to be sure that the next interrupt will generate an edge.
1245 */
1246 while ((ir_read = m_can_read(cdev, M_CAN_IR)) != 0) {
1247 ir |= ir_read;
1248
1249 /* ACK all irqs */
1250 m_can_write(cdev, M_CAN_IR, ir);
1251
1252 if (!cdev->irq_edge_triggered)
1253 break;
1254 }
1255
1256 m_can_coalescing_update(cdev, ir);
1257 if (!ir)
1258 return IRQ_NONE;
1259
1260 if (cdev->ops->clear_interrupts)
1261 cdev->ops->clear_interrupts(cdev);
1262
1263 /* schedule NAPI in case of
1264 * - rx IRQ
1265 * - state change IRQ
1266 * - bus error IRQ and bus error reporting
1267 */
1268 if (ir & (IR_RF0N | IR_RF0W | IR_ERR_ALL_30X)) {
1269 cdev->irqstatus = ir;
1270 if (!cdev->is_peripheral) {
1271 m_can_disable_all_interrupts(cdev);
1272 napi_schedule(&cdev->napi);
1273 } else {
1274 ret = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, ir);
1275 if (ret < 0)
1276 return ret;
1277 }
1278 }
1279
1280 if (cdev->version == 30) {
1281 if (ir & IR_TC) {
1282 /* Transmission Complete Interrupt*/
1283 u32 timestamp = 0;
1284 unsigned int frame_len;
1285
1286 if (cdev->is_peripheral)
1287 timestamp = m_can_get_timestamp(cdev);
1288 frame_len = m_can_tx_update_stats(cdev, 0, timestamp);
1289 m_can_finish_tx(cdev, 1, frame_len);
1290 }
1291 } else {
1292 if (ir & (IR_TEFN | IR_TEFW)) {
1293 /* New TX FIFO Element arrived */
1294 ret = m_can_echo_tx_event(dev);
1295 if (ret != 0)
1296 return ret;
1297 }
1298 }
1299
1300 if (cdev->is_peripheral)
1301 can_rx_offload_threaded_irq_finish(&cdev->offload);
1302
1303 return IRQ_HANDLED;
1304 }
1305
m_can_isr(int irq,void * dev_id)1306 static irqreturn_t m_can_isr(int irq, void *dev_id)
1307 {
1308 struct net_device *dev = (struct net_device *)dev_id;
1309 struct m_can_classdev *cdev = netdev_priv(dev);
1310 int ret;
1311
1312 ret = m_can_interrupt_handler(cdev);
1313 if (ret < 0) {
1314 m_can_disable_all_interrupts(cdev);
1315 return IRQ_HANDLED;
1316 }
1317
1318 return ret;
1319 }
1320
m_can_coalescing_timer(struct hrtimer * timer)1321 static enum hrtimer_restart m_can_coalescing_timer(struct hrtimer *timer)
1322 {
1323 struct m_can_classdev *cdev = container_of(timer, struct m_can_classdev, hrtimer);
1324
1325 if (cdev->can.state == CAN_STATE_BUS_OFF ||
1326 cdev->can.state == CAN_STATE_STOPPED)
1327 return HRTIMER_NORESTART;
1328
1329 irq_wake_thread(cdev->net->irq, cdev->net);
1330
1331 return HRTIMER_NORESTART;
1332 }
1333
1334 static const struct can_bittiming_const m_can_bittiming_const_30X = {
1335 .name = KBUILD_MODNAME,
1336 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1337 .tseg1_max = 64,
1338 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1339 .tseg2_max = 16,
1340 .sjw_max = 16,
1341 .brp_min = 1,
1342 .brp_max = 1024,
1343 .brp_inc = 1,
1344 };
1345
1346 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
1347 .name = KBUILD_MODNAME,
1348 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1349 .tseg1_max = 16,
1350 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1351 .tseg2_max = 8,
1352 .sjw_max = 4,
1353 .brp_min = 1,
1354 .brp_max = 32,
1355 .brp_inc = 1,
1356 };
1357
1358 static const struct can_bittiming_const m_can_bittiming_const_31X = {
1359 .name = KBUILD_MODNAME,
1360 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
1361 .tseg1_max = 256,
1362 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */
1363 .tseg2_max = 128,
1364 .sjw_max = 128,
1365 .brp_min = 1,
1366 .brp_max = 512,
1367 .brp_inc = 1,
1368 };
1369
1370 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1371 .name = KBUILD_MODNAME,
1372 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1373 .tseg1_max = 32,
1374 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1375 .tseg2_max = 16,
1376 .sjw_max = 16,
1377 .brp_min = 1,
1378 .brp_max = 32,
1379 .brp_inc = 1,
1380 };
1381
m_can_set_bittiming(struct net_device * dev)1382 static int m_can_set_bittiming(struct net_device *dev)
1383 {
1384 struct m_can_classdev *cdev = netdev_priv(dev);
1385 const struct can_bittiming *bt = &cdev->can.bittiming;
1386 const struct can_bittiming *dbt = &cdev->can.fd.data_bittiming;
1387 u16 brp, sjw, tseg1, tseg2;
1388 u32 reg_btp;
1389
1390 brp = bt->brp - 1;
1391 sjw = bt->sjw - 1;
1392 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1393 tseg2 = bt->phase_seg2 - 1;
1394 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
1395 FIELD_PREP(NBTP_NSJW_MASK, sjw) |
1396 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
1397 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
1398 m_can_write(cdev, M_CAN_NBTP, reg_btp);
1399
1400 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1401 reg_btp = 0;
1402 brp = dbt->brp - 1;
1403 sjw = dbt->sjw - 1;
1404 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1405 tseg2 = dbt->phase_seg2 - 1;
1406
1407 /* TDC is only needed for bitrates beyond 2.5 MBit/s.
1408 * This is mentioned in the "Bit Time Requirements for CAN FD"
1409 * paper presented at the International CAN Conference 2013
1410 */
1411 if (dbt->bitrate > 2500000) {
1412 u32 tdco, ssp;
1413
1414 /* Use the same value of secondary sampling point
1415 * as the data sampling point
1416 */
1417 ssp = dbt->sample_point;
1418
1419 /* Equation based on Bosch's M_CAN User Manual's
1420 * Transmitter Delay Compensation Section
1421 */
1422 tdco = (cdev->can.clock.freq / 1000) *
1423 ssp / dbt->bitrate;
1424
1425 /* Max valid TDCO value is 127 */
1426 if (tdco > 127) {
1427 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1428 tdco);
1429 tdco = 127;
1430 }
1431
1432 reg_btp |= DBTP_TDC;
1433 m_can_write(cdev, M_CAN_TDCR,
1434 FIELD_PREP(TDCR_TDCO_MASK, tdco));
1435 }
1436
1437 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) |
1438 FIELD_PREP(DBTP_DSJW_MASK, sjw) |
1439 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) |
1440 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2);
1441
1442 m_can_write(cdev, M_CAN_DBTP, reg_btp);
1443 }
1444
1445 return 0;
1446 }
1447
1448 /* Configure M_CAN chip:
1449 * - set rx buffer/fifo element size
1450 * - configure rx fifo
1451 * - accept non-matching frame into fifo 0
1452 * - configure tx buffer
1453 * - >= v3.1.x: TX FIFO is used
1454 * - configure mode
1455 * - setup bittiming
1456 * - configure timestamp generation
1457 */
m_can_chip_config(struct net_device * dev)1458 static int m_can_chip_config(struct net_device *dev)
1459 {
1460 struct m_can_classdev *cdev = netdev_priv(dev);
1461 u32 interrupts = IR_ALL_INT;
1462 u32 cccr, test;
1463 int err;
1464
1465 err = m_can_init_ram(cdev);
1466 if (err) {
1467 dev_err(cdev->dev, "Message RAM configuration failed\n");
1468 return err;
1469 }
1470
1471 /* Disable unused interrupts */
1472 interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TFE | IR_TCF |
1473 IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | IR_RF0F |
1474 IR_TSW);
1475
1476 err = m_can_config_enable(cdev);
1477 if (err)
1478 return err;
1479
1480 /* RX Buffer/FIFO Element Size 64 bytes data field */
1481 m_can_write(cdev, M_CAN_RXESC,
1482 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
1483 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
1484 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
1485
1486 /* Accept Non-matching Frames Into FIFO 0 */
1487 m_can_write(cdev, M_CAN_GFC, 0x0);
1488
1489 if (cdev->version == 30) {
1490 /* only support one Tx Buffer currently */
1491 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
1492 cdev->mcfg[MRAM_TXB].off);
1493 } else {
1494 /* TX FIFO is used for newer IP Core versions */
1495 m_can_write(cdev, M_CAN_TXBC,
1496 FIELD_PREP(TXBC_TFQS_MASK,
1497 cdev->mcfg[MRAM_TXB].num) |
1498 cdev->mcfg[MRAM_TXB].off);
1499 }
1500
1501 /* support 64 bytes payload */
1502 m_can_write(cdev, M_CAN_TXESC,
1503 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
1504
1505 /* TX Event FIFO */
1506 if (cdev->version == 30) {
1507 m_can_write(cdev, M_CAN_TXEFC,
1508 FIELD_PREP(TXEFC_EFS_MASK, 1) |
1509 cdev->mcfg[MRAM_TXE].off);
1510 } else {
1511 /* Full TX Event FIFO is used */
1512 m_can_write(cdev, M_CAN_TXEFC,
1513 FIELD_PREP(TXEFC_EFWM_MASK,
1514 cdev->tx_max_coalesced_frames_irq) |
1515 FIELD_PREP(TXEFC_EFS_MASK,
1516 cdev->mcfg[MRAM_TXE].num) |
1517 cdev->mcfg[MRAM_TXE].off);
1518 }
1519
1520 /* rx fifo configuration, blocking mode, fifo size 1 */
1521 m_can_write(cdev, M_CAN_RXF0C,
1522 FIELD_PREP(RXFC_FWM_MASK, cdev->rx_max_coalesced_frames_irq) |
1523 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
1524 cdev->mcfg[MRAM_RXF0].off);
1525
1526 m_can_write(cdev, M_CAN_RXF1C,
1527 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
1528 cdev->mcfg[MRAM_RXF1].off);
1529
1530 cccr = m_can_read(cdev, M_CAN_CCCR);
1531 test = m_can_read(cdev, M_CAN_TEST);
1532 test &= ~TEST_LBCK;
1533 if (cdev->version == 30) {
1534 /* Version 3.0.x */
1535
1536 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
1537 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
1538 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
1539
1540 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1541 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
1542
1543 } else {
1544 /* Version 3.1.x or 3.2.x */
1545 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1546 CCCR_NISO | CCCR_DAR);
1547
1548 /* Only 3.2.x has NISO Bit implemented */
1549 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1550 cccr |= CCCR_NISO;
1551
1552 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1553 cccr |= (CCCR_BRSE | CCCR_FDOE);
1554 }
1555
1556 /* Loopback Mode */
1557 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1558 cccr |= CCCR_TEST | CCCR_MON;
1559 test |= TEST_LBCK;
1560 }
1561
1562 /* Enable Monitoring (all versions) */
1563 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1564 cccr |= CCCR_MON;
1565
1566 /* Disable Auto Retransmission (all versions) */
1567 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
1568 cccr |= CCCR_DAR;
1569
1570 /* Write config */
1571 m_can_write(cdev, M_CAN_CCCR, cccr);
1572 m_can_write(cdev, M_CAN_TEST, test);
1573
1574 /* Enable interrupts */
1575 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1576 if (cdev->version == 30)
1577 interrupts &= ~(IR_ERR_LEC_30X);
1578 else
1579 interrupts &= ~(IR_ERR_LEC_31X);
1580 }
1581 cdev->active_interrupts = 0;
1582 m_can_interrupt_enable(cdev, interrupts);
1583
1584 /* route all interrupts to INT0 */
1585 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1586
1587 /* set bittiming params */
1588 m_can_set_bittiming(dev);
1589
1590 /* enable internal timestamp generation, with a prescaler of 16. The
1591 * prescaler is applied to the nominal bit timing
1592 */
1593 m_can_write(cdev, M_CAN_TSCC,
1594 FIELD_PREP(TSCC_TCP_MASK, 0xf) |
1595 FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL));
1596
1597 err = m_can_config_disable(cdev);
1598 if (err)
1599 return err;
1600
1601 if (cdev->ops->init)
1602 cdev->ops->init(cdev);
1603
1604 return 0;
1605 }
1606
m_can_start(struct net_device * dev)1607 static int m_can_start(struct net_device *dev)
1608 {
1609 struct m_can_classdev *cdev = netdev_priv(dev);
1610 int ret;
1611
1612 /* basic m_can configuration */
1613 ret = m_can_chip_config(dev);
1614 if (ret)
1615 return ret;
1616
1617 netdev_queue_set_dql_min_limit(netdev_get_tx_queue(cdev->net, 0),
1618 cdev->tx_max_coalesced_frames);
1619
1620 cdev->can.state = m_can_state_get_by_psr(cdev);
1621
1622 m_can_enable_all_interrupts(cdev);
1623
1624 if (cdev->version > 30)
1625 cdev->tx_fifo_putidx = FIELD_GET(TXFQS_TFQPI_MASK,
1626 m_can_read(cdev, M_CAN_TXFQS));
1627
1628 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, 0);
1629 if (ret)
1630 netdev_err(dev, "failed to enter normal mode\n");
1631
1632 return ret;
1633 }
1634
m_can_set_mode(struct net_device * dev,enum can_mode mode)1635 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1636 {
1637 switch (mode) {
1638 case CAN_MODE_START:
1639 m_can_clean(dev);
1640 m_can_start(dev);
1641 netif_wake_queue(dev);
1642 break;
1643 default:
1644 return -EOPNOTSUPP;
1645 }
1646
1647 return 0;
1648 }
1649
1650 /* Checks core release number of M_CAN
1651 * returns 0 if an unsupported device is detected
1652 * else it returns the release and step coded as:
1653 * return value = 10 * <release> + 1 * <step>
1654 */
m_can_check_core_release(struct m_can_classdev * cdev)1655 static int m_can_check_core_release(struct m_can_classdev *cdev)
1656 {
1657 u32 crel_reg;
1658 u8 rel;
1659 u8 step;
1660 int res;
1661
1662 /* Read Core Release Version and split into version number
1663 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1664 */
1665 crel_reg = m_can_read(cdev, M_CAN_CREL);
1666 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
1667 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
1668
1669 if (rel == 3) {
1670 /* M_CAN v3.x.y: create return value */
1671 res = 30 + step;
1672 } else {
1673 /* Unsupported M_CAN version */
1674 res = 0;
1675 }
1676
1677 return res;
1678 }
1679
1680 /* Selectable Non ISO support only in version 3.2.x
1681 * Return 1 if the bit is writable, 0 if it is not, or negative on error.
1682 */
m_can_niso_supported(struct m_can_classdev * cdev)1683 static int m_can_niso_supported(struct m_can_classdev *cdev)
1684 {
1685 int ret, niso;
1686
1687 ret = m_can_config_enable(cdev);
1688 if (ret)
1689 return ret;
1690
1691 /* First try to set the NISO bit. */
1692 niso = m_can_cccr_update_bits(cdev, CCCR_NISO, CCCR_NISO);
1693
1694 /* Then clear the it again. */
1695 ret = m_can_cccr_update_bits(cdev, CCCR_NISO, 0);
1696 if (ret) {
1697 dev_err(cdev->dev, "failed to revert the NON-ISO bit in CCCR\n");
1698 return ret;
1699 }
1700
1701 ret = m_can_config_disable(cdev);
1702 if (ret)
1703 return ret;
1704
1705 return niso == 0;
1706 }
1707
m_can_dev_setup(struct m_can_classdev * cdev)1708 static int m_can_dev_setup(struct m_can_classdev *cdev)
1709 {
1710 struct net_device *dev = cdev->net;
1711 int m_can_version, err, niso;
1712
1713 m_can_version = m_can_check_core_release(cdev);
1714 /* return if unsupported version */
1715 if (!m_can_version) {
1716 dev_err(cdev->dev, "Unsupported version number: %2d",
1717 m_can_version);
1718 return -EINVAL;
1719 }
1720
1721 /* Write the INIT bit, in case no hardware reset has happened before
1722 * the probe (for example, it was observed that the Intel Elkhart Lake
1723 * SoCs do not properly reset the CAN controllers on reboot)
1724 */
1725 err = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT);
1726 if (err)
1727 return err;
1728
1729 if (!cdev->is_peripheral)
1730 netif_napi_add(dev, &cdev->napi, m_can_poll);
1731
1732 /* Shared properties of all M_CAN versions */
1733 cdev->version = m_can_version;
1734 cdev->can.do_set_mode = m_can_set_mode;
1735 cdev->can.do_get_berr_counter = m_can_get_berr_counter;
1736
1737 /* Set M_CAN supported operations */
1738 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1739 CAN_CTRLMODE_LISTENONLY |
1740 CAN_CTRLMODE_BERR_REPORTING |
1741 CAN_CTRLMODE_FD |
1742 CAN_CTRLMODE_ONE_SHOT;
1743
1744 /* Set properties depending on M_CAN version */
1745 switch (cdev->version) {
1746 case 30:
1747 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1748 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1749 if (err)
1750 return err;
1751 cdev->can.bittiming_const = &m_can_bittiming_const_30X;
1752 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_30X;
1753 break;
1754 case 31:
1755 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1756 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1757 if (err)
1758 return err;
1759 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1760 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_31X;
1761 break;
1762 case 32:
1763 case 33:
1764 /* Support both MCAN version v3.2.x and v3.3.0 */
1765 cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1766 cdev->can.fd.data_bittiming_const = &m_can_data_bittiming_const_31X;
1767
1768 niso = m_can_niso_supported(cdev);
1769 if (niso < 0)
1770 return niso;
1771 if (niso)
1772 cdev->can.ctrlmode_supported |= CAN_CTRLMODE_FD_NON_ISO;
1773 break;
1774 default:
1775 dev_err(cdev->dev, "Unsupported version number: %2d",
1776 cdev->version);
1777 return -EINVAL;
1778 }
1779
1780 return 0;
1781 }
1782
m_can_stop(struct net_device * dev)1783 static void m_can_stop(struct net_device *dev)
1784 {
1785 struct m_can_classdev *cdev = netdev_priv(dev);
1786 int ret;
1787
1788 /* disable all interrupts */
1789 m_can_disable_all_interrupts(cdev);
1790
1791 /* Set init mode to disengage from the network */
1792 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT);
1793 if (ret)
1794 netdev_err(dev, "failed to enter standby mode: %pe\n",
1795 ERR_PTR(ret));
1796
1797 /* set the state as STOPPED */
1798 cdev->can.state = CAN_STATE_STOPPED;
1799
1800 if (cdev->ops->deinit) {
1801 ret = cdev->ops->deinit(cdev);
1802 if (ret)
1803 netdev_err(dev, "failed to deinitialize: %pe\n",
1804 ERR_PTR(ret));
1805 }
1806 }
1807
m_can_close(struct net_device * dev)1808 static int m_can_close(struct net_device *dev)
1809 {
1810 struct m_can_classdev *cdev = netdev_priv(dev);
1811
1812 netif_stop_queue(dev);
1813
1814 m_can_stop(dev);
1815 if (dev->irq)
1816 free_irq(dev->irq, dev);
1817
1818 m_can_clean(dev);
1819
1820 if (cdev->is_peripheral) {
1821 destroy_workqueue(cdev->tx_wq);
1822 cdev->tx_wq = NULL;
1823 can_rx_offload_disable(&cdev->offload);
1824 } else {
1825 napi_disable(&cdev->napi);
1826 }
1827
1828 close_candev(dev);
1829
1830 m_can_clk_stop(cdev);
1831 phy_power_off(cdev->transceiver);
1832
1833 return 0;
1834 }
1835
m_can_tx_handler(struct m_can_classdev * cdev,struct sk_buff * skb)1836 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev,
1837 struct sk_buff *skb)
1838 {
1839 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1840 u8 len_padded = DIV_ROUND_UP(cf->len, 4);
1841 struct m_can_fifo_element fifo_element;
1842 struct net_device *dev = cdev->net;
1843 u32 cccr, fdflags;
1844 int err;
1845 u32 putidx;
1846 unsigned int frame_len = can_skb_get_frame_len(skb);
1847
1848 /* Generate ID field for TX buffer Element */
1849 /* Common to all supported M_CAN versions */
1850 if (cf->can_id & CAN_EFF_FLAG) {
1851 fifo_element.id = cf->can_id & CAN_EFF_MASK;
1852 fifo_element.id |= TX_BUF_XTD;
1853 } else {
1854 fifo_element.id = ((cf->can_id & CAN_SFF_MASK) << 18);
1855 }
1856
1857 if (cf->can_id & CAN_RTR_FLAG)
1858 fifo_element.id |= TX_BUF_RTR;
1859
1860 if (cdev->version == 30) {
1861 netif_stop_queue(dev);
1862
1863 fifo_element.dlc = can_fd_len2dlc(cf->len) << 16;
1864
1865 /* Write the frame ID, DLC, and payload to the FIFO element. */
1866 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_element, 2);
1867 if (err)
1868 goto out_fail;
1869
1870 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA,
1871 cf->data, len_padded);
1872 if (err)
1873 goto out_fail;
1874
1875 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1876 cccr = m_can_read(cdev, M_CAN_CCCR);
1877 cccr &= ~CCCR_CMR_MASK;
1878 if (can_is_canfd_skb(skb)) {
1879 if (cf->flags & CANFD_BRS)
1880 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1881 CCCR_CMR_CANFD_BRS);
1882 else
1883 cccr |= FIELD_PREP(CCCR_CMR_MASK,
1884 CCCR_CMR_CANFD);
1885 } else {
1886 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
1887 }
1888 m_can_write(cdev, M_CAN_CCCR, cccr);
1889 }
1890 m_can_write(cdev, M_CAN_TXBTIE, 0x1);
1891
1892 can_put_echo_skb(skb, dev, 0, frame_len);
1893
1894 m_can_write(cdev, M_CAN_TXBAR, 0x1);
1895 /* End of xmit function for version 3.0.x */
1896 } else {
1897 /* Transmit routine for version >= v3.1.x */
1898
1899 /* get put index for frame */
1900 putidx = cdev->tx_fifo_putidx;
1901
1902 /* Construct DLC Field, with CAN-FD configuration.
1903 * Use the put index of the fifo as the message marker,
1904 * used in the TX interrupt for sending the correct echo frame.
1905 */
1906
1907 /* get CAN FD configuration of frame */
1908 fdflags = 0;
1909 if (can_is_canfd_skb(skb)) {
1910 fdflags |= TX_BUF_FDF;
1911 if (cf->flags & CANFD_BRS)
1912 fdflags |= TX_BUF_BRS;
1913 }
1914
1915 fifo_element.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
1916 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
1917 fdflags | TX_BUF_EFC;
1918
1919 memcpy_and_pad(fifo_element.data, CANFD_MAX_DLEN, &cf->data,
1920 cf->len, 0);
1921
1922 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID,
1923 &fifo_element, 2 + len_padded);
1924 if (err)
1925 goto out_fail;
1926
1927 /* Push loopback echo.
1928 * Will be looped back on TX interrupt based on message marker
1929 */
1930 can_put_echo_skb(skb, dev, putidx, frame_len);
1931
1932 if (cdev->is_peripheral) {
1933 /* Delay enabling TX FIFO element */
1934 cdev->tx_peripheral_submit |= BIT(putidx);
1935 } else {
1936 /* Enable TX FIFO element to start transfer */
1937 m_can_write(cdev, M_CAN_TXBAR, BIT(putidx));
1938 }
1939 cdev->tx_fifo_putidx = (++cdev->tx_fifo_putidx >= cdev->can.echo_skb_max ?
1940 0 : cdev->tx_fifo_putidx);
1941 }
1942
1943 return NETDEV_TX_OK;
1944
1945 out_fail:
1946 netdev_err(dev, "FIFO write returned %d\n", err);
1947 m_can_disable_all_interrupts(cdev);
1948 return NETDEV_TX_BUSY;
1949 }
1950
m_can_tx_submit(struct m_can_classdev * cdev)1951 static void m_can_tx_submit(struct m_can_classdev *cdev)
1952 {
1953 if (cdev->version == 30)
1954 return;
1955 if (!cdev->is_peripheral)
1956 return;
1957
1958 m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit);
1959 cdev->tx_peripheral_submit = 0;
1960 }
1961
m_can_tx_work_queue(struct work_struct * ws)1962 static void m_can_tx_work_queue(struct work_struct *ws)
1963 {
1964 struct m_can_tx_op *op = container_of(ws, struct m_can_tx_op, work);
1965 struct m_can_classdev *cdev = op->cdev;
1966 struct sk_buff *skb = op->skb;
1967
1968 op->skb = NULL;
1969 m_can_tx_handler(cdev, skb);
1970 if (op->submit)
1971 m_can_tx_submit(cdev);
1972 }
1973
m_can_tx_queue_skb(struct m_can_classdev * cdev,struct sk_buff * skb,bool submit)1974 static void m_can_tx_queue_skb(struct m_can_classdev *cdev, struct sk_buff *skb,
1975 bool submit)
1976 {
1977 cdev->tx_ops[cdev->next_tx_op].skb = skb;
1978 cdev->tx_ops[cdev->next_tx_op].submit = submit;
1979 queue_work(cdev->tx_wq, &cdev->tx_ops[cdev->next_tx_op].work);
1980
1981 ++cdev->next_tx_op;
1982 if (cdev->next_tx_op >= cdev->tx_fifo_size)
1983 cdev->next_tx_op = 0;
1984 }
1985
m_can_start_peripheral_xmit(struct m_can_classdev * cdev,struct sk_buff * skb)1986 static netdev_tx_t m_can_start_peripheral_xmit(struct m_can_classdev *cdev,
1987 struct sk_buff *skb)
1988 {
1989 bool submit;
1990
1991 ++cdev->nr_txs_without_submit;
1992 if (cdev->nr_txs_without_submit >= cdev->tx_max_coalesced_frames ||
1993 !netdev_xmit_more()) {
1994 cdev->nr_txs_without_submit = 0;
1995 submit = true;
1996 } else {
1997 submit = false;
1998 }
1999 m_can_tx_queue_skb(cdev, skb, submit);
2000
2001 return NETDEV_TX_OK;
2002 }
2003
m_can_start_xmit(struct sk_buff * skb,struct net_device * dev)2004 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
2005 struct net_device *dev)
2006 {
2007 struct m_can_classdev *cdev = netdev_priv(dev);
2008 unsigned int frame_len;
2009 netdev_tx_t ret;
2010
2011 if (can_dev_dropped_skb(dev, skb))
2012 return NETDEV_TX_OK;
2013
2014 frame_len = can_skb_get_frame_len(skb);
2015
2016 if (cdev->can.state == CAN_STATE_BUS_OFF) {
2017 m_can_clean(cdev->net);
2018 return NETDEV_TX_OK;
2019 }
2020
2021 ret = m_can_start_tx(cdev);
2022 if (ret != NETDEV_TX_OK)
2023 return ret;
2024
2025 netdev_sent_queue(dev, frame_len);
2026
2027 if (cdev->is_peripheral)
2028 ret = m_can_start_peripheral_xmit(cdev, skb);
2029 else
2030 ret = m_can_tx_handler(cdev, skb);
2031
2032 if (ret != NETDEV_TX_OK)
2033 netdev_completed_queue(dev, 1, frame_len);
2034
2035 return ret;
2036 }
2037
hrtimer_callback(struct hrtimer * timer)2038 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer)
2039 {
2040 struct m_can_classdev *cdev = container_of(timer, struct
2041 m_can_classdev, hrtimer);
2042 int ret;
2043
2044 if (cdev->can.state == CAN_STATE_BUS_OFF ||
2045 cdev->can.state == CAN_STATE_STOPPED)
2046 return HRTIMER_NORESTART;
2047
2048 ret = m_can_interrupt_handler(cdev);
2049
2050 /* On error or if napi is scheduled to read, stop the timer */
2051 if (ret < 0 || napi_is_scheduled(&cdev->napi))
2052 return HRTIMER_NORESTART;
2053
2054 hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS));
2055
2056 return HRTIMER_RESTART;
2057 }
2058
m_can_open(struct net_device * dev)2059 static int m_can_open(struct net_device *dev)
2060 {
2061 struct m_can_classdev *cdev = netdev_priv(dev);
2062 int err;
2063
2064 err = phy_power_on(cdev->transceiver);
2065 if (err)
2066 return err;
2067
2068 err = m_can_clk_start(cdev);
2069 if (err)
2070 goto out_phy_power_off;
2071
2072 /* open the can device */
2073 err = open_candev(dev);
2074 if (err) {
2075 netdev_err(dev, "failed to open can device\n");
2076 goto exit_disable_clks;
2077 }
2078
2079 if (cdev->is_peripheral)
2080 can_rx_offload_enable(&cdev->offload);
2081 else
2082 napi_enable(&cdev->napi);
2083
2084 /* register interrupt handler */
2085 if (cdev->is_peripheral) {
2086 cdev->tx_wq = alloc_ordered_workqueue("mcan_wq",
2087 WQ_FREEZABLE | WQ_MEM_RECLAIM);
2088 if (!cdev->tx_wq) {
2089 err = -ENOMEM;
2090 goto out_wq_fail;
2091 }
2092
2093 for (int i = 0; i != cdev->tx_fifo_size; ++i) {
2094 cdev->tx_ops[i].cdev = cdev;
2095 INIT_WORK(&cdev->tx_ops[i].work, m_can_tx_work_queue);
2096 }
2097
2098 err = request_threaded_irq(dev->irq, NULL, m_can_isr,
2099 IRQF_ONESHOT,
2100 dev->name, dev);
2101 } else if (dev->irq) {
2102 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
2103 dev);
2104 }
2105
2106 if (err < 0) {
2107 netdev_err(dev, "failed to request interrupt\n");
2108 goto exit_irq_fail;
2109 }
2110
2111 /* start the m_can controller */
2112 err = m_can_start(dev);
2113 if (err)
2114 goto exit_start_fail;
2115
2116 netif_start_queue(dev);
2117
2118 return 0;
2119
2120 exit_start_fail:
2121 if (cdev->is_peripheral || dev->irq)
2122 free_irq(dev->irq, dev);
2123 exit_irq_fail:
2124 if (cdev->is_peripheral)
2125 destroy_workqueue(cdev->tx_wq);
2126 out_wq_fail:
2127 if (cdev->is_peripheral)
2128 can_rx_offload_disable(&cdev->offload);
2129 else
2130 napi_disable(&cdev->napi);
2131 close_candev(dev);
2132 exit_disable_clks:
2133 m_can_clk_stop(cdev);
2134 out_phy_power_off:
2135 phy_power_off(cdev->transceiver);
2136 return err;
2137 }
2138
2139 static const struct net_device_ops m_can_netdev_ops = {
2140 .ndo_open = m_can_open,
2141 .ndo_stop = m_can_close,
2142 .ndo_start_xmit = m_can_start_xmit,
2143 .ndo_change_mtu = can_change_mtu,
2144 };
2145
m_can_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kec,struct netlink_ext_ack * ext_ack)2146 static int m_can_get_coalesce(struct net_device *dev,
2147 struct ethtool_coalesce *ec,
2148 struct kernel_ethtool_coalesce *kec,
2149 struct netlink_ext_ack *ext_ack)
2150 {
2151 struct m_can_classdev *cdev = netdev_priv(dev);
2152
2153 ec->rx_max_coalesced_frames_irq = cdev->rx_max_coalesced_frames_irq;
2154 ec->rx_coalesce_usecs_irq = cdev->rx_coalesce_usecs_irq;
2155 ec->tx_max_coalesced_frames = cdev->tx_max_coalesced_frames;
2156 ec->tx_max_coalesced_frames_irq = cdev->tx_max_coalesced_frames_irq;
2157 ec->tx_coalesce_usecs_irq = cdev->tx_coalesce_usecs_irq;
2158
2159 return 0;
2160 }
2161
m_can_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kec,struct netlink_ext_ack * ext_ack)2162 static int m_can_set_coalesce(struct net_device *dev,
2163 struct ethtool_coalesce *ec,
2164 struct kernel_ethtool_coalesce *kec,
2165 struct netlink_ext_ack *ext_ack)
2166 {
2167 struct m_can_classdev *cdev = netdev_priv(dev);
2168
2169 if (cdev->can.state != CAN_STATE_STOPPED) {
2170 netdev_err(dev, "Device is in use, please shut it down first\n");
2171 return -EBUSY;
2172 }
2173
2174 if (ec->rx_max_coalesced_frames_irq > cdev->mcfg[MRAM_RXF0].num) {
2175 netdev_err(dev, "rx-frames-irq %u greater than the RX FIFO %u\n",
2176 ec->rx_max_coalesced_frames_irq,
2177 cdev->mcfg[MRAM_RXF0].num);
2178 return -EINVAL;
2179 }
2180 if ((ec->rx_max_coalesced_frames_irq == 0) != (ec->rx_coalesce_usecs_irq == 0)) {
2181 netdev_err(dev, "rx-frames-irq and rx-usecs-irq can only be set together\n");
2182 return -EINVAL;
2183 }
2184 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXE].num) {
2185 netdev_err(dev, "tx-frames-irq %u greater than the TX event FIFO %u\n",
2186 ec->tx_max_coalesced_frames_irq,
2187 cdev->mcfg[MRAM_TXE].num);
2188 return -EINVAL;
2189 }
2190 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXB].num) {
2191 netdev_err(dev, "tx-frames-irq %u greater than the TX FIFO %u\n",
2192 ec->tx_max_coalesced_frames_irq,
2193 cdev->mcfg[MRAM_TXB].num);
2194 return -EINVAL;
2195 }
2196 if ((ec->tx_max_coalesced_frames_irq == 0) != (ec->tx_coalesce_usecs_irq == 0)) {
2197 netdev_err(dev, "tx-frames-irq and tx-usecs-irq can only be set together\n");
2198 return -EINVAL;
2199 }
2200 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXE].num) {
2201 netdev_err(dev, "tx-frames %u greater than the TX event FIFO %u\n",
2202 ec->tx_max_coalesced_frames,
2203 cdev->mcfg[MRAM_TXE].num);
2204 return -EINVAL;
2205 }
2206 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXB].num) {
2207 netdev_err(dev, "tx-frames %u greater than the TX FIFO %u\n",
2208 ec->tx_max_coalesced_frames,
2209 cdev->mcfg[MRAM_TXB].num);
2210 return -EINVAL;
2211 }
2212 if (ec->rx_coalesce_usecs_irq != 0 && ec->tx_coalesce_usecs_irq != 0 &&
2213 ec->rx_coalesce_usecs_irq != ec->tx_coalesce_usecs_irq) {
2214 netdev_err(dev, "rx-usecs-irq %u needs to be equal to tx-usecs-irq %u if both are enabled\n",
2215 ec->rx_coalesce_usecs_irq,
2216 ec->tx_coalesce_usecs_irq);
2217 return -EINVAL;
2218 }
2219
2220 cdev->rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
2221 cdev->rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
2222 cdev->tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
2223 cdev->tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
2224 cdev->tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
2225
2226 if (cdev->rx_coalesce_usecs_irq)
2227 cdev->irq_timer_wait = us_to_ktime(cdev->rx_coalesce_usecs_irq);
2228 else
2229 cdev->irq_timer_wait = us_to_ktime(cdev->tx_coalesce_usecs_irq);
2230
2231 return 0;
2232 }
2233
2234 static const struct ethtool_ops m_can_ethtool_ops_coalescing = {
2235 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS_IRQ |
2236 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ |
2237 ETHTOOL_COALESCE_TX_USECS_IRQ |
2238 ETHTOOL_COALESCE_TX_MAX_FRAMES |
2239 ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ,
2240 .get_ts_info = ethtool_op_get_ts_info,
2241 .get_coalesce = m_can_get_coalesce,
2242 .set_coalesce = m_can_set_coalesce,
2243 };
2244
2245 static const struct ethtool_ops m_can_ethtool_ops = {
2246 .get_ts_info = ethtool_op_get_ts_info,
2247 };
2248
register_m_can_dev(struct m_can_classdev * cdev)2249 static int register_m_can_dev(struct m_can_classdev *cdev)
2250 {
2251 struct net_device *dev = cdev->net;
2252
2253 dev->flags |= IFF_ECHO; /* we support local echo */
2254 dev->netdev_ops = &m_can_netdev_ops;
2255 if (dev->irq && cdev->is_peripheral)
2256 dev->ethtool_ops = &m_can_ethtool_ops_coalescing;
2257 else
2258 dev->ethtool_ops = &m_can_ethtool_ops;
2259
2260 return register_candev(dev);
2261 }
2262
m_can_check_mram_cfg(struct m_can_classdev * cdev,u32 mram_max_size)2263 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size)
2264 {
2265 u32 total_size;
2266
2267 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off +
2268 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2269 if (total_size > mram_max_size) {
2270 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n",
2271 total_size, mram_max_size);
2272 return -EINVAL;
2273 }
2274
2275 return 0;
2276 }
2277 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg);
2278
m_can_of_parse_mram(struct m_can_classdev * cdev,const u32 * mram_config_vals)2279 static void m_can_of_parse_mram(struct m_can_classdev *cdev,
2280 const u32 *mram_config_vals)
2281 {
2282 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
2283 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
2284 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
2285 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
2286 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
2287 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
2288 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
2289 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
2290 FIELD_MAX(RXFC_FS_MASK);
2291 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
2292 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
2293 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
2294 FIELD_MAX(RXFC_FS_MASK);
2295 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
2296 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
2297 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
2298 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
2299 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
2300 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
2301 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
2302 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
2303 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
2304 FIELD_MAX(TXBC_NDTB_MASK);
2305
2306 dev_dbg(cdev->dev,
2307 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
2308 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
2309 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
2310 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
2311 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
2312 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
2313 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
2314 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
2315 }
2316
m_can_init_ram(struct m_can_classdev * cdev)2317 int m_can_init_ram(struct m_can_classdev *cdev)
2318 {
2319 int end, i, start;
2320 int err = 0;
2321
2322 /* initialize the entire Message RAM in use to avoid possible
2323 * ECC/parity checksum errors when reading an uninitialized buffer
2324 */
2325 start = cdev->mcfg[MRAM_SIDF].off;
2326 end = cdev->mcfg[MRAM_TXB].off +
2327 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2328
2329 for (i = start; i < end; i += 4) {
2330 err = m_can_fifo_write_no_off(cdev, i, 0x0);
2331 if (err)
2332 break;
2333 }
2334
2335 return err;
2336 }
2337 EXPORT_SYMBOL_GPL(m_can_init_ram);
2338
m_can_class_get_clocks(struct m_can_classdev * cdev)2339 int m_can_class_get_clocks(struct m_can_classdev *cdev)
2340 {
2341 int ret = 0;
2342
2343 cdev->hclk = devm_clk_get(cdev->dev, "hclk");
2344 cdev->cclk = devm_clk_get(cdev->dev, "cclk");
2345
2346 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) {
2347 dev_err(cdev->dev, "no clock found\n");
2348 ret = -ENODEV;
2349 }
2350
2351 return ret;
2352 }
2353 EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
2354
m_can_class_allocate_dev(struct device * dev,int sizeof_priv)2355 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
2356 int sizeof_priv)
2357 {
2358 struct m_can_classdev *class_dev = NULL;
2359 u32 mram_config_vals[MRAM_CFG_LEN];
2360 struct net_device *net_dev;
2361 u32 tx_fifo_size;
2362 int ret;
2363
2364 ret = fwnode_property_read_u32_array(dev_fwnode(dev),
2365 "bosch,mram-cfg",
2366 mram_config_vals,
2367 sizeof(mram_config_vals) / 4);
2368 if (ret) {
2369 dev_err(dev, "Could not get Message RAM configuration.");
2370 goto out;
2371 }
2372
2373 /* Get TX FIFO size
2374 * Defines the total amount of echo buffers for loopback
2375 */
2376 tx_fifo_size = mram_config_vals[7];
2377
2378 /* allocate the m_can device */
2379 net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
2380 if (!net_dev) {
2381 dev_err(dev, "Failed to allocate CAN device");
2382 goto out;
2383 }
2384
2385 class_dev = netdev_priv(net_dev);
2386 class_dev->net = net_dev;
2387 class_dev->dev = dev;
2388 SET_NETDEV_DEV(net_dev, dev);
2389
2390 m_can_of_parse_mram(class_dev, mram_config_vals);
2391 spin_lock_init(&class_dev->tx_handling_spinlock);
2392 out:
2393 return class_dev;
2394 }
2395 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
2396
m_can_class_free_dev(struct net_device * net)2397 void m_can_class_free_dev(struct net_device *net)
2398 {
2399 free_candev(net);
2400 }
2401 EXPORT_SYMBOL_GPL(m_can_class_free_dev);
2402
m_can_class_register(struct m_can_classdev * cdev)2403 int m_can_class_register(struct m_can_classdev *cdev)
2404 {
2405 int ret;
2406
2407 cdev->tx_fifo_size = max(1, min(cdev->mcfg[MRAM_TXB].num,
2408 cdev->mcfg[MRAM_TXE].num));
2409 if (cdev->is_peripheral) {
2410 cdev->tx_ops =
2411 devm_kzalloc(cdev->dev,
2412 cdev->tx_fifo_size * sizeof(*cdev->tx_ops),
2413 GFP_KERNEL);
2414 if (!cdev->tx_ops) {
2415 dev_err(cdev->dev, "Failed to allocate tx_ops for workqueue\n");
2416 return -ENOMEM;
2417 }
2418 }
2419
2420 ret = m_can_clk_start(cdev);
2421 if (ret)
2422 return ret;
2423
2424 if (cdev->is_peripheral) {
2425 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload,
2426 NAPI_POLL_WEIGHT);
2427 if (ret)
2428 goto clk_disable;
2429 }
2430
2431 if (!cdev->net->irq) {
2432 dev_dbg(cdev->dev, "Polling enabled, initialize hrtimer");
2433 hrtimer_setup(&cdev->hrtimer, &hrtimer_callback, CLOCK_MONOTONIC,
2434 HRTIMER_MODE_REL_PINNED);
2435 } else {
2436 hrtimer_setup(&cdev->hrtimer, m_can_coalescing_timer, CLOCK_MONOTONIC,
2437 HRTIMER_MODE_REL);
2438 }
2439
2440 ret = m_can_dev_setup(cdev);
2441 if (ret)
2442 goto rx_offload_del;
2443
2444 ret = register_m_can_dev(cdev);
2445 if (ret) {
2446 dev_err(cdev->dev, "registering %s failed (err=%d)\n",
2447 cdev->net->name, ret);
2448 goto rx_offload_del;
2449 }
2450
2451 of_can_transceiver(cdev->net);
2452
2453 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
2454 KBUILD_MODNAME, cdev->net->irq, cdev->version);
2455
2456 /* Probe finished
2457 * Stop clocks. They will be reactivated once the M_CAN device is opened
2458 */
2459 m_can_clk_stop(cdev);
2460
2461 return 0;
2462
2463 rx_offload_del:
2464 if (cdev->is_peripheral)
2465 can_rx_offload_del(&cdev->offload);
2466 clk_disable:
2467 m_can_clk_stop(cdev);
2468
2469 return ret;
2470 }
2471 EXPORT_SYMBOL_GPL(m_can_class_register);
2472
m_can_class_unregister(struct m_can_classdev * cdev)2473 void m_can_class_unregister(struct m_can_classdev *cdev)
2474 {
2475 unregister_candev(cdev->net);
2476 if (cdev->is_peripheral)
2477 can_rx_offload_del(&cdev->offload);
2478 }
2479 EXPORT_SYMBOL_GPL(m_can_class_unregister);
2480
m_can_class_suspend(struct device * dev)2481 int m_can_class_suspend(struct device *dev)
2482 {
2483 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2484 struct net_device *ndev = cdev->net;
2485 int ret = 0;
2486
2487 if (netif_running(ndev)) {
2488 netif_stop_queue(ndev);
2489 netif_device_detach(ndev);
2490
2491 /* leave the chip running with rx interrupt enabled if it is
2492 * used as a wake-up source. Coalescing needs to be reset then,
2493 * the timer is cancelled here, interrupts are done in resume.
2494 */
2495 if (cdev->pm_wake_source) {
2496 hrtimer_cancel(&cdev->hrtimer);
2497 m_can_write(cdev, M_CAN_IE, IR_RF0N);
2498
2499 if (cdev->ops->deinit)
2500 ret = cdev->ops->deinit(cdev);
2501 } else {
2502 m_can_stop(ndev);
2503 }
2504
2505 m_can_clk_stop(cdev);
2506 cdev->can.state = CAN_STATE_SLEEPING;
2507 }
2508
2509 pinctrl_pm_select_sleep_state(dev);
2510
2511 return ret;
2512 }
2513 EXPORT_SYMBOL_GPL(m_can_class_suspend);
2514
m_can_class_resume(struct device * dev)2515 int m_can_class_resume(struct device *dev)
2516 {
2517 struct m_can_classdev *cdev = dev_get_drvdata(dev);
2518 struct net_device *ndev = cdev->net;
2519 int ret = 0;
2520
2521 pinctrl_pm_select_default_state(dev);
2522
2523 if (netif_running(ndev)) {
2524 ret = m_can_clk_start(cdev);
2525 if (ret)
2526 return ret;
2527
2528 if (cdev->pm_wake_source) {
2529 /* Restore active interrupts but disable coalescing as
2530 * we may have missed important waterlevel interrupts
2531 * between suspend and resume. Timers are already
2532 * stopped in suspend. Here we enable all interrupts
2533 * again.
2534 */
2535 cdev->active_interrupts |= IR_RF0N | IR_TEFN;
2536
2537 if (cdev->ops->init)
2538 ret = cdev->ops->init(cdev);
2539
2540 cdev->can.state = m_can_state_get_by_psr(cdev);
2541
2542 m_can_write(cdev, M_CAN_IE, cdev->active_interrupts);
2543 } else {
2544 ret = m_can_start(ndev);
2545 if (ret) {
2546 m_can_clk_stop(cdev);
2547 return ret;
2548 }
2549 }
2550
2551 netif_device_attach(ndev);
2552 netif_start_queue(ndev);
2553 }
2554
2555 return ret;
2556 }
2557 EXPORT_SYMBOL_GPL(m_can_class_resume);
2558
2559 MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
2560 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
2561 MODULE_LICENSE("GPL v2");
2562 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
2563