1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2020-2026 Intel Corporation
4 */
5
6 #include <linux/firmware.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/workqueue.h>
11 #include <generated/utsrelease.h>
12
13 #include <drm/drm_accel.h>
14 #include <drm/drm_file.h>
15 #include <drm/drm_gem.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_prime.h>
18
19 #include "ivpu_coredump.h"
20 #include "ivpu_debugfs.h"
21 #include "ivpu_drv.h"
22 #include "ivpu_fw.h"
23 #include "ivpu_fw_log.h"
24 #include "ivpu_gem.h"
25 #include "ivpu_hw.h"
26 #include "ivpu_ipc.h"
27 #include "ivpu_job.h"
28 #include "ivpu_jsm_msg.h"
29 #include "ivpu_mmu.h"
30 #include "ivpu_mmu_context.h"
31 #include "ivpu_ms.h"
32 #include "ivpu_pm.h"
33 #include "ivpu_sysfs.h"
34 #include "vpu_boot_api.h"
35
36 #ifndef DRIVER_VERSION_STR
37 #define DRIVER_VERSION_STR "1.0.0 " UTS_RELEASE
38 #endif
39
40 int ivpu_dbg_mask;
41 module_param_named(dbg_mask, ivpu_dbg_mask, int, 0644);
42 MODULE_PARM_DESC(dbg_mask, "Driver debug mask. See IVPU_DBG_* macros.");
43
44 int ivpu_test_mode;
45 #if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG)
46 module_param_named_unsafe(test_mode, ivpu_test_mode, int, 0644);
47 MODULE_PARM_DESC(test_mode, "Test mode mask. See IVPU_TEST_MODE_* macros.");
48 #endif
49
50 u8 ivpu_pll_min_ratio;
51 module_param_named(pll_min_ratio, ivpu_pll_min_ratio, byte, 0644);
52 MODULE_PARM_DESC(pll_min_ratio, "Minimum PLL ratio used to set NPU frequency");
53
54 u8 ivpu_pll_max_ratio = U8_MAX;
55 module_param_named(pll_max_ratio, ivpu_pll_max_ratio, byte, 0644);
56 MODULE_PARM_DESC(pll_max_ratio, "Maximum PLL ratio used to set NPU frequency");
57
58 int ivpu_sched_mode = IVPU_SCHED_MODE_AUTO;
59 module_param_named(sched_mode, ivpu_sched_mode, int, 0444);
60 MODULE_PARM_DESC(sched_mode, "Scheduler mode: -1 - Use default scheduler, 0 - Use OS scheduler (supported on 27XX - 50XX), 1 - Use HW scheduler");
61
62 bool ivpu_disable_mmu_cont_pages;
63 module_param_named(disable_mmu_cont_pages, ivpu_disable_mmu_cont_pages, bool, 0444);
64 MODULE_PARM_DESC(disable_mmu_cont_pages, "Disable MMU contiguous pages optimization");
65
66 bool ivpu_force_snoop;
67 module_param_named(force_snoop, ivpu_force_snoop, bool, 0444);
68 MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access");
69
ivpu_user_limits_alloc(struct ivpu_device * vdev,uid_t uid)70 static struct ivpu_user_limits *ivpu_user_limits_alloc(struct ivpu_device *vdev, uid_t uid)
71 {
72 struct ivpu_user_limits *limits;
73
74 limits = kzalloc_obj(*limits);
75 if (!limits)
76 return ERR_PTR(-ENOMEM);
77
78 kref_init(&limits->ref);
79 atomic_set(&limits->db_count, 0);
80 limits->vdev = vdev;
81 limits->uid = uid;
82
83 /* Allow root user to allocate all contexts */
84 if (uid == 0) {
85 limits->max_ctx_count = ivpu_get_context_count(vdev);
86 limits->max_db_count = ivpu_get_doorbell_count(vdev);
87 } else {
88 limits->max_ctx_count = ivpu_get_context_count(vdev) / 2;
89 limits->max_db_count = ivpu_get_doorbell_count(vdev) / 2;
90 }
91
92 hash_add(vdev->user_limits, &limits->hash_node, uid);
93
94 return limits;
95 }
96
ivpu_user_limits_get(struct ivpu_device * vdev)97 static struct ivpu_user_limits *ivpu_user_limits_get(struct ivpu_device *vdev)
98 {
99 struct ivpu_user_limits *limits;
100 uid_t uid = current_uid().val;
101
102 guard(mutex)(&vdev->user_limits_lock);
103
104 hash_for_each_possible(vdev->user_limits, limits, hash_node, uid) {
105 if (limits->uid == uid) {
106 if (kref_read(&limits->ref) >= limits->max_ctx_count) {
107 ivpu_dbg(vdev, IOCTL, "User %u exceeded max ctx count %u\n", uid,
108 limits->max_ctx_count);
109 return ERR_PTR(-EMFILE);
110 }
111
112 kref_get(&limits->ref);
113 return limits;
114 }
115 }
116
117 return ivpu_user_limits_alloc(vdev, uid);
118 }
119
ivpu_user_limits_release(struct kref * ref)120 static void ivpu_user_limits_release(struct kref *ref)
121 {
122 struct ivpu_user_limits *limits = container_of(ref, struct ivpu_user_limits, ref);
123 struct ivpu_device *vdev = limits->vdev;
124
125 lockdep_assert_held(&vdev->user_limits_lock);
126 drm_WARN_ON(&vdev->drm, atomic_read(&limits->db_count));
127 hash_del(&limits->hash_node);
128 kfree(limits);
129 }
130
ivpu_user_limits_put(struct ivpu_device * vdev,struct ivpu_user_limits * limits)131 static void ivpu_user_limits_put(struct ivpu_device *vdev, struct ivpu_user_limits *limits)
132 {
133 guard(mutex)(&vdev->user_limits_lock);
134 kref_put(&limits->ref, ivpu_user_limits_release);
135 }
136
ivpu_file_priv_get(struct ivpu_file_priv * file_priv)137 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv)
138 {
139 struct ivpu_device *vdev = file_priv->vdev;
140
141 kref_get(&file_priv->ref);
142
143 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n",
144 file_priv->ctx.id, kref_read(&file_priv->ref));
145
146 return file_priv;
147 }
148
file_priv_unbind(struct ivpu_device * vdev,struct ivpu_file_priv * file_priv)149 static void file_priv_unbind(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv)
150 {
151 mutex_lock(&file_priv->lock);
152 if (file_priv->bound) {
153 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id);
154
155 ivpu_cmdq_release_all_locked(file_priv);
156 ivpu_bo_unbind_all_bos_from_context(vdev, &file_priv->ctx);
157 ivpu_mmu_context_fini(vdev, &file_priv->ctx);
158 file_priv->bound = false;
159 drm_WARN_ON(&vdev->drm, !xa_erase_irq(&vdev->context_xa, file_priv->ctx.id));
160 }
161 mutex_unlock(&file_priv->lock);
162 }
163
file_priv_release(struct kref * ref)164 static void file_priv_release(struct kref *ref)
165 {
166 struct ivpu_file_priv *file_priv = container_of(ref, struct ivpu_file_priv, ref);
167 struct ivpu_device *vdev = file_priv->vdev;
168
169 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n",
170 file_priv->ctx.id, (bool)file_priv->bound);
171
172 pm_runtime_get_sync(vdev->drm.dev);
173 mutex_lock(&vdev->context_list_lock);
174 file_priv_unbind(vdev, file_priv);
175 drm_WARN_ON(&vdev->drm, !xa_empty(&file_priv->cmdq_xa));
176 xa_destroy(&file_priv->cmdq_xa);
177 mutex_unlock(&vdev->context_list_lock);
178 pm_runtime_put_autosuspend(vdev->drm.dev);
179
180 ivpu_user_limits_put(vdev, file_priv->user_limits);
181 mutex_destroy(&file_priv->ms_lock);
182 mutex_destroy(&file_priv->lock);
183 kfree(file_priv);
184 }
185
ivpu_file_priv_put(struct ivpu_file_priv ** link)186 void ivpu_file_priv_put(struct ivpu_file_priv **link)
187 {
188 struct ivpu_file_priv *file_priv = *link;
189 struct ivpu_device *vdev = file_priv->vdev;
190
191 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n",
192 file_priv->ctx.id, kref_read(&file_priv->ref));
193
194 *link = NULL;
195 kref_put(&file_priv->ref, file_priv_release);
196 }
197
ivpu_is_capable(struct ivpu_device * vdev,u32 capability)198 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability)
199 {
200 switch (capability) {
201 case DRM_IVPU_CAP_METRIC_STREAMER:
202 return true;
203 case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
204 return true;
205 case DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR:
206 return true;
207 case DRM_IVPU_CAP_MANAGE_CMDQ:
208 return vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW;
209 default:
210 return false;
211 }
212 }
213
ivpu_get_param_ioctl(struct drm_device * dev,void * data,struct drm_file * file)214 static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
215 {
216 struct ivpu_file_priv *file_priv = file->driver_priv;
217 struct ivpu_device *vdev = file_priv->vdev;
218 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
219 struct drm_ivpu_param *args = data;
220 int ret = 0;
221 int idx;
222
223 if (!drm_dev_enter(dev, &idx))
224 return -ENODEV;
225
226 switch (args->param) {
227 case DRM_IVPU_PARAM_DEVICE_ID:
228 args->value = pdev->device;
229 break;
230 case DRM_IVPU_PARAM_DEVICE_REVISION:
231 args->value = pdev->revision;
232 break;
233 case DRM_IVPU_PARAM_PLATFORM_TYPE:
234 args->value = vdev->platform;
235 break;
236 case DRM_IVPU_PARAM_CORE_CLOCK_RATE:
237 args->value = ivpu_hw_btrs_pll_ratio_to_hz(vdev, vdev->hw->pll.max_ratio);
238 break;
239 case DRM_IVPU_PARAM_NUM_CONTEXTS:
240 args->value = file_priv->user_limits->max_ctx_count;
241 break;
242 case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
243 args->value = vdev->hw->ranges.user.start;
244 break;
245 case DRM_IVPU_PARAM_CONTEXT_ID:
246 args->value = file_priv->ctx.id;
247 break;
248 case DRM_IVPU_PARAM_FW_API_VERSION:
249 if (args->index < VPU_FW_API_VER_NUM) {
250 struct vpu_firmware_header *fw_hdr;
251
252 fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data;
253 args->value = fw_hdr->api_version[args->index];
254 } else {
255 ret = -EINVAL;
256 }
257 break;
258 case DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
259 ret = ivpu_jsm_get_heartbeat(vdev, args->index, &args->value);
260 break;
261 case DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
262 args->value = (u64)atomic64_inc_return(&vdev->unique_id_counter);
263 break;
264 case DRM_IVPU_PARAM_TILE_CONFIG:
265 args->value = vdev->hw->tile_fuse;
266 break;
267 case DRM_IVPU_PARAM_SKU:
268 args->value = vdev->hw->sku;
269 break;
270 case DRM_IVPU_PARAM_CAPABILITIES:
271 args->value = ivpu_is_capable(vdev, args->index);
272 break;
273 case DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE:
274 args->value = ivpu_fw_preempt_buf_size(vdev);
275 break;
276 default:
277 ret = -EINVAL;
278 break;
279 }
280
281 drm_dev_exit(idx);
282 return ret;
283 }
284
ivpu_set_param_ioctl(struct drm_device * dev,void * data,struct drm_file * file)285 static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
286 {
287 struct drm_ivpu_param *args = data;
288 int ret = 0;
289
290 switch (args->param) {
291 default:
292 ret = -EINVAL;
293 }
294
295 return ret;
296 }
297
ivpu_open(struct drm_device * dev,struct drm_file * file)298 static int ivpu_open(struct drm_device *dev, struct drm_file *file)
299 {
300 struct ivpu_device *vdev = to_ivpu_device(dev);
301 struct ivpu_file_priv *file_priv;
302 struct ivpu_user_limits *limits;
303 u32 ctx_id;
304 int idx, ret;
305
306 if (!drm_dev_enter(dev, &idx))
307 return -ENODEV;
308
309 limits = ivpu_user_limits_get(vdev);
310 if (IS_ERR(limits) && PTR_ERR(limits) == -EMFILE) {
311 /* Context limit may be held by jobs pending deferred cleanup */
312 flush_work(&vdev->job_destroy_work);
313 limits = ivpu_user_limits_get(vdev);
314 }
315 if (IS_ERR(limits)) {
316 ret = PTR_ERR(limits);
317 goto err_dev_exit;
318 }
319
320 file_priv = kzalloc_obj(*file_priv);
321 if (!file_priv) {
322 ret = -ENOMEM;
323 goto err_user_limits_put;
324 }
325
326 INIT_LIST_HEAD(&file_priv->ms_instance_list);
327
328 file_priv->vdev = vdev;
329 file_priv->bound = true;
330 file_priv->user_limits = limits;
331 kref_init(&file_priv->ref);
332 mutex_init(&file_priv->lock);
333 mutex_init(&file_priv->ms_lock);
334
335 mutex_lock(&vdev->context_list_lock);
336
337 ret = xa_alloc_irq(&vdev->context_xa, &ctx_id, file_priv,
338 vdev->context_xa_limit, GFP_KERNEL);
339 if (ret) {
340 ivpu_err(vdev, "Failed to allocate context id: %d\n", ret);
341 goto err_unlock;
342 }
343
344 ivpu_mmu_context_init(vdev, &file_priv->ctx, ctx_id);
345
346 file_priv->job_limit.min = FIELD_PREP(IVPU_JOB_ID_CONTEXT_MASK, (file_priv->ctx.id - 1));
347 file_priv->job_limit.max = file_priv->job_limit.min | IVPU_JOB_ID_JOB_MASK;
348
349 xa_init_flags(&file_priv->cmdq_xa, XA_FLAGS_ALLOC1);
350 file_priv->cmdq_limit.min = IVPU_CMDQ_MIN_ID;
351 file_priv->cmdq_limit.max = IVPU_CMDQ_MAX_ID;
352
353 mutex_unlock(&vdev->context_list_lock);
354 drm_dev_exit(idx);
355
356 file->driver_priv = file_priv;
357
358 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n",
359 ctx_id, current->comm, task_pid_nr(current));
360
361 return 0;
362
363 err_unlock:
364 mutex_unlock(&vdev->context_list_lock);
365 mutex_destroy(&file_priv->ms_lock);
366 mutex_destroy(&file_priv->lock);
367 kfree(file_priv);
368 err_user_limits_put:
369 ivpu_user_limits_put(vdev, limits);
370 err_dev_exit:
371 drm_dev_exit(idx);
372 return ret;
373 }
374
ivpu_postclose(struct drm_device * dev,struct drm_file * file)375 static void ivpu_postclose(struct drm_device *dev, struct drm_file *file)
376 {
377 struct ivpu_file_priv *file_priv = file->driver_priv;
378 struct ivpu_device *vdev = to_ivpu_device(dev);
379
380 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n",
381 file_priv->ctx.id, current->comm, task_pid_nr(current));
382
383 ivpu_ms_cleanup(file_priv);
384 ivpu_file_priv_put(&file_priv);
385 }
386
387 static const struct drm_ioctl_desc ivpu_drm_ioctls[] = {
388 DRM_IOCTL_DEF_DRV(IVPU_GET_PARAM, ivpu_get_param_ioctl, 0),
389 DRM_IOCTL_DEF_DRV(IVPU_SET_PARAM, ivpu_set_param_ioctl, 0),
390 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE, ivpu_bo_create_ioctl, 0),
391 DRM_IOCTL_DEF_DRV(IVPU_BO_INFO, ivpu_bo_info_ioctl, 0),
392 DRM_IOCTL_DEF_DRV(IVPU_SUBMIT, ivpu_submit_ioctl, 0),
393 DRM_IOCTL_DEF_DRV(IVPU_BO_WAIT, ivpu_bo_wait_ioctl, 0),
394 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_START, ivpu_ms_start_ioctl, 0),
395 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_DATA, ivpu_ms_get_data_ioctl, 0),
396 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_STOP, ivpu_ms_stop_ioctl, 0),
397 DRM_IOCTL_DEF_DRV(IVPU_METRIC_STREAMER_GET_INFO, ivpu_ms_get_info_ioctl, 0),
398 DRM_IOCTL_DEF_DRV(IVPU_CMDQ_CREATE, ivpu_cmdq_create_ioctl, 0),
399 DRM_IOCTL_DEF_DRV(IVPU_CMDQ_DESTROY, ivpu_cmdq_destroy_ioctl, 0),
400 DRM_IOCTL_DEF_DRV(IVPU_CMDQ_SUBMIT, ivpu_cmdq_submit_ioctl, 0),
401 DRM_IOCTL_DEF_DRV(IVPU_BO_CREATE_FROM_USERPTR, ivpu_bo_create_from_userptr_ioctl, 0),
402 };
403
ivpu_wait_for_ready(struct ivpu_device * vdev)404 static int ivpu_wait_for_ready(struct ivpu_device *vdev)
405 {
406 struct ivpu_ipc_consumer cons;
407 struct ivpu_ipc_hdr ipc_hdr;
408 unsigned long timeout;
409 int ret;
410
411 if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST)
412 return 0;
413
414 ivpu_ipc_consumer_add(vdev, &cons, IVPU_IPC_CHAN_BOOT_MSG, NULL);
415
416 timeout = jiffies + msecs_to_jiffies(vdev->timeout.boot);
417 while (1) {
418 ivpu_ipc_irq_handler(vdev);
419 ret = ivpu_ipc_receive(vdev, &cons, &ipc_hdr, NULL, 0);
420 if (ret != -ETIMEDOUT || time_after_eq(jiffies, timeout))
421 break;
422
423 cond_resched();
424 }
425
426 ivpu_ipc_consumer_del(vdev, &cons);
427
428 if (!ret && ipc_hdr.data_addr != IVPU_IPC_BOOT_MSG_DATA_ADDR) {
429 ivpu_err(vdev, "Invalid NPU ready message: 0x%x\n", ipc_hdr.data_addr);
430 return -EIO;
431 }
432
433 if (!ret)
434 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n");
435
436 return ret;
437 }
438
ivpu_hw_sched_init(struct ivpu_device * vdev)439 static int ivpu_hw_sched_init(struct ivpu_device *vdev)
440 {
441 int ret = 0;
442
443 if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) {
444 ret = ivpu_jsm_hws_setup_priority_bands(vdev);
445 if (ret) {
446 ivpu_err(vdev, "Failed to enable hw scheduler: %d", ret);
447 return ret;
448 }
449 }
450
451 return ret;
452 }
453
454 /**
455 * ivpu_boot() - Start VPU firmware
456 * @vdev: VPU device
457 *
458 * This function is paired with ivpu_shutdown() but it doesn't power up the
459 * VPU because power up has to be called very early in ivpu_probe().
460 */
ivpu_boot(struct ivpu_device * vdev)461 int ivpu_boot(struct ivpu_device *vdev)
462 {
463 int ret;
464
465 drm_WARN_ON(&vdev->drm, atomic_read(&vdev->job_timeout_counter));
466 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
467
468 ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem_bp));
469 vdev->fw->last_boot_mode = vdev->fw->next_boot_mode;
470
471 ret = ivpu_hw_boot_fw(vdev);
472 if (ret) {
473 ivpu_err(vdev, "Failed to start the firmware: %d\n", ret);
474 return ret;
475 }
476
477 ret = ivpu_wait_for_ready(vdev);
478 if (ret) {
479 ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret);
480 goto err_diagnose_failure;
481 }
482 ivpu_hw_irq_clear(vdev);
483 enable_irq(vdev->irq);
484 ivpu_hw_irq_enable(vdev);
485 ivpu_ipc_enable(vdev);
486
487 if (!ivpu_fw_is_warm_boot(vdev)) {
488 ret = ivpu_pm_dct_init(vdev);
489 if (ret)
490 goto err_disable_ipc;
491
492 ret = ivpu_hw_sched_init(vdev);
493 if (ret)
494 goto err_disable_ipc;
495
496 ret = ivpu_hw_btrs_cfg_freq_init(vdev);
497 if (ret)
498 goto err_disable_ipc;
499 }
500
501 return 0;
502
503 err_disable_ipc:
504 ivpu_ipc_disable(vdev);
505 ivpu_hw_irq_disable(vdev);
506 disable_irq(vdev->irq);
507 err_diagnose_failure:
508 ivpu_hw_diagnose_failure(vdev);
509 ivpu_mmu_evtq_dump(vdev);
510 ivpu_dev_coredump(vdev);
511 return ret;
512 }
513
ivpu_prepare_for_reset(struct ivpu_device * vdev)514 void ivpu_prepare_for_reset(struct ivpu_device *vdev)
515 {
516 ivpu_hw_irq_disable(vdev);
517 disable_irq(vdev->irq);
518 atomic_set(&vdev->job_timeout_detected, 0);
519 flush_work(&vdev->irq_dct_work);
520 flush_work(&vdev->context_abort_work);
521 flush_work(&vdev->job_destroy_work);
522 ivpu_ipc_disable(vdev);
523 ivpu_mmu_disable(vdev);
524 }
525
ivpu_shutdown(struct ivpu_device * vdev)526 int ivpu_shutdown(struct ivpu_device *vdev)
527 {
528 int ret;
529
530 /* Save PCI state before powering down as it sometimes gets corrupted if NPU hangs */
531 pci_save_state(to_pci_dev(vdev->drm.dev));
532
533 ret = ivpu_hw_power_down(vdev);
534 if (ret)
535 ivpu_warn(vdev, "Failed to power down HW: %d\n", ret);
536
537 pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
538
539 return ret;
540 }
541
542 static const struct file_operations ivpu_fops = {
543 .owner = THIS_MODULE,
544 DRM_ACCEL_FOPS,
545 #ifdef CONFIG_PROC_FS
546 .show_fdinfo = drm_show_fdinfo,
547 #endif
548 };
549
ivpu_gem_prime_handle_to_fd(struct drm_device * dev,struct drm_file * file_priv,u32 handle,u32 flags,int * prime_fd)550 static int ivpu_gem_prime_handle_to_fd(struct drm_device *dev, struct drm_file *file_priv,
551 u32 handle, u32 flags, int *prime_fd)
552 {
553 struct drm_gem_object *obj;
554
555 obj = drm_gem_object_lookup(file_priv, handle);
556 if (!obj)
557 return -ENOENT;
558
559 if (drm_gem_is_imported(obj)) {
560 /* Do not allow re-exporting */
561 drm_gem_object_put(obj);
562 return -EOPNOTSUPP;
563 }
564
565 drm_gem_object_put(obj);
566
567 return drm_gem_prime_handle_to_fd(dev, file_priv, handle, flags, prime_fd);
568 }
569
570 static const struct drm_driver driver = {
571 .driver_features = DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
572
573 .open = ivpu_open,
574 .postclose = ivpu_postclose,
575
576 .gem_create_object = ivpu_gem_create_object,
577 .gem_prime_import = ivpu_gem_prime_import,
578 .prime_handle_to_fd = ivpu_gem_prime_handle_to_fd,
579
580 .ioctls = ivpu_drm_ioctls,
581 .num_ioctls = ARRAY_SIZE(ivpu_drm_ioctls),
582 .fops = &ivpu_fops,
583 #ifdef CONFIG_PROC_FS
584 .show_fdinfo = drm_show_memory_stats,
585 #endif
586
587 .name = DRIVER_NAME,
588 .desc = DRIVER_DESC,
589
590 .major = 1,
591 };
592
ivpu_destroy_workqueue(void * wq)593 static void ivpu_destroy_workqueue(void *wq)
594 {
595 destroy_workqueue(wq);
596 }
597
ivpu_irq_init(struct ivpu_device * vdev)598 static int ivpu_irq_init(struct ivpu_device *vdev)
599 {
600 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
601 int ret;
602
603 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
604 if (ret < 0) {
605 ivpu_err(vdev, "Failed to allocate a MSI IRQ: %d\n", ret);
606 return ret;
607 }
608
609 INIT_WORK(&vdev->irq_dct_work, ivpu_pm_irq_dct_work_fn);
610 INIT_WORK(&vdev->context_abort_work, ivpu_context_abort_work_fn);
611 init_llist_head(&vdev->job_destroy_list);
612 INIT_WORK(&vdev->job_destroy_work, ivpu_job_destroy_work_fn);
613
614 vdev->job_destroy_wq = alloc_workqueue("ivpu_job_destroy", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
615 if (!vdev->job_destroy_wq)
616 return -ENOMEM;
617
618 ret = devm_add_action_or_reset(vdev->drm.dev, ivpu_destroy_workqueue, vdev->job_destroy_wq);
619 if (ret)
620 return ret;
621
622 ivpu_irq_handlers_init(vdev);
623
624 vdev->irq = pci_irq_vector(pdev, 0);
625
626 ret = devm_request_threaded_irq(vdev->drm.dev, vdev->irq, ivpu_hw_irq_handler,
627 ivpu_ipc_irq_thread_handler, IRQF_NO_AUTOEN,
628 DRIVER_NAME, vdev);
629 if (ret)
630 ivpu_err(vdev, "Failed to request an IRQ %d\n", ret);
631
632 return ret;
633 }
634
ivpu_pci_init(struct ivpu_device * vdev)635 static int ivpu_pci_init(struct ivpu_device *vdev)
636 {
637 struct pci_dev *pdev = to_pci_dev(vdev->drm.dev);
638 struct resource *bar0 = &pdev->resource[0];
639 struct resource *bar4 = &pdev->resource[4];
640 int ret;
641
642 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
643 vdev->regv = devm_ioremap_resource(vdev->drm.dev, bar0);
644 if (IS_ERR(vdev->regv)) {
645 ivpu_err(vdev, "Failed to map bar 0: %pe\n", vdev->regv);
646 return PTR_ERR(vdev->regv);
647 }
648
649 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
650 vdev->regb = devm_ioremap_resource(vdev->drm.dev, bar4);
651 if (IS_ERR(vdev->regb)) {
652 ivpu_err(vdev, "Failed to map bar 4: %pe\n", vdev->regb);
653 return PTR_ERR(vdev->regb);
654 }
655
656 ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits));
657 if (ret) {
658 ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret);
659 return ret;
660 }
661 dma_set_max_seg_size(vdev->drm.dev, UINT_MAX);
662
663 /* Clear any pending errors */
664 pcie_capability_clear_word(pdev, PCI_EXP_DEVSTA, 0x3f);
665
666 /* NPU does not require 10m D3hot delay */
667 pdev->d3hot_delay = 0;
668
669 ret = pcim_enable_device(pdev);
670 if (ret) {
671 ivpu_err(vdev, "Failed to enable PCI device: %d\n", ret);
672 return ret;
673 }
674
675 pci_set_master(pdev);
676
677 return 0;
678 }
679
ivpu_dev_init(struct ivpu_device * vdev)680 static int ivpu_dev_init(struct ivpu_device *vdev)
681 {
682 int ret;
683
684 vdev->hw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->hw), GFP_KERNEL);
685 if (!vdev->hw)
686 return -ENOMEM;
687
688 vdev->mmu = drmm_kzalloc(&vdev->drm, sizeof(*vdev->mmu), GFP_KERNEL);
689 if (!vdev->mmu)
690 return -ENOMEM;
691
692 vdev->fw = drmm_kzalloc(&vdev->drm, sizeof(*vdev->fw), GFP_KERNEL);
693 if (!vdev->fw)
694 return -ENOMEM;
695
696 vdev->ipc = drmm_kzalloc(&vdev->drm, sizeof(*vdev->ipc), GFP_KERNEL);
697 if (!vdev->ipc)
698 return -ENOMEM;
699
700 vdev->pm = drmm_kzalloc(&vdev->drm, sizeof(*vdev->pm), GFP_KERNEL);
701 if (!vdev->pm)
702 return -ENOMEM;
703
704 if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX)
705 vdev->hw->dma_bits = 48;
706 else
707 vdev->hw->dma_bits = 38;
708
709 vdev->platform = IVPU_PLATFORM_INVALID;
710 vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID;
711 vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID;
712 atomic64_set(&vdev->unique_id_counter, 0);
713 atomic_set(&vdev->job_timeout_counter, 0);
714 atomic_set(&vdev->job_timeout_detected, 0);
715 xa_init_flags(&vdev->context_xa, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
716 xa_init_flags(&vdev->submitted_jobs_xa, XA_FLAGS_ALLOC1);
717 xa_init_flags(&vdev->db_xa, XA_FLAGS_ALLOC1);
718 INIT_LIST_HEAD(&vdev->bo_list);
719 hash_init(vdev->user_limits);
720
721 vdev->db_limit.min = IVPU_MIN_DB;
722 vdev->db_limit.max = IVPU_MAX_DB;
723
724 ret = drmm_mutex_init(&vdev->drm, &vdev->context_list_lock);
725 if (ret)
726 goto err_xa_destroy;
727
728 ret = drmm_mutex_init(&vdev->drm, &vdev->user_limits_lock);
729 if (ret)
730 goto err_xa_destroy;
731
732 ret = drmm_mutex_init(&vdev->drm, &vdev->submitted_jobs_lock);
733 if (ret)
734 goto err_xa_destroy;
735
736 ret = drmm_mutex_init(&vdev->drm, &vdev->bo_list_lock);
737 if (ret)
738 goto err_xa_destroy;
739
740 ret = ivpu_pci_init(vdev);
741 if (ret)
742 goto err_xa_destroy;
743
744 ret = ivpu_irq_init(vdev);
745 if (ret)
746 goto err_xa_destroy;
747
748 /* Init basic HW info based on buttress registers which are accessible before power up */
749 ret = ivpu_hw_init(vdev);
750 if (ret)
751 goto err_xa_destroy;
752
753 /* Power up early so the rest of init code can access VPU registers */
754 ret = ivpu_hw_power_up(vdev);
755 if (ret)
756 goto err_shutdown;
757
758 ivpu_mmu_global_context_init(vdev);
759
760 ret = ivpu_mmu_init(vdev);
761 if (ret)
762 goto err_mmu_gctx_fini;
763
764 ret = ivpu_mmu_reserved_context_init(vdev);
765 if (ret)
766 goto err_mmu_gctx_fini;
767
768 ret = ivpu_fw_init(vdev);
769 if (ret)
770 goto err_mmu_rctx_fini;
771
772 ret = ivpu_ipc_init(vdev);
773 if (ret)
774 goto err_fw_fini;
775
776 ivpu_pm_init(vdev);
777
778 ret = ivpu_boot(vdev);
779 if (ret)
780 goto err_ipc_fini;
781
782 ivpu_job_done_consumer_init(vdev);
783 ivpu_pm_enable(vdev);
784
785 return 0;
786
787 err_ipc_fini:
788 ivpu_ipc_fini(vdev);
789 err_fw_fini:
790 ivpu_fw_fini(vdev);
791 err_mmu_rctx_fini:
792 ivpu_mmu_reserved_context_fini(vdev);
793 err_mmu_gctx_fini:
794 ivpu_mmu_global_context_fini(vdev);
795 err_shutdown:
796 ivpu_shutdown(vdev);
797 err_xa_destroy:
798 xa_destroy(&vdev->db_xa);
799 xa_destroy(&vdev->submitted_jobs_xa);
800 xa_destroy(&vdev->context_xa);
801 return ret;
802 }
803
ivpu_bo_unbind_all_user_contexts(struct ivpu_device * vdev)804 static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
805 {
806 struct ivpu_file_priv *file_priv;
807 unsigned long ctx_id;
808
809 mutex_lock(&vdev->context_list_lock);
810
811 xa_for_each(&vdev->context_xa, ctx_id, file_priv)
812 file_priv_unbind(vdev, file_priv);
813
814 mutex_unlock(&vdev->context_list_lock);
815 }
816
ivpu_dev_fini(struct ivpu_device * vdev)817 static void ivpu_dev_fini(struct ivpu_device *vdev)
818 {
819 ivpu_jobs_abort_all(vdev);
820 ivpu_pm_disable_recovery(vdev);
821 ivpu_pm_disable(vdev);
822 ivpu_prepare_for_reset(vdev);
823 ivpu_shutdown(vdev);
824
825 ivpu_ms_cleanup_all(vdev);
826 ivpu_job_done_consumer_fini(vdev);
827 ivpu_bo_unbind_all_user_contexts(vdev);
828
829 ivpu_ipc_fini(vdev);
830 ivpu_fw_fini(vdev);
831 ivpu_mmu_reserved_context_fini(vdev);
832 ivpu_mmu_global_context_fini(vdev);
833
834 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->db_xa));
835 xa_destroy(&vdev->db_xa);
836 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
837 xa_destroy(&vdev->submitted_jobs_xa);
838 drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->context_xa));
839 xa_destroy(&vdev->context_xa);
840 }
841
842 static struct pci_device_id ivpu_pci_ids[] = {
843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_WCL) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NVL) },
849 {}
850 };
851 MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
852
ivpu_probe(struct pci_dev * pdev,const struct pci_device_id * id)853 static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
854 {
855 struct ivpu_device *vdev;
856 int ret;
857
858 vdev = devm_drm_dev_alloc(&pdev->dev, &driver, struct ivpu_device, drm);
859 if (IS_ERR(vdev))
860 return PTR_ERR(vdev);
861
862 pci_set_drvdata(pdev, vdev);
863
864 ret = ivpu_dev_init(vdev);
865 if (ret)
866 return ret;
867
868 ivpu_debugfs_init(vdev);
869 ivpu_sysfs_init(vdev);
870
871 ret = drm_dev_register(&vdev->drm, 0);
872 if (ret) {
873 dev_err(&pdev->dev, "Failed to register DRM device: %d\n", ret);
874 ivpu_dev_fini(vdev);
875 }
876
877 return ret;
878 }
879
ivpu_remove(struct pci_dev * pdev)880 static void ivpu_remove(struct pci_dev *pdev)
881 {
882 struct ivpu_device *vdev = pci_get_drvdata(pdev);
883
884 drm_dev_unplug(&vdev->drm);
885 ivpu_dev_fini(vdev);
886 }
887
888 static const struct dev_pm_ops ivpu_drv_pci_pm = {
889 SET_SYSTEM_SLEEP_PM_OPS(ivpu_pm_suspend_cb, ivpu_pm_resume_cb)
890 SET_RUNTIME_PM_OPS(ivpu_pm_runtime_suspend_cb, ivpu_pm_runtime_resume_cb, NULL)
891 };
892
893 static const struct pci_error_handlers ivpu_drv_pci_err = {
894 .reset_prepare = ivpu_pm_reset_prepare_cb,
895 .reset_done = ivpu_pm_reset_done_cb,
896 };
897
898 static struct pci_driver ivpu_pci_driver = {
899 .name = KBUILD_MODNAME,
900 .id_table = ivpu_pci_ids,
901 .probe = ivpu_probe,
902 .remove = ivpu_remove,
903 .driver = {
904 .pm = &ivpu_drv_pci_pm,
905 },
906 .err_handler = &ivpu_drv_pci_err,
907 };
908
909 module_pci_driver(ivpu_pci_driver);
910
911 MODULE_AUTHOR("Intel Corporation");
912 MODULE_DESCRIPTION(DRIVER_DESC);
913 MODULE_LICENSE("GPL and additional rights");
914 MODULE_VERSION(DRIVER_VERSION_STR);
915