1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_MDSS_H 8 #define _DPU_HW_MDSS_H 9 10 #include <linux/kernel.h> 11 #include <linux/err.h> 12 13 #include "msm_drv.h" 14 15 #include "disp/mdp_format.h" 16 17 #define DPU_DBG_NAME "dpu" 18 19 #define DPU_NONE 0 20 21 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 22 #define DPU_CSC_MATRIX_COEFF_SIZE 9 23 #endif 24 25 #ifndef DPU_CSC_CLAMP_SIZE 26 #define DPU_CSC_CLAMP_SIZE 6 27 #endif 28 29 #ifndef DPU_CSC_BIAS_SIZE 30 #define DPU_CSC_BIAS_SIZE 3 31 #endif 32 33 #ifndef DPU_MAX_PLANES 34 #define DPU_MAX_PLANES 4 35 #endif 36 37 #define PIPES_PER_STAGE 2 38 #ifndef DPU_MAX_DE_CURVES 39 #define DPU_MAX_DE_CURVES 3 40 #endif 41 42 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 43 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 44 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 45 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 46 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 47 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 48 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 49 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 50 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 51 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 52 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 53 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 54 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 55 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 56 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 57 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 58 59 enum dpu_vsync_source { 60 DPU_VSYNC_SOURCE_GPIO_0, 61 DPU_VSYNC_SOURCE_GPIO_1, 62 DPU_VSYNC_SOURCE_GPIO_2, 63 DPU_VSYNC_SOURCE_INTF_0 = 3, 64 DPU_VSYNC_SOURCE_INTF_1, 65 DPU_VSYNC_SOURCE_INTF_2, 66 DPU_VSYNC_SOURCE_INTF_3, 67 DPU_VSYNC_SOURCE_WD_TIMER_4 = 11, 68 DPU_VSYNC_SOURCE_WD_TIMER_3, 69 DPU_VSYNC_SOURCE_WD_TIMER_2, 70 DPU_VSYNC_SOURCE_WD_TIMER_1, 71 DPU_VSYNC_SOURCE_WD_TIMER_0, 72 }; 73 74 enum dpu_hw_blk_type { 75 DPU_HW_BLK_TOP = 0, 76 DPU_HW_BLK_SSPP, 77 DPU_HW_BLK_LM, 78 DPU_HW_BLK_CTL, 79 DPU_HW_BLK_PINGPONG, 80 DPU_HW_BLK_DCWB_PINGPONG, 81 DPU_HW_BLK_INTF, 82 DPU_HW_BLK_WB, 83 DPU_HW_BLK_DSPP, 84 DPU_HW_BLK_MERGE_3D, 85 DPU_HW_BLK_DSC, 86 DPU_HW_BLK_CDM, 87 DPU_HW_BLK_CWB, 88 DPU_HW_BLK_MAX, 89 }; 90 91 enum dpu_sspp { 92 SSPP_NONE, 93 SSPP_VIG0, 94 SSPP_VIG1, 95 SSPP_VIG2, 96 SSPP_VIG3, 97 SSPP_RGB0, 98 SSPP_RGB1, 99 SSPP_RGB2, 100 SSPP_RGB3, 101 SSPP_DMA0, 102 SSPP_DMA1, 103 SSPP_DMA2, 104 SSPP_DMA3, 105 SSPP_DMA4, 106 SSPP_DMA5, 107 SSPP_CURSOR0, 108 SSPP_CURSOR1, 109 SSPP_MAX 110 }; 111 112 enum dpu_sspp_type { 113 SSPP_TYPE_VIG, 114 SSPP_TYPE_RGB, 115 SSPP_TYPE_DMA, 116 SSPP_TYPE_CURSOR, 117 SSPP_TYPE_MAX 118 }; 119 120 enum dpu_lm { 121 LM_0 = 1, 122 LM_1, 123 LM_2, 124 LM_3, 125 LM_4, 126 LM_5, 127 LM_6, 128 LM_MAX 129 }; 130 131 enum dpu_stage { 132 DPU_STAGE_BASE = 0, 133 DPU_STAGE_0, 134 DPU_STAGE_1, 135 DPU_STAGE_2, 136 DPU_STAGE_3, 137 DPU_STAGE_4, 138 DPU_STAGE_5, 139 DPU_STAGE_6, 140 DPU_STAGE_7, 141 DPU_STAGE_8, 142 DPU_STAGE_9, 143 DPU_STAGE_10, 144 DPU_STAGE_MAX 145 }; 146 enum dpu_dspp { 147 DSPP_0 = 1, 148 DSPP_1, 149 DSPP_2, 150 DSPP_3, 151 DSPP_MAX 152 }; 153 154 enum dpu_ctl { 155 CTL_0 = 1, 156 CTL_1, 157 CTL_2, 158 CTL_3, 159 CTL_4, 160 CTL_5, 161 CTL_MAX 162 }; 163 164 enum dpu_dsc { 165 DSC_NONE = 0, 166 DSC_0, 167 DSC_1, 168 DSC_2, 169 DSC_3, 170 DSC_4, 171 DSC_5, 172 DSC_MAX 173 }; 174 175 enum dpu_cdm { 176 CDM_0 = 1, 177 CDM_MAX 178 }; 179 180 enum dpu_pingpong { 181 PINGPONG_NONE, 182 PINGPONG_0, 183 PINGPONG_1, 184 PINGPONG_2, 185 PINGPONG_3, 186 PINGPONG_4, 187 PINGPONG_5, 188 PINGPONG_CWB_0, 189 PINGPONG_CWB_1, 190 PINGPONG_CWB_2, 191 PINGPONG_CWB_3, 192 PINGPONG_S0, 193 PINGPONG_MAX 194 }; 195 196 enum dpu_merge_3d { 197 MERGE_3D_0 = 1, 198 MERGE_3D_1, 199 MERGE_3D_2, 200 MERGE_3D_3, 201 MERGE_3D_4, 202 MERGE_3D_MAX 203 }; 204 205 enum dpu_intf { 206 INTF_0 = 1, 207 INTF_1, 208 INTF_2, 209 INTF_3, 210 INTF_4, 211 INTF_5, 212 INTF_6, 213 INTF_7, 214 INTF_8, 215 INTF_MAX 216 }; 217 218 /* 219 * Historically these values correspond to the values written to the 220 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 221 * generations this register is NOP, but we keep the values for historical 222 * reasons. 223 */ 224 enum dpu_intf_type { 225 INTF_NONE = 0x0, 226 INTF_DSI = 0x1, 227 INTF_HDMI = 0x3, 228 INTF_LCDC = 0x5, 229 /* old eDP found on 8x74 and 8x84 */ 230 INTF_EDP = 0x9, 231 /* both DP and eDP, handled by the new DP driver */ 232 INTF_DP = 0xa, 233 234 /* virtual interfaces */ 235 INTF_WB = 0x100, 236 }; 237 238 enum dpu_intf_mode { 239 INTF_MODE_NONE = 0, 240 INTF_MODE_CMD, 241 INTF_MODE_VIDEO, 242 INTF_MODE_WB_BLOCK, 243 INTF_MODE_WB_LINE, 244 INTF_MODE_MAX 245 }; 246 247 enum dpu_wb { 248 WB_0 = 1, 249 WB_1, 250 WB_2, 251 WB_3, 252 WB_MAX 253 }; 254 255 enum dpu_cwb { 256 CWB_0 = 0x1, 257 CWB_1, 258 CWB_2, 259 CWB_3, 260 CWB_MAX 261 }; 262 263 enum dpu_wd_timer { 264 WD_TIMER_0 = 0x1, 265 WD_TIMER_1, 266 WD_TIMER_2, 267 WD_TIMER_3, 268 WD_TIMER_4, 269 WD_TIMER_5, 270 WD_TIMER_MAX 271 }; 272 273 enum dpu_vbif { 274 VBIF_RT, 275 VBIF_NRT, 276 VBIF_MAX, 277 }; 278 279 /** 280 * enum dpu_3d_blend_mode 281 * Desribes how the 3d data is blended 282 * @BLEND_3D_NONE : 3d blending not enabled 283 * @BLEND_3D_FRAME_INT : Frame interleaving 284 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 285 * @BLEND_3D_V_ROW_INT : vertical row interleaving 286 * @BLEND_3D_COL_INT : column interleaving 287 * @BLEND_3D_MAX : 288 */ 289 enum dpu_3d_blend_mode { 290 BLEND_3D_NONE = 0, 291 BLEND_3D_FRAME_INT, 292 BLEND_3D_H_ROW_INT, 293 BLEND_3D_V_ROW_INT, 294 BLEND_3D_COL_INT, 295 BLEND_3D_MAX 296 }; 297 298 /** 299 * struct dpu_hw_fmt_layout - format information of the source pixel data 300 * @num_planes: number of planes (including meta data planes) 301 * @width: image width 302 * @height: image height 303 * @total_size: total size in bytes 304 * @plane_addr: address of each plane 305 * @plane_size: length of each plane 306 * @plane_pitch: pitch of each plane 307 */ 308 struct dpu_hw_fmt_layout { 309 uint32_t num_planes; 310 uint32_t width; 311 uint32_t height; 312 uint32_t total_size; 313 uint32_t plane_addr[DPU_MAX_PLANES]; 314 uint32_t plane_size[DPU_MAX_PLANES]; 315 uint32_t plane_pitch[DPU_MAX_PLANES]; 316 }; 317 318 struct dpu_csc_cfg { 319 /* matrix coefficients in S15.16 format */ 320 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 321 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 322 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 323 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 324 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 325 }; 326 327 /** 328 * struct dpu_mdss_color - mdss color description 329 * color 0 : green 330 * color 1 : blue 331 * color 2 : red 332 * color 3 : alpha 333 */ 334 struct dpu_mdss_color { 335 u32 color_0; 336 u32 color_1; 337 u32 color_2; 338 u32 color_3; 339 }; 340 341 /* 342 * Define bit masks for h/w logging. 343 */ 344 #define DPU_DBG_MASK_NONE (1 << 0) 345 #define DPU_DBG_MASK_INTF (1 << 1) 346 #define DPU_DBG_MASK_LM (1 << 2) 347 #define DPU_DBG_MASK_CTL (1 << 3) 348 #define DPU_DBG_MASK_PINGPONG (1 << 4) 349 #define DPU_DBG_MASK_SSPP (1 << 5) 350 #define DPU_DBG_MASK_WB (1 << 6) 351 #define DPU_DBG_MASK_TOP (1 << 7) 352 #define DPU_DBG_MASK_VBIF (1 << 8) 353 #define DPU_DBG_MASK_ROT (1 << 9) 354 #define DPU_DBG_MASK_DSPP (1 << 10) 355 #define DPU_DBG_MASK_DSC (1 << 11) 356 #define DPU_DBG_MASK_CDM (1 << 12) 357 #define DPU_DBG_MASK_CWB (1 << 13) 358 359 /** 360 * struct dpu_hw_tear_check - Struct contains parameters to configure 361 * tear-effect module. This structure is used to configure tear-check 362 * logic present either in ping-pong or in interface module. 363 * @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided 364 * by no of lines 365 * @sync_cfg_height: Total vertical lines (display height - 1) 366 * @vsync_init_val: Init value to which the read pointer gets loaded at 367 * vsync edge 368 * @sync_threshold_start: Read pointer threshold start ROI for write operation 369 * @sync_threshold_continue: The minimum number of lines the write pointer 370 * needs to be above the read pointer 371 * @start_pos: The position from which the start_threshold value is added 372 * @rd_ptr_irq: The read pointer line at which interrupt has to be generated 373 * @hw_vsync_mode: Sync with external frame sync input 374 */ 375 struct dpu_hw_tear_check { 376 /* 377 * This is ratio of MDP VSYNC clk freq(Hz) to 378 * refresh rate divided by no of lines 379 */ 380 u32 vsync_count; 381 u32 sync_cfg_height; 382 u32 vsync_init_val; 383 u32 sync_threshold_start; 384 u32 sync_threshold_continue; 385 u32 start_pos; 386 u32 rd_ptr_irq; 387 u8 hw_vsync_mode; 388 }; 389 390 /** 391 * struct dpu_hw_pp_vsync_info - Struct contains parameters to configure 392 * read and write pointers for command mode panels 393 * @rd_ptr_init_val: Value of rd pointer at vsync edge 394 * @rd_ptr_frame_count: Num frames sent since enabling interface 395 * @rd_ptr_line_count: Current line on panel (rd ptr) 396 * @wr_ptr_line_count: Current line within pp fifo (wr ptr) 397 * @intf_frame_count: Frames read from intf 398 */ 399 struct dpu_hw_pp_vsync_info { 400 u32 rd_ptr_init_val; 401 u32 rd_ptr_frame_count; 402 u32 rd_ptr_line_count; 403 u32 wr_ptr_line_count; 404 u32 intf_frame_count; 405 }; 406 407 #endif /* _DPU_HW_MDSS_H */ 408