1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, 2020-2025 Intel Corporation 4 */ 5 #ifndef __iwl_context_info_file_v2_h__ 6 #define __iwl_context_info_file_v2_h__ 7 8 #include "iwl-context-info.h" 9 10 #define CSR_CTXT_INFO_BOOT_CTRL 0x0 11 #define CSR_CTXT_INFO_ADDR 0x118 12 #define CSR_IML_DATA_ADDR 0x120 13 #define CSR_IML_SIZE_ADDR 0x128 14 #define CSR_IML_RESP_ADDR 0x12c 15 16 #define UNFRAGMENTED_PNVM_PAYLOADS_NUMBER 2 17 18 /* Set bit for enabling automatic function boot */ 19 #define CSR_AUTO_FUNC_BOOT_ENA BIT(1) 20 /* Set bit for initiating function boot */ 21 #define CSR_AUTO_FUNC_INIT BIT(7) 22 23 /** 24 * enum iwl_prph_scratch_mtr_format - tfd size configuration 25 * @IWL_PRPH_MTR_FORMAT_16B: 16 bit tfd 26 * @IWL_PRPH_MTR_FORMAT_32B: 32 bit tfd 27 * @IWL_PRPH_MTR_FORMAT_64B: 64 bit tfd 28 * @IWL_PRPH_MTR_FORMAT_256B: 256 bit tfd 29 */ 30 enum iwl_prph_scratch_mtr_format { 31 IWL_PRPH_MTR_FORMAT_16B = 0x0, 32 IWL_PRPH_MTR_FORMAT_32B = 0x40000, 33 IWL_PRPH_MTR_FORMAT_64B = 0x80000, 34 IWL_PRPH_MTR_FORMAT_256B = 0xC0000, 35 }; 36 37 /** 38 * enum iwl_prph_scratch_flags - PRPH scratch control flags 39 * @IWL_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 40 * @IWL_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 41 * @IWL_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 42 * in hwm config. 43 * @IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 44 * @IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 45 * multicomm. 46 * @IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 47 * @IWL_PRPH_SCRATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 48 * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 49 * completion descriptor, 1 for responses (legacy) 50 * @IWL_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 51 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 52 * 3: 256 bit. 53 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 54 * by older firmware versions, so set IWL_PRPH_SCRATCH_RB_SIZE_4K 55 * appropriately; use the below values for this. 56 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 57 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 58 * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 59 * @IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE: Indicate fw to set SCU_FORCE_ACTIVE 60 * upon reset. 61 * @IWL_PRPH_SCRATCH_TOP_RESET: request TOP reset 62 */ 63 enum iwl_prph_scratch_flags { 64 IWL_PRPH_SCRATCH_IMR_DEBUG_EN = BIT(1), 65 IWL_PRPH_SCRATCH_EARLY_DEBUG_EN = BIT(4), 66 IWL_PRPH_SCRATCH_EDBG_DEST_DRAM = BIT(8), 67 IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL = BIT(9), 68 IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER = BIT(10), 69 IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF = BIT(11), 70 IWL_PRPH_SCRATCH_RB_SIZE_4K = BIT(16), 71 IWL_PRPH_SCRATCH_MTR_MODE = BIT(17), 72 IWL_PRPH_SCRATCH_MTR_FORMAT = BIT(18) | BIT(19), 73 IWL_PRPH_SCRATCH_RB_SIZE_EXT_MASK = 0xf << 20, 74 IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K = 8 << 20, 75 IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K = 9 << 20, 76 IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K = 10 << 20, 77 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE = BIT(29), 78 IWL_PRPH_SCRATCH_TOP_RESET = BIT(30), 79 }; 80 81 /** 82 * enum iwl_prph_scratch_ext_flags - PRPH scratch control ext flags 83 * @IWL_PRPH_SCRATCH_EXT_EXT_FSEQ: external FSEQ image provided 84 * @IWL_PRPH_SCRATCH_EXT_URM_FW: switch to URM mode based on fw setting 85 * @IWL_PRPH_SCRATCH_EXT_URM_PERM: switch to permanent URM mode 86 * @IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID: use external 32 KHz clock 87 */ 88 enum iwl_prph_scratch_ext_flags { 89 IWL_PRPH_SCRATCH_EXT_EXT_FSEQ = BIT(0), 90 IWL_PRPH_SCRATCH_EXT_URM_FW = BIT(4), 91 IWL_PRPH_SCRATCH_EXT_URM_PERM = BIT(5), 92 IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID = BIT(8), 93 }; 94 95 /** 96 * struct iwl_prph_scratch_version - version structure 97 * @mac_id: SKU and revision id 98 * @version: prph scratch information version id 99 * @size: the size of the context information in DWs 100 * @reserved: reserved 101 */ 102 struct iwl_prph_scratch_version { 103 __le16 mac_id; 104 __le16 version; 105 __le16 size; 106 __le16 reserved; 107 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 108 109 /** 110 * struct iwl_prph_scratch_control - control structure 111 * @control_flags: context information flags see &enum iwl_prph_scratch_flags 112 * @control_flags_ext: context information for extended flags, 113 * see &enum iwl_prph_scratch_ext_flags 114 */ 115 struct iwl_prph_scratch_control { 116 __le32 control_flags; 117 __le32 control_flags_ext; 118 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 119 120 /** 121 * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch 122 * @pnvm_base_addr: PNVM start address 123 * @pnvm_size: the size of the PNVM image in bytes 124 * @reserved: reserved 125 */ 126 struct iwl_prph_scratch_pnvm_cfg { 127 __le64 pnvm_base_addr; 128 __le32 pnvm_size; 129 __le32 reserved; 130 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 131 132 /** 133 * struct iwl_prph_scratch_mem_desc_addr_array - DRAM 134 * @mem_descs: array of dram addresses. 135 * Each address is the beginning of a PNVM payload. 136 */ 137 struct iwl_prph_scratch_mem_desc_addr_array { 138 __le64 mem_descs[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 139 } __packed; /* PERIPH_SCRATCH_MEM_DESC_ADDR_ARRAY_S_VER_1 */ 140 141 /** 142 * struct iwl_prph_scratch_hwm_cfg - hwm config 143 * @hwm_base_addr: hwm start address 144 * @hwm_size: hwm size in DWs 145 * @debug_token_config: debug preset 146 */ 147 struct iwl_prph_scratch_hwm_cfg { 148 __le64 hwm_base_addr; 149 __le32 hwm_size; 150 __le32 debug_token_config; 151 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 152 153 /** 154 * struct iwl_prph_scratch_rbd_cfg - RBDs configuration 155 * @free_rbd_addr: default queue free RB CB base address 156 * @reserved: reserved 157 */ 158 struct iwl_prph_scratch_rbd_cfg { 159 __le64 free_rbd_addr; 160 __le32 reserved; 161 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 162 163 /** 164 * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table 165 * @base_addr: reduce power table address 166 * @size: the size of the entire power table image 167 * @reserved: (reserved) 168 */ 169 struct iwl_prph_scratch_uefi_cfg { 170 __le64 base_addr; 171 __le32 size; 172 __le32 reserved; 173 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 174 175 /** 176 * struct iwl_prph_scratch_step_cfg - prph scratch step configuration 177 * @mbx_addr_0: [0:7] revision, 178 * [8:15] cnvi_to_cnvr length, 179 * [16:23] cnvr_to_cnvi channel length, 180 * [24:31] radio1 reserved 181 * @mbx_addr_1: [0:7] radio2 reserved 182 */ 183 184 struct iwl_prph_scratch_step_cfg { 185 __le32 mbx_addr_0; 186 __le32 mbx_addr_1; 187 } __packed; 188 189 /** 190 * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config 191 * @version: version information of context info and HW 192 * @control: control flags of FH configurations 193 * @pnvm_cfg: ror configuration 194 * @hwm_cfg: hwm configuration 195 * @rbd_cfg: default RX queue configuration 196 * @reduce_power_cfg: UEFI power reduction table 197 * @step_cfg: step configuration 198 */ 199 struct iwl_prph_scratch_ctrl_cfg { 200 struct iwl_prph_scratch_version version; 201 struct iwl_prph_scratch_control control; 202 struct iwl_prph_scratch_pnvm_cfg pnvm_cfg; 203 struct iwl_prph_scratch_hwm_cfg hwm_cfg; 204 struct iwl_prph_scratch_rbd_cfg rbd_cfg; 205 struct iwl_prph_scratch_uefi_cfg reduce_power_cfg; 206 struct iwl_prph_scratch_step_cfg step_cfg; 207 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 208 209 #define IWL_NUM_DRAM_FSEQ_ENTRIES 8 210 211 /** 212 * struct iwl_context_info_dram_fseq - images DRAM map (with fseq) 213 * each entry in the map represents a DRAM chunk of up to 32 KB 214 * @common: UMAC/LMAC/virtual images 215 * @fseq_img: FSEQ image DRAM map 216 */ 217 struct iwl_context_info_dram_fseq { 218 struct iwl_context_info_dram_nonfseq common; 219 __le64 fseq_img[IWL_NUM_DRAM_FSEQ_ENTRIES]; 220 } __packed; /* PERIPH_SCRATCH_DRAM_MAP_S */ 221 222 /** 223 * struct iwl_prph_scratch - peripheral scratch mapping 224 * @ctrl_cfg: control and configuration of prph scratch 225 * @dram: firmware images addresses in DRAM 226 * @fseq_override: FSEQ override parameters 227 * @step_analog_params: STEP analog calibration values 228 * @reserved: reserved 229 */ 230 struct iwl_prph_scratch { 231 struct iwl_prph_scratch_ctrl_cfg ctrl_cfg; 232 __le32 fseq_override; 233 __le32 step_analog_params; 234 __le32 reserved[8]; 235 struct iwl_context_info_dram_fseq dram; 236 } __packed; /* PERIPH_SCRATCH_S */ 237 238 /** 239 * struct iwl_prph_info - peripheral information 240 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 241 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 242 * @sleep_notif: indicates the peripheral sleep status 243 * @reserved: reserved 244 */ 245 struct iwl_prph_info { 246 __le32 boot_stage_mirror; 247 __le32 ipc_status_mirror; 248 __le32 sleep_notif; 249 __le32 reserved; 250 } __packed; /* PERIPH_INFO_S */ 251 252 /** 253 * struct iwl_context_info_v2 - device INIT configuration 254 * @version: version of the context information 255 * @size: size of context information in DWs 256 * @config: context in which the peripheral would execute - a subset of 257 * capability csr register published by the peripheral 258 * @prph_info_base_addr: the peripheral information structure start address 259 * @cr_head_idx_arr_base_addr: the completion ring head index array 260 * start address 261 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 262 * start address 263 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 264 * start address 265 * @tr_head_idx_arr_base_addr: the transfer ring head index array 266 * start address 267 * @cr_idx_arr_size: number of entries in the completion ring index array 268 * @tr_idx_arr_size: number of entries in the transfer ring index array 269 * @mtr_base_addr: the message transfer ring start address 270 * @mcr_base_addr: the message completion ring start address 271 * @mtr_size: number of entries which the message transfer ring can hold 272 * @mcr_size: number of entries which the message completion ring can hold 273 * @mtr_doorbell_vec: the doorbell vector associated with the message 274 * transfer ring 275 * @mcr_doorbell_vec: the doorbell vector associated with the message 276 * completion ring 277 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 278 * completing a transfer descriptor in the message transfer ring 279 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 280 * completing a completion descriptor in the message completion ring 281 * @mtr_opt_header_size: the size of the optional header in the transfer 282 * descriptor associated with the message transfer ring in DWs 283 * @mtr_opt_footer_size: the size of the optional footer in the transfer 284 * descriptor associated with the message transfer ring in DWs 285 * @mcr_opt_header_size: the size of the optional header in the completion 286 * descriptor associated with the message completion ring in DWs 287 * @mcr_opt_footer_size: the size of the optional footer in the completion 288 * descriptor associated with the message completion ring in DWs 289 * @msg_rings_ctrl_flags: message rings control flags 290 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 291 * after updating the Peripheral Information structure 292 * @prph_scratch_base_addr: the peripheral scratch structure start address 293 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 294 * @reserved: reserved 295 */ 296 struct iwl_context_info_v2 { 297 __le16 version; 298 __le16 size; 299 __le32 config; 300 __le64 prph_info_base_addr; 301 __le64 cr_head_idx_arr_base_addr; 302 __le64 tr_tail_idx_arr_base_addr; 303 __le64 cr_tail_idx_arr_base_addr; 304 __le64 tr_head_idx_arr_base_addr; 305 __le16 cr_idx_arr_size; 306 __le16 tr_idx_arr_size; 307 __le64 mtr_base_addr; 308 __le64 mcr_base_addr; 309 __le16 mtr_size; 310 __le16 mcr_size; 311 __le16 mtr_doorbell_vec; 312 __le16 mcr_doorbell_vec; 313 __le16 mtr_msi_vec; 314 __le16 mcr_msi_vec; 315 u8 mtr_opt_header_size; 316 u8 mtr_opt_footer_size; 317 u8 mcr_opt_header_size; 318 u8 mcr_opt_footer_size; 319 __le16 msg_rings_ctrl_flags; 320 __le16 prph_info_msi_vec; 321 __le64 prph_scratch_base_addr; 322 __le32 prph_scratch_size; 323 __le32 reserved; 324 } __packed; /* IPC_CONTEXT_INFO_S */ 325 326 int iwl_pcie_ctxt_info_v2_alloc(struct iwl_trans *trans, 327 const struct iwl_fw *fw, 328 const struct fw_img *img); 329 void iwl_pcie_ctxt_info_v2_kick(struct iwl_trans *trans); 330 void iwl_pcie_ctxt_info_v2_free(struct iwl_trans *trans, bool alive); 331 332 int iwl_trans_pcie_ctx_info_v2_load_pnvm(struct iwl_trans *trans, 333 const struct iwl_pnvm_image *pnvm_payloads, 334 const struct iwl_ucode_capabilities *capa); 335 void iwl_trans_pcie_ctx_info_v2_set_pnvm(struct iwl_trans *trans, 336 const struct iwl_ucode_capabilities *capa); 337 int 338 iwl_trans_pcie_ctx_info_v2_load_reduce_power(struct iwl_trans *trans, 339 const struct iwl_pnvm_image *payloads, 340 const struct iwl_ucode_capabilities *capa); 341 void 342 iwl_trans_pcie_ctx_info_v2_set_reduce_power(struct iwl_trans *trans, 343 const struct iwl_ucode_capabilities *capa); 344 #endif /* __iwl_context_info_file_v2_h__ */ 345