1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/clk-provider.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of_clk.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <sound/soc.h>
16 #include <sound/soc-dapm.h>
17 #include <sound/tlv.h>
18
19 #include "lpass-macro-common.h"
20
21 /* VA macro registers */
22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
23 #define CDC_VA_MCLK_CONTROL_EN BIT(0)
24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
25 #define CDC_VA_FS_CONTROL_EN BIT(0)
26 #define CDC_VA_FS_COUNTER_CLR BIT(1)
27 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008)
28 #define CDC_VA_SWR_RESET_MASK BIT(1)
29 #define CDC_VA_SWR_RESET_ENABLE BIT(1)
30 #define CDC_VA_SWR_CLK_EN_MASK BIT(0)
31 #define CDC_VA_SWR_CLK_ENABLE BIT(0)
32 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080)
33 #define CDC_VA_FS_BROADCAST_EN BIT(1)
34 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084)
35 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088)
36 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C)
37 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090)
38 #define CDC_VA_DMIC_EN_MASK BIT(0)
39 #define CDC_VA_DMIC_ENABLE BIT(0)
40 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1)
41 #define CDC_VA_DMIC_CLK_SEL_SHFT 1
42 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0
43 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2
44 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4
45 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6
46 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8
47 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa
48 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094)
49 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7)
50 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7)
51 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0
52 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3)
53 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3)
54 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2)
55 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2)
56 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1)
57 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1)
58 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0)
59 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0)
60 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0
61 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C)
62 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0)
63 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4)
64 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8)
65 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC)
66 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0)
67 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4)
68 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8)
69 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC)
70 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0)
71 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4)
72 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8)
73 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK (0xEE)
74 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1 (0xCC)
75 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC)
76 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100)
77 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104)
78 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108)
79 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C)
80 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110)
81 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114)
82 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118)
83 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C)
84 #define CDC_VA_TX0_TX_PATH_CTL (0x0400)
85 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5)
86 #define CDC_VA_TX_PATH_CLK_EN BIT(5)
87 #define CDC_VA_TX_PATH_CLK_DISABLE 0
88 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4)
89 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4)
90 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0
91 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404)
92 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1)
93 #define CDC_VA_ADC_MODE_SHIFT 1
94 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5)
95 #define CF_MIN_3DB_4HZ 0x0
96 #define CF_MIN_3DB_75HZ 0x1
97 #define CF_MIN_3DB_150HZ 0x2
98 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408)
99 #define CDC_VA_TX0_TX_VOL_CTL (0x040C)
100 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410)
101 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414)
102 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418)
103 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1)
104 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1)
105 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0)
106 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0)
107 #define CDC_VA_TX_HPF_ZERO_GATE 0
108 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C)
109 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420)
110 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424)
111 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428)
112 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C)
113 #define CDC_VA_TX1_TX_PATH_CTL (0x0480)
114 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484)
115 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488)
116 #define CDC_VA_TX1_TX_VOL_CTL (0x048C)
117 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490)
118 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494)
119 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498)
120 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C)
121 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0)
122 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4)
123 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8)
124 #define CDC_VA_TX2_TX_PATH_CTL (0x0500)
125 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504)
126 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508)
127 #define CDC_VA_TX2_TX_VOL_CTL (0x050C)
128 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510)
129 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514)
130 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518)
131 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C)
132 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520)
133 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524)
134 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528)
135 #define CDC_VA_TX3_TX_PATH_CTL (0x0580)
136 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584)
137 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7)
138 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7)
139 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0
140 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588)
141 #define CDC_VA_TX3_TX_VOL_CTL (0x058C)
142 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590)
143 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594)
144 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598)
145 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C)
146 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0)
147 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4)
148 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8)
149
150 #define VA_MAX_OFFSET (0x07A8)
151
152 #define VA_MACRO_NUM_DECIMATORS 4
153 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
154 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
155 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
156 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
157 SNDRV_PCM_FMTBIT_S24_LE |\
158 SNDRV_PCM_FMTBIT_S24_3LE)
159
160 #define VA_MACRO_MCLK_FREQ 9600000
161 #define VA_MACRO_TX_PATH_OFFSET 0x80
162 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF
163 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8
164
165 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
166
167 enum {
168 VA_MACRO_AIF1_CAP,
169 VA_MACRO_AIF2_CAP,
170 VA_MACRO_AIF3_CAP,
171 VA_MACRO_MAX_DAIS,
172 };
173
174 enum {
175 VA_MACRO_DEC0,
176 VA_MACRO_DEC1,
177 VA_MACRO_DEC2,
178 VA_MACRO_DEC3,
179 VA_MACRO_DEC4,
180 VA_MACRO_DEC5,
181 VA_MACRO_DEC6,
182 VA_MACRO_DEC7,
183 VA_MACRO_DEC_MAX,
184 };
185
186 enum {
187 VA_MACRO_CLK_DIV_2,
188 VA_MACRO_CLK_DIV_3,
189 VA_MACRO_CLK_DIV_4,
190 VA_MACRO_CLK_DIV_6,
191 VA_MACRO_CLK_DIV_8,
192 VA_MACRO_CLK_DIV_16,
193 };
194
195 #define VA_NUM_CLKS_MAX 3
196
197 struct va_macro {
198 struct device *dev;
199 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
200 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
201 u16 dmic_clk_div;
202 bool has_swr_master;
203 bool has_npl_clk;
204
205 int dec_mode[VA_MACRO_NUM_DECIMATORS];
206 struct regmap *regmap;
207 struct clk *mclk;
208 struct clk *npl;
209 struct clk *macro;
210 struct clk *dcodec;
211 struct clk *fsgen;
212 struct clk_hw hw;
213 struct lpass_macro *pds;
214
215 s32 dmic_0_1_clk_cnt;
216 s32 dmic_2_3_clk_cnt;
217 s32 dmic_4_5_clk_cnt;
218 s32 dmic_6_7_clk_cnt;
219 u8 dmic_0_1_clk_div;
220 u8 dmic_2_3_clk_div;
221 u8 dmic_4_5_clk_div;
222 u8 dmic_6_7_clk_div;
223 };
224
225 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw)
226
227 struct va_macro_data {
228 bool has_swr_master;
229 bool has_npl_clk;
230 int version;
231 };
232
233 static const struct va_macro_data sm8250_va_data = {
234 .has_swr_master = false,
235 .has_npl_clk = false,
236 .version = LPASS_CODEC_VERSION_1_0,
237 };
238
239 static const struct va_macro_data sm8450_va_data = {
240 .has_swr_master = true,
241 .has_npl_clk = true,
242 };
243
244 static const struct va_macro_data sm8550_va_data = {
245 .has_swr_master = true,
246 .has_npl_clk = false,
247 };
248
va_is_volatile_register(struct device * dev,unsigned int reg)249 static bool va_is_volatile_register(struct device *dev, unsigned int reg)
250 {
251 switch (reg) {
252 case CDC_VA_TOP_CSR_CORE_ID_0:
253 case CDC_VA_TOP_CSR_CORE_ID_1:
254 case CDC_VA_TOP_CSR_CORE_ID_2:
255 case CDC_VA_TOP_CSR_CORE_ID_3:
256 case CDC_VA_TOP_CSR_DMIC0_CTL:
257 case CDC_VA_TOP_CSR_DMIC1_CTL:
258 case CDC_VA_TOP_CSR_DMIC2_CTL:
259 case CDC_VA_TOP_CSR_DMIC3_CTL:
260 return true;
261 }
262 return false;
263 }
264
265 static const struct reg_default va_defaults[] = {
266 /* VA macro */
267 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
268 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
269 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
270 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
271 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
272 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
273 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
274 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
275 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
276 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
277 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
278 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
279 { CDC_VA_TOP_CSR_I2S_CLK, 0x00},
280 { CDC_VA_TOP_CSR_I2S_RESET, 0x00},
281 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
282 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
283 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
284 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
285 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
286 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
287 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
288 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
289
290 /* VA core */
291 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
292 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
293 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
294 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
295 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
296 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
297 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
298 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
299 { CDC_VA_TX0_TX_PATH_CTL, 0x04},
300 { CDC_VA_TX0_TX_PATH_CFG0, 0x10},
301 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
302 { CDC_VA_TX0_TX_VOL_CTL, 0x00},
303 { CDC_VA_TX0_TX_PATH_SEC0, 0x00},
304 { CDC_VA_TX0_TX_PATH_SEC1, 0x00},
305 { CDC_VA_TX0_TX_PATH_SEC2, 0x01},
306 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
307 { CDC_VA_TX0_TX_PATH_SEC4, 0x20},
308 { CDC_VA_TX0_TX_PATH_SEC5, 0x00},
309 { CDC_VA_TX0_TX_PATH_SEC6, 0x00},
310 { CDC_VA_TX0_TX_PATH_SEC7, 0x25},
311 { CDC_VA_TX1_TX_PATH_CTL, 0x04},
312 { CDC_VA_TX1_TX_PATH_CFG0, 0x10},
313 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
314 { CDC_VA_TX1_TX_VOL_CTL, 0x00},
315 { CDC_VA_TX1_TX_PATH_SEC0, 0x00},
316 { CDC_VA_TX1_TX_PATH_SEC1, 0x00},
317 { CDC_VA_TX1_TX_PATH_SEC2, 0x01},
318 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
319 { CDC_VA_TX1_TX_PATH_SEC4, 0x20},
320 { CDC_VA_TX1_TX_PATH_SEC5, 0x00},
321 { CDC_VA_TX1_TX_PATH_SEC6, 0x00},
322 { CDC_VA_TX2_TX_PATH_CTL, 0x04},
323 { CDC_VA_TX2_TX_PATH_CFG0, 0x10},
324 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
325 { CDC_VA_TX2_TX_VOL_CTL, 0x00},
326 { CDC_VA_TX2_TX_PATH_SEC0, 0x00},
327 { CDC_VA_TX2_TX_PATH_SEC1, 0x00},
328 { CDC_VA_TX2_TX_PATH_SEC2, 0x01},
329 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
330 { CDC_VA_TX2_TX_PATH_SEC4, 0x20},
331 { CDC_VA_TX2_TX_PATH_SEC5, 0x00},
332 { CDC_VA_TX2_TX_PATH_SEC6, 0x00},
333 { CDC_VA_TX3_TX_PATH_CTL, 0x04},
334 { CDC_VA_TX3_TX_PATH_CFG0, 0x10},
335 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
336 { CDC_VA_TX3_TX_VOL_CTL, 0x00},
337 { CDC_VA_TX3_TX_PATH_SEC0, 0x00},
338 { CDC_VA_TX3_TX_PATH_SEC1, 0x00},
339 { CDC_VA_TX3_TX_PATH_SEC2, 0x01},
340 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
341 { CDC_VA_TX3_TX_PATH_SEC4, 0x20},
342 { CDC_VA_TX3_TX_PATH_SEC5, 0x00},
343 { CDC_VA_TX3_TX_PATH_SEC6, 0x00},
344 };
345
va_is_rw_register(struct device * dev,unsigned int reg)346 static bool va_is_rw_register(struct device *dev, unsigned int reg)
347 {
348 switch (reg) {
349 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL:
350 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL:
351 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL:
352 case CDC_VA_TOP_CSR_TOP_CFG0:
353 case CDC_VA_TOP_CSR_DMIC0_CTL:
354 case CDC_VA_TOP_CSR_DMIC1_CTL:
355 case CDC_VA_TOP_CSR_DMIC2_CTL:
356 case CDC_VA_TOP_CSR_DMIC3_CTL:
357 case CDC_VA_TOP_CSR_DMIC_CFG:
358 case CDC_VA_TOP_CSR_SWR_MIC_CTL0:
359 case CDC_VA_TOP_CSR_SWR_MIC_CTL1:
360 case CDC_VA_TOP_CSR_SWR_MIC_CTL2:
361 case CDC_VA_TOP_CSR_DEBUG_BUS:
362 case CDC_VA_TOP_CSR_DEBUG_EN:
363 case CDC_VA_TOP_CSR_TX_I2S_CTL:
364 case CDC_VA_TOP_CSR_I2S_CLK:
365 case CDC_VA_TOP_CSR_I2S_RESET:
366 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
367 case CDC_VA_INP_MUX_ADC_MUX0_CFG1:
368 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
369 case CDC_VA_INP_MUX_ADC_MUX1_CFG1:
370 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
371 case CDC_VA_INP_MUX_ADC_MUX2_CFG1:
372 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
373 case CDC_VA_INP_MUX_ADC_MUX3_CFG1:
374 case CDC_VA_TX0_TX_PATH_CTL:
375 case CDC_VA_TX0_TX_PATH_CFG0:
376 case CDC_VA_TX0_TX_PATH_CFG1:
377 case CDC_VA_TX0_TX_VOL_CTL:
378 case CDC_VA_TX0_TX_PATH_SEC0:
379 case CDC_VA_TX0_TX_PATH_SEC1:
380 case CDC_VA_TX0_TX_PATH_SEC2:
381 case CDC_VA_TX0_TX_PATH_SEC3:
382 case CDC_VA_TX0_TX_PATH_SEC4:
383 case CDC_VA_TX0_TX_PATH_SEC5:
384 case CDC_VA_TX0_TX_PATH_SEC6:
385 case CDC_VA_TX0_TX_PATH_SEC7:
386 case CDC_VA_TX1_TX_PATH_CTL:
387 case CDC_VA_TX1_TX_PATH_CFG0:
388 case CDC_VA_TX1_TX_PATH_CFG1:
389 case CDC_VA_TX1_TX_VOL_CTL:
390 case CDC_VA_TX1_TX_PATH_SEC0:
391 case CDC_VA_TX1_TX_PATH_SEC1:
392 case CDC_VA_TX1_TX_PATH_SEC2:
393 case CDC_VA_TX1_TX_PATH_SEC3:
394 case CDC_VA_TX1_TX_PATH_SEC4:
395 case CDC_VA_TX1_TX_PATH_SEC5:
396 case CDC_VA_TX1_TX_PATH_SEC6:
397 case CDC_VA_TX2_TX_PATH_CTL:
398 case CDC_VA_TX2_TX_PATH_CFG0:
399 case CDC_VA_TX2_TX_PATH_CFG1:
400 case CDC_VA_TX2_TX_VOL_CTL:
401 case CDC_VA_TX2_TX_PATH_SEC0:
402 case CDC_VA_TX2_TX_PATH_SEC1:
403 case CDC_VA_TX2_TX_PATH_SEC2:
404 case CDC_VA_TX2_TX_PATH_SEC3:
405 case CDC_VA_TX2_TX_PATH_SEC4:
406 case CDC_VA_TX2_TX_PATH_SEC5:
407 case CDC_VA_TX2_TX_PATH_SEC6:
408 case CDC_VA_TX3_TX_PATH_CTL:
409 case CDC_VA_TX3_TX_PATH_CFG0:
410 case CDC_VA_TX3_TX_PATH_CFG1:
411 case CDC_VA_TX3_TX_VOL_CTL:
412 case CDC_VA_TX3_TX_PATH_SEC0:
413 case CDC_VA_TX3_TX_PATH_SEC1:
414 case CDC_VA_TX3_TX_PATH_SEC2:
415 case CDC_VA_TX3_TX_PATH_SEC3:
416 case CDC_VA_TX3_TX_PATH_SEC4:
417 case CDC_VA_TX3_TX_PATH_SEC5:
418 case CDC_VA_TX3_TX_PATH_SEC6:
419 return true;
420 }
421
422 return false;
423 }
424
va_is_readable_register(struct device * dev,unsigned int reg)425 static bool va_is_readable_register(struct device *dev, unsigned int reg)
426 {
427 switch (reg) {
428 case CDC_VA_TOP_CSR_CORE_ID_0:
429 case CDC_VA_TOP_CSR_CORE_ID_1:
430 case CDC_VA_TOP_CSR_CORE_ID_2:
431 case CDC_VA_TOP_CSR_CORE_ID_3:
432 return true;
433 }
434
435 return va_is_rw_register(dev, reg);
436 }
437
438 static const struct regmap_config va_regmap_config = {
439 .name = "va_macro",
440 .reg_bits = 32,
441 .val_bits = 32,
442 .reg_stride = 4,
443 .cache_type = REGCACHE_FLAT,
444 .reg_defaults = va_defaults,
445 .num_reg_defaults = ARRAY_SIZE(va_defaults),
446 .max_register = VA_MAX_OFFSET,
447 .volatile_reg = va_is_volatile_register,
448 .readable_reg = va_is_readable_register,
449 .writeable_reg = va_is_rw_register,
450 };
451
va_clk_rsc_fs_gen_request(struct va_macro * va,bool enable)452 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)
453 {
454 struct regmap *regmap = va->regmap;
455
456 if (enable) {
457 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
458 CDC_VA_MCLK_CONTROL_EN,
459 CDC_VA_MCLK_CONTROL_EN);
460 /* clear the fs counter */
461 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
462 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
463 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR);
464 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
465 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR,
466 CDC_VA_FS_CONTROL_EN);
467
468 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
469 CDC_VA_FS_BROADCAST_EN,
470 CDC_VA_FS_BROADCAST_EN);
471 } else {
472 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL,
473 CDC_VA_MCLK_CONTROL_EN, 0x0);
474
475 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL,
476 CDC_VA_FS_CONTROL_EN, 0x0);
477
478 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0,
479 CDC_VA_FS_BROADCAST_EN, 0x0);
480 }
481
482 return 0;
483 }
484
va_macro_mclk_enable(struct va_macro * va,bool mclk_enable)485 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)
486 {
487 struct regmap *regmap = va->regmap;
488
489 if (mclk_enable) {
490 va_clk_rsc_fs_gen_request(va, true);
491 regcache_mark_dirty(regmap);
492 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET);
493 } else {
494 va_clk_rsc_fs_gen_request(va, false);
495 }
496
497 return 0;
498 }
499
va_macro_mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)500 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w,
501 struct snd_kcontrol *kcontrol, int event)
502 {
503 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
504 struct va_macro *va = snd_soc_component_get_drvdata(comp);
505
506 switch (event) {
507 case SND_SOC_DAPM_PRE_PMU:
508 return clk_prepare_enable(va->fsgen);
509 case SND_SOC_DAPM_POST_PMD:
510 clk_disable_unprepare(va->fsgen);
511 }
512
513 return 0;
514 }
515
va_macro_put_dec_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)516 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
517 struct snd_ctl_elem_value *ucontrol)
518 {
519 struct snd_soc_dapm_widget *widget =
520 snd_soc_dapm_kcontrol_widget(kcontrol);
521 struct snd_soc_component *component =
522 snd_soc_dapm_to_component(widget->dapm);
523 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
524 unsigned int val;
525 u16 mic_sel_reg;
526
527 val = ucontrol->value.enumerated.item[0];
528
529 switch (e->reg) {
530 case CDC_VA_INP_MUX_ADC_MUX0_CFG0:
531 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0;
532 break;
533 case CDC_VA_INP_MUX_ADC_MUX1_CFG0:
534 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0;
535 break;
536 case CDC_VA_INP_MUX_ADC_MUX2_CFG0:
537 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0;
538 break;
539 case CDC_VA_INP_MUX_ADC_MUX3_CFG0:
540 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0;
541 break;
542 default:
543 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
544 __func__, e->reg);
545 return -EINVAL;
546 }
547
548 if (val != 0)
549 snd_soc_component_update_bits(component, mic_sel_reg,
550 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK,
551 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC);
552
553 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
554 }
555
va_macro_tx_mixer_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)556 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
557 struct snd_ctl_elem_value *ucontrol)
558 {
559 struct snd_soc_dapm_widget *widget =
560 snd_soc_dapm_kcontrol_widget(kcontrol);
561 struct snd_soc_component *component =
562 snd_soc_dapm_to_component(widget->dapm);
563 struct soc_mixer_control *mc =
564 (struct soc_mixer_control *)kcontrol->private_value;
565 u32 dai_id = widget->shift;
566 u32 dec_id = mc->shift;
567 struct va_macro *va = snd_soc_component_get_drvdata(component);
568
569 if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
570 ucontrol->value.integer.value[0] = 1;
571 else
572 ucontrol->value.integer.value[0] = 0;
573
574 return 0;
575 }
576
va_macro_tx_mixer_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)577 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
578 struct snd_ctl_elem_value *ucontrol)
579 {
580 struct snd_soc_dapm_widget *widget =
581 snd_soc_dapm_kcontrol_widget(kcontrol);
582 struct snd_soc_component *component =
583 snd_soc_dapm_to_component(widget->dapm);
584 struct snd_soc_dapm_update *update = NULL;
585 struct soc_mixer_control *mc =
586 (struct soc_mixer_control *)kcontrol->private_value;
587 u32 dai_id = widget->shift;
588 u32 dec_id = mc->shift;
589 u32 enable = ucontrol->value.integer.value[0];
590 struct va_macro *va = snd_soc_component_get_drvdata(component);
591
592 if (enable) {
593 set_bit(dec_id, &va->active_ch_mask[dai_id]);
594 va->active_ch_cnt[dai_id]++;
595 } else {
596 clear_bit(dec_id, &va->active_ch_mask[dai_id]);
597 va->active_ch_cnt[dai_id]--;
598 }
599
600 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
601
602 return 0;
603 }
604
va_dmic_clk_enable(struct snd_soc_component * component,u32 dmic,bool enable)605 static int va_dmic_clk_enable(struct snd_soc_component *component,
606 u32 dmic, bool enable)
607 {
608 struct va_macro *va = snd_soc_component_get_drvdata(component);
609 u16 dmic_clk_reg;
610 s32 *dmic_clk_cnt;
611 u8 *dmic_clk_div;
612 u8 freq_change_mask;
613 u8 clk_div;
614
615 switch (dmic) {
616 case 0:
617 case 1:
618 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
619 dmic_clk_div = &(va->dmic_0_1_clk_div);
620 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL;
621 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK;
622 break;
623 case 2:
624 case 3:
625 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
626 dmic_clk_div = &(va->dmic_2_3_clk_div);
627 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL;
628 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK;
629 break;
630 case 4:
631 case 5:
632 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
633 dmic_clk_div = &(va->dmic_4_5_clk_div);
634 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL;
635 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK;
636 break;
637 case 6:
638 case 7:
639 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
640 dmic_clk_div = &(va->dmic_6_7_clk_div);
641 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL;
642 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK;
643 break;
644 default:
645 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
646 __func__);
647 return -EINVAL;
648 }
649
650 if (enable) {
651 clk_div = va->dmic_clk_div;
652 (*dmic_clk_cnt)++;
653 if (*dmic_clk_cnt == 1) {
654 snd_soc_component_update_bits(component,
655 CDC_VA_TOP_CSR_DMIC_CFG,
656 CDC_VA_RESET_ALL_DMICS_MASK,
657 CDC_VA_RESET_ALL_DMICS_DISABLE);
658 snd_soc_component_update_bits(component, dmic_clk_reg,
659 CDC_VA_DMIC_CLK_SEL_MASK,
660 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
661 snd_soc_component_update_bits(component, dmic_clk_reg,
662 CDC_VA_DMIC_EN_MASK,
663 CDC_VA_DMIC_ENABLE);
664 } else {
665 if (*dmic_clk_div > clk_div) {
666 snd_soc_component_update_bits(component,
667 CDC_VA_TOP_CSR_DMIC_CFG,
668 freq_change_mask,
669 freq_change_mask);
670 snd_soc_component_update_bits(component, dmic_clk_reg,
671 CDC_VA_DMIC_CLK_SEL_MASK,
672 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
673 snd_soc_component_update_bits(component,
674 CDC_VA_TOP_CSR_DMIC_CFG,
675 freq_change_mask,
676 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
677 } else {
678 clk_div = *dmic_clk_div;
679 }
680 }
681 *dmic_clk_div = clk_div;
682 } else {
683 (*dmic_clk_cnt)--;
684 if (*dmic_clk_cnt == 0) {
685 snd_soc_component_update_bits(component, dmic_clk_reg,
686 CDC_VA_DMIC_EN_MASK, 0);
687 clk_div = 0;
688 snd_soc_component_update_bits(component, dmic_clk_reg,
689 CDC_VA_DMIC_CLK_SEL_MASK,
690 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
691 } else {
692 clk_div = va->dmic_clk_div;
693 if (*dmic_clk_div > clk_div) {
694 clk_div = va->dmic_clk_div;
695 snd_soc_component_update_bits(component,
696 CDC_VA_TOP_CSR_DMIC_CFG,
697 freq_change_mask,
698 freq_change_mask);
699 snd_soc_component_update_bits(component, dmic_clk_reg,
700 CDC_VA_DMIC_CLK_SEL_MASK,
701 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT);
702 snd_soc_component_update_bits(component,
703 CDC_VA_TOP_CSR_DMIC_CFG,
704 freq_change_mask,
705 CDC_VA_DMIC_FREQ_CHANGE_DISABLE);
706 } else {
707 clk_div = *dmic_clk_div;
708 }
709 }
710 *dmic_clk_div = clk_div;
711 }
712
713 return 0;
714 }
715
va_macro_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)716 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w,
717 struct snd_kcontrol *kcontrol, int event)
718 {
719 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
720 unsigned int dmic = w->shift;
721
722 switch (event) {
723 case SND_SOC_DAPM_PRE_PMU:
724 va_dmic_clk_enable(comp, dmic, true);
725 break;
726 case SND_SOC_DAPM_POST_PMD:
727 va_dmic_clk_enable(comp, dmic, false);
728 break;
729 }
730
731 return 0;
732 }
733
va_macro_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)734 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
735 struct snd_kcontrol *kcontrol, int event)
736 {
737 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
738 unsigned int decimator;
739 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg;
740 u16 tx_gain_ctl_reg;
741 u8 hpf_cut_off_freq;
742
743 struct va_macro *va = snd_soc_component_get_drvdata(comp);
744
745 decimator = w->shift;
746
747 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
748 VA_MACRO_TX_PATH_OFFSET * decimator;
749 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 +
750 VA_MACRO_TX_PATH_OFFSET * decimator;
751 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 +
752 VA_MACRO_TX_PATH_OFFSET * decimator;
753 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL +
754 VA_MACRO_TX_PATH_OFFSET * decimator;
755
756 switch (event) {
757 case SND_SOC_DAPM_PRE_PMU:
758 snd_soc_component_update_bits(comp,
759 dec_cfg_reg, CDC_VA_ADC_MODE_MASK,
760 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
761 /* Enable TX PGA Mute */
762 break;
763 case SND_SOC_DAPM_POST_PMU:
764 /* Enable TX CLK */
765 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
766 CDC_VA_TX_PATH_CLK_EN_MASK,
767 CDC_VA_TX_PATH_CLK_EN);
768 snd_soc_component_update_bits(comp, hpf_gate_reg,
769 CDC_VA_TX_HPF_ZERO_GATE_MASK,
770 CDC_VA_TX_HPF_ZERO_GATE);
771
772 usleep_range(1000, 1010);
773 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
774 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
775
776 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
777 snd_soc_component_update_bits(comp, dec_cfg_reg,
778 TX_HPF_CUT_OFF_FREQ_MASK,
779 CF_MIN_3DB_150HZ << 5);
780
781 snd_soc_component_update_bits(comp, hpf_gate_reg,
782 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
783 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ);
784
785 /*
786 * Minimum 1 clk cycle delay is required as per HW spec
787 */
788 usleep_range(1000, 1010);
789
790 snd_soc_component_update_bits(comp,
791 hpf_gate_reg,
792 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK,
793 0x0);
794 }
795
796
797 usleep_range(1000, 1010);
798 snd_soc_component_update_bits(comp, hpf_gate_reg,
799 CDC_VA_TX_HPF_ZERO_GATE_MASK,
800 CDC_VA_TX_HPF_ZERO_NO_GATE);
801 /*
802 * 6ms delay is required as per HW spec
803 */
804 usleep_range(6000, 6010);
805 /* apply gain after decimator is enabled */
806 snd_soc_component_write(comp, tx_gain_ctl_reg,
807 snd_soc_component_read(comp, tx_gain_ctl_reg));
808 break;
809 case SND_SOC_DAPM_POST_PMD:
810 /* Disable TX CLK */
811 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
812 CDC_VA_TX_PATH_CLK_EN_MASK,
813 CDC_VA_TX_PATH_CLK_DISABLE);
814 break;
815 }
816 return 0;
817 }
818
va_macro_dec_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)819 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
820 struct snd_ctl_elem_value *ucontrol)
821 {
822 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
823 struct va_macro *va = snd_soc_component_get_drvdata(comp);
824 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
825 int path = e->shift_l;
826
827 ucontrol->value.enumerated.item[0] = va->dec_mode[path];
828
829 return 0;
830 }
831
va_macro_dec_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)832 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
833 struct snd_ctl_elem_value *ucontrol)
834 {
835 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
836 int value = ucontrol->value.enumerated.item[0];
837 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
838 int path = e->shift_l;
839 struct va_macro *va = snd_soc_component_get_drvdata(comp);
840
841 va->dec_mode[path] = value;
842
843 return 0;
844 }
845
va_macro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)846 static int va_macro_hw_params(struct snd_pcm_substream *substream,
847 struct snd_pcm_hw_params *params,
848 struct snd_soc_dai *dai)
849 {
850 int tx_fs_rate;
851 struct snd_soc_component *component = dai->component;
852 u32 decimator, sample_rate;
853 u16 tx_fs_reg;
854 struct device *va_dev = component->dev;
855 struct va_macro *va = snd_soc_component_get_drvdata(component);
856
857 sample_rate = params_rate(params);
858 switch (sample_rate) {
859 case 8000:
860 tx_fs_rate = 0;
861 break;
862 case 16000:
863 tx_fs_rate = 1;
864 break;
865 case 32000:
866 tx_fs_rate = 3;
867 break;
868 case 48000:
869 tx_fs_rate = 4;
870 break;
871 case 96000:
872 tx_fs_rate = 5;
873 break;
874 case 192000:
875 tx_fs_rate = 6;
876 break;
877 case 384000:
878 tx_fs_rate = 7;
879 break;
880 default:
881 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
882 __func__, params_rate(params));
883 return -EINVAL;
884 }
885
886 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
887 VA_MACRO_DEC_MAX) {
888 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL +
889 VA_MACRO_TX_PATH_OFFSET * decimator;
890 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F,
891 tx_fs_rate);
892 }
893 return 0;
894 }
895
va_macro_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)896 static int va_macro_get_channel_map(const struct snd_soc_dai *dai,
897 unsigned int *tx_num, unsigned int *tx_slot,
898 unsigned int *rx_num, unsigned int *rx_slot)
899 {
900 struct snd_soc_component *component = dai->component;
901 struct device *va_dev = component->dev;
902 struct va_macro *va = snd_soc_component_get_drvdata(component);
903
904 switch (dai->id) {
905 case VA_MACRO_AIF1_CAP:
906 case VA_MACRO_AIF2_CAP:
907 case VA_MACRO_AIF3_CAP:
908 *tx_slot = va->active_ch_mask[dai->id];
909 *tx_num = va->active_ch_cnt[dai->id];
910 break;
911 default:
912 dev_err(va_dev, "%s: Invalid AIF\n", __func__);
913 break;
914 }
915 return 0;
916 }
917
va_macro_digital_mute(struct snd_soc_dai * dai,int mute,int stream)918 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
919 {
920 struct snd_soc_component *component = dai->component;
921 struct va_macro *va = snd_soc_component_get_drvdata(component);
922 u16 tx_vol_ctl_reg, decimator;
923
924 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
925 VA_MACRO_DEC_MAX) {
926 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
927 VA_MACRO_TX_PATH_OFFSET * decimator;
928 if (mute)
929 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
930 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
931 CDC_VA_TX_PATH_PGA_MUTE_EN);
932 else
933 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
934 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
935 CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
936 }
937
938 return 0;
939 }
940
941 static const struct snd_soc_dai_ops va_macro_dai_ops = {
942 .hw_params = va_macro_hw_params,
943 .get_channel_map = va_macro_get_channel_map,
944 .mute_stream = va_macro_digital_mute,
945 };
946
947 static struct snd_soc_dai_driver va_macro_dais[] = {
948 {
949 .name = "va_macro_tx1",
950 .id = VA_MACRO_AIF1_CAP,
951 .capture = {
952 .stream_name = "VA_AIF1 Capture",
953 .rates = VA_MACRO_RATES,
954 .formats = VA_MACRO_FORMATS,
955 .rate_max = 192000,
956 .rate_min = 8000,
957 .channels_min = 1,
958 .channels_max = 8,
959 },
960 .ops = &va_macro_dai_ops,
961 },
962 {
963 .name = "va_macro_tx2",
964 .id = VA_MACRO_AIF2_CAP,
965 .capture = {
966 .stream_name = "VA_AIF2 Capture",
967 .rates = VA_MACRO_RATES,
968 .formats = VA_MACRO_FORMATS,
969 .rate_max = 192000,
970 .rate_min = 8000,
971 .channels_min = 1,
972 .channels_max = 8,
973 },
974 .ops = &va_macro_dai_ops,
975 },
976 {
977 .name = "va_macro_tx3",
978 .id = VA_MACRO_AIF3_CAP,
979 .capture = {
980 .stream_name = "VA_AIF3 Capture",
981 .rates = VA_MACRO_RATES,
982 .formats = VA_MACRO_FORMATS,
983 .rate_max = 192000,
984 .rate_min = 8000,
985 .channels_min = 1,
986 .channels_max = 8,
987 },
988 .ops = &va_macro_dai_ops,
989 },
990 };
991
992 static const char * const adc_mux_text[] = {
993 "VA_DMIC", "SWR_MIC"
994 };
995
996 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1,
997 0, adc_mux_text);
998 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1,
999 0, adc_mux_text);
1000 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1,
1001 0, adc_mux_text);
1002 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1,
1003 0, adc_mux_text);
1004
1005 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0",
1006 va_dec0_enum);
1007 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1",
1008 va_dec1_enum);
1009 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2",
1010 va_dec2_enum);
1011 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3",
1012 va_dec3_enum);
1013
1014 static const char * const dmic_mux_text[] = {
1015 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1016 "DMIC4", "DMIC5", "DMIC6", "DMIC7"
1017 };
1018
1019 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0,
1020 4, dmic_mux_text);
1021
1022 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0,
1023 4, dmic_mux_text);
1024
1025 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0,
1026 4, dmic_mux_text);
1027
1028 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0,
1029 4, dmic_mux_text);
1030
1031 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0",
1032 va_dmic0_enum, snd_soc_dapm_get_enum_double,
1033 va_macro_put_dec_enum);
1034
1035 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1",
1036 va_dmic1_enum, snd_soc_dapm_get_enum_double,
1037 va_macro_put_dec_enum);
1038
1039 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2",
1040 va_dmic2_enum, snd_soc_dapm_get_enum_double,
1041 va_macro_put_dec_enum);
1042
1043 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3",
1044 va_dmic3_enum, snd_soc_dapm_get_enum_double,
1045 va_macro_put_dec_enum);
1046
1047 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = {
1048 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1049 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1050 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1051 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1052 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1053 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1054 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1055 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1056 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1058 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1059 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1060 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1061 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1062 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1063 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1064 };
1065
1066 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = {
1067 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1068 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1069 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1070 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1071 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1072 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1073 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1074 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1075 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1076 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1077 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1078 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1079 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1080 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1081 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1082 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1083 };
1084
1085 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = {
1086 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0,
1087 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1088 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0,
1089 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1090 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0,
1091 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1092 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0,
1093 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1094 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0,
1095 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1096 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0,
1097 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1098 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0,
1099 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1100 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0,
1101 va_macro_tx_mixer_get, va_macro_tx_mixer_put),
1102 };
1103
1104 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = {
1105 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0,
1106 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0),
1107
1108 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0,
1109 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0),
1110
1111 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0,
1112 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0),
1113
1114 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM,
1115 VA_MACRO_AIF1_CAP, 0,
1116 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)),
1117
1118 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM,
1119 VA_MACRO_AIF2_CAP, 0,
1120 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)),
1121
1122 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM,
1123 VA_MACRO_AIF3_CAP, 0,
1124 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)),
1125
1126 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1127 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1128 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1129 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1130
1131 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1132 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
1133 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
1134 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
1135 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
1136 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
1137 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
1138 SND_SOC_DAPM_INPUT("DMIC6 Pin"),
1139 SND_SOC_DAPM_INPUT("DMIC7 Pin"),
1140
1141 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1142 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1143 SND_SOC_DAPM_POST_PMD),
1144
1145 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1146 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1147 SND_SOC_DAPM_POST_PMD),
1148
1149 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1150 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1151 SND_SOC_DAPM_POST_PMD),
1152
1153 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1154 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1155 SND_SOC_DAPM_POST_PMD),
1156
1157 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1158 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1159 SND_SOC_DAPM_POST_PMD),
1160
1161 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1162 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1163 SND_SOC_DAPM_POST_PMD),
1164
1165 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1166 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1167 SND_SOC_DAPM_POST_PMD),
1168
1169 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1170 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU |
1171 SND_SOC_DAPM_POST_PMD),
1172
1173 SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1174 SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1175 SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1176 SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1177 SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1178 SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1179 SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1180 SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1181 SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1182 SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1183 SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1184 SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1185
1186 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1187 &va_dec0_mux, va_macro_enable_dec,
1188 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1189 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1190
1191 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1192 &va_dec1_mux, va_macro_enable_dec,
1193 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1194 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1195
1196 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1197 &va_dec2_mux, va_macro_enable_dec,
1198 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1199 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1200
1201 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1202 &va_dec3_mux, va_macro_enable_dec,
1203 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1204 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1205
1206 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1207 va_macro_mclk_event,
1208 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1209 };
1210
1211 static const struct snd_soc_dapm_route va_audio_map[] = {
1212 {"VA_AIF1 CAP", NULL, "VA_MCLK"},
1213 {"VA_AIF2 CAP", NULL, "VA_MCLK"},
1214 {"VA_AIF3 CAP", NULL, "VA_MCLK"},
1215
1216 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"},
1217 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"},
1218 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"},
1219
1220 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1221 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1222 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1223 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1224
1225 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1226 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1227 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1228 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1229
1230 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1231 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1232 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1233 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1234
1235 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1236 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1237 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1238 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1239 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1240 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1241 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1242 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1243 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1244
1245 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1246 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1247 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1248 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1249 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1250 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1251 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1252 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1253 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1254
1255 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1256 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1257 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1258 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1259 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1260 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1261 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1262 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1263 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1264
1265 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1266 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1267 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1268 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1269 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1270 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1271 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1272 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1273 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1274
1275 { "VA DMIC0", NULL, "DMIC0 Pin" },
1276 { "VA DMIC1", NULL, "DMIC1 Pin" },
1277 { "VA DMIC2", NULL, "DMIC2 Pin" },
1278 { "VA DMIC3", NULL, "DMIC3 Pin" },
1279 { "VA DMIC4", NULL, "DMIC4 Pin" },
1280 { "VA DMIC5", NULL, "DMIC5 Pin" },
1281 { "VA DMIC6", NULL, "DMIC6 Pin" },
1282 { "VA DMIC7", NULL, "DMIC7 Pin" },
1283 };
1284
1285 static const char * const dec_mode_mux_text[] = {
1286 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1287 };
1288
1289 static const struct soc_enum dec_mode_mux_enum[] = {
1290 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1291 dec_mode_mux_text),
1292 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1293 dec_mode_mux_text),
1294 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1295 dec_mode_mux_text),
1296 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1297 dec_mode_mux_text),
1298 };
1299
1300 static const struct snd_kcontrol_new va_macro_snd_controls[] = {
1301 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL,
1302 -84, 40, digital_gain),
1303 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL,
1304 -84, 40, digital_gain),
1305 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL,
1306 -84, 40, digital_gain),
1307 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL,
1308 -84, 40, digital_gain),
1309
1310 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0],
1311 va_macro_dec_mode_get, va_macro_dec_mode_put),
1312 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1],
1313 va_macro_dec_mode_get, va_macro_dec_mode_put),
1314 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2],
1315 va_macro_dec_mode_get, va_macro_dec_mode_put),
1316 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3],
1317 va_macro_dec_mode_get, va_macro_dec_mode_put),
1318 };
1319
va_macro_component_probe(struct snd_soc_component * component)1320 static int va_macro_component_probe(struct snd_soc_component *component)
1321 {
1322 struct va_macro *va = snd_soc_component_get_drvdata(component);
1323
1324 snd_soc_component_init_regmap(component, va->regmap);
1325
1326 return 0;
1327 }
1328
1329 static const struct snd_soc_component_driver va_macro_component_drv = {
1330 .name = "VA MACRO",
1331 .probe = va_macro_component_probe,
1332 .controls = va_macro_snd_controls,
1333 .num_controls = ARRAY_SIZE(va_macro_snd_controls),
1334 .dapm_widgets = va_macro_dapm_widgets,
1335 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets),
1336 .dapm_routes = va_audio_map,
1337 .num_dapm_routes = ARRAY_SIZE(va_audio_map),
1338 };
1339
fsgen_gate_enable(struct clk_hw * hw)1340 static int fsgen_gate_enable(struct clk_hw *hw)
1341 {
1342 struct va_macro *va = to_va_macro(hw);
1343 struct regmap *regmap = va->regmap;
1344 int ret;
1345
1346 if (va->has_swr_master) {
1347 ret = clk_prepare_enable(va->mclk);
1348 if (ret)
1349 return ret;
1350 }
1351
1352 ret = va_macro_mclk_enable(va, true);
1353 if (va->has_swr_master)
1354 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1355 CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
1356
1357 return ret;
1358 }
1359
fsgen_gate_disable(struct clk_hw * hw)1360 static void fsgen_gate_disable(struct clk_hw *hw)
1361 {
1362 struct va_macro *va = to_va_macro(hw);
1363 struct regmap *regmap = va->regmap;
1364
1365 if (va->has_swr_master)
1366 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1367 CDC_VA_SWR_CLK_EN_MASK, 0x0);
1368
1369 va_macro_mclk_enable(va, false);
1370 if (va->has_swr_master)
1371 clk_disable_unprepare(va->mclk);
1372 }
1373
fsgen_gate_is_enabled(struct clk_hw * hw)1374 static int fsgen_gate_is_enabled(struct clk_hw *hw)
1375 {
1376 struct va_macro *va = to_va_macro(hw);
1377 int val;
1378
1379 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1380
1381 return !!(val & CDC_VA_FS_BROADCAST_EN);
1382 }
1383
1384 static const struct clk_ops fsgen_gate_ops = {
1385 .prepare = fsgen_gate_enable,
1386 .unprepare = fsgen_gate_disable,
1387 .is_enabled = fsgen_gate_is_enabled,
1388 };
1389
va_macro_register_fsgen_output(struct va_macro * va)1390 static int va_macro_register_fsgen_output(struct va_macro *va)
1391 {
1392 struct clk *parent = va->mclk;
1393 struct device *dev = va->dev;
1394 struct device_node *np = dev->of_node;
1395 const char *parent_clk_name;
1396 const char *clk_name = "fsgen";
1397 struct clk_init_data init;
1398 int ret;
1399
1400 if (va->has_npl_clk)
1401 parent = va->npl;
1402
1403 parent_clk_name = __clk_get_name(parent);
1404
1405 of_property_read_string(np, "clock-output-names", &clk_name);
1406
1407 init.name = clk_name;
1408 init.ops = &fsgen_gate_ops;
1409 init.flags = 0;
1410 init.parent_names = &parent_clk_name;
1411 init.num_parents = 1;
1412 va->hw.init = &init;
1413 ret = devm_clk_hw_register(va->dev, &va->hw);
1414 if (ret)
1415 return ret;
1416
1417 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1418 }
1419
va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,struct va_macro * va)1420 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
1421 struct va_macro *va)
1422 {
1423 u32 div_factor;
1424 u32 mclk_rate = VA_MACRO_MCLK_FREQ;
1425
1426 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0)
1427 goto undefined_rate;
1428
1429 div_factor = mclk_rate / dmic_sample_rate;
1430
1431 switch (div_factor) {
1432 case 2:
1433 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1434 break;
1435 case 3:
1436 va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1437 break;
1438 case 4:
1439 va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1440 break;
1441 case 6:
1442 va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1443 break;
1444 case 8:
1445 va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1446 break;
1447 case 16:
1448 va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1449 break;
1450 default:
1451 /* Any other DIV factor is invalid */
1452 goto undefined_rate;
1453 }
1454
1455 return dmic_sample_rate;
1456
1457 undefined_rate:
1458 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1459 __func__, dmic_sample_rate, mclk_rate);
1460 dmic_sample_rate = 0;
1461
1462 return dmic_sample_rate;
1463 }
1464
va_macro_set_lpass_codec_version(struct va_macro * va)1465 static void va_macro_set_lpass_codec_version(struct va_macro *va)
1466 {
1467 int core_id_0 = 0, core_id_1 = 0, core_id_2 = 0;
1468 int version = LPASS_CODEC_VERSION_UNKNOWN;
1469
1470 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &core_id_0);
1471 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &core_id_1);
1472 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &core_id_2);
1473
1474 if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
1475 version = LPASS_CODEC_VERSION_2_0;
1476 if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && core_id_2 == 0x01)
1477 version = LPASS_CODEC_VERSION_2_0;
1478 if ((core_id_0 == 0x02) && (core_id_1 == 0x0E))
1479 version = LPASS_CODEC_VERSION_2_1;
1480 if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x50 || core_id_2 == 0x51))
1481 version = LPASS_CODEC_VERSION_2_5;
1482 if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x60 || core_id_2 == 0x61))
1483 version = LPASS_CODEC_VERSION_2_6;
1484 if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x70 || core_id_2 == 0x71))
1485 version = LPASS_CODEC_VERSION_2_7;
1486 if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
1487 version = LPASS_CODEC_VERSION_2_8;
1488
1489 if (version == LPASS_CODEC_VERSION_UNKNOWN)
1490 dev_warn(va->dev, "Unknown Codec version, ID: %02x / %02x / %02x\n",
1491 core_id_0, core_id_1, core_id_2);
1492
1493 lpass_macro_set_codec_version(version);
1494
1495 dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));
1496 }
1497
va_macro_probe(struct platform_device * pdev)1498 static int va_macro_probe(struct platform_device *pdev)
1499 {
1500 struct device *dev = &pdev->dev;
1501 const struct va_macro_data *data;
1502 struct va_macro *va;
1503 void __iomem *base;
1504 u32 sample_rate = 0;
1505 int ret;
1506
1507 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);
1508 if (!va)
1509 return -ENOMEM;
1510
1511 va->dev = dev;
1512
1513 va->macro = devm_clk_get_optional(dev, "macro");
1514 if (IS_ERR(va->macro))
1515 return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");
1516
1517 va->dcodec = devm_clk_get_optional(dev, "dcodec");
1518 if (IS_ERR(va->dcodec))
1519 return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");
1520
1521 va->mclk = devm_clk_get(dev, "mclk");
1522 if (IS_ERR(va->mclk))
1523 return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");
1524
1525 va->pds = lpass_macro_pds_init(dev);
1526 if (IS_ERR(va->pds))
1527 return PTR_ERR(va->pds);
1528
1529 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1530 &sample_rate);
1531 if (ret) {
1532 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1533 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1534 } else {
1535 ret = va_macro_validate_dmic_sample_rate(sample_rate, va);
1536 if (!ret) {
1537 ret = -EINVAL;
1538 goto err;
1539 }
1540 }
1541
1542 base = devm_platform_ioremap_resource(pdev, 0);
1543 if (IS_ERR(base)) {
1544 ret = PTR_ERR(base);
1545 goto err;
1546 }
1547
1548 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
1549 if (IS_ERR(va->regmap)) {
1550 ret = -EINVAL;
1551 goto err;
1552 }
1553
1554 dev_set_drvdata(dev, va);
1555
1556 data = of_device_get_match_data(dev);
1557 va->has_swr_master = data->has_swr_master;
1558 va->has_npl_clk = data->has_npl_clk;
1559
1560 /* mclk rate */
1561 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1562
1563 if (va->has_npl_clk) {
1564 va->npl = devm_clk_get(dev, "npl");
1565 if (IS_ERR(va->npl)) {
1566 ret = PTR_ERR(va->npl);
1567 goto err;
1568 }
1569
1570 clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ);
1571 }
1572
1573 ret = clk_prepare_enable(va->macro);
1574 if (ret)
1575 goto err;
1576
1577 ret = clk_prepare_enable(va->dcodec);
1578 if (ret)
1579 goto err_dcodec;
1580
1581 ret = clk_prepare_enable(va->mclk);
1582 if (ret)
1583 goto err_mclk;
1584
1585 if (va->has_npl_clk) {
1586 ret = clk_prepare_enable(va->npl);
1587 if (ret)
1588 goto err_npl;
1589 }
1590
1591 /**
1592 * old version of codecs do not have a reliable way to determine the
1593 * version from registers, get them from soc specific data
1594 */
1595 if (data->version)
1596 lpass_macro_set_codec_version(data->version);
1597 else /* read version from register */
1598 va_macro_set_lpass_codec_version(va);
1599
1600 if (va->has_swr_master) {
1601 /* Set default CLK div to 1 */
1602 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
1603 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1604 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1605 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
1606 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1607 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1608 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
1609 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK,
1610 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1);
1611
1612 }
1613
1614 if (va->has_swr_master) {
1615 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1616 CDC_VA_SWR_RESET_MASK, CDC_VA_SWR_RESET_ENABLE);
1617 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1618 CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE);
1619 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1620 CDC_VA_SWR_RESET_MASK, 0x0);
1621 }
1622
1623 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv,
1624 va_macro_dais,
1625 ARRAY_SIZE(va_macro_dais));
1626 if (ret)
1627 goto err_clkout;
1628
1629 pm_runtime_set_autosuspend_delay(dev, 3000);
1630 pm_runtime_use_autosuspend(dev);
1631 pm_runtime_mark_last_busy(dev);
1632 pm_runtime_set_active(dev);
1633 pm_runtime_enable(dev);
1634
1635 ret = va_macro_register_fsgen_output(va);
1636 if (ret)
1637 goto err_clkout;
1638
1639 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
1640 if (IS_ERR(va->fsgen)) {
1641 ret = PTR_ERR(va->fsgen);
1642 goto err_clkout;
1643 }
1644
1645 return 0;
1646
1647 err_clkout:
1648 if (va->has_npl_clk)
1649 clk_disable_unprepare(va->npl);
1650 err_npl:
1651 clk_disable_unprepare(va->mclk);
1652 err_mclk:
1653 clk_disable_unprepare(va->dcodec);
1654 err_dcodec:
1655 clk_disable_unprepare(va->macro);
1656 err:
1657 lpass_macro_pds_exit(va->pds);
1658
1659 return ret;
1660 }
1661
va_macro_remove(struct platform_device * pdev)1662 static void va_macro_remove(struct platform_device *pdev)
1663 {
1664 struct va_macro *va = dev_get_drvdata(&pdev->dev);
1665
1666 if (va->has_npl_clk)
1667 clk_disable_unprepare(va->npl);
1668
1669 clk_disable_unprepare(va->mclk);
1670 clk_disable_unprepare(va->dcodec);
1671 clk_disable_unprepare(va->macro);
1672
1673 lpass_macro_pds_exit(va->pds);
1674 }
1675
va_macro_runtime_suspend(struct device * dev)1676 static int va_macro_runtime_suspend(struct device *dev)
1677 {
1678 struct va_macro *va = dev_get_drvdata(dev);
1679
1680 regcache_cache_only(va->regmap, true);
1681 regcache_mark_dirty(va->regmap);
1682
1683 if (va->has_npl_clk)
1684 clk_disable_unprepare(va->npl);
1685
1686 clk_disable_unprepare(va->mclk);
1687
1688 return 0;
1689 }
1690
va_macro_runtime_resume(struct device * dev)1691 static int va_macro_runtime_resume(struct device *dev)
1692 {
1693 struct va_macro *va = dev_get_drvdata(dev);
1694 int ret;
1695
1696 ret = clk_prepare_enable(va->mclk);
1697 if (ret) {
1698 dev_err(va->dev, "unable to prepare mclk\n");
1699 return ret;
1700 }
1701
1702 if (va->has_npl_clk) {
1703 ret = clk_prepare_enable(va->npl);
1704 if (ret) {
1705 clk_disable_unprepare(va->mclk);
1706 dev_err(va->dev, "unable to prepare npl\n");
1707 return ret;
1708 }
1709 }
1710
1711 regcache_cache_only(va->regmap, false);
1712 regcache_sync(va->regmap);
1713
1714 return 0;
1715 }
1716
1717
1718 static const struct dev_pm_ops va_macro_pm_ops = {
1719 RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL)
1720 };
1721
1722 static const struct of_device_id va_macro_dt_match[] = {
1723 { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1724 { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1725 { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1726 { .compatible = "qcom,sm8550-lpass-va-macro", .data = &sm8550_va_data },
1727 { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
1728 {}
1729 };
1730 MODULE_DEVICE_TABLE(of, va_macro_dt_match);
1731
1732 static struct platform_driver va_macro_driver = {
1733 .driver = {
1734 .name = "va_macro",
1735 .of_match_table = va_macro_dt_match,
1736 .suppress_bind_attrs = true,
1737 .pm = pm_ptr(&va_macro_pm_ops),
1738 },
1739 .probe = va_macro_probe,
1740 .remove = va_macro_remove,
1741 };
1742
1743 module_platform_driver(va_macro_driver);
1744 MODULE_DESCRIPTION("VA macro driver");
1745 MODULE_LICENSE("GPL");
1746