Home
last modified time | relevance | path

Searched refs:outw (Results 1 – 25 of 36) sorted by relevance

12

/titanic_50/usr/src/grub/grub-0.97/netboot/
H A D3c595.c73 outw(RX_DISABLE, BASE + VX_COMMAND); in t595_reset()
74 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_reset()
76 outw(TX_DISABLE, BASE + VX_COMMAND); in t595_reset()
77 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in t595_reset()
79 outw(RX_RESET, BASE + VX_COMMAND); in t595_reset()
81 outw(TX_RESET, BASE + VX_COMMAND); in t595_reset()
83 outw(C_INTR_LATCH, BASE + VX_COMMAND); in t595_reset()
84 outw(SET_RD_0_MASK, BASE + VX_COMMAND); in t595_reset()
85 outw(SET_INTR_MASK, BASE + VX_COMMAND); in t595_reset()
86 outw(SET_RX_FILTER, BASE + VX_COMMAND); in t595_reset()
[all …]
H A Dsundance.c324 outw(inw(BASE + MACCtrl0) | EnbFullDuplex, in check_duplex()
337 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0, in check_duplex()
403 outw(addr16, BASE + StationAddr); in sundance_reset()
405 outw(addr16, BASE + StationAddr + 2); in sundance_reset()
407 outw(addr16, BASE + StationAddr + 4); in sundance_reset()
410 outw(sdc->mtu + 14, BASE + MaxFrameSize); in sundance_reset()
416 outw(0, BASE + DownCounter); in sundance_reset()
424 outw(RxEnable | TxEnable, BASE + MACCtrl1); in sundance_reset()
458 outw(intr_status, nic->ioaddr + IntrEnable); in sundance_irq()
461 outw(0x0200, BASE + ASICCtrl); in sundance_irq()
[all …]
H A Deepro100.c338 outw(EE_ENB, ee_addr); udelay(2); in do_eeprom_cmd()
339 outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2); in do_eeprom_cmd()
344 outw(dataval, ee_addr); udelay(2); in do_eeprom_cmd()
345 outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2); in do_eeprom_cmd()
348 outw(EE_ENB, ee_addr); udelay(2); in do_eeprom_cmd()
351 outw(EE_ENB & ~EE_CS, ee_addr); in do_eeprom_cmd()
399 outw(status & 0xfc00, ioaddr + SCBStatus); in eepro100_transmit()
429 outw(INT_MASK | CU_START, ioaddr + SCBCmd); in eepro100_transmit()
517 outw(INT_MASK | RX_START, ioaddr + SCBCmd); in eepro100_poll()
557 outw(INT_MASK, ioaddr + SCBCmd); in eepro100_disable()
[all …]
H A D3c90x.c265 outw(val, ioaddr + regCommandIntStatus_w); in a3c90x_internal_IssueCommand()
305 outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w); in a3c90x_internal_ReadEeprom()
329 outw(0x30, ioaddr + regEepromCommand_0_w);
333 outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
337 outw(value, ioaddr + regEepromData_0_w);
338 outw(0x30, ioaddr + regEepromCommand_0_w);
342 outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
416 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0); in a3c90x_reset()
417 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2); in a3c90x_reset()
418 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4); in a3c90x_reset()
[all …]
H A Dtlan.h398 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead8()
408 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead16()
418 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead32()
428 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite8()
438 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite16()
439 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); in TLan_DioWrite16()
448 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite32()
H A Drtl8139.c364 outw(0, nic->ioaddr + IntrMask); in rtl_reset()
402 outw(status & (TxOK | TxErr | PCIErr), nic->ioaddr + IntrStatus); in rtl_transmit()
438 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus); in rtl_poll()
478 outw(cur_rx - 16, nic->ioaddr + RxBufPtr); in rtl_poll()
482 outw(status & (RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus); in rtl_poll()
498 outw(mask, nic->ioaddr + IntrMask); in rtl_irq()
H A Dvia-rhine.c821 outw (ReadMIItmp, wMIIDATA); in WriteMII()
902 outw(intr_status, nic->ioaddr + IntrEnable); in rhine_irq()
905 outw(0x0010, nic->ioaddr + 0x84); in rhine_irq()
1033 outw (CR_FDX, byCR0); in rhine_probe1()
1167 outw (0x0000, byIMR0); in rhine_reset()
1179 outw (CR_FDX, byCR0); in rhine_reset()
1185 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0); in rhine_reset()
1188 outw (IMRShadow, byIMR0); in rhine_reset()
1215 outw(intr_status & 0xffff, nic->ioaddr + IntrStatus); in rhine_poll()
1241 outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus); in rhine_poll()
H A Dnatsemi.c463 outw(0x0001, ioaddr + PGSEL); in natsemi_reset()
464 outw(0x189C, ioaddr + PMDCSR); in natsemi_reset()
465 outw(0x0000, ioaddr + TSTDAT); in natsemi_reset()
466 outw(0x5040, ioaddr + DSPCFG); in natsemi_reset()
467 outw(0x008C, ioaddr + SDCFG); in natsemi_reset()
490 outw(nic->node_addr[i] + (nic->node_addr[i+1] << 8), ioaddr + RxFilterData); in natsemi_init_rxfilter()
H A Dpcnet32.c294 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_read_csr()
300 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_csr()
301 outw(val, addr + PCNET32_WIO_RDP); in pcnet32_wio_write_csr()
306 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_read_bcr()
312 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_bcr()
313 outw(val, addr + PCNET32_WIO_BDP); in pcnet32_wio_write_bcr()
323 outw(val, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_rap()
333 outw(88, addr + PCNET32_WIO_RAP); in pcnet32_wio_check()
H A Dtlan.c374 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); in TLan_ResetAdapter()
545 outw(host_int, BASE + TLAN_HOST_INT); in tlan_poll()
906 outw(data, BASE + TLAN_HOST_CMD);
964 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1006 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1066 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1194 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1272 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1311 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1350 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
H A Dpnic.c58 outw ( input_length, nic->ioaddr + PNIC_REG_LEN ); in pnic_command_quiet()
65 outw ( command, nic->ioaddr + PNIC_REG_CMD ); in pnic_command_quiet()
H A D3c595.h416 #define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND)
H A Dio.h204 #define outw(val,port) \ macro
H A Dpci_io.c64 outw(value, 0xCFC + (where&2)); in pcibios_write_config_word()
H A Depic100.c219 outw(((unsigned short *)mc_filter)[i], mc0 + i*4); in set_rx_mode()
/titanic_50/usr/src/uts/i86pc/ml/
H A Damd64.il149 .inline outw,8
152 outw (%dx)
H A Dia32.il136 .inline outw,8
139 outw (%dx)
/titanic_50/usr/src/uts/intel/asm/
H A Dsunddi.h92 outw(int port, uint16_t value) in outw() function
/titanic_50/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c543 outw((uintptr_t)addr, ddi_swap16(value)); in i_ddi_io_swap_put16()
798 outw(port, ddi_swap16(*h++)); in i_ddi_io_swap_rep_put16()
801 outw(port, ddi_swap16(*h++)); in i_ddi_io_swap_rep_put16()
1145 outw((uintptr_t)addr, value); in i_ddi_prot_io_put16()
1193 outw((uintptr_t)addr, ddi_swap16(value)); in i_ddi_prot_io_swap_put16()
1618 outw(port, *h++); in i_ddi_prot_io_rep_put16()
1621 outw(port, *h++); in i_ddi_prot_io_rep_put16()
1659 outw(port, ddi_swap16(*h++)); in i_ddi_prot_io_swap_rep_put16()
1662 outw(port, ddi_swap16(*h++)); in i_ddi_prot_io_swap_rep_put16()
/titanic_50/usr/src/uts/i86pc/os/
H A Dpci_mech1.c121 outw(PCI_CONFDATA | (reg & 0x2), val); in pci_mech1_putw()
H A Dpci_mech2.c142 outw(PCI_CADDR2(device, reg), val); in pci_mech2_putw()
H A Dpci_mech1_amd.c169 outw(PCI_CONFDATA | (reg & 0x2), val); in pci_mech1_amd_putw()
/titanic_50/usr/src/cmd/mdb/intel/amd64/kmdb/
H A Dkmdb_asmutil.s161 outw (%dx)
/titanic_50/usr/src/uts/intel/sys/
H A Darchsystm.h105 extern void outw(int port, uint16_t value);
/titanic_50/usr/src/uts/intel/ia32/ml/
H A Dddi_i86_asm.s558 outw (%dx)
588 outw (%dx)
1257 outw (%dx)
1266 outw (%dx)
1631 outw (%dx)
1663 outw (%dx)

12