| /titanic_44/usr/src/uts/sun4u/sys/ |
| H A D | cheetahasm.h | 78 #define GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3) \ argument
79 set CH_DCACHE_IDX_MASK, scr3; \
80 and afar, scr3, scr3; \
86 ldxa [scr3]ASI_DC_TAG, scr1; /* read tag */ \
90 stxa scr3, [datap + CH_DC_IDX]%asi; /* store index */ \
93 ldxa [scr3]ASI_DC_UTAG, scr1; /* read utag */ \
96 ldxa [scr3]ASI_DC_SNP_TAG, scr1; /* read snoop tag */ \
102 ldxa [scr3 + scr2]ASI_DC_DATA, scr1; /* read data */ \
118 or scr3, scr1, scr3; /* add DC_data_parity bit to index */ \
121 ldxa [scr3 + scr2]ASI_DC_DATA, scr1; /* read parity bits */ \
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| H A D | traptrace.h | 213 #define TRACE_NEXT(scr1, scr2, scr3) \ argument
225 ld [scr2 + TRAPTR_LIMIT], scr3; \
228 sub scr3, TRAP_ENT_SIZE, scr3; \
229 cmp scr1, scr3; \
258 #define TRACE_RTT(code, scr1, scr2, scr3, scr4) \ argument
260 andn scr4, PSTATE_IE | PSTATE_AM, scr3; \
261 wrpr %g0, scr3, %pstate; \
263 GET_TRACE_TICK(scr2, scr3); \
284 TRACE_NEXT(scr1, scr2, scr3); \
291 #define TRACE_WIN_INFO(code, scr1, scr2, scr3) \ argument
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| /titanic_44/usr/src/uts/sun4v/sys/ |
| H A D | traptrace.h | 270 #define TRACE_NEXT(scr1, scr2, scr3) \ argument
282 ld [scr2 + TRAPTR_LIMIT], scr3; \
285 sub scr3, TRAP_ENT_SIZE, scr3; \
286 cmp scr1, scr3; \
318 #define TRACE_RTT(code, scr1, scr2, scr3, scr4) \ argument
320 andn scr4, PSTATE_IE | PSTATE_AM, scr3; \
321 wrpr %g0, scr3, %pstate; \
323 GET_TRACE_TICK(scr2, scr3); \
341 TRACE_NEXT(scr1, scr2, scr3); \
348 #define TRACE_WIN_INFO(code, scr1, scr2, scr3) \ argument
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| /titanic_44/usr/src/uts/sun4u/cpu/ |
| H A D | us3_jalapeno_asm.s | 183 #define JP_FORCE_FULL_SPEED(old_lvl, scr2, scr3, scr4) \ argument
187 SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA); \
188 ldxa [scr2]ASI_IO, scr3; \
190 and scr3, scr4, scr3; \
191 or old_lvl, scr3, old_lvl; \
200 SET_JP_SPEED(JBUS_CONFIG_ECLK_2, scr3, scr4); \
201 SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3); \
202 SET_SLAVE_T_SPEED(TOM_HALF_SPEED, scr3, scr4); \
203 JP_ADJUST_FSM(0, scr3, scr4); \
204 set jp_estar_tl0_data, scr3; \
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| H A D | us3_cheetahplus_asm.s | 102 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
104 set PN_L2_SET_SIZE, scr3; \
109 sub scr2, scr3, scr2; \
116 set PN_L3_SET_SIZE, scr3; \
121 sub scr2, scr3, scr2;
137 #define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \ argument
146 set PN_L2_IDX_DISP_FLUSH, scr3; \
147 or l2_idx_out, scr3, l2_idx_out; \
148 PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
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| H A D | common_asm.s | 56 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
186 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
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| /titanic_44/usr/src/cmd/mdb/sparc/v9/kmdb/ |
| H A D | kaif_handlers.s | 103 #define KAIF_ITLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
106 mov %o2, scr3; \
122 mov scr3, %o2; \
136 #define KAIF_DTLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
139 mov %o2, scr3; \
155 mov scr3, %o2; \
171 #define KAIF_DTLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
172 DTLB_STUFF(tte, scr1, scr2, scr3, scr4)
174 #define KAIF_ITLB_STUFF(tte, ouch, scr1, scr2, scr3, scr4) \ argument
175 ITLB_STUFF(tte, scr1, scr2, scr3, scr4)
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| /titanic_44/usr/src/uts/sun4v/vm/ |
| H A D | mach_sfmmu.h | 236 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
239 mov %o2, scr3; \
253 mov scr3, %o2; \
263 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
266 mov %o2, scr3; \
280 mov scr3, %o2; \
293 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ argument
298 add scr2, MMU_PAGESHIFT + TTE_PA_LSHIFT, scr3; \
301 srlx tte, scr3, tte; \
304 add scr2, MMU_PAGESHIFT, scr3; \
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| /titanic_44/usr/src/uts/sun4u/vm/ |
| H A D | mach_sfmmu.h | 215 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
225 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
239 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ argument
242 srlx tte, TTE_SZ2_SHFT, scr3; \
243 and scr3, TTE_SZ2_BITS, scr3; /* scr3 = tte_size2 */ \
244 or scr1, scr3, scr1; \
248 add scr2, MMU_PAGESHIFT + TTE_PA_LSHIFT, scr3; \
251 srlx tte, scr3, tte; \
255 add scr2, MMU_PAGESHIFT, scr3; \
256 sllx scr1, scr3, scr1; \
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| /titanic_44/usr/src/uts/sun4u/io/ |
| H A D | panther_asm.s | 81 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
83 set PN_L2_SET_SIZE, scr3; \
88 sub scr2, scr3, scr2; \
95 set PN_L3_SET_SIZE, scr3; \
100 sub scr2, scr3, scr2;
116 #define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \ argument
125 set PN_L2_IDX_DISP_FLUSH, scr3; \
126 or l2_idx_out, scr3, l2_idx_out; \
127 PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
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| /titanic_44/usr/src/uts/sparc/v7/sys/ |
| H A D | traptrace.h | 163 #define TRACE_UNFL(code, addr, scr1, scr2, scr3) \ argument
172 TRACE_NEXT(scr1, scr2, scr3)
176 #define TRACE_UNFL(code, addr, scr1, scr2, scr3)
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