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Searched refs:regs (Results 1 – 25 of 254) sorted by relevance

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/titanic_41/usr/src/cmd/mdb/intel/mdb/
H A Dkvm_amd64dep.c161 kt_regs_to_kregs(struct regs *regs, mdb_tgt_gregset_t *gregs) in kt_regs_to_kregs() argument
163 gregs->kregs[KREG_SAVFP] = regs->r_savfp; in kt_regs_to_kregs()
164 gregs->kregs[KREG_SAVPC] = regs->r_savpc; in kt_regs_to_kregs()
165 gregs->kregs[KREG_RDI] = regs->r_rdi; in kt_regs_to_kregs()
166 gregs->kregs[KREG_RSI] = regs->r_rsi; in kt_regs_to_kregs()
167 gregs->kregs[KREG_RDX] = regs->r_rdx; in kt_regs_to_kregs()
168 gregs->kregs[KREG_RCX] = regs->r_rcx; in kt_regs_to_kregs()
169 gregs->kregs[KREG_R8] = regs->r_r8; in kt_regs_to_kregs()
170 gregs->kregs[KREG_R9] = regs->r_r9; in kt_regs_to_kregs()
171 gregs->kregs[KREG_RAX] = regs->r_rax; in kt_regs_to_kregs()
[all …]
H A Dkvm_ia32dep.c161 kt_regs_to_kregs(struct regs *regs, mdb_tgt_gregset_t *gregs) in kt_regs_to_kregs() argument
163 gregs->kregs[KREG_SAVFP] = regs->r_savfp; in kt_regs_to_kregs()
164 gregs->kregs[KREG_SAVPC] = regs->r_savpc; in kt_regs_to_kregs()
165 gregs->kregs[KREG_EAX] = regs->r_eax; in kt_regs_to_kregs()
166 gregs->kregs[KREG_EBX] = regs->r_ebx; in kt_regs_to_kregs()
167 gregs->kregs[KREG_ECX] = regs->r_ecx; in kt_regs_to_kregs()
168 gregs->kregs[KREG_EDX] = regs->r_edx; in kt_regs_to_kregs()
169 gregs->kregs[KREG_ESI] = regs->r_esi; in kt_regs_to_kregs()
170 gregs->kregs[KREG_EDI] = regs->r_edi; in kt_regs_to_kregs()
171 gregs->kregs[KREG_EBP] = regs->r_ebp; in kt_regs_to_kregs()
[all …]
/titanic_41/usr/src/uts/common/io/rtw/
H A Drtw.c252 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where) in rtw_print_regs() argument
257 dvname, reg, RTW_READ(regs, reg)) in rtw_print_regs()
262 dvname, reg, RTW_READ16(regs, reg)) in rtw_print_regs()
267 dvname, reg, RTW_READ8(regs, reg)) in rtw_print_regs()
271 PRINTREG32(regs, RTW_IDR0); in rtw_print_regs()
272 PRINTREG32(regs, RTW_IDR1); in rtw_print_regs()
273 PRINTREG32(regs, RTW_MAR0); in rtw_print_regs()
274 PRINTREG32(regs, RTW_MAR1); in rtw_print_regs()
275 PRINTREG32(regs, RTW_TSFTRL); in rtw_print_regs()
276 PRINTREG32(regs, RTW_TSFTRH); in rtw_print_regs()
[all …]
H A Drtwphyio.c52 rtw_bbp_read(struct rtw_regs *regs, uint_t addr) in rtw_bbp_read() argument
54 RTW_WRITE(regs, RTW_BB, in rtw_bbp_read()
57 RTW_WBR(regs, RTW_BB, RTW_BB); in rtw_bbp_read()
58 return (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK)); in rtw_bbp_read()
62 rtw_bbp_write(struct rtw_regs *regs, uint_t addr, uint_t val) in rtw_bbp_write() argument
81 RTW_RBW(regs, RTW_BB, RTW_BB); in rtw_bbp_write()
82 RTW_WRITE(regs, RTW_BB, wrbbp); in rtw_bbp_write()
83 RTW_SYNC(regs, RTW_BB, RTW_BB); in rtw_bbp_write()
84 RTW_WRITE(regs, RTW_BB, rdbbp); in rtw_bbp_write()
85 RTW_SYNC(regs, RTW_BB, RTW_BB); in rtw_bbp_write()
[all …]
H A Drtwreg.h1219 #define RTW_READ8(regs, ofs) \ argument
1220 ddi_get8((regs)->r_handle, \
1221 (uint8_t *)((regs)->r_base + (ofs)))
1223 #define RTW_READ16(regs, ofs) \ argument
1224 ddi_get16((regs)->r_handle, \
1225 (uint16_t *)((uintptr_t)(regs)->r_base + (ofs)))
1227 #define RTW_READ(regs, ofs) \ argument
1228 ddi_get32((regs)->r_handle, \
1229 (uint32_t *)((uintptr_t)(regs)->r_base + (ofs)))
1231 #define RTW_WRITE8(regs, ofs, val) \ argument
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/titanic_41/usr/src/uts/sun/io/audio/drv/audiocs/
H A Daudio_4231_eb2dma.c252 cs4231_eb2regs_t *regs = eng->ce_eb2regs; in eb2_start_engine() local
269 OR_SET_WORD(handle, &regs->eb2csr, EB2_RESET); in eb2_start_engine()
272 csr = ddi_get32(handle, &regs->eb2csr); in eb2_start_engine()
275 csr = ddi_get32(handle, &regs->eb2csr); in eb2_start_engine()
284 AND_SET_WORD(handle, &regs->eb2csr, ~(EB2_RESET|EB2_EN_DMA)); in eb2_start_engine()
287 OR_SET_WORD(handle, &regs->eb2csr, reset); in eb2_start_engine()
297 OR_SET_WORD(handle, &regs->eb2csr, enable); in eb2_start_engine()
323 cs4231_eb2regs_t *regs = eng->ce_eb2regs; in eb2_stop_engine() local
327 AND_SET_WORD(handle, &regs->eb2csr, ~(EB2_EN_DMA | EB2_INT_EN)); in eb2_stop_engine()
329 csr = ddi_get32(handle, &regs->eb2csr); in eb2_stop_engine()
[all …]
/titanic_41/usr/src/lib/libdtrace/i386/
H A DMakefile31 DLIBSRCS = regs.d
40 CLEANFILES += regs.sed regs.d
46 ../$(MACH)/regs.d: regs.sed regs.d.in
47 sed -f regs.sed < regs.d.in > $@
/titanic_41/usr/src/uts/i86pc/io/gfx_private/
H A Dgfxp_vgatext.c69 struct vgaregmap regs; member
421 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE, in gfxp_vgatext_attach()
422 &dev_attr, &softc->regs.handle); in gfxp_vgatext_attach()
425 softc->regs.mapped = B_TRUE; in gfxp_vgatext_attach()
437 if (ddi_get8(softc->regs.handle, in gfxp_vgatext_attach()
438 softc->regs.addr + VGA_MISC_R) & VGA_MISC_IOA_SEL) in gfxp_vgatext_attach()
504 if (softc->regs.mapped) in gfxp_vgatext_detach()
505 ddi_regs_map_free(&softc->regs.handle); in gfxp_vgatext_detach()
1073 vga_set_crtc(&softc->regs, VGA_CRTC_CLAH, addr >> 8); in vgatext_set_cursor()
1074 vga_set_crtc(&softc->regs, VGA_CRTC_CLAL, addr & 0xff); in vgatext_set_cursor()
[all …]
/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_fm.c56 px_err_pcie_t *regs);
59 static void px_pcie_log(dev_info_t *dip, px_err_pcie_t *regs);
586 px_err_check_pcie(dev_info_t *dip, ddi_fm_error_t *derr, px_err_pcie_t *regs, in px_err_check_pcie() argument
600 if (regs->primary_ue & PCIE_AER_UCE_UR) in px_err_check_pcie()
602 if (regs->primary_ue & PCIE_AER_UCE_CA) in px_err_check_pcie()
604 if (regs->primary_ue & (PCIE_AER_UCE_PTLP | PCIE_AER_UCE_ECRC)) in px_err_check_pcie()
607 if (!regs->primary_ue) in px_err_check_pcie()
610 adv_reg->pcie_ce_status = regs->ce_reg; in px_err_check_pcie()
611 adv_reg->pcie_ue_status = regs->ue_reg | regs->primary_ue; in px_err_check_pcie()
612 PCIE_ADV_HDR(pfd_p, 0) = regs->rx_hdr1; in px_err_check_pcie()
[all …]
/titanic_41/usr/src/uts/sparc/sys/
H A Dsimulate.h144 extern int simulate_unimp(struct regs *, caddr_t *);
145 extern int simulate_lddstd(struct regs *, caddr_t *);
146 extern int simulate_rdtick(struct regs *);
147 extern int do_unaligned(struct regs *, caddr_t *);
148 extern int calc_memaddr(struct regs *, caddr_t *);
149 extern int is_atomic(struct regs *);
150 extern int instr_size(struct regs *, caddr_t *, enum seg_rw);
151 extern int getreg(struct regs *, uint_t, uint64_t *, caddr_t *);
152 extern int putreg(uint64_t *, struct regs *, uint_t, caddr_t *);
/titanic_41/usr/src/uts/intel/io/vgatext/
H A Dvgatext.c143 struct vgaregmap regs; member
539 (caddr_t *)&softc->regs.addr, reg_offset, VGA_REG_SIZE, in vgatext_attach()
540 &dev_attr, &softc->regs.handle); in vgatext_attach()
543 softc->regs.mapped = B_TRUE; in vgatext_attach()
555 if (ddi_get8(softc->regs.handle, in vgatext_attach()
556 softc->regs.addr + VGA_MISC_R) & VGA_MISC_IOA_SEL) in vgatext_attach()
634 if (softc->regs.mapped) in vgatext_detach()
635 ddi_regs_map_free(&softc->regs.handle); in vgatext_detach()
1199 vga_set_crtc(&softc->regs, VGA_CRTC_CLAH, addr >> 8); in vgatext_set_cursor()
1200 vga_set_crtc(&softc->regs, VGA_CRTC_CLAL, addr & 0xff); in vgatext_set_cursor()
[all …]
/titanic_41/usr/src/uts/i86pc/os/
H A Dpci_cfgspace.c252 struct bop_regs regs; in pci_check_bios() local
256 bzero(&regs, sizeof (regs)); in pci_check_bios()
257 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT; in pci_check_bios()
259 BOP_DOINT(bootops, 0x1a, &regs); in pci_check_bios()
260 carryflag = regs.eflags & PS_C; in pci_check_bios()
261 ax = regs.eax.word.ax; in pci_check_bios()
262 dx = regs.edx.word.dx; in pci_check_bios()
276 pci_bios_vers = regs.ebx.word.bx; in pci_check_bios()
277 pci_bios_maxbus = (regs.ecx.word.cx & 0xff); in pci_check_bios()
H A Dpci_bios.c70 struct bop_regs regs; in pci_bios_get_irq_routing() local
93 bzero(&regs, sizeof (regs)); in pci_bios_get_irq_routing()
94 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_GET_IRQ_ROUTING; in pci_bios_get_irq_routing()
96 regs.ds = 0xf000; in pci_bios_get_irq_routing()
97 regs.es = FP_SEG((uint_t)(uintptr_t)hdrp); in pci_bios_get_irq_routing()
98 regs.edi.word.di = FP_OFF((uint_t)(uintptr_t)hdrp); in pci_bios_get_irq_routing()
100 BOP_DOINT(bootops, 0x1a, &regs); in pci_bios_get_irq_routing()
105 if ((regs.eflags & PS_C) != 0) { in pci_bios_get_irq_routing()
/titanic_41/usr/src/uts/common/io/scsi/adapters/smrt/
H A Dsmrt_device.c26 smrt_locate_bar(pci_regspec_t *regs, unsigned nregs, in smrt_locate_bar() argument
33 unsigned type = regs[i].pci_phys_hi & PCI_ADDR_MASK; in smrt_locate_bar()
45 smrt_locate_cfgtbl(smrt_t *smrt, pci_regspec_t *regs, unsigned nregs, in smrt_locate_cfgtbl() argument
75 unsigned type = regs[i].pci_phys_hi & PCI_ADDR_MASK; in smrt_locate_cfgtbl()
76 unsigned bar = PCI_REG_REG_G(regs[i].pci_phys_hi); in smrt_locate_cfgtbl()
115 pci_regspec_t *regs; in smrt_map_device() local
124 "reg", (int **)&regs, &regslen) != DDI_PROP_SUCCESS) { in smrt_map_device()
130 if (smrt_locate_bar(regs, nregs, &smrt->smrt_i2o_bar) != in smrt_map_device()
148 if (smrt_locate_cfgtbl(smrt, regs, nregs, &smrt->smrt_ct_bar, in smrt_map_device()
169 ddi_prop_free(regs); in smrt_map_device()
/titanic_41/usr/src/uts/intel/io/pciex/
H A Dpcie_nvidia.c222 pci_regspec_t regs[2] = {{0}}; in add_nvidia_isa_bridge_props() local
228 regs[0].pci_phys_hi = devloc; in add_nvidia_isa_bridge_props()
233 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; in add_nvidia_isa_bridge_props()
234 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | in add_nvidia_isa_bridge_props()
236 assigned[0].pci_phys_low = regs[0].pci_phys_low = in add_nvidia_isa_bridge_props()
242 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; in add_nvidia_isa_bridge_props()
243 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | in add_nvidia_isa_bridge_props()
245 assigned[1].pci_phys_low = regs[1].pci_phys_low = in add_nvidia_isa_bridge_props()
249 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int)); in add_nvidia_isa_bridge_props()
/titanic_41/usr/src/uts/common/io/
H A Dbusra.c937 pci_regspec_t *regs; in pci_resource_setup() local
1024 "available", (caddr_t)&regs, &rlen) == DDI_SUCCESS) { in pci_resource_setup()
1038 switch (PCI_REG_ADDR_G(regs[i].pci_phys_hi)) { in pci_resource_setup()
1041 (uint64_t)regs[i].pci_phys_low, in pci_resource_setup()
1042 (uint64_t)regs[i].pci_size_low, in pci_resource_setup()
1043 (regs[i].pci_phys_hi & PCI_REG_PF_M) ? in pci_resource_setup()
1050 ((uint64_t)(regs[i].pci_phys_mid) << 32) | in pci_resource_setup()
1051 ((uint64_t)(regs[i].pci_phys_low)), in pci_resource_setup()
1052 ((uint64_t)(regs[i].pci_size_hi) << 32) | in pci_resource_setup()
1053 ((uint64_t)(regs[i].pci_size_low)), in pci_resource_setup()
[all …]
/titanic_41/usr/src/cmd/luxadm/
H A Dfcalupdate.c143 volatile socal_reg_t *regs; in fcal_update() local
265 regs = (socal_reg_t *)((int)addr + REG_OFFSET); in fcal_update()
275 retval += load_file(file, addr, regs); in fcal_update()
442 volatile socal_reg_t *regs) in feprom_program() argument
447 if (!write_feprom((uchar_t *)0, dest_address, regs)) { in feprom_program()
456 if (feprom_erase(dest_address, regs)) in feprom_program()
476 if (!(write_feprom(source_address, dest_address, regs))) { in feprom_program()
484 regs->socal_cr.w &= ~(0x30000); in feprom_program()
494 volatile socal_reg_t *regs) in write_feprom() argument
505 regs->socal_cr.w &= ~(0x30000); in write_feprom()
[all …]
/titanic_41/usr/src/cmd/mdb/sparc/kmdb/
H A Dkaif.c893 struct regs regs; in kaif_kernpanic() local
904 regs.r_tstate = kaif_cb_save.krs_tstate; in kaif_kernpanic()
906 regs.r_g1 = kaif_cb_save.krs_gregs.kregs[KREG_G1]; in kaif_kernpanic()
907 regs.r_g2 = kaif_cb_save.krs_gregs.kregs[KREG_G2]; in kaif_kernpanic()
908 regs.r_g3 = kaif_cb_save.krs_gregs.kregs[KREG_G3]; in kaif_kernpanic()
909 regs.r_g4 = kaif_cb_save.krs_gregs.kregs[KREG_G4]; in kaif_kernpanic()
910 regs.r_g5 = kaif_cb_save.krs_gregs.kregs[KREG_G5]; in kaif_kernpanic()
911 regs.r_g6 = kaif_cb_save.krs_gregs.kregs[KREG_G6]; in kaif_kernpanic()
912 regs.r_g7 = kaif_cb_save.krs_gregs.kregs[KREG_G7]; in kaif_kernpanic()
914 regs.r_o0 = kaif_cb_save.krs_gregs.kregs[KREG_O0]; in kaif_kernpanic()
[all …]
/titanic_41/usr/src/cmd/mdb/intel/modules/mdb_kb/
H A Dmdb_kb.c1508 struct regs *regs; in xkb_getmregs() local
1519 regs = &mregs->pm_gregs; in xkb_getmregs()
1521 regs->r_ss = ur->ss; in xkb_getmregs()
1522 regs->r_cs = ur->cs; in xkb_getmregs()
1523 regs->r_ds = ur->ds; in xkb_getmregs()
1524 regs->r_es = ur->es; in xkb_getmregs()
1525 regs->r_fs = ur->fs; in xkb_getmregs()
1526 regs->r_gs = ur->gs; in xkb_getmregs()
1527 regs->r_trapno = ur->entry_vector; in xkb_getmregs()
1528 regs->r_err = ur->error_code; in xkb_getmregs()
[all …]
/titanic_41/usr/src/lib/libproc/common/
H A DPservice.c123 ps_lgetregs(struct ps_prochandle *P, lwpid_t lwpid, prgregset_t regs) in ps_lgetregs() argument
128 if (Plwp_getregs(P, lwpid, regs) == 0) in ps_lgetregs()
135 ps_lsetregs(struct ps_prochandle *P, lwpid_t lwpid, const prgregset_t regs) in ps_lsetregs() argument
140 if (Plwp_setregs(P, lwpid, regs) == 0) in ps_lsetregs()
147 ps_lgetfpregs(struct ps_prochandle *P, lwpid_t lwpid, prfpregset_t *regs) in ps_lgetfpregs() argument
152 if (Plwp_getfpregs(P, lwpid, regs) == 0) in ps_lgetfpregs()
159 ps_lsetfpregs(struct ps_prochandle *P, lwpid_t lwpid, const prfpregset_t *regs) in ps_lsetfpregs() argument
164 if (Plwp_setfpregs(P, lwpid, regs) == 0) in ps_lsetfpregs()
242 prgregset_t regs; in ps_lgetLDT() local
256 if ((error = ps_lgetregs(P, lwpid, regs)) != PS_OK) in ps_lgetLDT()
[all …]
/titanic_41/usr/src/uts/common/io/audio/drv/audioemu10k/
H A Daudioemu10k.c183 OUTB(devc, index, devc->regs + 0x1e); in emu10k_read_ac97()
185 if (INB(devc, devc->regs + 0x1e) & 0x80) in emu10k_read_ac97()
192 dtemp = INW(devc, devc->regs + 0x1c); in emu10k_read_ac97()
207 OUTB(devc, index, devc->regs + 0x1e); in emu10k_write_ac97()
209 if (INB(devc, devc->regs + 0x1e) & 0x80) in emu10k_write_ac97()
211 OUTW(devc, data, devc->regs + 0x1c); in emu10k_write_ac97()
225 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ in emu10k_read_reg()
226 val = INL(devc, devc->regs + 0x04); /* Data */ in emu10k_read_reg()
247 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */ in emu10k_write_reg()
254 value |= INL(devc, devc->regs + 0x04) & ~mask; /* data */ in emu10k_write_reg()
[all …]
/titanic_41/usr/src/uts/i86pc/sys/
H A Dmachsystm.h97 struct regs *trap_regs;
123 extern void trap(struct regs *, caddr_t, processorid_t);
125 extern void do_interrupt(struct regs *, trap_trace_rec_t *);
131 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
177 extern int linear_pc(struct regs *rp, proc_t *p, caddr_t *linearp);
178 extern int dtrace_linear_pc(struct regs *rp, proc_t *p, caddr_t *linearp);
/titanic_41/usr/src/uts/intel/sys/
H A Dfp.h212 struct regs;
213 extern int fpnoextflt(struct regs *);
214 extern int fpextovrflt(struct regs *);
215 extern int fpexterrflt(struct regs *);
216 extern int fpsimderrflt(struct regs *);
/titanic_41/usr/src/uts/sparc/sys/fpu/
H A Dfpu_simulator.h265 struct regs *fp_traprp;
396 struct regs *pregs, fsr_type *pfsr, uint64_t gsr, uint32_t inst);
408 struct regs *rp, void *prw, kfpu_t *pfpu);
413 extern void fp_traps(fp_simd_type *pfpsd, enum ftt_type ftt, struct regs *rp);
427 extern void fp_precise(struct regs *rp);
434 extern void fpu_trap(struct regs *rp, caddr_t addr, uint32_t type,
456 struct regs *pregs, /* Pointer to PCB image of registers. */
467 struct regs *rp); /* Pointer to PCB image of registers. */
482 struct regs *rp); /* Pointer to PCB image of registers. */
490 struct regs *rp, /* Pointer to PCB image of registers. */
/titanic_41/usr/src/uts/common/io/drm/
H A Ddrm_memory.c107 pci_regspec_t *regs; in drm_get_pci_index_reg() local
121 "assigned-addresses", (caddr_t)&regs, &length) != in drm_get_pci_index_reg()
128 base = (uint_t)regs[i].pci_phys_low; in drm_get_pci_index_reg()
129 regsize = (uint_t)regs[i].pci_size_low; in drm_get_pci_index_reg()
138 kmem_free(regs, (size_t)length); in drm_get_pci_index_reg()
141 kmem_free(regs, (size_t)length); in drm_get_pci_index_reg()

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