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/titanic_41/usr/src/cmd/sgs/rtld/sparcv9/
H A Dboot_elf.s211 sethi %hi(M_SAVE_SP176SP), %o0 ! Get save instruction
217 or %o4, %o2, %o4 ! or value into instruction
218 st %o4, [%i0 + 0x4] ! Store instruction in plt[1]
223 or %o4, %o2, %o4 ! or value into instruction
224 st %o4, [%i0 + 0x8] ! Store instruction in plt[2]
230 or %o4, %o2, %o4 ! or value into instruction
231 st %o4, [%i0 + 0xc] ! Store instruction in plt[3]
236 st %o4, [%i0 + 0x10] ! Store instruction in plt[4]
240 st %o4, [%i0 + 0x14] ! Store instruction in plt[5]
246 or %o4, %o2, %o4 ! or value into instruction
[all …]
/titanic_41/usr/src/cmd/sgs/rtld/sparc/
H A Dboot_a.out.s119 sethi %hi(M_SETHIG1), %o3 ! Get sethi instruction
121 st %o3, [%o0] ! Store instruction in plt[0]
124 sethi %hi(M_JMPL), %o3 ! Get jmpl instruction
H A Dboot_elf.s169 sethi %hi(M_SAVESP64), %o0 ! Get save instruction
180 sethi %hi(M_CALL), %o4 ! Get sethi instruction
182 st %o4, [%i0] ! Store instruction in plt
184 sethi %hi(M_NOP), %o0 ! Generate nop instruction
185 st %o0, [%i0 + 4] ! Store instruction in plt[2]
187 st %i1, [%i0 + 8] ! Store instruction in plt[3]
423 sethi %hi(M_JMPL), %o3 ! Get jmpl instruction
/titanic_41/usr/src/lib/libc/sparc/gen/
H A Dlsub.s50 nop ! delay instruction.
52 nop ! delay instruction.
H A Dladd.s51 nop ! delay instruction.
53 nop ! delay instruction.
H A Dlshiftl.s48 nop ! delay instruction.
50 nop ! delay instruction.
/titanic_41/usr/src/uts/intel/ia32/ml/
H A Dia32.il157 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
159 * instruction in these loops, the P4 Xeon processor may suffer a severe
161 * memory violation. Inserting the pause instruction significantly reduces
163 * The pause instruction is a NOP on all other IA-32 processors.
H A Dfloat.s180 .byte 0xf, 0xae, 0xf8 / [sfence instruction]
193 .byte 0xf, 0xae, 0xe8 / [lfence instruction]
/titanic_41/usr/src/uts/intel/amd64/ml/
H A Damd64.il161 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
163 * instruction in these loops, the P4 Xeon processor may suffer a severe
165 * memory violation. Inserting the pause instruction significantly reduces
167 * The pause instruction is a NOP on all other IA-32 processors.
/titanic_41/usr/src/uts/i86pc/ml/
H A Damd64.il162 * Call the halt instruction. This will put the CPU to sleep until
167 * subsequent instruction...in this case: "hlt".
174 / execute the bsrw instruction
H A Dia32.il158 * Call the halt instruction. This will put the CPU to sleep until
163 * subsequent instruction...in this case: "hlt".
171 * execute the bsrw instruction
/titanic_41/usr/src/common/bignum/i386/
H A Dbignum_i386_asm.s165 / the x86 32 X 32 -> 64 unsigned multiply instruction, MUL.
179 / Using the cpuid instruction directly would work equally
181 / cpuid instruction in the kernel, we use x86_featureset,
215 / Suitable only for x86 models that support SSE2 instruction set extensions
449 / Suitable only for x86 models that support SSE2 instruction set extensions
476 / Suitable only for x86 models that support SSE2 instruction set extensions
880 / Suitable only for x86 models that support SSE2 instruction set extensions
/titanic_41/usr/src/uts/sun4u/starcat/ml/
H A Ddrmach.il.cpp90 ! NOTE: The rdpr instruction executes as a noop. It has no
/titanic_41/usr/src/uts/sun4u/io/
H A Denvctrl_targets.c615 ehc_write_tda8444(struct ehc_envcunit *ehcp, int byteaddress, int instruction, in ehc_write_tda8444() argument
623 ASSERT(instruction == 0xf || instruction == 0x0); in ehc_write_tda8444()
626 control = (instruction << 4) | subaddress; in ehc_write_tda8444()
/titanic_41/usr/src/lib/librstp/common/
H A DREADME.CVS.HOWTO4 anonymous (pserver) CVS with the following instruction set. The module
/titanic_41/usr/src/cmd/sgs/librtld_db/common/
H A Dlibrtld_db.sparcv9.msg32 @ MSG_DB_BADFPLT "rtld_db: rpr: bad plt instruction found: \
/titanic_41/usr/src/cmd/sgs/libld/common/
H A Dlibld.intel.msg33 instruction sequence"
/titanic_41/usr/src/uts/
H A DREADME83 individual directories (one per module) under the "instruction-set
262 "instruction set architecture" directory (i.e.: sparc). If not, these
301 1] Create the build directory under the appropriate "instruction
311 "instruction set architecture" directory Makefile (i.e.:
/titanic_41/usr/src/ucbcmd/sbcp/
H A Dsbcp.s119 ! %g6 return address (after trap instruction)
/titanic_41/usr/src/lib/libast/amd64/src/lib/libast/FEATURE/
H A Dsignal128 "Illegal instruction",
/titanic_41/usr/src/lib/libast/i386/src/lib/libast/FEATURE/
H A Dsignal128 "Illegal instruction",
/titanic_41/usr/src/lib/libast/sparc/src/lib/libast/FEATURE/
H A Dsignal128 "Illegal instruction",
/titanic_41/usr/src/lib/libast/sparcv9/src/lib/libast/FEATURE/
H A Dsignal128 "Illegal instruction",
/titanic_41/usr/src/lib/libc/sparc/threads/
H A Dsparc.il52 * accept the 'cas' instruction, so we encode it in hex below.
/titanic_41/usr/src/lib/libtnfctl/
H A Dprb_rtld.c332 #error What is your breakpoint instruction?

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