xref: /titanic_41/usr/src/lib/libc/sparc/threads/sparc.il (revision 41efec2219526a9b3ecce26f97aba761ef1e1d0d)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"%Z%%M%	%I%	%E% SMI"

	.inline	_curthread, 0
	.register %g7, #scratch
	mov	%g7, %o0
	.end

	.inline	__curthread, 0
	.register %g7, #scratch
	ld	[%g7 + 80], %o0		! ul_self
	.end

	.inline	stkptr, 0
	mov	%sp, %o0
	.end

	.inline	gethrtime, 0
	ta	0x24
	.end

	.inline	set_lock_byte, 0
	ldstub	[%o0], %o0
	.end

	/*
	 * When compiling with -xarch=v8, the compiler refuses to
	 * accept the 'cas' instruction, so we encode it in hex below.
	 * We can't compile the 32-bit libc with -xarch=v8plus because
	 * then %g5 would become a scratch register and we would break
	 * 32-bit applications that use %g5 as an invariant register.
	 */

	.inline	atomic_cas_32, 0
	.word	0xd5e21009	! cas [%o0], %o1, %o2
	mov	%o2, %o0
	.end

	.inline	atomic_swap_32, 0
	ld	[%o0], %o2
1:
	mov	%o1, %o3
	.word	0xd7e2100a	! cas [%o0], %o2, %o3
	cmp	%o2, %o3
	bne,a	1b
	  mov	%o3, %o2
	mov	%o3, %o0
	.end

	.inline	atomic_inc_32, 0
	ld	[%o0], %o2
1:
	add	%o2, 1, %o3
	.word	0xd7e2100a	! cas [%o0], %o2, %o3
	cmp	%o2, %o3
	bne,a	1b
	  mov	%o3, %o2
	.end

	.inline	atomic_dec_32, 0
	ld	[%o0], %o2
1:
	sub	%o2, 1, %o3
	.word	0xd7e2100a	! cas [%o0], %o2, %o3
	cmp	%o2, %o3
	bne,a	1b
	  mov	%o3, %o2
	.end

	.inline	atomic_and_32, 0
	ld	[%o0], %o2
1:
	and	%o2, %o1, %o3
	.word	0xd7e2100a	! cas [%o0], %o2, %o3
	cmp	%o2, %o3
	bne,a	1b
	  mov	%o3, %o2
	.end

	.inline	atomic_or_32, 0
	ld	[%o0], %o2
1:
	or	%o2, %o1, %o3
	.word	0xd7e2100a	! cas [%o0], %o2, %o3
	cmp	%o2, %o3
	bne,a	1b
	  mov	%o3, %o2
	.end

	.inline	caller, 0
	mov	%i7, %o0
	.end

	.inline	getfp, 0
	mov	%fp, %o0
	.end