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/titanic_41/usr/src/uts/sfmmu/ml/
H A Dsfmmu_kdi.s72 set KHATID, %g5; \
73 ldx [%g5], %g5; \
74 cmp %g2, %g5; \
79 set UHMEHASH_SZ, %g5; \
80 ld [%g5], %g5; \
81 and %g4, %g5, %g4; \
83 set uhme_hash_pa, %g5; \
84 ldx [%g5], %g5; \
86 add %g4, %g5, %g4; \
89 set KHMEHASH_SZ, %g5; \
[all …]
H A Dsfmmu_asm.s683 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
706 cmp %g5, %o4
734 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
750 cmp %g5, %o4
1421 MAKE_JMP_INSTR(5, %o1, %o2) ! jmp %g5
1727 USE_ALTERNATE_GLOBALS(%g5)
1728 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g6, %g4)
1736 mov %g5, %g2
1768 USE_ALTERNATE_GLOBALS(%g5)
1769 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g6)
[all …]
/titanic_41/usr/src/uts/sun4v/ml/
H A Dmach_interrupt.s66 ! %g5 PC for fasttrap TL>0 handler
529 ldxa [%g7]ASI_MEM, %g5 ! %g5 = first 8 byte of ER buf
530 cmp 0, %g5
535 set 0, %g5
536 ldxa [%g4 + %g5]ASI_MEM, %g1
537 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 0 - 7
538 add %g5, 8, %g5
539 ldxa [%g4 + %g5]ASI_MEM, %g1
540 stxa %g1, [%g7 + %g5]ASI_MEM ! byte 8 - 15
541 add %g5, 8, %g5
[all …]
H A Dwbuf.s63 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
64 ! sfar (g5 == T_ALIGNMENT)
80 cmp %g5, T_ALIGNMENT
91 rdpr %tstate, %g5
92 and %g5, TSTATE_CWP, %g5
94 wrpr %g0, %g5, %cwp
160 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
161 CPU_PADDR(%g5, %g6)
166 ldxa [%g5 + CPU_MPCB_PA]%asi, %g6
167 lda [%g6 + MPCB_WBCNT]%asi, %g5
[all …]
H A Dtrap_table.s493 add %sp, 32, %g5 ;\
494 stxa %l4, [%g5 + %g1]asi_num ;\
495 stxa %l5, [%g5 + %g2]asi_num ;\
496 stxa %l6, [%g5 + %g3]asi_num ;\
497 stxa %l7, [%g5 + %g4]asi_num ;\
498 add %g5, 32, %g5 ;\
499 stxa %i0, [%g5 + %g1]asi_num ;\
500 stxa %i1, [%g5 + %g2]asi_num ;\
501 stxa %i2, [%g5 + %g3]asi_num ;\
502 stxa %i3, [%g5 + %g4]asi_num ;\
[all …]
/titanic_41/usr/src/uts/sun4u/ml/
H A Dwbuf.s62 ! g5 = mmu trap type, g6 = tag access reg (g5 != T_ALIGNMENT) or
63 ! sfar (g5 == T_ALIGNMENT)
79 cmp %g5, T_ALIGNMENT
90 rdpr %tstate, %g5
91 and %g5, TSTATE_CWP, %g5
93 wrpr %g0, %g5, %cwp
158 FAULT_WINTRACE(%g5, %g6, %g7, TT_F32_SO1)
159 CPU_ADDR(%g5, %g6)
163 ldn [%g5 + CPU_MPCB], %g6
164 ld [%g6 + MPCB_WBCNT], %g5
[all …]
H A Dzulu_asm.s62 ldxa [%g3]ASI_INTR_RECEIVE, %g5
63 stx %g5, [%g1 + ZULUVM_ASM_TLB_ADDR]
65 ldxa [%g3]ASI_INTR_RECEIVE, %g5
66 stx %g5, [%g1 + ZULUVM_ASM_TLB_TYPE]
183 sll %g2, 2, %g5
184 add %g5, %g3, %g5
185 lduw [%g5], %g3
187 stuw %g3, [%g5]
198 sll %g2, 2, %g5
199 add %g3, %g5, %g5
[all …]
H A Dtrap_table.s550 add %sp, 32, %g5 ;\
551 stxa %l4, [%g5 + %g1]asi_num ;\
552 stxa %l5, [%g5 + %g2]asi_num ;\
553 stxa %l6, [%g5 + %g3]asi_num ;\
554 stxa %l7, [%g5 + %g4]asi_num ;\
555 add %g5, 32, %g5 ;\
556 stxa %i0, [%g5 + %g1]asi_num ;\
557 stxa %i1, [%g5 + %g2]asi_num ;\
558 stxa %i2, [%g5 + %g3]asi_num ;\
559 stxa %i3, [%g5 + %g4]asi_num ;\
[all …]
H A Dzulu_hat_asm.s88 sllx %g4, 3, %g5
90 mov %g5, %g2 ! remember ctx * 8
92 add %g5, %g6, %g6
275 set zulu_ctx_tab, %g5
276 add %g6, %g5, %g5 ! %g5 = &zulu_ctx_tab[ctx_num]
277 ldx [%g5], %g6
279 stx %g6, [%g5]
/titanic_41/usr/src/common/crypto/arcfour/sun4u/
H A Darcfour_crypt_asm.s105 add %g3, %g4, %g5
107 and %g5, 255, %g5
119 ldub [%i5 + %g5], %g5
124 sllx %g5, 48, %g5
128 or %o0, %g5, %o0
144 add %g3, %g4, %g5
146 and %g5, 255, %g5
159 ldub [%i5 + %g5], %g5
164 sllx %g5, 32, %g5
168 or %o0, %g5, %o0
[all …]
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus_asm.s191 add %g1, CH_ERR_TL1_LOGOUT, %g5
192 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
207 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
208 stxa %g5, [%g0]ASI_ESTATE_ERR
216 PN_L2_FLUSHALL(%g3, %g4, %g5)
219 set CH_ECACHE_MIN_LSIZE, %g5
228 CHP_ECACHE_FLUSHALL(%g4, %g5, %g3)
248 ASM_LD(%g5, dcache_linesize)
249 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
275 mov CH_ICACHE_LSIZE, %g5
[all …]
H A Dus3_cheetah_asm.s120 add %g1, CH_ERR_TL1_LOGOUT, %g5
121 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
136 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
137 stxa %g5, [%g0]ASI_ESTATE_ERR
146 set CH_ECACHE_MIN_LSIZE, %g5
156 CH_ECACHE_FLUSHALL(%g4, %g5, %g6)
176 ASM_LD(%g5, dcache_linesize)
177 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
199 ASM_LD(%g5, icache_linesize)
200 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
[all …]
H A Dus3_jalapeno_asm.s428 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
435 CPU_INDEX(%g4, %g5)
437 set cpunodes, %g5
438 add %g4, %g5, %g4
439 ld [%g4 + ECACHE_LINESIZE], %g5
449 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
463 ASM_LD(%g5, dcache_size)
465 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
472 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4);
473 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
[all …]
H A Dus3_common_asm.s324 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
325 srlx %g5, CTXREG_NEXT_SHIFT, %g2 /* %g2 = nucleus pgsz */
331 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
378 sethi %hi(FLUSH_ADDR), %g5
382 flush %g5 ! flush required by immu
395 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
401 or %g5, %g4, %g5
407 or %g5, %g2, %g5 /* %g5 = nucleus pgsz | primary pgsz | cnum */
408 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */
411 sethi %hi(FLUSH_ADDR), %g5
[all …]
H A Dspitfire_asm.s565 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */
570 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */
600 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU
605 stxa %g5, [%g4]ASI_DMMU /* write new ctxum */
608 sethi %hi(FLUSH_ADDR), %g5
612 flush %g5
662 DCACHE_FLUSHPAGE(%g1, %g2, %g3, %g4, %g5)
821 andn %g4, PSTATE_IE, %g5
822 wrpr %g0, %g5, %pstate ! disable interrupts
825 or %g0, 1, %g5
[all …]
/titanic_41/usr/src/cmd/mdb/sparc/v9/kmdb/
H A Dkaif_resume.s74 mov %l5, %g5
116 ldx [%g5 + KREG_OFF(KREG_CWP)], %g4
118 ldx [%g5 + KREG_OFF(KREG_OTHERWIN)], %g4
120 ldx [%g5 + KREG_OFF(KREG_CLEANWIN)], %g4
122 ldx [%g5 + KREG_OFF(KREG_CANSAVE)], %g4
124 ldx [%g5 + KREG_OFF(KREG_CANRESTORE)], %g4
126 ldx [%g5 + KREG_OFF(KREG_WSTATE)], %g4
129 ldx [%g5 + KREG_OFF(KREG_Y)], %g4
132 ldx [%g5 + KREG_OFF(KREG_PIL)], %g4
150 ldx [%g5 + KREG_OFF(KREG_PC)], %g4
[all …]
H A Dkaif_startup.s102 mov %g7, %g5 ! we'll need %g7 for the ID retriever
132 add %g6, KRS_GREGS + GREG_KREGS, %g5
137 stx %g2, [%g5 + KREG_OFF(KREG_PC)]
139 stx %g2, [%g5 + KREG_OFF(KREG_NPC)]
141 stx %g2, [%g5 + KREG_OFF(KREG_TT)]
158 stx %g5, [%o5 + KREG_OFF(KREG_G5)]
184 add %g6, KRS_GREGS + GREG_KREGS, %g5
186 ldx [%g5 + KREG_OFF(KREG_PC)], %g4
188 ldx [%g5 + KREG_OFF(KREG_TT)], %g4
215 stx %g2, [%g5 + KREG_OFF(KREG_TBA)]
[all …]
/titanic_41/usr/src/uts/sun4u/starfire/ml/
H A Didn_asm.s178 sub %o5, %g5, %g2 ! limit - tick < 0 if timeout
246 sub %g5, %o4, %g5 ! how long did we wait?
248 1: orcc %g5, %g0, %g0 ! any bits left?
249 srlx %g5, 1, %g5 ! bits to the right
256 CPU_INDEX(%o0, %g5)
265 ld [%o0 + %o1], %g5
266 inc %g5
267 st %g5, [%o0 + %o1]
300 CPU_INDEX(%g6, %g5) ! g6 = cpuid
303 ! g5 = cur = idn_dmv_cpu[cpuid]
[all …]
/titanic_41/usr/src/cmd/mdb/sun4v/v9/kmdb/
H A Dmach_asmutil.h49 stx %o5, [%g5 + KREG_OFF(KREG_O5)]; \
50 stx %o4, [%g5 + KREG_OFF(KREG_O4)]; \
51 stx %o3, [%g5 + KREG_OFF(KREG_O3)]; \
53 mov %g5, %o5 /* %o5 is gregs pointer now */; \
61 mov %o5, %g5 /* restore %g5 as gregs pointer */; \
63 ldx [%g5 + KREG_OFF(KREG_O5)], %o5 /* restore saved %o5 */; \
64 ldx [%g5 + KREG_OFF(KREG_O4)], %o4 /* restore saved %o4 */; \
66 ldx [%g5 + KREG_OFF(KREG_O3)], %o3 /* restore saved %o3 */
/titanic_41/usr/src/common/bignum/sun4u/
H A Dmont_mulf_v9.s232 /* 0x0008 77 */ sra %i3,0,%g5
241 /* 0x0014 86 */ sub %g5,1,%g2
249 /* 0x0034 */ sub %g5,1,%g4
252 /* 0x0040 */ sub %g5,2,%l0
277 /* 0x0074 */ or %g0,3,%g5
279 /* 0x007c */ or %g0,32,%g5
293 /* 0x00b4 87 */ ldd [%i1+%g5],%f0
294 /* 0x00b8 91 */ sllx %g3,16,%g5
296 /* 0x00c0 86 */ add %l6,%g5,%l7
307 /* 0x00ec 90 */ ldx [%sp+2223],%g5
[all …]
/titanic_41/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu_asm.s134 CPU_TSBMISS_AREA(%g5, %g6) /* load cpu tsbmiss area */
135 ldx [%g5 + TSBMISS_UHATID], %g5 /* load usfmmup */
136 cmp %g5, %g1 /* hat toBe-invalid running? */
141 sethi %hi(shctx_on), %g5
142 ld [%g5 + %lo(shctx_on)], %g5
143 brz %g5, 1f
144 mov MMU_SHARED_CONTEXT, %g5
146 stxa %g0, [%g5]ASI_MMU_CTX
150 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = pgsz | sec-ctx */
152 and %g5, %g4, %g5 /* %g5 = sec-ctx */
[all …]
/titanic_41/usr/src/lib/libc/sparcv9/gen/
H A Dstrncpy.s105 andcc %g5, 7, %g0 ! dst word aligned ?
114 sub %o1, %o4, %g5 ! dword - 0x0101010101010101
115 andcc %g5, %g1, %g0 ! ((dword - 0x0101010101010101) & ~dword & 0x8080808080808080)
274 sub %o1, %o4, %g5 ! x - 0x0101010101010101
275 andcc %g5, %g1, %g0 ! ((x - 0x0101010101010101) & ~x & 0x8080808080808080)
277 add %o2, %g4, %g5 ! dst (in pointer form)
279 stb %g1, [%g5] ! store first byte
281 stw %g1, [%g5 + 1] ! store bytes 2, 3, 4, 5
283 sth %g1, [%g5 + 5] ! store bytes 6, 7
285 stb %o1, [%g5 + 7] ! store eigth byte
[all …]
H A Dmemcpy.s61 mov %o0, %g5 ! save des address for return val
71 stb %o3, [%g5] ! move a byte to align src
72 inc 1, %g5
76 andcc %g5, 3, %o5
81 stb %o4, [%g5] ! have to do bytes,
82 stb %o3, [%g5 + 1] ! don't know dst alingment
/titanic_41/usr/src/lib/libc/sparcv9/crt/
H A D__align_cpy_2.s44 mov %o0, %g5 ! save des address for return val
54 sth %o3, [%g5] ! move 2 bytes to align src
55 inc 2, %g5
59 andcc %g5, 6, %o5
64 sth %o4, [%g5] ! have to do 2-bytes,
65 sth %o3, [%g5 + 2] ! don't know dst alignment
/titanic_41/usr/src/uts/sun4u/sunfire/ml/
H A Dsysctrl_asm.s72 CPU_INDEX(%g4, %g5)
79 sethi %hi(panicstr), %g5
80 ldn [%g5 + %lo(panicstr)], %g5
81 brnz %g5, 2f ! exit if in panic

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