| #
bd963cb9 |
| 06-Oct-2009 |
Ethindra Ramamurthy <Ethindra.Ramamurthy@Sun.COM> |
6867095 application fails after upgrading from 137137-09 to 138888-01 or later
|
| #
444ce08e |
| 22-Aug-2008 |
Donghai Qiao <Donghai.Qiao@Sun.COM> |
6672470 Looping within uiomove()/xcopyout()/copyout_move()
6707987 kpm has some VAC handling issues
6388567 VAC flushing is broken on US III-IV+ for large pages
|
| #
19f938d5 |
| 21-May-2008 |
jfrank <none@none> |
6699498 Need workaround for Cheetah+ DTLB erratum 34
|
| #
2dd3029a |
| 05-May-2008 |
jimand <none@none> |
6675334 "bad kernel MMU trap at TL 2 panic" caused by an urgent error
|
| #
febcc4a5 |
| 04-Dec-2007 |
jimand <none@none> |
6551376 need ability to program kernel TLB page size on OPL
6572547 need to preserve nucleus page sizes when changing kernel context register
|
| #
63360950 |
| 31-Jan-2007 |
mp204432 <none@none> |
6363303 numerous source files misspell "relevant"
|
| #
b0fc0e77 |
| 24-Oct-2006 |
govinda <none@none> |
6402328 Add multi-pil and unlimited softint support for SPARC
|
| #
1e2e7a75 |
| 20-Jun-2006 |
huah <none@none> |
6373298 Integrate support for MMU context ID domains
|
| #
8f230a59 |
| 16-Jan-2006 |
bs21162 <none@none> |
4599450 sys_trap() should check both %tstate.priv bit and the primary context register
|
| #
4fd7ecab |
| 02-Nov-2005 |
dilpreet <none@none> |
6267828 Multiple secondary error reports leading to pci_ecc_classify() work improperly
6325373 6249127 Broke cautious error handling.
6335152 cpu_log_fast_ecc_error enables NCEEN even if it was disab
6267828 Multiple secondary error reports leading to pci_ecc_classify() work improperly
6325373 6249127 Broke cautious error handling.
6335152 cpu_log_fast_ecc_error enables NCEEN even if it was disabled on entry
show more ...
|
| #
7c478bd9 |
| 14-Jun-2005 |
stevel@tonic-gate <none@none> |
OpenSolaris Launch
|