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Searched refs:PIL_MAX (Results 1 – 22 of 22) sorted by relevance

/titanic_41/usr/src/uts/i86pc/sys/
H A Dmachcpuvar.h76 ulong_t pending_sel[PIL_MAX + 1]; /* event array selectors */
77 ulong_t pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8];
115 uint64_t intrstat[PIL_MAX + 1][2];
H A Dapix.h126 struct autovec *x_intr_head[PIL_MAX + 1];
128 struct autovec *x_intr_tail[PIL_MAX + 1];
/titanic_41/usr/src/uts/sparc/sys/
H A Dmachlock.h106 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
108 #define PIL_MAX 15 macro
/titanic_41/usr/src/uts/intel/sys/
H A Dmachlock.h109 #define PIL_MAX 15 macro
115 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
/titanic_41/usr/src/uts/sun4/io/
H A Divintr.c189 if (inum >= MAXIVNUM || pil > PIL_MAX) in add_ivintr()
233 if (inum >= MAXIVNUM || pil > PIL_MAX) in rem_ivintr()
270 if (pil > PIL_MAX) in add_softintr()
352 if (pil > PIL_MAX) in update_softint_pri()
/titanic_41/usr/src/uts/sun4/os/
H A Dmachdep.c449 KSTAT_TYPE_NAMED, PIL_MAX * 2, NULL, zoneid); in cpu_create_intrstat()
458 for (i = 0; i < PIL_MAX; i++) { in cpu_create_intrstat()
500 for (i = 0; i < PIL_MAX; i++) { in cpu_kstat_intrstat_update()
505 for (i = 0; i < PIL_MAX; i++) { in cpu_kstat_intrstat_update()
H A Dprom_subr.c310 ASSERT(getpil() == PIL_MAX); in kern_preprom()
H A Dddi_impl.c790 if ((hdlp->ih_pri < 1) || (hdlp->ih_pri > PIL_MAX)) in i_ddi_add_ivintr()
/titanic_41/usr/src/uts/sun4u/sys/
H A Dmachcpuvar.h139 uint64_t intrstat[PIL_MAX+1][2];
/titanic_41/usr/src/uts/i86pc/ml/
H A Dgenassym.c76 printf("#define\tPIL_MAX 0x%x\n", PIL_MAX); in main()
/titanic_41/usr/src/uts/sun4v/sys/
H A Dmachcpuvar.h154 uint64_t intrstat[PIL_MAX+1][2];
/titanic_41/usr/src/uts/i86pc/os/
H A Dintr.c1143 KSTAT_TYPE_NAMED, PIL_MAX * 2, NULL, zoneid); in cpu_create_intrstat()
1152 for (i = 0; i < PIL_MAX; i++) { in cpu_create_intrstat()
1189 for (i = 0; i < PIL_MAX; i++) { in cpu_kstat_intrstat_update()
/titanic_41/usr/src/uts/sun4v/ml/
H A Dmach_proc_init.s82 wrpr %g0, PIL_MAX, %pil
/titanic_41/usr/src/uts/sparc/v9/ml/
H A Dsparcv9_subr.s80 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
115 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
/titanic_41/usr/src/uts/common/sys/
H A Dsysinfo.h209 uint64_t intr[PIL_MAX]; /* device interrupts per PIL */
/titanic_41/usr/src/cmd/mdb/common/modules/genunix/
H A Dsobj.c603 sp->m_minspl > PIL_MAX || sp->m_oldspl > PIL_MAX || in mutex()
/titanic_41/usr/src/uts/sun4/ml/
H A Dinterrupt.s146 ! current_thread starts at PIL_MAX to protect cpu_intr_actv
151 mov PIL_MAX, %g4 ! %g4 = PIL_MAX (15)
1443 wrpr %g0, PIL_MAX, %pil ! disable interrupts (1-15)
2185 wrpr %g0, PIL_MAX, %pil ! make this easy -- block normal intrs
/titanic_41/usr/src/uts/common/io/
H A Davintr.c744 ASSERT(pil >= 0 && pil <= PIL_MAX); in av_dispatch_softvect()
/titanic_41/usr/src/uts/common/os/
H A Dcpu_event.c1118 for (val = 0, i = 0; i < PIL_MAX; i++) { in cpu_idle_prop_update_intr_cnt()
H A Dcpu.c3228 for (i = 0; i < PIL_MAX; i++) in cpu_sys_stats_ks_update()
3366 for (i = 0; i < PIL_MAX; i++) in cpu_stat_ks_update()
/titanic_41/usr/src/uts/sun4u/cpu/
H A Dopl_olympus_asm.s964 wrpr %g0, PIL_MAX, %pil ;\
/titanic_41/usr/src/uts/sfmmu/vm/
H A Dhat_sfmmu.c1365 mutex_init(&kpr_suspendlock, NULL, MUTEX_SPIN, (void *)PIL_MAX); in hat_init()
7438 ASSERT(getpil() == PIL_MAX); in hat_pagereload()