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Searched refs:PCI_REG_ADDR_G (Results 1 – 17 of 17) sorted by relevance

/titanic_41/usr/src/uts/sun4/io/px/
H A Dpx_util.c216 uint32_t space_type = PCI_REG_ADDR_G(px_rp->pci_phys_hi); in px_xlate_reg()
223 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in px_xlate_reg()
233 if (space_type != PCI_REG_ADDR_G(rng_p->child_high)) in px_xlate_reg()
238 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) in px_xlate_reg()
637 uint32_t cfg_space_type = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); in px_get_cfg_pabase()
642 if (PCI_REG_ADDR_G(rangep->child_high) == cfg_space_type) in px_get_cfg_pabase()
H A Dpx_tools.c39 #define PCI_CONFIG_SPACE (PCI_REG_ADDR_G(PCI_ADDR_CONFIG))
40 #define PCI_IO_SPACE (PCI_REG_ADDR_G(PCI_ADDR_IO))
41 #define PCI_MEM32_SPACE (PCI_REG_ADDR_G(PCI_ADDR_MEM32))
42 #define PCI_MEM64_SPACE (PCI_REG_ADDR_G(PCI_ADDR_MEM64))
/titanic_41/usr/src/uts/sun4u/io/pci/
H A Dpci_util.c217 uint32_t space_type = PCI_REG_ADDR_G(pci_rp->pci_phys_hi); in pci_xlate_reg()
223 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in pci_xlate_reg()
232 if (space_type != PCI_REG_ADDR_G(rng_p->child_high)) in pci_xlate_reg()
236 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) in pci_xlate_reg()
701 uint32_t cfg_space_type = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); in pci_get_cfg_pabase()
706 if (PCI_REG_ADDR_G(rangep->child_high) == cfg_space_type) in pci_get_cfg_pabase()
H A Dpci_tools.c49 #define PCI_CONFIG_RANGE_BANK (PCI_REG_ADDR_G(PCI_ADDR_CONFIG))
50 #define PCI_IO_RANGE_BANK (PCI_REG_ADDR_G(PCI_ADDR_IO))
51 #define PCI_MEM_RANGE_BANK (PCI_REG_ADDR_G(PCI_ADDR_MEM32))
52 #define PCI_MEM64_RANGE_BANK (PCI_REG_ADDR_G(PCI_ADDR_MEM64))
/titanic_41/usr/src/uts/sun4/io/
H A Dpcicfg.c1986 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_bridge_assign()
1987 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_bridge_assign()
2005 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pcicfg_bridge_assign()
2020 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pcicfg_bridge_assign()
2132 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_device_assign()
2133 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_device_assign()
2166 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pcicfg_device_assign()
2189 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pcicfg_device_assign()
2299 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { in pcicfg_device_assign_readonly()
2300 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_device_assign_readonly()
[all …]
/titanic_41/usr/src/uts/sun4u/opl/io/pcicmu/
H A Dpcmu_util.c194 uint32_t space_type = PCI_REG_ADDR_G(pcmu_rp->pci_phys_hi); in pcmu_xlate_reg()
200 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in pcmu_xlate_reg()
210 if (space_type != PCI_REG_ADDR_G(rng_p->child_high)) { in pcmu_xlate_reg()
215 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in pcmu_xlate_reg()
/titanic_41/usr/src/uts/common/io/
H A Dbusra.c1038 switch (PCI_REG_ADDR_G(regs[i].pci_phys_hi)) { in pci_resource_setup()
1039 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pci_resource_setup()
1048 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pci_resource_setup()
1059 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pci_resource_setup()
1066 case PCI_REG_ADDR_G(PCI_ADDR_CONFIG): in pci_resource_setup()
1071 PCI_REG_ADDR_G(regs[i].pci_phys_hi)); in pci_resource_setup()
1228 switch (PCI_REG_ADDR_G(avail_p->pci_phys_hi)) { in pci_resource_setup_avail()
1229 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): { in pci_resource_setup_avail()
1237 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pci_resource_setup_avail()
H A Dpcic.c5994 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == in pcic_init_assigned()
5995 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && in pcic_init_assigned()
6001 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == in pcic_init_assigned()
6002 PCI_REG_ADDR_G(PCI_ADDR_IO)) && in pcic_init_assigned()
/titanic_41/usr/src/uts/intel/io/hotplug/pcicfg/
H A Dpcicfg.c1882 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_bridge_assign()
1883 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_bridge_assign()
1905 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pcicfg_bridge_assign()
1926 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pcicfg_bridge_assign()
2042 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in pcicfg_device_assign()
2043 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_device_assign()
2081 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pcicfg_device_assign()
2109 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pcicfg_device_assign()
2227 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { in pcicfg_device_assign_readonly()
2228 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pcicfg_device_assign_readonly()
[all …]
/titanic_41/usr/src/uts/sun4/io/efcode/
H A Dfcpci.c1319 if (PCI_REG_ADDR_G(assigned[i].pci_phys_hi) != in pci_alloc_resource()
1320 PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) { in pci_alloc_resource()
1414 switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) { in pci_alloc_resource()
1415 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pci_alloc_resource()
1466 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pci_alloc_resource()
1505 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pci_alloc_resource()
1631 switch (PCI_REG_ADDR_G(phys_spec.pci_phys_hi)) { in pci_free_resource()
1632 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in pci_free_resource()
1645 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in pci_free_resource()
1656 case PCI_REG_ADDR_G(PCI_ADDR_IO): in pci_free_resource()
/titanic_41/usr/src/uts/sun4u/io/pciex/
H A Dpci_cfgacc_4u.c35 #define PCI_CFG_SPACE (PCI_REG_ADDR_G(PCI_ADDR_CONFIG))
/titanic_41/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c893 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in cardbus_bridge_assign()
894 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in cardbus_bridge_assign()
914 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in cardbus_bridge_assign()
951 case PCI_REG_ADDR_G(PCI_ADDR_IO): in cardbus_bridge_assign()
1040 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { in cardbus_isa_bridge_ranges()
1041 case PCI_REG_ADDR_G(PCI_ADDR_IO): in cardbus_isa_bridge_ranges()
2092 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { in cardbus_sum_resources()
2094 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): in cardbus_sum_resources()
2113 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): in cardbus_sum_resources()
2127 case PCI_REG_ADDR_G(PCI_ADDR_IO): in cardbus_sum_resources()
[all …]
H A Dcardbus.c1893 if (PCI_REG_ADDR_G(pci_rp->pci_phys_hi) == in pcirp2rp()
1894 PCI_REG_ADDR_G(PCI_ADDR_IO)) { in pcirp2rp()
/titanic_41/usr/src/uts/common/os/
H A Dpcifm.c1217 if (tgt_err->tgt_pci_space == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in pci_check_regs()
1230 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi) && in pci_check_regs()
1256 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) && in pci_check_regs()
1281 PCI_REG_ADDR_G(drv_regp[rn].pci_phys_hi)) && in pci_check_regs()
1388 space_type = PCI_REG_ADDR_G(rangep->child_high); in pci_check_ranges()
1389 if (space_type == PCI_REG_ADDR_G(PCI_ADDR_CONFIG)) { in pci_check_ranges()
/titanic_41/usr/src/uts/common/io/cpqary3/
H A Dcpqary3.c804 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x2) { in cpqary3_update_ctlrdetails()
819 if (PCI_REG_ADDR_G(*(regp + regset_index * 5)) == 0x3) { in cpqary3_update_ctlrdetails()
/titanic_41/usr/src/uts/common/sys/
H A Dpci.h1179 #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) macro
/titanic_41/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c2515 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); in px_lib_get_cfgacc_base()