1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip VDPU381 HEVC backend
4 *
5 * Copyright (C) 2025 Collabora, Ltd.
6 * Detlev Casanova <detlev.casanova@collabora.com>
7 */
8
9 #include <media/v4l2-mem2mem.h>
10
11 #include "rkvdec.h"
12 #include "rkvdec-cabac.h"
13 #include "rkvdec-rcb.h"
14 #include "rkvdec-hevc-common.h"
15 #include "rkvdec-vdpu381-regs.h"
16
17 // SPS
18 struct rkvdec_hevc_sps {
19 u16 video_parameters_set_id : 4;
20 u16 seq_parameters_set_id_sps : 4;
21 u16 chroma_format_idc : 2;
22 u16 width : 16;
23 u16 height : 16;
24 u16 bit_depth_luma : 4;
25 u16 bit_depth_chroma : 4;
26 u16 max_pic_order_count_lsb : 5;
27 u16 diff_max_min_luma_coding_block_size : 2;
28 u16 min_luma_coding_block_size : 3;
29 u16 min_transform_block_size : 3;
30 u16 diff_max_min_transform_block_size : 2;
31 u16 max_transform_hierarchy_depth_inter : 3;
32 u16 max_transform_hierarchy_depth_intra : 3;
33 u16 scaling_list_enabled_flag : 1;
34 u16 amp_enabled_flag : 1;
35 u16 sample_adaptive_offset_enabled_flag : 1;
36 u16 pcm_enabled_flag : 1;
37 u16 pcm_sample_bit_depth_luma : 4;
38 u16 pcm_sample_bit_depth_chroma : 4;
39 u16 pcm_loop_filter_disabled_flag : 1;
40 u16 diff_max_min_pcm_luma_coding_block_size : 3;
41 u16 min_pcm_luma_coding_block_size : 3;
42 u16 num_short_term_ref_pic_sets : 7;
43 u16 long_term_ref_pics_present_flag : 1;
44 u16 num_long_term_ref_pics_sps : 6;
45 u16 sps_temporal_mvp_enabled_flag : 1;
46 u16 strong_intra_smoothing_enabled_flag : 1;
47 u16 reserved_0 : 7;
48 u16 sps_max_dec_pic_buffering_minus1 : 4;
49 u16 reserved_0_2 : 3;
50 u16 reserved_f : 8;
51 } __packed;
52
53 //PPS
54 struct rkvdec_hevc_pps {
55 u16 picture_parameters_set_id : 6;
56 u16 seq_parameters_set_id_pps : 4;
57 u16 dependent_slice_segments_enabled_flag : 1;
58 u16 output_flag_present_flag : 1;
59 u16 num_extra_slice_header_bits : 13;
60 u16 sign_data_hiding_enabled_flag : 1;
61 u16 cabac_init_present_flag : 1;
62 u16 num_ref_idx_l0_default_active : 4;
63 u16 num_ref_idx_l1_default_active : 4;
64 u16 init_qp_minus26 : 7;
65 u16 constrained_intra_pred_flag : 1;
66 u16 transform_skip_enabled_flag : 1;
67 u16 cu_qp_delta_enabled_flag : 1;
68 u16 log2_min_cb_size : 3;
69 u16 pps_cb_qp_offset : 5;
70 u16 pps_cr_qp_offset : 5;
71 u16 pps_slice_chroma_qp_offsets_present_flag : 1;
72 u16 weighted_pred_flag : 1;
73 u16 weighted_bipred_flag : 1;
74 u16 transquant_bypass_enabled_flag : 1;
75 u16 tiles_enabled_flag : 1;
76 u16 entropy_coding_sync_enabled_flag : 1;
77 u16 pps_loop_filter_across_slices_enabled_flag : 1;
78 u16 loop_filter_across_tiles_enabled_flag : 1;
79 u16 deblocking_filter_override_enabled_flag : 1;
80 u16 pps_deblocking_filter_disabled_flag : 1;
81 u16 pps_beta_offset_div2 : 4;
82 u16 pps_tc_offset_div2 : 4;
83 u16 lists_modification_present_flag : 1;
84 u16 log2_parallel_merge_level : 3;
85 u16 slice_segment_header_extension_present_flag : 1;
86 u16 zeroes : 3;
87 u16 num_tile_columns : 5;
88 u16 num_tile_rows : 5;
89 u16 sps_pps_mode : 4;
90 u16 reserved_bits : 14;
91 u16 reserved;
92 } __packed;
93
94 struct rkvdec_hevc_tile {
95 u16 value0 : 12;
96 u16 value1 : 12;
97 } __packed;
98
99 struct rkvdec_sps_pps_packet {
100 struct rkvdec_hevc_sps sps;
101 struct rkvdec_hevc_pps pps;
102 struct rkvdec_hevc_tile column_width[10];
103 struct rkvdec_hevc_tile row_height[11];
104 u32 zeroes[3];
105 u32 zeroes_bits : 6;
106 u32 padding_bits : 2;
107 u32 padding;
108 } __packed;
109
110 struct rkvdec_hevc_priv_tbl {
111 struct rkvdec_sps_pps_packet param_set[64];
112 struct rkvdec_rps rps;
113 struct scaling_factor scaling_list;
114 u8 cabac_table[27456];
115 };
116
117 struct rkvdec_hevc_ctx {
118 struct rkvdec_aux_buf priv_tbl;
119 struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
120 struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache;
121 struct rkvdec_vdpu381_regs_hevc regs;
122 };
123
assemble_hw_pps(struct rkvdec_ctx * ctx,struct rkvdec_hevc_run * run)124 static void assemble_hw_pps(struct rkvdec_ctx *ctx,
125 struct rkvdec_hevc_run *run)
126 {
127 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
128 const struct v4l2_ctrl_hevc_sps *sps = run->sps;
129 const struct v4l2_ctrl_hevc_pps *pps = run->pps;
130 struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
131 struct rkvdec_sps_pps_packet *hw_ps;
132 bool tiles_enabled;
133 s32 max_cu_width;
134 s32 pic_in_cts_width;
135 s32 pic_in_cts_height;
136 u16 log2_min_cb_size, width, height;
137 u16 column_width[20];
138 u16 row_height[22];
139 u8 pcm_enabled;
140 u32 i;
141
142 /*
143 * HW read the SPS/PPS information from PPS packet index by PPS id.
144 * offset from the base can be calculated by PPS_id * 32 (size per PPS
145 * packet unit). so the driver copy SPS/PPS information to the exact PPS
146 * packet unit for HW accessing.
147 */
148 if (pps->pic_parameter_set_id >= ARRAY_SIZE(priv_tbl->param_set))
149 return;
150 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
151 memset(hw_ps, 0, sizeof(*hw_ps));
152
153 /* write sps */
154 hw_ps->sps.video_parameters_set_id = sps->video_parameter_set_id;
155 hw_ps->sps.seq_parameters_set_id_sps = sps->seq_parameter_set_id;
156 hw_ps->sps.chroma_format_idc = sps->chroma_format_idc;
157
158 log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
159 width = sps->pic_width_in_luma_samples;
160 height = sps->pic_height_in_luma_samples;
161 hw_ps->sps.width = width;
162 hw_ps->sps.height = height;
163 hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8 + 8;
164 hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8;
165 hw_ps->sps.max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
166 hw_ps->sps.diff_max_min_luma_coding_block_size =
167 sps->log2_diff_max_min_luma_coding_block_size;
168 hw_ps->sps.min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
169 hw_ps->sps.min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2;
170 hw_ps->sps.diff_max_min_transform_block_size =
171 sps->log2_diff_max_min_luma_transform_block_size;
172 hw_ps->sps.max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter;
173 hw_ps->sps.max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra;
174 hw_ps->sps.scaling_list_enabled_flag =
175 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
176 hw_ps->sps.amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED);
177 hw_ps->sps.sample_adaptive_offset_enabled_flag =
178 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET);
179
180 pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
181 hw_ps->sps.pcm_enabled_flag = pcm_enabled;
182 hw_ps->sps.pcm_sample_bit_depth_luma =
183 pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0;
184 hw_ps->sps.pcm_sample_bit_depth_chroma =
185 pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0;
186 hw_ps->sps.pcm_loop_filter_disabled_flag =
187 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED);
188 hw_ps->sps.diff_max_min_pcm_luma_coding_block_size =
189 sps->log2_diff_max_min_pcm_luma_coding_block_size;
190 hw_ps->sps.min_pcm_luma_coding_block_size =
191 pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0;
192 hw_ps->sps.num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets;
193 hw_ps->sps.long_term_ref_pics_present_flag =
194 !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT);
195 hw_ps->sps.num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps;
196 hw_ps->sps.sps_temporal_mvp_enabled_flag =
197 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED);
198 hw_ps->sps.strong_intra_smoothing_enabled_flag =
199 !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED);
200 hw_ps->sps.sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1;
201 hw_ps->sps.reserved_f = 0xff;
202
203 /* write pps */
204 hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id;
205 hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id;
206 hw_ps->pps.dependent_slice_segments_enabled_flag =
207 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED);
208 hw_ps->pps.output_flag_present_flag =
209 !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT);
210 hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits;
211 hw_ps->pps.sign_data_hiding_enabled_flag =
212 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED);
213 hw_ps->pps.cabac_init_present_flag =
214 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT);
215 hw_ps->pps.num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1;
216 hw_ps->pps.num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1;
217 hw_ps->pps.init_qp_minus26 = pps->init_qp_minus26;
218 hw_ps->pps.constrained_intra_pred_flag =
219 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED);
220 hw_ps->pps.transform_skip_enabled_flag =
221 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED);
222 hw_ps->pps.cu_qp_delta_enabled_flag =
223 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED);
224 hw_ps->pps.log2_min_cb_size = log2_min_cb_size +
225 sps->log2_diff_max_min_luma_coding_block_size -
226 pps->diff_cu_qp_delta_depth;
227 hw_ps->pps.pps_cb_qp_offset = pps->pps_cb_qp_offset;
228 hw_ps->pps.pps_cr_qp_offset = pps->pps_cr_qp_offset;
229 hw_ps->pps.pps_slice_chroma_qp_offsets_present_flag =
230 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT);
231 hw_ps->pps.weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED);
232 hw_ps->pps.weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED);
233 hw_ps->pps.transquant_bypass_enabled_flag =
234 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED);
235
236 tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
237 hw_ps->pps.tiles_enabled_flag = tiles_enabled;
238 hw_ps->pps.entropy_coding_sync_enabled_flag =
239 !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED);
240 hw_ps->pps.pps_loop_filter_across_slices_enabled_flag =
241 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED);
242 hw_ps->pps.loop_filter_across_tiles_enabled_flag =
243 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED);
244 hw_ps->pps.deblocking_filter_override_enabled_flag =
245 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED);
246 hw_ps->pps.pps_deblocking_filter_disabled_flag =
247 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER);
248 hw_ps->pps.pps_beta_offset_div2 = pps->pps_beta_offset_div2;
249 hw_ps->pps.pps_tc_offset_div2 = pps->pps_tc_offset_div2;
250 hw_ps->pps.lists_modification_present_flag =
251 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT);
252 hw_ps->pps.log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2;
253 hw_ps->pps.slice_segment_header_extension_present_flag =
254 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT);
255 hw_ps->pps.num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 0;
256 hw_ps->pps.num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 0;
257 hw_ps->pps.sps_pps_mode = 0;
258 hw_ps->pps.reserved_bits = 0x3fff;
259 hw_ps->pps.reserved = 0xffff;
260
261 // Setup tiles information
262 memset(column_width, 0, sizeof(column_width));
263 memset(row_height, 0, sizeof(row_height));
264
265 max_cu_width = 1 << (sps->log2_diff_max_min_luma_coding_block_size + log2_min_cb_size);
266 pic_in_cts_width = DIV_ROUND_UP(width, max_cu_width);
267 pic_in_cts_height = DIV_ROUND_UP(height, max_cu_width);
268
269 if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
270 if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) {
271 compute_tiles_uniform(run, log2_min_cb_size, width, height,
272 pic_in_cts_width, pic_in_cts_height,
273 column_width, row_height);
274 } else {
275 compute_tiles_non_uniform(run, log2_min_cb_size, width, height,
276 pic_in_cts_width, pic_in_cts_height,
277 column_width, row_height);
278 }
279 } else {
280 column_width[0] = DIV_ROUND_UP(width, max_cu_width);
281 row_height[0] = DIV_ROUND_UP(height, max_cu_width);
282 }
283
284 for (i = 0; i < 20; i++) {
285 if (column_width[i] > 0)
286 column_width[i]--;
287
288 if (i & 1)
289 hw_ps->column_width[i / 2].value1 = column_width[i];
290 else
291 hw_ps->column_width[i / 2].value0 = column_width[i];
292 }
293
294 for (i = 0; i < 22; i++) {
295 if (row_height[i] > 0)
296 row_height[i]--;
297
298 if (i & 1)
299 hw_ps->row_height[i / 2].value1 = row_height[i];
300 else
301 hw_ps->row_height[i / 2].value0 = row_height[i];
302 }
303
304 hw_ps->padding = 0xffffffff;
305 hw_ps->padding_bits = 0x3;
306 }
307
set_ref_valid(struct rkvdec_vdpu381_regs_hevc * regs,int id,u32 valid)308 static void set_ref_valid(struct rkvdec_vdpu381_regs_hevc *regs, int id, u32 valid)
309 {
310 switch (id) {
311 case 0:
312 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_0 = valid;
313 break;
314 case 1:
315 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_1 = valid;
316 break;
317 case 2:
318 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_2 = valid;
319 break;
320 case 3:
321 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_3 = valid;
322 break;
323 case 4:
324 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_4 = valid;
325 break;
326 case 5:
327 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_5 = valid;
328 break;
329 case 6:
330 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_6 = valid;
331 break;
332 case 7:
333 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_7 = valid;
334 break;
335 case 8:
336 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_8 = valid;
337 break;
338 case 9:
339 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_9 = valid;
340 break;
341 case 10:
342 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_10 = valid;
343 break;
344 case 11:
345 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_11 = valid;
346 break;
347 case 12:
348 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_12 = valid;
349 break;
350 case 13:
351 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_13 = valid;
352 break;
353 case 14:
354 regs->hevc_param.reg099_hevc_ref_valid.hevc_ref_valid_14 = valid;
355 break;
356 }
357 }
358
rkvdec_write_regs(struct rkvdec_ctx * ctx)359 static void rkvdec_write_regs(struct rkvdec_ctx *ctx)
360 {
361 struct rkvdec_dev *rkvdec = ctx->dev;
362 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
363
364 rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS,
365 &hevc_ctx->regs.common,
366 sizeof(hevc_ctx->regs.common));
367 rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS,
368 &hevc_ctx->regs.hevc_param,
369 sizeof(hevc_ctx->regs.hevc_param));
370 rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS,
371 &hevc_ctx->regs.common_addr,
372 sizeof(hevc_ctx->regs.common_addr));
373 rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS,
374 &hevc_ctx->regs.hevc_addr,
375 sizeof(hevc_ctx->regs.hevc_addr));
376 rkvdec_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS,
377 &hevc_ctx->regs.hevc_highpoc,
378 sizeof(hevc_ctx->regs.hevc_highpoc));
379 }
380
config_registers(struct rkvdec_ctx * ctx,struct rkvdec_hevc_run * run)381 static void config_registers(struct rkvdec_ctx *ctx,
382 struct rkvdec_hevc_run *run)
383 {
384 const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params;
385 const struct v4l2_hevc_dpb_entry *dpb = dec_params->dpb;
386 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
387 struct rkvdec_vdpu381_regs_hevc *regs = &hevc_ctx->regs;
388 dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
389 const struct v4l2_pix_format_mplane *dst_fmt;
390 struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
391 struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
392 const struct v4l2_format *f;
393 dma_addr_t rlc_addr;
394 u32 hor_virstride = 0;
395 u32 ver_virstride = 0;
396 u32 y_virstride = 0;
397 u32 offset;
398 u32 pixels;
399 dma_addr_t dst_addr;
400 u32 i;
401
402 memset(regs, 0, sizeof(*regs));
403
404 /* Set HEVC mode */
405 regs->common.reg009_dec_mode.dec_mode = VDPU381_MODE_HEVC;
406
407 /* Set config */
408 regs->common.reg011_important_en.buf_empty_en = 1;
409 regs->common.reg011_important_en.dec_clkgate_e = 1;
410 regs->common.reg011_important_en.dec_timeout_e = 1;
411 regs->common.reg011_important_en.pix_range_det_e = 1;
412
413 /* Set IDR flag */
414 regs->common.reg013_en_mode_set.cur_pic_is_idr =
415 !!(dec_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC);
416
417 /* Set input stream length */
418 regs->common.reg016_stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
419
420 /* Set max slice number */
421 regs->common.reg017_slice_number.slice_num = 1;
422
423 /* Set strides */
424 f = &ctx->decoded_fmt;
425 dst_fmt = &f->fmt.pix_mp;
426 hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
427 ver_virstride = dst_fmt->height;
428 y_virstride = hor_virstride * ver_virstride;
429
430 regs->common.reg018_y_hor_stride.y_hor_virstride = hor_virstride / 16;
431 regs->common.reg019_uv_hor_stride.uv_hor_virstride = hor_virstride / 16;
432 regs->common.reg020_y_stride.y_virstride = y_virstride / 16;
433
434 /* Activate block gating */
435 regs->common.reg026_block_gating_en.inter_auto_gating_e = 1;
436 regs->common.reg026_block_gating_en.filterd_auto_gating_e = 1;
437 regs->common.reg026_block_gating_en.strmd_auto_gating_e = 1;
438 regs->common.reg026_block_gating_en.mcp_auto_gating_e = 1;
439 regs->common.reg026_block_gating_en.busifd_auto_gating_e = 0;
440 regs->common.reg026_block_gating_en.dec_ctrl_auto_gating_e = 1;
441 regs->common.reg026_block_gating_en.intra_auto_gating_e = 1;
442 regs->common.reg026_block_gating_en.mc_auto_gating_e = 1;
443 regs->common.reg026_block_gating_en.transd_auto_gating_e = 1;
444 regs->common.reg026_block_gating_en.sram_auto_gating_e = 1;
445 regs->common.reg026_block_gating_en.cru_auto_gating_e = 1;
446 regs->common.reg026_block_gating_en.reg_cfg_gating_en = 1;
447
448 /* Set timeout threshold */
449 pixels = dst_fmt->height * dst_fmt->width;
450 if (pixels < RKVDEC_1080P_PIXELS)
451 regs->common.reg032_timeout_threshold = RKVDEC_TIMEOUT_1080p;
452 else if (pixels < RKVDEC_4K_PIXELS)
453 regs->common.reg032_timeout_threshold = RKVDEC_TIMEOUT_4K;
454 else if (pixels < RKVDEC_8K_PIXELS)
455 regs->common.reg032_timeout_threshold = RKVDEC_TIMEOUT_8K;
456 else
457 regs->common.reg032_timeout_threshold = RKVDEC_TIMEOUT_MAX;
458
459 /* Set POC val */
460 regs->hevc_param.reg065_cur_top_poc = dec_params->pic_order_cnt_val;
461
462 /* Set ref pic address & poc */
463 for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
464 struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
465 dma_addr_t buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
466 u32 valid = !!(dec_params->num_active_dpb_entries > i);
467
468 /* Set reference addresses */
469 regs->hevc_addr.reg164_180_ref_base[i] = buf_dma;
470
471 /* Set COLMV addresses */
472 regs->hevc_addr.reg182_198_colmv_base[i] = buf_dma + ctx->colmv_offset;
473
474 regs->hevc_param.reg067_082_ref_poc[i] =
475 dpb[i].pic_order_cnt_val;
476
477 set_ref_valid(regs, i, valid);
478 regs->hevc_param.reg103_hevc_mvc0.ref_pic_layer_same_with_cur |= 1 << i;
479 }
480
481 /* Set rlc base address (input stream) */
482 rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
483 regs->common_addr.rlc_base = rlc_addr;
484 regs->common_addr.rlcwrite_base = rlc_addr;
485
486 /* Set output base address */
487 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
488 regs->common_addr.decout_base = dst_addr;
489 regs->common_addr.error_ref_base = dst_addr;
490
491 /* Set colmv address */
492 regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset;
493
494 /* Set RCB addresses */
495 for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++)
496 regs->common_addr.rcb_base[i] = rkvdec_rcb_buf_dma_addr(ctx, i);
497
498 /* Set hw pps address */
499 offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
500 regs->hevc_addr.reg161_pps_base = priv_start_addr + offset;
501
502 /* Set hw rps address */
503 offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
504 regs->hevc_addr.reg163_rps_base = priv_start_addr + offset;
505
506 /* Set cabac table */
507 offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
508 regs->hevc_addr.reg199_cabactbl_base = priv_start_addr + offset;
509
510 /* Set scaling matrix */
511 offset = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
512 regs->hevc_addr.reg181_scanlist_addr = priv_start_addr + offset;
513
514 rkvdec_write_regs(ctx);
515 }
516
rkvdec_hevc_validate_sps(struct rkvdec_ctx * ctx,const struct v4l2_ctrl_hevc_sps * sps)517 static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
518 const struct v4l2_ctrl_hevc_sps *sps)
519 {
520 if (sps->chroma_format_idc != 1)
521 /* Only 4:2:0 is supported */
522 return -EINVAL;
523
524 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
525 /* Luma and chroma bit depth mismatch */
526 return -EINVAL;
527
528 if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
529 /* Only 8-bit and 10-bit are supported */
530 return -EINVAL;
531
532 if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
533 sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
534 return -EINVAL;
535
536 return 0;
537 }
538
rkvdec_hevc_start(struct rkvdec_ctx * ctx)539 static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
540 {
541 struct rkvdec_dev *rkvdec = ctx->dev;
542 struct rkvdec_hevc_priv_tbl *priv_tbl;
543 struct rkvdec_hevc_ctx *hevc_ctx;
544 struct v4l2_ctrl *ctrl;
545 int ret;
546
547 ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
548 V4L2_CID_STATELESS_HEVC_SPS);
549 if (!ctrl)
550 return -EINVAL;
551
552 ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
553 if (ret)
554 return ret;
555
556 hevc_ctx = kzalloc_obj(*hevc_ctx);
557 if (!hevc_ctx)
558 return -ENOMEM;
559
560 priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
561 &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
562 if (!priv_tbl) {
563 ret = -ENOMEM;
564 goto err_free_ctx;
565 }
566
567 hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
568 hevc_ctx->priv_tbl.cpu = priv_tbl;
569 memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
570 sizeof(rkvdec_hevc_cabac_table));
571
572 ctx->priv = hevc_ctx;
573 return 0;
574
575 err_free_ctx:
576 kfree(hevc_ctx);
577 return ret;
578 }
579
rkvdec_hevc_stop(struct rkvdec_ctx * ctx)580 static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
581 {
582 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
583 struct rkvdec_dev *rkvdec = ctx->dev;
584
585 dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
586 hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
587 kfree(hevc_ctx);
588 }
589
rkvdec_hevc_run(struct rkvdec_ctx * ctx)590 static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
591 {
592 struct rkvdec_dev *rkvdec = ctx->dev;
593 struct rkvdec_hevc_run run;
594 struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
595 struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
596
597 rkvdec_hevc_run_preamble(ctx, &run);
598
599 rkvdec_hevc_assemble_hw_scaling_list(ctx, &run, &tbl->scaling_list,
600 &hevc_ctx->scaling_matrix_cache);
601 assemble_hw_pps(ctx, &run);
602
603 /*
604 * On vdpu381, not setting the long and short term ref sets will just output wrong frames.
605 * Let's just warn about it and let the decoder run anyway.
606 */
607 if ((!ctx->has_sps_lt_rps && run.sps->num_long_term_ref_pics_sps) ||
608 (!ctx->has_sps_st_rps && run.sps->num_short_term_ref_pic_sets)) {
609 dev_warn_ratelimited(rkvdec->dev, "Long and short term RPS not set\n");
610 } else {
611 rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache);
612 }
613
614 config_registers(ctx, &run);
615
616 rkvdec_run_postamble(ctx, &run.base);
617
618 rkvdec_schedule_watchdog(rkvdec, hevc_ctx->regs.common.reg032_timeout_threshold);
619
620 /* Start decoding! */
621 writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E);
622
623 return 0;
624 }
625
rkvdec_hevc_try_ctrl(struct rkvdec_ctx * ctx,struct v4l2_ctrl * ctrl)626 static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
627 {
628 if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
629 return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
630
631 return 0;
632 }
633
634 const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops = {
635 .adjust_fmt = rkvdec_hevc_adjust_fmt,
636 .start = rkvdec_hevc_start,
637 .stop = rkvdec_hevc_stop,
638 .run = rkvdec_hevc_run,
639 .try_ctrl = rkvdec_hevc_try_ctrl,
640 .get_image_fmt = rkvdec_hevc_get_image_fmt,
641 };
642