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Searched refs:xe_mmio_write32 (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_irq.c48 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
50 xe_mmio_write32(mmio, reg, 0xffffffff); in assert_iir_is_zero()
68 xe_mmio_write32(mmio, IER(irqregs), bits); in unmask_and_enable()
69 xe_mmio_write32(mmio, IMR(irqregs), ~bits); in unmask_and_enable()
80 xe_mmio_write32(mmio, IMR(irqregs), ~0); in mask_and_disable()
84 xe_mmio_write32(mmio, IER(irqregs), 0); in mask_and_disable()
87 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
89 xe_mmio_write32(mmio, IIR(irqregs), ~0); in mask_and_disable()
97 xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0); in xelp_intr_disable()
119 xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir); in gu_misc_irq_ack()
[all …]
H A Dxe_gt_idle.c139 xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25); in xe_gt_idle_enable_pg()
140 xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25); in xe_gt_idle_enable_pg()
143 xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable); in xe_gt_idle_enable_pg()
159 xe_mmio_write32(&gt->mmio, POWERGATE_ENABLE, gtidle->powergate_enable); in xe_gt_idle_disable_pg()
366 xe_mmio_write32(&gt->mmio, RC_IDLE_HYSTERSIS, 0x3B9ACA); in xe_gt_idle_enable_c6()
368 xe_mmio_write32(&gt->mmio, RC_CONTROL, in xe_gt_idle_enable_c6()
380 xe_mmio_write32(&gt->mmio, RC_CONTROL, 0); in xe_gt_idle_disable_c6()
381 xe_mmio_write32(&gt->mmio, RC_STATE, 0); in xe_gt_idle_disable_c6()
H A Dxe_gt_sriov_pf.c91 xe_mmio_write32(&gt->mmio, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN); in pf_enable_ggtt_guest_update()
133 xe_mmio_write32(&gt->mmio, scratch, 0); in pf_clear_vf_scratch_regs()
139 xe_mmio_write32(&gt->mmio, scratch, 0); in pf_clear_vf_scratch_regs()
H A Dxe_gt_mcr.c526 xe_mmio_write32(&gt->mmio, MCFG_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
527 xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val); in xe_gt_mcr_set_implicit_defaults()
621 xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, 0x1); in mcr_unlock()
668 xe_mmio_write32(mmio, steer_reg, steer_val); in rw_with_mcr_steering()
673 xe_mmio_write32(mmio, reg, value); in rw_with_mcr_steering()
682 xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST); in rw_with_mcr_steering()
790 xe_mmio_write32(&gt->mmio, reg, value); in xe_gt_mcr_multicast_write()
H A Dxe_execlist.c64 xe_mmio_write32(mmio, RCU_MODE, in __start_lrc()
82 xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base), in __start_lrc()
88 xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode); in __start_lrc()
90 xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base), in __start_lrc()
92 xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base), in __start_lrc()
94 xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base), in __start_lrc()
H A Dxe_guc.c277 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(0), 0); in guc_write_params()
280 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); in guc_write_params()
778 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); in xe_guc_reset()
819 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
821 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
840 xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); in guc_xfer_rsa()
849 xe_mmio_write32(&gt->mmio, UOS_RSA_SCRATCH(i), rsa[i]); in guc_xfer_rsa()
1174 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(15), 0); in guc_handle_mmio_msg()
1191 xe_mmio_write32(&gt->mmio, GUC_SG_INTR_ENABLE, in guc_enable_irq()
1254 xe_mmio_write32(&gt->mmio, guc->notify_reg, default_notify_data); in xe_guc_notify()
[all …]
H A Dxe_pcode.c70 xe_mmio_write32(mmio, PCODE_DATA0, *data0); in __pcode_mailbox_rw()
71 xe_mmio_write32(mmio, PCODE_DATA1, data1 ? *data1 : 0); in __pcode_mailbox_rw()
72 xe_mmio_write32(mmio, PCODE_MAILBOX, PCODE_READY | mbox); in __pcode_mailbox_rw()
H A Dxe_uc_fw.c820 xe_mmio_write32(mmio, DMA_ADDR_0_LOW, lower_32_bits(src_offset)); in uc_fw_xfer()
821 xe_mmio_write32(mmio, DMA_ADDR_0_HIGH, in uc_fw_xfer()
825 xe_mmio_write32(mmio, DMA_ADDR_1_LOW, offset); in uc_fw_xfer()
826 xe_mmio_write32(mmio, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); in uc_fw_xfer()
832 xe_mmio_write32(mmio, DMA_COPY_SIZE, in uc_fw_xfer()
836 xe_mmio_write32(mmio, DMA_CTRL, in uc_fw_xfer()
847 xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); in uc_fw_xfer()
H A Dxe_mmio.c230 void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val) in xe_mmio_write32() function
266 xe_mmio_write32(mmio, reg, reg_val); in xe_mmio_rmw32()
276 xe_mmio_write32(mmio, reg, val); in xe_mmio_write32_and_verify()
H A Dxe_device.c427 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); in __xe_driver_flr()
448 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); in __xe_driver_flr()
855 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); in xe_device_wmb()
898 xe_mmio_write32(&gt->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); in xe_device_td_flush()
929 xe_mmio_write32(&gt->mmio, XE2_GLOBAL_INVAL, 0x1); in xe_device_l2_flush()
H A Dxe_gt_tlb_invalidation.c311 xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1, in xe_gt_tlb_invalidation_ggtt()
313 xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0, in xe_gt_tlb_invalidation_ggtt()
316 xe_mmio_write32(mmio, GUC_TLB_INV_CR, in xe_gt_tlb_invalidation_ggtt()
H A Dxe_pat.c168 xe_mmio_write32(&gt->mmio, reg, table[i].value); in program_pat()
320 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_ATS), xe2_pat_ats.value); in xe2lpm_program_pat()
323 xe_mmio_write32(&gt->mmio, XE_REG(_PAT_PTA), xe2_pat_pta.value); in xe2lpm_program_pat()
H A Dxe_mmio.h19 void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
H A Dxe_oa.c385 xe_mmio_write32(&stream->gt->mmio, oaheadptr, in xe_oa_append_reports()
411 xe_mmio_write32(mmio, __oa_regs(stream)->oa_status, 0); in xe_oa_init_oa_buffer()
412 xe_mmio_write32(mmio, __oa_regs(stream)->oa_head_ptr, in xe_oa_init_oa_buffer()
419 xe_mmio_write32(mmio, __oa_regs(stream)->oa_buffer, oa_buf); in xe_oa_init_oa_buffer()
420 xe_mmio_write32(mmio, __oa_regs(stream)->oa_tail_ptr, in xe_oa_init_oa_buffer()
493 xe_mmio_write32(mmio, OA_TLB_INV_CR, 1); in xe_oa_disable()
781 xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_ctrl, in xe_oa_configure_oac_context()
825 xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, in xe_oa_disable_metric_set()
1089 xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug, in xe_oa_enable_metric_set()
1095 xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ? in xe_oa_enable_metric_set()
[all …]
H A Dxe_hw_engine.c300 xe_mmio_write32(&hwe->gt->mmio, reg, val); in xe_hw_engine_mmio_write32()
330 xe_mmio_write32(&hwe->gt->mmio, RCU_MODE, in xe_hw_engine_enable_ring()
775 xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_ENABLE, 0); in check_gsc_availability()
776 xe_mmio_write32(&gt->mmio, GUNIT_GSC_INTR_MASK, ~0); in check_gsc_availability()
H A Dxe_gt_ccs_mode.c77 xe_mmio_write32(&gt->mmio, CCS_MODE, mode); in __xe_gt_apply_ccs_mode()
H A Dxe_reg_sr.c164 xe_mmio_write32(&gt->mmio, reg, val); in apply_one_mmio()
H A Dxe_guc_pc.c266 xe_mmio_write32(&gt->mmio, RP_CONTROL, state); in pc_set_manual_rp_ctrl()
278 xe_mmio_write32(&gt->mmio, RPNSWREQ, rpnswreq); in pc_set_cur_freq()
H A Dxe_lmtt.c196 xe_mmio_write32(&tile->mmio, in lmtt_setup_dir_ptr()
H A Dxe_ggtt.c124 xe_mmio_write32(mmio, GMD_ID, 0x0); in ggtt_update_access_counter()
H A Dxe_gt.c681 xe_mmio_write32(&gt->mmio, GDRST, GRDOM_FULL); in do_gt_reset()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h88 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write()
153 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write_fw()
169 xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val); in intel_uncore_write_notrace()