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Searched refs:xe_mmio_rmw32 (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_mmio.h21 u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);
H A Dxe_hwmon.c204 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN, 0); in xe_hwmon_power_max_write()
216 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val); in xe_hwmon_power_max_write()
383 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index), in xe_hwmon_power_max_interval_store()
H A Dxe_gsc.c584 xe_mmio_rmw32(&gt->mmio, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set); in xe_gsc_wa_14015076503()
588 xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), in xe_gsc_wa_14015076503()
H A Dxe_mmio.c260 u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set) in xe_mmio_rmw32() function
H A Dxe_guc.c490 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); in guc_prepare_xfer()
864 xe_mmio_rmw32(&gt->mmio, GUC_SG_INTR_MASK, events, 0); in guc_enable_irq()
H A Dxe_gsc_proxy.c81 xe_mmio_rmw32(&gt->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set); in __gsc_proxy_irq_rmw()
H A Dxe_oa.c507 stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status, in __xe_oa_read()
823 xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0); in xe_oa_disable_metric_set()
829 xe_mmio_rmw32(mmio, XELPMP_SQCNT1, sqcnt1, 0); in xe_oa_disable_metric_set()
1094 xe_mmio_rmw32(mmio, XELPMP_SQCNT1, 0, sqcnt1); in xe_oa_enable_metric_set()
H A Dxe_device.c423 xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR); in __xe_driver_flr()
H A Dxe_wa.c954 xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); in xe_wa_apply_tile_workarounds()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h91 return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set); in intel_uncore_rmw()