1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include "xe_hw_engine.h"
7
8 #include <linux/nospec.h>
9
10 #include <drm/drm_managed.h>
11 #include <drm/drm_print.h>
12 #include <uapi/drm/xe_drm.h>
13 #include <generated/xe_wa_oob.h>
14
15 #include "regs/xe_engine_regs.h"
16 #include "regs/xe_gt_regs.h"
17 #include "regs/xe_irq_regs.h"
18 #include "xe_assert.h"
19 #include "xe_bo.h"
20 #include "xe_configfs.h"
21 #include "xe_device.h"
22 #include "xe_execlist.h"
23 #include "xe_force_wake.h"
24 #include "xe_gsc.h"
25 #include "xe_gt.h"
26 #include "xe_gt_ccs_mode.h"
27 #include "xe_gt_clock.h"
28 #include "xe_gt_printk.h"
29 #include "xe_gt_mcr.h"
30 #include "xe_gt_topology.h"
31 #include "xe_guc_capture.h"
32 #include "xe_hw_engine_group.h"
33 #include "xe_hw_fence.h"
34 #include "xe_irq.h"
35 #include "xe_lrc.h"
36 #include "xe_mmio.h"
37 #include "xe_reg_sr.h"
38 #include "xe_reg_whitelist.h"
39 #include "xe_rtp.h"
40 #include "xe_sched_job.h"
41 #include "xe_sriov.h"
42 #include "xe_tuning.h"
43 #include "xe_uc_fw.h"
44 #include "xe_wa.h"
45
46 #define MAX_MMIO_BASES 3
47 struct engine_info {
48 const char *name;
49 unsigned int class : 8;
50 unsigned int instance : 8;
51 unsigned int irq_offset : 8;
52 enum xe_force_wake_domains domain;
53 u32 mmio_base;
54 };
55
56 static const struct engine_info engine_infos[] = {
57 [XE_HW_ENGINE_RCS0] = {
58 .name = "rcs0",
59 .class = XE_ENGINE_CLASS_RENDER,
60 .instance = 0,
61 .irq_offset = ilog2(INTR_RCS0),
62 .domain = XE_FW_RENDER,
63 .mmio_base = RENDER_RING_BASE,
64 },
65 [XE_HW_ENGINE_BCS0] = {
66 .name = "bcs0",
67 .class = XE_ENGINE_CLASS_COPY,
68 .instance = 0,
69 .irq_offset = ilog2(INTR_BCS(0)),
70 .domain = XE_FW_GT,
71 .mmio_base = BLT_RING_BASE,
72 },
73 [XE_HW_ENGINE_BCS1] = {
74 .name = "bcs1",
75 .class = XE_ENGINE_CLASS_COPY,
76 .instance = 1,
77 .irq_offset = ilog2(INTR_BCS(1)),
78 .domain = XE_FW_GT,
79 .mmio_base = XEHPC_BCS1_RING_BASE,
80 },
81 [XE_HW_ENGINE_BCS2] = {
82 .name = "bcs2",
83 .class = XE_ENGINE_CLASS_COPY,
84 .instance = 2,
85 .irq_offset = ilog2(INTR_BCS(2)),
86 .domain = XE_FW_GT,
87 .mmio_base = XEHPC_BCS2_RING_BASE,
88 },
89 [XE_HW_ENGINE_BCS3] = {
90 .name = "bcs3",
91 .class = XE_ENGINE_CLASS_COPY,
92 .instance = 3,
93 .irq_offset = ilog2(INTR_BCS(3)),
94 .domain = XE_FW_GT,
95 .mmio_base = XEHPC_BCS3_RING_BASE,
96 },
97 [XE_HW_ENGINE_BCS4] = {
98 .name = "bcs4",
99 .class = XE_ENGINE_CLASS_COPY,
100 .instance = 4,
101 .irq_offset = ilog2(INTR_BCS(4)),
102 .domain = XE_FW_GT,
103 .mmio_base = XEHPC_BCS4_RING_BASE,
104 },
105 [XE_HW_ENGINE_BCS5] = {
106 .name = "bcs5",
107 .class = XE_ENGINE_CLASS_COPY,
108 .instance = 5,
109 .irq_offset = ilog2(INTR_BCS(5)),
110 .domain = XE_FW_GT,
111 .mmio_base = XEHPC_BCS5_RING_BASE,
112 },
113 [XE_HW_ENGINE_BCS6] = {
114 .name = "bcs6",
115 .class = XE_ENGINE_CLASS_COPY,
116 .instance = 6,
117 .irq_offset = ilog2(INTR_BCS(6)),
118 .domain = XE_FW_GT,
119 .mmio_base = XEHPC_BCS6_RING_BASE,
120 },
121 [XE_HW_ENGINE_BCS7] = {
122 .name = "bcs7",
123 .class = XE_ENGINE_CLASS_COPY,
124 .irq_offset = ilog2(INTR_BCS(7)),
125 .instance = 7,
126 .domain = XE_FW_GT,
127 .mmio_base = XEHPC_BCS7_RING_BASE,
128 },
129 [XE_HW_ENGINE_BCS8] = {
130 .name = "bcs8",
131 .class = XE_ENGINE_CLASS_COPY,
132 .instance = 8,
133 .irq_offset = ilog2(INTR_BCS8),
134 .domain = XE_FW_GT,
135 .mmio_base = XEHPC_BCS8_RING_BASE,
136 },
137
138 [XE_HW_ENGINE_VCS0] = {
139 .name = "vcs0",
140 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
141 .instance = 0,
142 .irq_offset = 32 + ilog2(INTR_VCS(0)),
143 .domain = XE_FW_MEDIA_VDBOX0,
144 .mmio_base = BSD_RING_BASE,
145 },
146 [XE_HW_ENGINE_VCS1] = {
147 .name = "vcs1",
148 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
149 .instance = 1,
150 .irq_offset = 32 + ilog2(INTR_VCS(1)),
151 .domain = XE_FW_MEDIA_VDBOX1,
152 .mmio_base = BSD2_RING_BASE,
153 },
154 [XE_HW_ENGINE_VCS2] = {
155 .name = "vcs2",
156 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
157 .instance = 2,
158 .irq_offset = 32 + ilog2(INTR_VCS(2)),
159 .domain = XE_FW_MEDIA_VDBOX2,
160 .mmio_base = BSD3_RING_BASE,
161 },
162 [XE_HW_ENGINE_VCS3] = {
163 .name = "vcs3",
164 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
165 .instance = 3,
166 .irq_offset = 32 + ilog2(INTR_VCS(3)),
167 .domain = XE_FW_MEDIA_VDBOX3,
168 .mmio_base = BSD4_RING_BASE,
169 },
170 [XE_HW_ENGINE_VCS4] = {
171 .name = "vcs4",
172 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
173 .instance = 4,
174 .irq_offset = 32 + ilog2(INTR_VCS(4)),
175 .domain = XE_FW_MEDIA_VDBOX4,
176 .mmio_base = XEHP_BSD5_RING_BASE,
177 },
178 [XE_HW_ENGINE_VCS5] = {
179 .name = "vcs5",
180 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
181 .instance = 5,
182 .irq_offset = 32 + ilog2(INTR_VCS(5)),
183 .domain = XE_FW_MEDIA_VDBOX5,
184 .mmio_base = XEHP_BSD6_RING_BASE,
185 },
186 [XE_HW_ENGINE_VCS6] = {
187 .name = "vcs6",
188 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
189 .instance = 6,
190 .irq_offset = 32 + ilog2(INTR_VCS(6)),
191 .domain = XE_FW_MEDIA_VDBOX6,
192 .mmio_base = XEHP_BSD7_RING_BASE,
193 },
194 [XE_HW_ENGINE_VCS7] = {
195 .name = "vcs7",
196 .class = XE_ENGINE_CLASS_VIDEO_DECODE,
197 .instance = 7,
198 .irq_offset = 32 + ilog2(INTR_VCS(7)),
199 .domain = XE_FW_MEDIA_VDBOX7,
200 .mmio_base = XEHP_BSD8_RING_BASE,
201 },
202 [XE_HW_ENGINE_VECS0] = {
203 .name = "vecs0",
204 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
205 .instance = 0,
206 .irq_offset = 32 + ilog2(INTR_VECS(0)),
207 .domain = XE_FW_MEDIA_VEBOX0,
208 .mmio_base = VEBOX_RING_BASE,
209 },
210 [XE_HW_ENGINE_VECS1] = {
211 .name = "vecs1",
212 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
213 .instance = 1,
214 .irq_offset = 32 + ilog2(INTR_VECS(1)),
215 .domain = XE_FW_MEDIA_VEBOX1,
216 .mmio_base = VEBOX2_RING_BASE,
217 },
218 [XE_HW_ENGINE_VECS2] = {
219 .name = "vecs2",
220 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
221 .instance = 2,
222 .irq_offset = 32 + ilog2(INTR_VECS(2)),
223 .domain = XE_FW_MEDIA_VEBOX2,
224 .mmio_base = XEHP_VEBOX3_RING_BASE,
225 },
226 [XE_HW_ENGINE_VECS3] = {
227 .name = "vecs3",
228 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
229 .instance = 3,
230 .irq_offset = 32 + ilog2(INTR_VECS(3)),
231 .domain = XE_FW_MEDIA_VEBOX3,
232 .mmio_base = XEHP_VEBOX4_RING_BASE,
233 },
234 [XE_HW_ENGINE_CCS0] = {
235 .name = "ccs0",
236 .class = XE_ENGINE_CLASS_COMPUTE,
237 .instance = 0,
238 .irq_offset = ilog2(INTR_CCS(0)),
239 .domain = XE_FW_RENDER,
240 .mmio_base = COMPUTE0_RING_BASE,
241 },
242 [XE_HW_ENGINE_CCS1] = {
243 .name = "ccs1",
244 .class = XE_ENGINE_CLASS_COMPUTE,
245 .instance = 1,
246 .irq_offset = ilog2(INTR_CCS(1)),
247 .domain = XE_FW_RENDER,
248 .mmio_base = COMPUTE1_RING_BASE,
249 },
250 [XE_HW_ENGINE_CCS2] = {
251 .name = "ccs2",
252 .class = XE_ENGINE_CLASS_COMPUTE,
253 .instance = 2,
254 .irq_offset = ilog2(INTR_CCS(2)),
255 .domain = XE_FW_RENDER,
256 .mmio_base = COMPUTE2_RING_BASE,
257 },
258 [XE_HW_ENGINE_CCS3] = {
259 .name = "ccs3",
260 .class = XE_ENGINE_CLASS_COMPUTE,
261 .instance = 3,
262 .irq_offset = ilog2(INTR_CCS(3)),
263 .domain = XE_FW_RENDER,
264 .mmio_base = COMPUTE3_RING_BASE,
265 },
266 [XE_HW_ENGINE_GSCCS0] = {
267 .name = "gsccs0",
268 .class = XE_ENGINE_CLASS_OTHER,
269 .instance = OTHER_GSC_INSTANCE,
270 .domain = XE_FW_GSC,
271 .mmio_base = GSCCS_RING_BASE,
272 },
273 };
274
hw_engine_fini(void * arg)275 static void hw_engine_fini(void *arg)
276 {
277 struct xe_hw_engine *hwe = arg;
278
279 if (hwe->exl_port)
280 xe_execlist_port_destroy(hwe->exl_port);
281
282 hwe->gt = NULL;
283 }
284
285 /**
286 * xe_hw_engine_mmio_read32() - Read engine register
287 * @hwe: engine
288 * @reg: register to read from
289 *
290 * This function will read from an engine specific register.
291 * Forcewake must be held by the caller.
292 *
293 * Return: value of the 32-bit register.
294 */
xe_hw_engine_mmio_read32(struct xe_hw_engine * hwe,struct xe_reg reg)295 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
296 {
297 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base));
298 xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain);
299
300 reg.addr += hwe->mmio_base;
301
302 return xe_mmio_read32(&hwe->gt->mmio, reg);
303 }
304
xe_hw_engine_enable_ring(struct xe_hw_engine * hwe)305 void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
306 {
307 xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base),
308 xe_bo_ggtt_addr(hwe->hwsp));
309 }
310
xe_hw_engine_match_fixed_cslice_mode(const struct xe_device * xe,const struct xe_gt * gt,const struct xe_hw_engine * hwe)311 static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,
312 const struct xe_gt *gt,
313 const struct xe_hw_engine *hwe)
314 {
315 /*
316 * Xe3p no longer supports load balance mode, so "fixed cslice" mode
317 * is automatic and no RCU_MODE programming is required.
318 */
319 if (GRAPHICS_VER(gt_to_xe(gt)) >= 35)
320 return false;
321
322 return xe_gt_ccs_mode_enabled(gt) &&
323 xe_rtp_match_first_render_or_compute(xe, gt, hwe);
324 }
325
xe_rtp_cfeg_wmtp_disabled(const struct xe_device * xe,const struct xe_gt * gt,const struct xe_hw_engine * hwe)326 static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe,
327 const struct xe_gt *gt,
328 const struct xe_hw_engine *hwe)
329 {
330 if (GRAPHICS_VER(xe) < 20)
331 return false;
332
333 if (hwe->class != XE_ENGINE_CLASS_COMPUTE &&
334 hwe->class != XE_ENGINE_CLASS_RENDER)
335 return false;
336
337 return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
338 }
339
340 static void
hw_engine_setup_default_lrc_state(struct xe_hw_engine * hwe)341 hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe)
342 {
343 struct xe_gt *gt = hwe->gt;
344 const u8 mocs_write_idx = gt->mocs.uc_index;
345 const u8 mocs_read_idx = gt->mocs.uc_index;
346 u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
347 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
348 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
349 const struct xe_rtp_table_sr lrc_setup = XE_RTP_TABLE_SR(
350 /*
351 * Some blitter commands do not have a field for MOCS, those
352 * commands will use MOCS index pointed by BLIT_CCTL.
353 * BLIT_CCTL registers are needed to be programmed to un-cached.
354 */
355 { XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
356 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
357 ENGINE_CLASS(COPY)),
358 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
359 BLIT_CCTL_DST_MOCS_MASK |
360 BLIT_CCTL_SRC_MOCS_MASK,
361 blit_cctl_val,
362 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
363 },
364 /* Disable WMTP if HW doesn't support it */
365 { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),
366 XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),
367 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0),
368 PREEMPT_GPGPU_LEVEL_MASK,
369 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)),
370 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE)
371 },
372 );
373
374 xe_rtp_process_to_sr(&ctx, &lrc_setup, &hwe->reg_lrc, true);
375 }
376
xe_hw_engine_setup_reg_lrc(struct xe_hw_engine * hwe)377 void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
378 {
379 struct xe_gt *gt = hwe->gt;
380 struct xe_device *xe = gt_to_xe(gt);
381
382 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe);
383 xe_wa_process_lrc(hwe);
384 hw_engine_setup_default_lrc_state(hwe);
385 xe_tuning_process_lrc(hwe);
386 }
387
388 static void
hw_engine_setup_default_state(struct xe_hw_engine * hwe)389 hw_engine_setup_default_state(struct xe_hw_engine *hwe)
390 {
391 struct xe_gt *gt = hwe->gt;
392 struct xe_device *xe = gt_to_xe(gt);
393 /*
394 * RING_CMD_CCTL specifies the default MOCS entry that will be
395 * used by the command streamer when executing commands that
396 * don't have a way to explicitly specify a MOCS setting.
397 * The default should usually reference whichever MOCS entry
398 * corresponds to uncached behavior, although use of a WB cached
399 * entry is recommended by the spec in certain circumstances on
400 * specific platforms.
401 * Bspec: 72161
402 */
403 const u8 mocs_write_idx = gt->mocs.uc_index;
404 const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
405 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
406 gt->mocs.wb_index : gt->mocs.uc_index;
407 u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
408 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
409 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
410 const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
411 { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
412 XE_RTP_RULES(FUNC(xe_rtp_match_always)),
413 XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
414 CMD_CCTL_WRITE_OVERRIDE_MASK |
415 CMD_CCTL_READ_OVERRIDE_MASK,
416 ring_cmd_cctl_val,
417 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
418 },
419 { XE_RTP_NAME("Disable HW status page updates for interrupts"),
420 XE_RTP_RULES(FUNC(xe_rtp_match_always)),
421 XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
422 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
423 },
424 { XE_RTP_NAME("Disable engine 'legacy' mode"),
425 XE_RTP_RULES(FUNC(xe_rtp_match_always)),
426 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
427 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
428 },
429 /*
430 * To allow the GSC engine to go idle on MTL we need to enable
431 * idle messaging and set the hysteresis value (we use 0xA=5us
432 * as recommended in spec). On platforms after MTL this is
433 * enabled by default.
434 */
435 { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
436 XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
437 XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
438 IDLE_MSG_DISABLE,
439 XE_RTP_ACTION_FLAG(ENGINE_BASE)),
440 FIELD_SET(RING_PWRCTX_MAXCNT(0),
441 IDLE_WAIT_TIME,
442 0xA,
443 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
444 },
445 /* Enable Priority Mem Read */
446 { XE_RTP_NAME("Priority_Mem_Read"),
447 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
448 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
449 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
450 },
451 { XE_RTP_NAME("Enable CCS Engine(s)"),
452 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
453 FUNC(xe_rtp_match_first_render_or_compute)),
454 XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
455 },
456 /* Use Fixed slice CCS mode */
457 { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
458 XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
459 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
460 RCU_MODE_FIXED_SLICE_CCS_MODE))
461 },
462 { XE_RTP_NAME("Enable MSI-X interrupt support"),
463 XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
464 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
465 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
466 },
467 );
468
469 xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
470 }
471
find_engine_info(enum xe_engine_class class,int instance)472 static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance)
473 {
474 const struct engine_info *info;
475 enum xe_hw_engine_id id;
476
477 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) {
478 info = &engine_infos[id];
479 if (info->class == class && info->instance == instance)
480 return info;
481 }
482
483 return NULL;
484 }
485
get_msix_irq_offset(struct xe_gt * gt,enum xe_engine_class class)486 static u16 get_msix_irq_offset(struct xe_gt *gt, enum xe_engine_class class)
487 {
488 /* For MSI-X, hw engines report to offset of engine instance zero */
489 const struct engine_info *info = find_engine_info(class, 0);
490
491 xe_gt_assert(gt, info);
492
493 return info ? info->irq_offset : 0;
494 }
495
hw_engine_init_early(struct xe_gt * gt,struct xe_hw_engine * hwe,enum xe_hw_engine_id id)496 static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
497 enum xe_hw_engine_id id)
498 {
499 const struct engine_info *info;
500
501 if (WARN_ON(id >= ARRAY_SIZE(engine_infos) || !engine_infos[id].name))
502 return;
503
504 if (!(gt->info.engine_mask & BIT(id)))
505 return;
506
507 info = &engine_infos[id];
508
509 xe_gt_assert(gt, !hwe->gt);
510
511 hwe->gt = gt;
512 hwe->class = info->class;
513 hwe->instance = info->instance;
514 hwe->mmio_base = info->mmio_base;
515 if (xe_device_has_msix(gt_to_xe(gt))) {
516 hwe->irq_offset = get_msix_irq_offset(gt, info->class);
517 hwe->irq_page = info->instance;
518
519 } else {
520 hwe->irq_offset = info->irq_offset;
521 hwe->irq_page = 0;
522 }
523 hwe->domain = info->domain;
524 hwe->name = info->name;
525 hwe->fence_irq = >->fence_irq[info->class];
526 hwe->engine_id = id;
527
528 hwe->eclass = >->eclass[hwe->class];
529 if (!hwe->eclass->sched_props.job_timeout_ms) {
530 hwe->eclass->sched_props.job_timeout_ms = 5 * 1000;
531 hwe->eclass->sched_props.job_timeout_min = XE_HW_ENGINE_JOB_TIMEOUT_MIN;
532 hwe->eclass->sched_props.job_timeout_max = XE_HW_ENGINE_JOB_TIMEOUT_MAX;
533 hwe->eclass->sched_props.timeslice_us = 1 * 1000;
534 hwe->eclass->sched_props.timeslice_min = XE_HW_ENGINE_TIMESLICE_MIN;
535 hwe->eclass->sched_props.timeslice_max = XE_HW_ENGINE_TIMESLICE_MAX;
536 hwe->eclass->sched_props.preempt_timeout_us = XE_HW_ENGINE_PREEMPT_TIMEOUT;
537 hwe->eclass->sched_props.preempt_timeout_min = XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN;
538 hwe->eclass->sched_props.preempt_timeout_max = XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX;
539
540 /*
541 * The GSC engine can accept submissions while the GSC shim is
542 * being reset, during which time the submission is stalled. In
543 * the worst case, the shim reset can take up to the maximum GSC
544 * command execution time (250ms), so the request start can be
545 * delayed by that much; the request itself can take that long
546 * without being preemptible, which means worst case it can
547 * theoretically take up to 500ms for a preemption to go through
548 * on the GSC engine. Adding to that an extra 100ms as a safety
549 * margin, we get a minimum recommended timeout of 600ms.
550 * The preempt_timeout value can't be tuned for OTHER_CLASS
551 * because the class is reserved for kernel usage, so we just
552 * need to make sure that the starting value is above that
553 * threshold; since our default value (640ms) is greater than
554 * 600ms, the only way we can go below is via a kconfig setting.
555 * If that happens, log it in dmesg and update the value.
556 */
557 if (hwe->class == XE_ENGINE_CLASS_OTHER) {
558 const u32 min_preempt_timeout = 600 * 1000;
559 if (hwe->eclass->sched_props.preempt_timeout_us < min_preempt_timeout) {
560 hwe->eclass->sched_props.preempt_timeout_us = min_preempt_timeout;
561 xe_gt_notice(gt, "Increasing preempt_timeout for GSC to 600ms\n");
562 }
563 }
564
565 /* Record default props */
566 hwe->eclass->defaults = hwe->eclass->sched_props;
567 }
568
569 xe_reg_sr_init(&hwe->reg_sr, hwe->name, gt_to_xe(gt));
570 xe_tuning_process_engine(hwe);
571 xe_wa_process_engine(hwe);
572 hw_engine_setup_default_state(hwe);
573
574 xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt));
575 xe_reg_sr_init(&hwe->oa_whitelist, hwe->name, gt_to_xe(gt));
576 xe_reg_sr_init(&hwe->oa_sr, hwe->name, gt_to_xe(gt));
577 xe_reg_whitelist_process_engine(hwe);
578 }
579
adjust_idledly(struct xe_hw_engine * hwe)580 static void adjust_idledly(struct xe_hw_engine *hwe)
581 {
582 struct xe_gt *gt = hwe->gt;
583 u32 idledly, maxcnt;
584 u32 idledly_units_ps = 8 * gt->info.timestamp_base;
585 u32 maxcnt_units_ns = 640;
586 bool inhibit_switch = 0;
587
588 if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) {
589 idledly = xe_mmio_read32(>->mmio, RING_IDLEDLY(hwe->mmio_base));
590 maxcnt = xe_mmio_read32(>->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base));
591
592 inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED;
593 idledly = REG_FIELD_GET(IDLE_DELAY, idledly);
594 idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps, 1000);
595 maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt);
596 maxcnt *= maxcnt_units_ns;
597
598 if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) {
599 idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000),
600 idledly_units_ps);
601 xe_mmio_write32(>->mmio, RING_IDLEDLY(hwe->mmio_base), idledly);
602 }
603 }
604 }
605
hw_engine_init(struct xe_gt * gt,struct xe_hw_engine * hwe,enum xe_hw_engine_id id)606 static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
607 enum xe_hw_engine_id id)
608 {
609 struct xe_device *xe = gt_to_xe(gt);
610 struct xe_tile *tile = gt_to_tile(gt);
611 int err;
612
613 xe_gt_assert(gt, id < ARRAY_SIZE(engine_infos) && engine_infos[id].name);
614 xe_gt_assert(gt, gt->info.engine_mask & BIT(id));
615
616 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt);
617
618 hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K,
619 XE_BO_FLAG_VRAM_IF_DGFX(tile) |
620 XE_BO_FLAG_GGTT |
621 XE_BO_FLAG_GGTT_INVALIDATE);
622 if (IS_ERR(hwe->hwsp)) {
623 err = PTR_ERR(hwe->hwsp);
624 goto err_name;
625 }
626
627 if (!xe_device_uc_enabled(xe)) {
628 hwe->exl_port = xe_execlist_port_create(xe, hwe);
629 if (IS_ERR(hwe->exl_port)) {
630 err = PTR_ERR(hwe->exl_port);
631 goto err_name;
632 }
633 } else {
634 /* GSCCS has a special interrupt for reset */
635 if (hwe->class == XE_ENGINE_CLASS_OTHER)
636 hwe->irq_handler = xe_gsc_hwe_irq_handler;
637
638 if (!IS_SRIOV_VF(xe))
639 xe_hw_engine_enable_ring(hwe);
640 }
641
642 /* We reserve the highest BCS instance for USM */
643 if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY)
644 gt->usm.reserved_bcs_instance = hwe->instance;
645
646 /* Ensure IDLEDLY is lower than MAXCNT */
647 adjust_idledly(hwe);
648
649 return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);
650
651 err_name:
652 hwe->name = NULL;
653
654 return err;
655 }
656
hw_engine_setup_logical_mapping(struct xe_gt * gt)657 static void hw_engine_setup_logical_mapping(struct xe_gt *gt)
658 {
659 int class;
660
661 /* FIXME: Doing a simple logical mapping that works for most hardware */
662 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
663 struct xe_hw_engine *hwe;
664 enum xe_hw_engine_id id;
665 int logical_instance = 0;
666
667 for_each_hw_engine(hwe, gt, id)
668 if (hwe->class == class)
669 hwe->logical_instance = logical_instance++;
670 }
671 }
672
read_media_fuses(struct xe_gt * gt)673 static void read_media_fuses(struct xe_gt *gt)
674 {
675 struct xe_device *xe = gt_to_xe(gt);
676 u32 media_fuse;
677 u16 vdbox_mask;
678 u16 vebox_mask;
679 int i, j;
680
681 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
682
683 media_fuse = xe_mmio_read32(>->mmio, GT_VEBOX_VDBOX_DISABLE);
684
685 /*
686 * Pre-Xe_HP platforms had register bits representing absent engines,
687 * whereas Xe_HP and beyond have bits representing present engines.
688 * Invert the polarity on old platforms so that we can use common
689 * handling below.
690 */
691 if (GRAPHICS_VERx100(xe) < 1250)
692 media_fuse = ~media_fuse;
693
694 vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse);
695 vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse);
696
697 for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
698 if (!(gt->info.engine_mask & BIT(i)))
699 continue;
700
701 if (!(BIT(j) & vdbox_mask)) {
702 gt->info.engine_mask &= ~BIT(i);
703 xe_gt_info(gt, "vcs%u fused off\n", j);
704 }
705 }
706
707 for (i = XE_HW_ENGINE_VECS0, j = 0; i <= XE_HW_ENGINE_VECS3; ++i, ++j) {
708 if (!(gt->info.engine_mask & BIT(i)))
709 continue;
710
711 if (!(BIT(j) & vebox_mask)) {
712 gt->info.engine_mask &= ~BIT(i);
713 xe_gt_info(gt, "vecs%u fused off\n", j);
714 }
715 }
716 }
717
infer_svccopy_from_meml3(struct xe_gt * gt)718 static u32 infer_svccopy_from_meml3(struct xe_gt *gt)
719 {
720 u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK,
721 xe_mmio_read32(>->mmio, MIRROR_FUSE3));
722 u32 svccopy_mask = 0;
723
724 /*
725 * Each of the four meml3 bits determines the fusing of two service
726 * copy engines.
727 */
728 for (int i = 0; i < 4; i++)
729 svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0;
730
731 return svccopy_mask;
732 }
733
read_svccopy_fuses(struct xe_gt * gt)734 static u32 read_svccopy_fuses(struct xe_gt *gt)
735 {
736 return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK,
737 xe_mmio_read32(>->mmio, SERVICE_COPY_ENABLE));
738 }
739
read_copy_fuses(struct xe_gt * gt)740 static void read_copy_fuses(struct xe_gt *gt)
741 {
742 struct xe_device *xe = gt_to_xe(gt);
743 u32 bcs_mask;
744
745 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
746
747 if (GRAPHICS_VER(xe) >= 35)
748 bcs_mask = read_svccopy_fuses(gt);
749 else if (GRAPHICS_VERx100(xe) == 1260)
750 bcs_mask = infer_svccopy_from_meml3(gt);
751 else
752 return;
753
754 /* Only BCS1-BCS8 may be fused off */
755 bcs_mask <<= XE_HW_ENGINE_BCS1;
756 for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) {
757 if (!(gt->info.engine_mask & BIT(i)))
758 continue;
759
760 if (!(bcs_mask & BIT(i))) {
761 gt->info.engine_mask &= ~BIT(i);
762 xe_gt_info(gt, "bcs%u fused off\n",
763 i - XE_HW_ENGINE_BCS0);
764 }
765 }
766 }
767
read_compute_fuses_from_dss(struct xe_gt * gt)768 static void read_compute_fuses_from_dss(struct xe_gt *gt)
769 {
770 /*
771 * CCS fusing based on DSS masks only applies to platforms that can
772 * have more than one CCS.
773 */
774 if (hweight64(gt->info.engine_mask &
775 GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)) <= 1)
776 return;
777
778 /*
779 * CCS availability on Xe_HP is inferred from the presence of DSS in
780 * each quadrant.
781 */
782 for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
783 if (!(gt->info.engine_mask & BIT(i)))
784 continue;
785
786 if (!xe_gt_topology_has_dss_in_quadrant(gt, j)) {
787 gt->info.engine_mask &= ~BIT(i);
788 xe_gt_info(gt, "ccs%u fused off\n", j);
789 }
790 }
791 }
792
read_compute_fuses_from_reg(struct xe_gt * gt)793 static void read_compute_fuses_from_reg(struct xe_gt *gt)
794 {
795 u32 ccs_mask;
796
797 ccs_mask = xe_mmio_read32(>->mmio, XEHP_FUSE4);
798 ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);
799
800 for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
801 if (!(gt->info.engine_mask & BIT(i)))
802 continue;
803
804 if ((ccs_mask & BIT(j)) == 0) {
805 gt->info.engine_mask &= ~BIT(i);
806 xe_gt_info(gt, "ccs%u fused off\n", j);
807 }
808 }
809 }
810
read_compute_fuses(struct xe_gt * gt)811 static void read_compute_fuses(struct xe_gt *gt)
812 {
813 if (GRAPHICS_VER(gt_to_xe(gt)) >= 20)
814 read_compute_fuses_from_reg(gt);
815 else
816 read_compute_fuses_from_dss(gt);
817 }
818
check_gsc_availability(struct xe_gt * gt)819 static void check_gsc_availability(struct xe_gt *gt)
820 {
821 if (!(gt->info.engine_mask & BIT(XE_HW_ENGINE_GSCCS0)))
822 return;
823
824 /*
825 * The GSCCS is only used to communicate with the GSC FW, so if we don't
826 * have the FW there is nothing we need the engine for and can therefore
827 * skip its initialization.
828 */
829 if (!xe_uc_fw_is_available(>->uc.gsc.fw)) {
830 gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0);
831
832 /* interrupts where previously enabled, so turn them off */
833 xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_ENABLE, 0);
834 xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_MASK, ~0);
835
836 xe_gt_dbg(gt, "GSC FW not used, disabling gsccs\n");
837 }
838 }
839
check_sw_disable(struct xe_gt * gt)840 static void check_sw_disable(struct xe_gt *gt)
841 {
842 struct xe_device *xe = gt_to_xe(gt);
843 u64 sw_allowed = xe_configfs_get_engines_allowed(to_pci_dev(xe->drm.dev));
844 enum xe_hw_engine_id id;
845
846 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) {
847 if (!(gt->info.engine_mask & BIT(id)))
848 continue;
849
850 if (!(sw_allowed & BIT(id))) {
851 gt->info.engine_mask &= ~BIT(id);
852 xe_gt_info(gt, "%s disabled via configfs\n",
853 engine_infos[id].name);
854 }
855 }
856 }
857
xe_hw_engines_init_early(struct xe_gt * gt)858 int xe_hw_engines_init_early(struct xe_gt *gt)
859 {
860 int i;
861
862 read_media_fuses(gt);
863 read_copy_fuses(gt);
864 read_compute_fuses(gt);
865 check_gsc_availability(gt);
866 check_sw_disable(gt);
867
868 BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT < XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN);
869 BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT > XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX);
870
871 for (i = 0; i < ARRAY_SIZE(gt->hw_engines); i++)
872 hw_engine_init_early(gt, >->hw_engines[i], i);
873
874 return 0;
875 }
876
xe_hw_engines_init(struct xe_gt * gt)877 int xe_hw_engines_init(struct xe_gt *gt)
878 {
879 int err;
880 struct xe_hw_engine *hwe;
881 enum xe_hw_engine_id id;
882
883 for_each_hw_engine(hwe, gt, id) {
884 err = hw_engine_init(gt, hwe, id);
885 if (err)
886 return err;
887 }
888
889 hw_engine_setup_logical_mapping(gt);
890 err = xe_hw_engine_setup_groups(gt);
891 if (err)
892 return err;
893
894 return 0;
895 }
896
xe_hw_engine_handle_irq(struct xe_hw_engine * hwe,u16 intr_vec)897 void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
898 {
899 wake_up_all(>_to_xe(hwe->gt)->ufence_wq);
900
901 if (hwe->irq_handler)
902 hwe->irq_handler(hwe, intr_vec);
903
904 if (intr_vec & GT_MI_USER_INTERRUPT)
905 xe_hw_fence_irq_run(hwe->fence_irq);
906 }
907
908 /**
909 * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW Engine.
910 * @hwe: Xe HW Engine.
911 * @q: The exec queue object.
912 *
913 * This can be printed out in a later stage like during dev_coredump
914 * analysis.
915 *
916 * Returns: a Xe HW Engine snapshot object that must be freed by the
917 * caller, using `xe_hw_engine_snapshot_free`.
918 */
919 struct xe_hw_engine_snapshot *
xe_hw_engine_snapshot_capture(struct xe_hw_engine * hwe,struct xe_exec_queue * q)920 xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe, struct xe_exec_queue *q)
921 {
922 struct xe_hw_engine_snapshot *snapshot;
923 struct __guc_capture_parsed_output *node;
924
925 if (!xe_hw_engine_is_valid(hwe))
926 return NULL;
927
928 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC);
929
930 if (!snapshot)
931 return NULL;
932
933 snapshot->name = kstrdup(hwe->name, GFP_ATOMIC);
934 snapshot->hwe = hwe;
935 snapshot->logical_instance = hwe->logical_instance;
936 snapshot->forcewake.domain = hwe->domain;
937 snapshot->forcewake.ref = xe_force_wake_ref(gt_to_fw(hwe->gt),
938 hwe->domain);
939 snapshot->mmio_base = hwe->mmio_base;
940 snapshot->kernel_reserved = xe_hw_engine_is_reserved(hwe);
941
942 /* no more VF accessible data below this point */
943 if (IS_SRIOV_VF(gt_to_xe(hwe->gt)))
944 return snapshot;
945
946 if (q) {
947 /* If got guc capture, set source to GuC */
948 node = xe_guc_capture_get_matching_and_lock(q);
949 if (node) {
950 struct xe_device *xe = gt_to_xe(hwe->gt);
951 struct xe_devcoredump *coredump = &xe->devcoredump;
952
953 coredump->snapshot.matched_node = node;
954 xe_gt_dbg(hwe->gt, "Found and locked GuC-err-capture node");
955 return snapshot;
956 }
957 }
958
959 /* otherwise, do manual capture */
960 xe_engine_manual_capture(hwe, snapshot);
961 xe_gt_dbg(hwe->gt, "Proceeding with manual engine snapshot");
962
963 return snapshot;
964 }
965
966 /**
967 * xe_hw_engine_snapshot_free - Free all allocated objects for a given snapshot.
968 * @snapshot: Xe HW Engine snapshot object.
969 *
970 * This function free all the memory that needed to be allocated at capture
971 * time.
972 */
xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot * snapshot)973 void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot)
974 {
975 struct xe_gt *gt;
976 if (!snapshot)
977 return;
978
979 gt = snapshot->hwe->gt;
980 /*
981 * xe_guc_capture_put_matched_nodes is called here and from
982 * xe_devcoredump_snapshot_free, to cover the 2 calling paths
983 * of hw_engines - debugfs and devcoredump free.
984 */
985 xe_guc_capture_put_matched_nodes(>->uc.guc);
986
987 kfree(snapshot->name);
988 kfree(snapshot);
989 }
990
991 /**
992 * xe_hw_engine_print - Xe HW Engine Print.
993 * @hwe: Hardware Engine.
994 * @p: drm_printer.
995 *
996 * This function quickly capture a snapshot and immediately print it out.
997 */
xe_hw_engine_print(struct xe_hw_engine * hwe,struct drm_printer * p)998 void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p)
999 {
1000 struct xe_hw_engine_snapshot *snapshot;
1001
1002 snapshot = xe_hw_engine_snapshot_capture(hwe, NULL);
1003 xe_engine_snapshot_print(snapshot, p);
1004 xe_hw_engine_snapshot_free(snapshot);
1005 }
1006
xe_hw_engine_mask_per_class(struct xe_gt * gt,enum xe_engine_class engine_class)1007 u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
1008 enum xe_engine_class engine_class)
1009 {
1010 u32 mask = 0;
1011 enum xe_hw_engine_id id;
1012
1013 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) {
1014 if (engine_infos[id].class == engine_class &&
1015 gt->info.engine_mask & BIT(id))
1016 mask |= BIT(engine_infos[id].instance);
1017 }
1018 return mask;
1019 }
1020
xe_hw_engine_is_reserved(struct xe_hw_engine * hwe)1021 bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe)
1022 {
1023 struct xe_gt *gt = hwe->gt;
1024 struct xe_device *xe = gt_to_xe(gt);
1025
1026 if (xe_device_is_admin_only(xe))
1027 return true;
1028
1029 if (hwe->class == XE_ENGINE_CLASS_OTHER)
1030 return true;
1031
1032 /* Check for engines disabled by ccs_mode setting */
1033 if (xe_gt_ccs_mode_enabled(gt) &&
1034 hwe->class == XE_ENGINE_CLASS_COMPUTE &&
1035 hwe->logical_instance >= gt->ccs_mode)
1036 return true;
1037
1038 return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
1039 hwe->instance == gt->usm.reserved_bcs_instance;
1040 }
1041
xe_hw_engine_class_to_str(enum xe_engine_class class)1042 const char *xe_hw_engine_class_to_str(enum xe_engine_class class)
1043 {
1044 switch (class) {
1045 case XE_ENGINE_CLASS_RENDER:
1046 return "rcs";
1047 case XE_ENGINE_CLASS_VIDEO_DECODE:
1048 return "vcs";
1049 case XE_ENGINE_CLASS_VIDEO_ENHANCE:
1050 return "vecs";
1051 case XE_ENGINE_CLASS_COPY:
1052 return "bcs";
1053 case XE_ENGINE_CLASS_OTHER:
1054 return "other";
1055 case XE_ENGINE_CLASS_COMPUTE:
1056 return "ccs";
1057 case XE_ENGINE_CLASS_MAX:
1058 break;
1059 }
1060
1061 return NULL;
1062 }
1063
xe_hw_engine_read_timestamp(struct xe_hw_engine * hwe)1064 u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe)
1065 {
1066 return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base));
1067 }
1068
xe_hw_engine_to_fw_domain(struct xe_hw_engine * hwe)1069 enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe)
1070 {
1071 return engine_infos[hwe->engine_id].domain;
1072 }
1073
1074 static const enum xe_engine_class user_to_xe_engine_class[] = {
1075 [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER,
1076 [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY,
1077 [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE,
1078 [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE,
1079 [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,
1080 };
1081
1082 /**
1083 * xe_hw_engine_lookup() - Lookup hardware engine for class:instance
1084 * @xe: xe device
1085 * @eci: engine class and instance
1086 *
1087 * This function will find a hardware engine for given engine
1088 * class and instance.
1089 *
1090 * Return: If found xe_hw_engine pointer, NULL otherwise.
1091 */
1092 struct xe_hw_engine *
xe_hw_engine_lookup(struct xe_device * xe,struct drm_xe_engine_class_instance eci)1093 xe_hw_engine_lookup(struct xe_device *xe,
1094 struct drm_xe_engine_class_instance eci)
1095 {
1096 struct xe_gt *gt = xe_device_get_gt(xe, eci.gt_id);
1097 unsigned int idx;
1098
1099 if (eci.engine_class >= ARRAY_SIZE(user_to_xe_engine_class))
1100 return NULL;
1101
1102 if (!gt)
1103 return NULL;
1104
1105 idx = array_index_nospec(eci.engine_class,
1106 ARRAY_SIZE(user_to_xe_engine_class));
1107
1108 return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id),
1109 user_to_xe_engine_class[idx],
1110 eci.engine_instance, true);
1111 }
1112