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Searched refs:writel_relaxed (Results 1 – 25 of 548) sorted by relevance

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/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1056 writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10, in meson_venc_hdmi_mode_set()
1058 writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) | in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1070 writel_relaxed(vmode->enci.hso_begin, in meson_venc_hdmi_mode_set()
1072 writel_relaxed(vmode->enci.hso_end, in meson_venc_hdmi_mode_set()
1076 writel_relaxed(vmode->enci.vso_even, in meson_venc_hdmi_mode_set()
[all …]
H A Dmeson_crtc.c107 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
110 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
113 writel_relaxed(crtc_state->mode.hdisplay << 16 | in meson_g12a_crtc_atomic_enable()
251 writel_relaxed(priv->viu.osd1_blk2_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
257 writel_relaxed(priv->viu.osd1_blk1_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h, in meson_g12a_crtc_enable_osd1()
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v, in meson_g12a_crtc_enable_osd1()
277 writel_relaxed(priv->viu.osb_blend0_size, in meson_g12a_crtc_enable_osd1()
280 writel_relaxed(priv->viu.osb_blend1_size, in meson_g12a_crtc_enable_osd1()
302 writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 | in meson_g12a_crtc_enable_vd1()
[all …]
H A Dmeson_vpp.c59 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_scaling_filter_coefs()
62 writel_relaxed(coefs[i], in meson_vpp_write_scaling_filter_coefs()
84 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_vd_scaling_filter_coefs()
87 writel_relaxed(coefs[i], in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, in meson_vpp_init()
101 writel_relaxed(0x1020080, in meson_vpp_init()
103 writel_relaxed(0x42020, in meson_vpp_init()
106 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
110 writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, in meson_vpp_init()
[all …]
/linux/drivers/clocksource/
H A Dtimer-gx6605s.c30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); in gx6605s_timer_interrupt()
31 writel_relaxed(0, base + TIMER_INI); in gx6605s_timer_interrupt()
43 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_oneshot()
46 writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, in gx6605s_timer_set_oneshot()
58 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
61 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); in gx6605s_timer_set_next_event()
62 writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
71 writel_relaxed(0, base + TIMER_CONTRL); in gx6605s_timer_shutdown()
72 writel_relaxed(0, base + TIMER_CONFIG); in gx6605s_timer_shutdown()
105 writel_relaxed(0, base + TIMER_DIV); in gx6605s_clkevt_init()
[all …]
H A Dtimer-lpc32xx.c75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
105 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | in lpc32xx_clkevt_oneshot()
116 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, in lpc32xx_clkevt_periodic()
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_periodic()
125 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
[all …]
H A Dasm9260_timer.c113 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event()
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in __asm9260_timer_shutdown()
136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_oneshot()
146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_periodic()
149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_periodic()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt()
218 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); in asm9260_timer_init()
220 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); in asm9260_timer_init()
[all …]
/linux/drivers/media/platform/qcom/camss/
H A Dcamss-vfe-4-8.c263 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
270 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
286 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
290 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
295 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, in vfe_halt_request()
301 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
385 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
394 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
397 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
399 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
[all …]
H A Dcamss-vfe-4-7.c280 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
287 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
303 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
307 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
312 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, in vfe_halt_request()
318 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
412 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
421 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
424 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
426 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
[all …]
H A Dcamss-csid-gen2.c191 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); in __csid_configure_rx()
197 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1); in __csid_configure_rx()
208 writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi)); in __csid_ctrl_rdi()
228 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0); in __csid_configure_testgen()
232 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1); in __csid_configure_testgen()
234 writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED); in __csid_configure_testgen()
238 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0)); in __csid_configure_testgen()
241 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0)); in __csid_configure_testgen()
246 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0)); in __csid_configure_testgen()
248 writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG); in __csid_configure_testgen()
[all …]
H A Dcamss-csiphy-2ph-1-0.c58 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_reset()
60 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_reset()
108 writel_relaxed(0x1, csiphy->base + in csiphy_lanes_enable()
110 writel_relaxed(0x1, csiphy->base + in csiphy_lanes_enable()
115 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); in csiphy_lanes_enable()
118 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_lanes_enable()
126 writel_relaxed(0x10, csiphy->base + in csiphy_lanes_enable()
128 writel_relaxed(settle_cnt, csiphy->base + in csiphy_lanes_enable()
130 writel_relaxed(0x3f, csiphy->base + in csiphy_lanes_enable()
132 writel_relaxed(0x3f, csiphy->base + in csiphy_lanes_enable()
[all …]
H A Dcamss-csid-4-1.c75 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); in csid_configure_stream()
80 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); in csid_configure_stream()
84 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); in csid_configure_stream()
88 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); in csid_configure_stream()
100 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); in csid_configure_stream()
105 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); in csid_configure_stream()
114 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); in csid_configure_stream()
120 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); in csid_configure_stream()
124 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); in csid_configure_stream()
129 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); in csid_configure_stream()
[all …]
H A Dcamss-vfe-480.c110 writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); in vfe_global_reset()
111 writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); in vfe_global_reset()
122 writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); in vfe_wm_start()
124 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); in vfe_wm_start()
126 writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height, in vfe_wm_start()
128 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); in vfe_wm_start()
129 writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH, in vfe_wm_start()
131 writel_relaxed(pix->plane_fmt[0].bytesperline, in vfe_wm_start()
133 writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); in vfe_wm_start()
136 writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); in vfe_wm_start()
[all …]
H A Dcamss-vfe-17x.c197 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
215 writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0); in vfe_global_reset()
220 writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD); in vfe_global_reset()
230 writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG); in vfe_wm_start()
233 writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER); in vfe_wm_start()
237 writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); in vfe_wm_start()
239 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); in vfe_wm_start()
243 writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC); in vfe_wm_start()
245 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); in vfe_wm_start()
248 writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm)); in vfe_wm_start()
[all …]
H A Dcamss-csid-4-7.c76 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); in csid_configure_stream()
81 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); in csid_configure_stream()
85 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); in csid_configure_stream()
89 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); in csid_configure_stream()
101 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); in csid_configure_stream()
106 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); in csid_configure_stream()
116 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); in csid_configure_stream()
132 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); in csid_configure_stream()
136 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); in csid_configure_stream()
141 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); in csid_configure_stream()
[all …]
/linux/arch/arm/mach-hisi/
H A Dhotplug.c82 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
87 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
92 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
95 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
99 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
106 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
111 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
116 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
119 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
123 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
/linux/drivers/mailbox/
H A Dpl320-ipc.c50 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox)); in set_destination()
51 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox)); in set_destination()
56 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox)); in clear_destination()
57 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox)); in clear_destination()
64 writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i)); in __ipc_send()
65 writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox)); in __ipc_send()
106 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in ipc_handler()
112 writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX)); in ipc_handler()
138 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in pl320_probe()
146 writel_relaxed(CHAN_MASK(A9_SOURCE), in pl320_probe()
[all …]
/linux/drivers/mmc/host/
H A Dmmci_qcom_dml.c64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
70 writel_relaxed(data->blocks * data->blksz, in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
84 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
88 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
90 writel_relaxed(1, base + DML_CONSUMER_START); in qcom_dma_start()
140 writel_relaxed(1, base + DML_SW_RESET); in qcom_dma_setup()
161 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_setup()
[all …]
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.c42 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
126 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
139 writel_relaxed(win->pitch[0], in overlay_set_win()
141 writel_relaxed(win->pitch[2] << 16 | win->pitch[1], in overlay_set_win()
144 writel_relaxed((win->ysrc << 16) | win->xsrc, in overlay_set_win()
146 writel_relaxed((win->ydst << 16) | win->xdst, in overlay_set_win()
148 writel_relaxed(win->ypos << 16 | win->xpos, in overlay_set_win()
151 writel_relaxed(win->pitch[0], (void __iomem *)&regs->g_pitch); in overlay_set_win()
153 writel_relaxed((win->ysrc << 16) | win->xsrc, in overlay_set_win()
155 writel_relaxed((win->ydst << 16) | win->xdst, in overlay_set_win()
[all …]
/linux/arch/arm/mach-qcom/
H A Dplatsmp.c70 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
71 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
72 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
171 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
177 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
179 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
184 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
189 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
194 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
199 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/linux/drivers/rtc/
H A Drtc-st-lpc.c59 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
61 writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF); in st_rtc_set_hw_alarm()
62 writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF); in st_rtc_set_hw_alarm()
63 writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_set_hw_alarm()
65 writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
114 writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF); in st_rtc_set_time()
115 writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF); in st_rtc_set_time()
116 writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF); in st_rtc_set_time()
264 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_suspend()
265 writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_suspend()
[all …]
H A Drtc-rtd119x.c61 writel_relaxed(val, data->base + RTD_RTCCR); in rtd119x_rtc_reset()
76 writel_relaxed(0x5a, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
78 writel_relaxed(0, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
145 writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); in rtd119x_rtc_set_time()
146 writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); in rtd119x_rtc_set_time()
147 writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); in rtd119x_rtc_set_time()
148 writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); in rtd119x_rtc_set_time()
149 writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); in rtd119x_rtc_set_time()
195 writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); in rtd119x_rtc_probe()
199 writel_relaxed(0, data->base + RTD_RTCMIN); in rtd119x_rtc_probe()
[all …]
H A Drtc-sa1100.c57 writel_relaxed(0, info->rtsr); in sa1100_rtc_interrupt()
64 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); in sa1100_rtc_interrupt()
73 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); in sa1100_rtc_interrupt()
79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt()
105 writel_relaxed(rtsr, info->rtsr); in sa1100_rtc_alarm_irq_enable()
122 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); in sa1100_rtc_set_time()
143 writel_relaxed(readl_relaxed(info->rtsr) & in sa1100_rtc_set_alarm()
145 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); in sa1100_rtc_set_alarm()
147 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
149 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
[all …]
/linux/arch/arm/common/
H A Dsa1111.c217 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0); in sa1111_irq_handler()
221 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1); in sa1111_irq_handler()
275 writel_relaxed(ie, mapbase + SA1111_INTEN0); in sa1111_unmask_irq()
294 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
295 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
326 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_type_irq()
327 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0); in sa1111_type_irq()
343 writel_relaxed(we, mapbase + SA1111_WAKEEN0); in sa1111_wake_irq()
401 writel_relaxed(0, irqbase + SA1111_INTEN0); in sa1111_setup_irq()
402 writel_relaxed(0, irqbase + SA1111_INTEN1); in sa1111_setup_irq()
[all …]
/linux/drivers/crypto/hisilicon/sec/
H A Dsec_drv.c262 writel_relaxed(regval, addr); in sec_queue_ar_pkgattr()
274 writel_relaxed(regval, addr); in sec_queue_aw_pkgattr()
284 writel_relaxed(0x7, base + SEC_ALGSUB_CLK_EN_REG); in sec_clk_en()
301 writel_relaxed(0x7, base + SEC_ALGSUB_CLK_DIS_REG); in sec_clk_dis()
319 writel_relaxed(1, base + SEC_ALGSUB_RST_REQ_REG); in sec_reset_whole_module()
320 writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_REQ_REG); in sec_reset_whole_module()
337 writel_relaxed(1, base + SEC_ALGSUB_RST_DREQ_REG); in sec_reset_whole_module()
338 writel_relaxed(1, base + SEC_ALGSUB_BUILD_RST_DREQ_REG); in sec_reset_whole_module()
365 writel_relaxed(regval, addr); in sec_bd_endian_little()
380 writel_relaxed(0x44cf9e, addr); in sec_cache_config()
[all …]
/linux/drivers/irqchip/
H A Dirq-sa11x0.c40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend()
110 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume()
111 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume()
113 writel_relaxed(st->icmr, iobase + ICMR); in sa1100irq_resume()
154 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt()
157 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
163 writel_relaxed(1, iobase + ICCR); in sa11x0_init_irq_nodt()

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