Home
last modified time | relevance | path

Searched refs:writel_relaxed (Results 1 – 25 of 495) sorted by relevance

12345678910>>...20

/linux/drivers/gpu/drm/meson/
H A Dmeson_crtc.c107 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
110 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
113 writel_relaxed(crtc_state->mode.hdisplay << 16 | in meson_g12a_crtc_atomic_enable()
251 writel_relaxed(priv->viu.osd1_blk2_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
257 writel_relaxed(priv->viu.osd1_blk1_cfg4, in meson_crtc_g12a_enable_osd1_afbc()
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h, in meson_g12a_crtc_enable_osd1()
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v, in meson_g12a_crtc_enable_osd1()
277 writel_relaxed(priv->viu.osb_blend0_size, in meson_g12a_crtc_enable_osd1()
280 writel_relaxed(priv->viu.osb_blend1_size, in meson_g12a_crtc_enable_osd1()
302 writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 | in meson_g12a_crtc_enable_vd1()
[all …]
H A Dmeson_vpp.c59 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_scaling_filter_coefs()
62 writel_relaxed(coefs[i], in meson_vpp_write_scaling_filter_coefs()
84 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_vd_scaling_filter_coefs()
87 writel_relaxed(coefs[i], in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, in meson_vpp_init()
101 writel_relaxed(0x1020080, in meson_vpp_init()
103 writel_relaxed(0x42020, in meson_vpp_init()
106 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
110 writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, in meson_vpp_init()
[all …]
/linux/drivers/clocksource/
H A Dtimer-gx6605s.c30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); in gx6605s_timer_interrupt()
31 writel_relaxed(0, base + TIMER_INI); in gx6605s_timer_interrupt()
43 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_oneshot()
46 writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, in gx6605s_timer_set_oneshot()
58 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
61 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); in gx6605s_timer_set_next_event()
62 writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
71 writel_relaxed(0, base + TIMER_CONTRL); in gx6605s_timer_shutdown()
72 writel_relaxed(0, base + TIMER_CONFIG); in gx6605s_timer_shutdown()
105 writel_relaxed(0, base + TIMER_DIV); in gx6605s_clkevt_init()
[all …]
H A Dtimer-lpc32xx.c75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
105 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | in lpc32xx_clkevt_oneshot()
116 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, in lpc32xx_clkevt_periodic()
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_periodic()
125 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
[all …]
H A Dasm9260_timer.c113 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event()
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in __asm9260_timer_shutdown()
136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_oneshot()
146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_periodic()
149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_periodic()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt()
218 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); in asm9260_timer_init()
220 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); in asm9260_timer_init()
[all …]
H A Dtimer-imx-gpt.c99 writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); in imx1_gpt_irq_disable()
104 writel_relaxed(0, imxtm->base + V2_IR); in imx31_gpt_irq_disable()
112 writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); in imx1_gpt_irq_enable()
117 writel_relaxed(1<<0, imxtm->base + V2_IR); in imx31_gpt_irq_enable()
122 writel_relaxed(0, imxtm->base + MX1_2_TSTAT); in imx1_gpt_irq_acknowledge()
127 writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, in imx21_gpt_irq_acknowledge()
133 writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); in imx31_gpt_irq_acknowledge()
180 writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); in mx1_2_set_next_event()
194 writel_relaxed(tcmp, imxtm->base + V2_TCMP); in v2_set_next_event()
211 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); in mxc_shutdown()
[all …]
H A Dtimer-davinci.c82 writel_relaxed(val, clockevent->base + reg); in davinci_clockevent_write()
99 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_tim12_shutdown()
112 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_tim12_set_oneshot()
205 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); in davinci_clocksource_init_tim34()
206 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); in davinci_clocksource_init_tim34()
207 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_clocksource_init_tim34()
222 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); in davinci_clocksource_init_tim12()
223 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); in davinci_clocksource_init_tim12()
224 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); in davinci_clocksource_init_tim12()
230 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); in davinci_timer_init()
[all …]
H A Dtimer-milbeaut.c57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_timer_interrupt()
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_start()
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_evt_timer_stop()
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); in mlb_evt_timer_register_count()
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); in mlb_config_clock_source()
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); in mlb_config_clock_source()
133 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); in mlb_config_clock_source()
139 writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); in mlb_config_clock_event()
H A Dtimer-ti-dm-systimer.c82 writel_relaxed(val, t->base + t->sysc); in dmtimer_systimer_enable()
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); in dmtimer_systimer_disable()
100 writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl); in dmtimer_systimer_type1_reset()
116 writel_relaxed(l, sysc); in dmtimer_systimer_type2_reset()
439 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); in dmtimer_clockevent_interrupt()
454 writel_relaxed(0xffffffff - cycles, t->base + t->counter); in dmtimer_set_next_event()
458 writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl); in dmtimer_set_next_event()
473 writel_relaxed(l, ctrl); in dmtimer_clockevent_shutdown()
479 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat); in dmtimer_clockevent_shutdown()
495 writel_relaxed(clkevt->period, t->base + t->load); in dmtimer_set_periodic()
[all …]
/linux/arch/arm/mach-hisi/
H A Dhotplug.c82 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
87 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
92 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
95 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
99 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
106 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
111 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
116 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
119 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
123 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
/linux/drivers/mmc/host/
H A Dmmci_qcom_dml.c64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
70 writel_relaxed(data->blocks * data->blksz, in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
84 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
88 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
90 writel_relaxed(1, base + DML_CONSUMER_START); in qcom_dma_start()
141 writel_relaxed(1, base + DML_SW_RESET); in qcom_dma_setup()
162 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_setup()
[all …]
/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.c42 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
126 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
139 writel_relaxed(win->pitch[0], in overlay_set_win()
141 writel_relaxed(win->pitch[2] << 16 | win->pitch[1], in overlay_set_win()
144 writel_relaxed((win->ysrc << 16) | win->xsrc, in overlay_set_win()
146 writel_relaxed((win->ydst << 16) | win->xdst, in overlay_set_win()
148 writel_relaxed(win->ypos << 16 | win->xpos, in overlay_set_win()
151 writel_relaxed(win->pitch[0], (void __iomem *)&regs->g_pitch); in overlay_set_win()
153 writel_relaxed((win->ysrc << 16) | win->xsrc, in overlay_set_win()
155 writel_relaxed((win->ydst << 16) | win->xdst, in overlay_set_win()
[all …]
/linux/arch/arm/mach-qcom/
H A Dplatsmp.c70 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
71 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
72 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
171 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
177 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
179 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
184 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
189 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
194 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
199 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/linux/drivers/rtc/
H A Drtc-st-lpc.c59 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
61 writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF); in st_rtc_set_hw_alarm()
62 writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF); in st_rtc_set_hw_alarm()
63 writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_set_hw_alarm()
65 writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
114 writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF); in st_rtc_set_time()
115 writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF); in st_rtc_set_time()
116 writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF); in st_rtc_set_time()
264 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_suspend()
265 writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_suspend()
[all …]
H A Drtc-rtd119x.c61 writel_relaxed(val, data->base + RTD_RTCCR); in rtd119x_rtc_reset()
76 writel_relaxed(0x5a, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
78 writel_relaxed(0, data->base + RTD_RTCEN); in rtd119x_rtc_set_enabled()
145 writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); in rtd119x_rtc_set_time()
146 writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); in rtd119x_rtc_set_time()
147 writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); in rtd119x_rtc_set_time()
148 writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); in rtd119x_rtc_set_time()
149 writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); in rtd119x_rtc_set_time()
195 writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); in rtd119x_rtc_probe()
199 writel_relaxed(0, data->base + RTD_RTCMIN); in rtd119x_rtc_probe()
[all …]
H A Drtc-sa1100.c55 writel_relaxed(0, info->rtsr); in sa1100_rtc_interrupt()
62 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); in sa1100_rtc_interrupt()
71 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); in sa1100_rtc_interrupt()
77 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt()
103 writel_relaxed(rtsr, info->rtsr); in sa1100_rtc_alarm_irq_enable()
120 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); in sa1100_rtc_set_time()
141 writel_relaxed(readl_relaxed(info->rtsr) & in sa1100_rtc_set_alarm()
143 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); in sa1100_rtc_set_alarm()
145 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
147 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr); in sa1100_rtc_set_alarm()
[all …]
/linux/arch/arm/common/
H A Dsa1111.c217 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0); in sa1111_irq_handler()
221 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1); in sa1111_irq_handler()
275 writel_relaxed(ie, mapbase + SA1111_INTEN0); in sa1111_unmask_irq()
294 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
295 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_retrigger_irq()
326 writel_relaxed(ip, mapbase + SA1111_INTPOL0); in sa1111_type_irq()
327 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0); in sa1111_type_irq()
343 writel_relaxed(we, mapbase + SA1111_WAKEEN0); in sa1111_wake_irq()
401 writel_relaxed(0, irqbase + SA1111_INTEN0); in sa1111_setup_irq()
402 writel_relaxed(0, irqbase + SA1111_INTEN1); in sa1111_setup_irq()
[all …]
/linux/drivers/irqchip/
H A Dirq-sa11x0.c40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend()
110 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume()
111 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume()
113 writel_relaxed(st->icmr, iobase + ICMR); in sa1100irq_resume()
158 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt()
161 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
167 writel_relaxed(1, iobase + ICCR); in sa11x0_init_irq_nodt()
H A Dirq-gic-common.c82 writel_relaxed(val, base + confoff); in gic_configure_irq()
99 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config()
106 writel_relaxed(REPEAT_BYTE_U32(priority), in gic_dist_config()
114 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
116 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
130 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
132 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
140 writel_relaxed(REPEAT_BYTE_U32(priority), in gic_cpu_config()
H A Dirq-tegra.c88 writel_relaxed(mask, base + reg); in tegra_ictlr_write_mask()
151 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_suspend()
154 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_suspend()
157 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET); in tegra_ictlr_suspend()
173 writel_relaxed(lic->cpu_iep[i], in tegra_ictlr_resume()
175 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR); in tegra_ictlr_resume()
176 writel_relaxed(lic->cpu_ier[i], in tegra_ictlr_resume()
178 writel_relaxed(lic->cop_iep[i], in tegra_ictlr_resume()
180 writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR); in tegra_ictlr_resume()
181 writel_relaxed(lic->cop_ier[i], in tegra_ictlr_resume()
[all …]
/linux/drivers/gpio/
H A Dgpio-sa1100.c51 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
72 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); in sa1100_direction_input()
85 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); in sa1100_direction_output()
125 writel_relaxed(grer, base + R_GRER); in sa1100_update_edge_regs()
126 writel_relaxed(gfer, base + R_GFER); in sa1100_update_edge_regs()
161 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
245 writel_relaxed(mask, gedr); in sa1100_gpio_handler()
266 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); in sa1100_gpio_suspend()
267 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); in sa1100_gpio_suspend()
272 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR), in sa1100_gpio_suspend()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c525 writel_relaxed(value, clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
552 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
562 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
574 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
584 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
604 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
613 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); in tegra210_clk_emc_dll_enable()
619 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); in tegra210_clk_emc_dll_update_setting()
[all …]
/linux/arch/arm/mach-imx/
H A Dgpc.c36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_up_timing()
42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | in imx_gpc_set_arm_power_down_timing()
48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); in imx_gpc_set_arm_power_in_lpm()
59 writel_relaxed(val, gpc_base + GPC_CNTR); in imx_gpc_set_l2_mem_power_in_lpm()
73 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); in imx_gpc_pre_suspend()
86 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_post_resume()
112 writel_relaxed(~0, reg_imr1 + i * 4); in imx_gpc_mask_all()
122 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); in imx_gpc_restore_all()
133 writel_relaxed(val, reg); in imx_gpc_hwirq_unmask()
144 writel_relaxed(val, reg); in imx_gpc_hwirq_mask()
[all …]
/linux/drivers/spi/
H A Dspi-microchip-core-qspi.c163 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_set_mode()
214 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
226 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
242 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_op()
250 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA); in mchp_coreqspi_write_op()
254 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_op()
260 writel_relaxed(data, qspi->regs + REG_TX_DATA); in mchp_coreqspi_write_op()
272 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_read_op()
282 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA); in mchp_coreqspi_write_read_op()
327 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_read_op()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-at91.c405 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
416 writel_relaxed(mask, pio + PIO_PPDDR); in at91_mux_set_pullup()
418 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
430 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_mux_set_output()
431 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); in at91_mux_set_output()
441 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
446 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
451 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
457 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
459 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
[all …]

12345678910>>...20