Lines Matching refs:writel_relaxed

181 	writel_relaxed(bits | set_bits, vfe->base + reg);
199 	writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0);
204 	writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD);
214 	writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);
217 	writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);
221 	writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
223 	writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
227 	writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);
229 	writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
232 	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));
235 	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));
238 	writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8?
242 	writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));
247 	writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));
253 	writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
263 	writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
264 	writel_relaxed(stride * pix->height, vfe->base + VFE_BUS_WM_FRAME_INC(wm));
274 	writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
291 	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(0));
292 	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(1));
293 	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(2));
306 	writel_relaxed(*status0, vfe->base + VFE_IRQ_CLEAR_0);
307 	writel_relaxed(*status1, vfe->base + VFE_IRQ_CLEAR_1);
311 	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
337 	writel_relaxed(status0, vfe->base + VFE_IRQ_CLEAR_0);
338 	writel_relaxed(status1, vfe->base + VFE_IRQ_CLEAR_1);
342 		writel_relaxed(vfe_bus_status[i], vfe->base + VFE_BUS_IRQ_CLEAR(i));
348 	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
349 	writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);