| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/ |
| H A D | dcn401_hubbub.c | 69 union dcn_watermark_set *watermarks, in hubbub401_program_urgent_watermarks() argument 78 if (safe_to_lower || watermarks->dcn4x.a.urgent > hubbub2->watermarks.dcn4x.a.urgent) { in hubbub401_program_urgent_watermarks() 79 hubbub2->watermarks.dcn4x.a.urgent = watermarks->dcn4x.a.urgent; in hubbub401_program_urgent_watermarks() 81 DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, watermarks->dcn4x.a.urgent); in hubbub401_program_urgent_watermarks() 84 watermarks->dcn4x.a.urgent, watermarks->dcn4x.a.urgent); in hubbub401_program_urgent_watermarks() 85 } else if (watermarks->dcn4x.a.urgent < hubbub2->watermarks.dcn4x.a.urgent) in hubbub401_program_urgent_watermarks() 89 if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_flip in hubbub401_program_urgent_watermarks() 90 > hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip) { in hubbub401_program_urgent_watermarks() 91 hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip = watermarks->dcn4x.a.frac_urg_bw_flip; in hubbub401_program_urgent_watermarks() 93 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->dcn4x.a.frac_urg_bw_flip); in hubbub401_program_urgent_watermarks() [all …]
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| H A D | dcn401_hubbub.h | 140 union dcn_watermark_set *watermarks, 146 union dcn_watermark_set *watermarks, 152 union dcn_watermark_set *watermarks, 158 union dcn_watermark_set *watermarks,
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| /linux/mm/damon/ |
| H A D | sysfs-schemes.c | 852 struct damon_sysfs_watermarks *watermarks = kmalloc_obj(*watermarks); in damon_sysfs_watermarks_alloc() local 854 if (!watermarks) in damon_sysfs_watermarks_alloc() 856 watermarks->kobj = (struct kobject){}; in damon_sysfs_watermarks_alloc() 857 watermarks->metric = metric; in damon_sysfs_watermarks_alloc() 858 watermarks->interval_us = interval_us; in damon_sysfs_watermarks_alloc() 859 watermarks->high = high; in damon_sysfs_watermarks_alloc() 860 watermarks->mid = mid; in damon_sysfs_watermarks_alloc() 861 watermarks->low = low; in damon_sysfs_watermarks_alloc() 862 return watermarks; in damon_sysfs_watermarks_alloc() 885 struct damon_sysfs_watermarks *watermarks = container_of(kobj, in metric_show() local [all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = 568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = 570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = 572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000; 580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = 582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = 584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = 586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; 587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000; [all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp() 524 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn31_calculate_wm_and_dlg_fp() 525 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn31_calculate_wm_and_dlg_fp() 526 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn31_calculate_wm_and_dlg_fp() 527 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dcn31_calculate_wm_and_dlg_fp() 528 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&cont… in dcn31_calculate_wm_and_dlg_fp() 529 …context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn31_calculate_wm_and_dlg_fp() 530 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn31_calculate_wm_and_dlg_fp() 531 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn31_calculate_wm_and_dlg_fp() 532 …context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn31_calculate_wm_and_dlg_fp() [all …]
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| /linux/tools/testing/selftests/damon/ |
| H A D | sysfs.py | 36 def assert_watermarks_committed(watermarks, dump): argument 41 assert_true(dump['metric'] == wmark_metric_val[watermarks.metric], 43 assert_true(dump['interval'] == watermarks.interval, 'interval', dump) 44 assert_true(dump['high'] == watermarks.high, 'high', dump) 45 assert_true(dump['mid'] == watermarks.mid, 'mid', dump) 46 assert_true(dump['low'] == watermarks.low, 'low', dump) 132 assert_watermarks_committed(scheme.watermarks, dump['wmarks']) 238 watermarks=_damon_sysfs.DamosWatermarks(
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| H A D | drgn_dump_damon_status.py | 119 def damos_watermarks_to_dict(watermarks): argument 120 return to_dict(watermarks, [
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| H A D | _damon_sysfs.py | 393 watermarks = None variable in Damos 407 quota=DamosQuota(), watermarks=DamosWatermarks(), argument 415 self.watermarks = watermarks 416 self.watermarks.scheme = self 453 err = self.watermarks.stage()
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| H A D | dcn201_hubbub.c | 55 union dcn_watermark_set *watermarks, in hubbub201_program_watermarks() argument 62 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks() 65 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 30 struct watermarks; 36 struct watermarks *wm_set;
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| H A D | dcn301_smu.h | 129 struct watermarks { struct
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/ |
| H A D | dcn21_hubbub.h | 130 union dcn_watermark_set *watermarks, 135 union dcn_watermark_set *watermarks, 140 union dcn_watermark_set *watermarks, 145 union dcn_watermark_set *watermarks,
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/ |
| H A D | dcn32_hubbub.h | 121 union dcn_watermark_set *watermarks, 127 union dcn_watermark_set *watermarks, 133 union dcn_watermark_set *watermarks, 139 union dcn_watermark_set *watermarks,
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| /linux/Documentation/admin-guide/mm/damon/ |
| H A D | reclaim.rst | 38 automatically activated and deactivated with three memory pressure watermarks. 60 no real monitoring and reclamation due to the watermarks-based activation 61 condition. Refer to below descriptions for the watermarks parameter for this. 150 Minimal time to wait before checking the watermarks, when DAMON_RECLAIM is 151 enabled but inactive due to its watermarks rule. 160 the watermarks. 178 watermarks. In the case, the system falls back to the LRU-list based page
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/ |
| H A D | dcn20_hubbub.c | 594 union dcn_watermark_set *watermarks, in hubbub2_program_watermarks() argument 604 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks() 607 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks() 619 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 825 …hub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2… in wm_set_index_to_dc_wm_set() argument 831 wm_regs = &watermarks->dcn4x.a; in wm_set_index_to_dc_wm_set() 834 wm_regs = &watermarks->dcn4x.b; in wm_set_index_to_dc_wm_set() 837 wm_regs = &watermarks->dcn4x.c; in wm_set_index_to_dc_wm_set() 840 wm_regs = &watermarks->dcn4x.d; in wm_set_index_to_dc_wm_set() 851 void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, stru… in dml21_extract_watermark_sets() argument 859 struct dml2_dchub_watermark_regs *wm_regs = wm_set_index_to_dc_wm_set(watermarks, wm_index); in dml21_extract_watermark_sets()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu_helper.h | 45 struct watermarks { struct
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| H A D | smu7_hwmgr.c | 5362 struct dm_pp_wm_sets_with_clock_ranges *watermarks = in smu7_set_watermarks_for_clocks_ranges() local 5374 for (k = 0; k < watermarks->num_wm_sets; k++) { in smu7_set_watermarks_for_clocks_ranges() 5375 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges() 5376 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges() 5377 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges() 5378 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { in smu7_set_watermarks_for_clocks_ranges() 5380 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; in smu7_set_watermarks_for_clocks_ranges() 5386 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); in smu7_set_watermarks_for_clocks_ranges()
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| H A D | smu_helper.c | 717 struct watermarks *table = wt_table; in smu_set_watermarks_for_clocks_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 564 union dcn_watermark_set watermarks; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 213 struct dml2_core_internal_watermarks watermarks; member
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 2368 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth() 2381 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth() 2391 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth() 2397 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth() 2425 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth() 2432 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 7286 const struct dml2_core_internal_watermarks *watermarks, in calculate_pstate_keepout_dst_lines() argument 7297 …(unsigned int)math_ceil(watermarks->DRAMClockChangeWatermark / ((double)stream_descriptor->timing.… in calculate_pstate_keepout_dst_lines() 7927 CalculateWatermarks_params->Watermark = &mode_lib->ms.support.watermarks; // Watermarks *Watermark in dml_core_ms_prefetch_check() 7942 …calculate_pstate_keepout_dst_lines(display_cfg, &mode_lib->ms.support.watermarks, s->dummy_integer… in dml_core_ms_prefetch_check() 13135 out->informative.watermarks.urgent_us = dml_get_wm_urgent(mode_lib); in dml2_core_calcs_get_informative() 13136 out->informative.watermarks.writeback_urgent_us = dml_get_wm_writeback_urgent(mode_lib); in dml2_core_calcs_get_informative() 13137 out->informative.watermarks.writeback_pstate_us = dml_get_wm_writeback_dram_clock_change(mode_lib); in dml2_core_calcs_get_informative() 13138 out->informative.watermarks.writeback_fclk_pstate_us = dml_get_wm_writeback_fclk_change(mode_lib); in dml2_core_calcs_get_informative() 13140 out->informative.watermarks.cstate_exit_us = dml_get_wm_stutter_exit(mode_lib); in dml2_core_calcs_get_informative() 13141 out->informative.watermarks.cstate_enter_plus_exit_us = dml_get_wm_stutter_enter_exit(mode_lib); in dml2_core_calcs_get_informative() [all …]
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| /linux/Documentation/admin-guide/sysctl/ |
| H A D | vm.rst | 335 implies that the allocation will succeed as long as watermarks are met. 1104 distances between watermarks are 0.1% of the available memory in the
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 3354 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth() 3392 &context->bw_ctx.bw.dcn.watermarks, in dcn10_optimize_bandwidth()
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