| /linux/tools/testing/selftests/damon/ |
| H A D | sysfs.py | 39 def assert_watermarks_committed(watermarks, dump):
44 assert_true(dump['metric'] == wmark_metric_val[watermarks.metric],
46 assert_true(dump['interval'] == watermarks.interval, 'interval', dump)
47 assert_true(dump['high'] == watermarks.high, 'high', dump)
48 assert_true(dump['mid'] == watermarks.mid, 'mid', dump)
49 assert_true(dump['low'] == watermarks.low, 'low', dump)
146 assert_watermarks_committed(scheme.watermarks, dump['wmarks'])
323 watermarks=_damon_sysfs.DamosWatermarks(
36 assert_watermarks_committed(watermarks, dump) global() argument
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| H A D | drgn_dump_damon_status.py | 121 def damos_watermarks_to_dict(watermarks):
122 return to_dict(watermarks, [
119 damos_watermarks_to_dict(watermarks) global() argument
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| H A D | _damon_sysfs.py | 235 return os.path.join(self.scheme.sysfs_dir(), 'watermarks')
416 watermarks = None
430 quota=DamosQuota(), watermarks=DamosWatermarks(),
438 self.watermarks = watermarks
439 self.watermarks.scheme = self
476 err = self.watermarks.stage()
393 watermarks = None global() variable in Damos
407 __init__(self, action='stat', access_pattern=DamosAccessPattern(), quota=DamosQuota(), watermarks=DamosWatermarks(), core_filters=[], ops_filters=[], filters=[], target_nid=0, dests=DamosDests(), apply_interval_us=0) global() argument
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/ |
| H A D | dcn201_hubbub.c | 55 union dcn_watermark_set *watermarks, in hubbub201_program_watermarks() argument
62 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
65 if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub201_program_watermarks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 30 struct watermarks;
36 struct watermarks *wm_set;
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| H A D | dcn301_smu.h | 129 struct watermarks { struct
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/ |
| H A D | dcn21_hubbub.h | 130 union dcn_watermark_set *watermarks,
135 union dcn_watermark_set *watermarks,
140 union dcn_watermark_set *watermarks,
145 union dcn_watermark_set *watermarks,
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| /linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/ |
| H A D | dcn32_hubbub.h | 121 union dcn_watermark_set *watermarks,
127 union dcn_watermark_set *watermarks,
133 union dcn_watermark_set *watermarks,
139 union dcn_watermark_set *watermarks,
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_wrapper_fpu.c | 488 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
489 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
491 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
493 …emcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context-… in dml2_validate_and_build_resource()
494 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
499 …cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus… in dml2_validate_and_build_resource()
505 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dml2_validate_and_build_resource()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 5478 struct dm_pp_wm_sets_with_clock_ranges *watermarks = in smu7_set_watermarks_for_clocks_ranges() local
5490 for (k = 0; k < watermarks->num_wm_sets; k++) { in smu7_set_watermarks_for_clocks_ranges()
5491 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5492 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5493 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && in smu7_set_watermarks_for_clocks_ranges()
5494 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { in smu7_set_watermarks_for_clocks_ranges()
5496 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; in smu7_set_watermarks_for_clocks_ranges()
5502 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); in smu7_set_watermarks_for_clocks_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2181 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn30_setup_mclk_switch_using_fw_based_vblank_stretch()
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