Searched refs:vuip (Results 1 – 19 of 19) sorted by relevance
102 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()103 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; in conf_read()105 *(vuip)MCPCIA_CAP_ERR(mid); in conf_read()116 value = *((vuip)addr); in conf_read()147 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); in conf_write()149 *(vuip)MCPCIA_CAP_ERR(mid); in conf_write()158 *((vuip)addr) = value; in conf_write()161 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ in conf_write()249 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0; in mcpcia_pci_tbi()[all …]
41 *(vuip)GRU_INT_MASK = mask; in alcor_update_irq_hw()63 *(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb(); in alcor_mask_and_ack_irq()64 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_mask_and_ack_irq()73 *(vuip)GRU_INT_CLEAR = 0x80000000; mb(); in alcor_isa_mask_and_ack_irq()74 *(vuip)GRU_INT_CLEAR = 0; mb(); in alcor_isa_mask_and_ack_irq()91 pld = (*(vuip)GRU_INT_REQ) & GRU_INT_REQ_BITS; in alcor_device_interrupt()116 *(vuip)GRU_INT_MASK = 0; mb(); /* all disabled */ in alcor_init_irq()117 *(vuip)GRU_INT_EDGE = 0; mb(); /* all are level */ in alcor_init_irq()118 *(vuip)GRU_INT_HILO = 0x80000000U; mb(); /* ISA only HI */ in alcor_init_irq()119 *(vuip)GRU_INT_CLEAR = 0; mb(); /* all clear */ in alcor_init_irq()[all …]
49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; in rawhide_update_irq_hw()51 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)); in rawhide_update_irq_hw()121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; in rawhide_init_irq()178 *(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0; in rawhide_init_irq()
101 *value = *(vuip)addr; in polaris_read_config()131 *(vuip)addr = value; in polaris_write_config()133 *(vuip)addr; in polaris_write_config()
120 *value = *(vuip)addr; in irongate_read_config()149 *(vuip)addr = value; in irongate_write_config()151 *(vuip)addr; in irongate_write_config()
133 *value = *(vuip)addr; in tsunami_read_config()162 *(vuip)addr = value; in tsunami_write_config()164 *(vuip)addr; in tsunami_write_config()
552 *value = *(vuip)addr; in marvel_read_config()582 *(vuip)addr = value; in marvel_write_config()584 *(vuip)addr; in marvel_write_config()1035 vuip addr; in marvel_agp_info()1041 addr = (vuip)build_conf_addr(h, 0, PCI_DEVFN(5, 0), 0); in marvel_agp_info()
101 *(vuip) CIA_IACK_SC; in init_pyxis_irqs()
125 int j = *(vuip) IACK_SC; in isa_device_interrupt()
399 *value = *(vuip)addr; in wildfire_read_config()428 *(vuip)addr = value; in wildfire_write_config()430 *(vuip)addr; in wildfire_write_config()
95 *(vuip) PYXIS_RESET = 0x0000dead; in ruffian_kill_arch()
254 *(vuip) PYXIS_RESET = 0x0000dead; in miata_kill_arch()
205 value = *(vuip)addr; in conf_read()257 *(vuip)addr = value; in conf_write()
156 *value = *(vuip)addr; in titan_read_config()185 *(vuip)addr = value; in titan_write_config()187 *(vuip)addr; in titan_write_config()
11 #define vuip volatile unsigned int * macro
1229 car = *(vuip) phys_to_virt (0x120000078UL); in determine_cpu_caches()
354 #define vuip volatile unsigned int * macro368 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; in t2_outb()383 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; in t2_outw()389 return *(vuip) ((addr << 5) + T2_IO + 0x18); in t2_inl()394 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; in t2_outl()475 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); in t2_readw()490 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); in t2_readl()502 r0 = *(vuip)(work); in t2_readq()503 r1 = *(vuip)(work + (4 << 5)); in t2_readq()515 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; in t2_writeb()[all …]
250 #define vuip volatile unsigned int __force * macro292 *(vuip) ((addr << 5) + hose + 0x00) = w; in mcpcia_iowrite8()316 *(vuip) ((addr << 5) + hose + 0x08) = w; in mcpcia_iowrite16()326 return *(vuip)addr; in mcpcia_ioread32()336 *(vuip)addr = b; in mcpcia_iowrite32()385 #undef vuip
342 #define vuip volatile unsigned int __force * macro374 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite8()404 *(vuip) ((addr << 5) + base_and_type) = w; in cia_iowrite16()412 return *(vuip)addr; in cia_ioread32()420 *(vuip)addr = b; in cia_iowrite32()482 #undef vuip